Data processing method based on FlexE one-layer cross connection

Abstract

The invention discloses a data processing method based on FlexE one-layer cross connection. The data processing method comprises the following steps: constructing cross connection between two FlexE board cards in a network node; wherein each FlexE board card comprises a FlexE Group at a line side and a FlexE Group at a system side; each FlexE Group comprises a plurality of PHY (Physical Layer) interfaces of the same type; each PHY interface comprises a plurality of Lanes, and supports a plurality of FlexE Channels; defining data structures of a line side FlexE Group and a system side FlexE Group in each FlexE board card, and performing data processing from the line side to the system side and from the system side to the line side; according to the method, through efficient processing of reverse transmission of data in a single FlexE board card from a line side to a system side, reliability and real-time performance of data cross connection transmission between the FlexE board card at the home terminal and the FlexE board card at the opposite terminal are improved, and performance optimization and stability enhancement of the slice packet network are realized.

Description

Technical Field

[0001] The present invention relates to the field of 5G network transmission, and more specifically to a data processing method based on FlexE layer one cross connection. Background Art

[0002] In today's high-speed data transmission field, with the rapid development of communication technology, higher requirements are placed on the latency and bandwidth of data transmission. As a key technology defined by the Optical Internetworking Forum (OIF) standard, Flexible Ethernet (FlexE) plays an important role in 5G SPN (Slicing Packet Network).

[0003] FlexE technology not only supports flexible connection scheduling of Ethernet packets, but also has SPN channel switching capabilities and supports FlexE layer 1 data cross-connection (which means directly exchanging and connecting data between FlexE channels at the physical layer level without the need for higher-layer processing), ensuring hard pipe isolation and bandwidth guarantee for services.

[0004] In the existing FlexE channel data cross-connection processing, it is usually implemented by a dedicated network processor (NP). This processing method requires multiple processing links, including the interconnection between the FlexE module and the NP through the Interlaken bus interface, the data slicing and reassembly (SAR) processing, and the data transmission of the Interlaken interface. These links not only increase the complexity of the processing, but also lead to higher latency.

[0005] Specifically, the existing solution involves the interconnection of multiple processing modules and interfaces, and each link may introduce additional processing delay. In addition, the SAR module performs data sharding and reassembly between the FlexE module and the NP, and the additional overhead generated in this process also increases the overall delay.

[0006] Due to the excessive number of processing links mentioned above, the cross-processing delay of the first layer of data is relatively high, usually around 8us, which cannot meet the ITU-T standard requirement that the single-node delay of the access device should be less than 3us, and it is difficult to meet the current network communication requirements for low-latency, high-bandwidth data transmission.

[0007] Therefore, how to design a data processing method based on FlexE layer one cross connection, reduce the data processing steps in multiple links, and ensure low latency, high reliability and scalability of data transmission is a problem that technical personnel in this field urgently need to solve. Summary of the invention

[0008] In view of this, the present invention provides a data processing method based on FlexE layer one cross-connection. By performing cross-connection of FlexE layer one data, the data conversion and processing steps in multiple links are reduced, thereby significantly reducing the single-node layer one data exchange delay, and supporting flexible bandwidth configuration and efficient data verification mechanism, ensuring low-latency, high-reliability and scalability data transmission, which is particularly suitable for application scenarios with extremely high performance requirements such as 5G transmission.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] This embodiment provides a data processing method based on a FlexE layer 1 cross connection, including the following steps:

[0011] S1. Build a cross connection between two FlexE boards in a network node; each FlexE board includes a line-side FlexE Group and a system-side FlexE Group; each FlexE Group includes multiple PHY interfaces of the same type; each PHY interface includes multiple Lanes and supports multiple FlexE Channels;

[0012] S2. Define the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board, and perform data processing from the line side to the system side and from the system side to the line side;

[0013] The data processing from the line side to the system side includes:

[0014] S211, framing, checking, and scrambling the data of each FlexE Channel in the FlexE Group on the line side of the local FlexE board, and storing the data in a layer 1 data FIFO buffer;

[0015] S212: forward the data to the FlexE Group on the system side of the local FlexE board, and send the data to the FlexE Channel corresponding to the FlexE Group on the line side of the opposite FlexE board.

[0016] Data processing from the system side to the line side includes:

[0017] S221, receiving data from each FlexE Channel in the FlexE Group on the opposite FlexE board system side, performing deframing, descrambling and verification processing, and storing the data in a layer 1 data FIFO buffer;

[0018] S222: Forward the data to the FlexE Group on the line side of the local FlexE board.

[0019] Further, the S1 includes:

[0020] Determine the FlexE Channels for cross-connection between two FlexE cards and configure the same bandwidth for the cross-connected FlexE Channels.

[0021] Furthermore, in S2, when the type of the PHY interface is a 100G PHY interface, the data structure of the line side FlexE Group and the system side FlexE Group in each FlexE board is defined, including:

[0022] Define the data structure of the line-side FlexE Group:

[0023] Each 100G PHY interface includes 4 Lanes, and the data of each Lane is processed in 66-bit block units; each FlexE Channel sends and receives data structures consisting of 4*66-bit data blocks, 5-bit Channel ID, and 1-bit Sync for each 100G PHY interface; the data structure is 270 bits in total;

[0024] Define the data structure of the FlexE Group on the system side:

[0025] The 270-bit data of each 100G PHY interface is divided into 5 lanes for transmission. Each lane transmits a 54-bit data frame, and the sixth lane is used as a control frame.

[0026] The data structure of each data frame includes 54-bit data, 1-bit SPR, 1-bit Skip, 1-bit Sync and 7-bit BIP check bit; the data structure of the control frame includes 5-bit Channel id, 10-bit valid transmit and receive frame counter CNT, 40-bit Spare, 1-bit Skip, 1-bit Sync and 7-bit BIP check bit.

[0027] Furthermore, when the type of the PHY interface is a 50G PHY interface, the data structure of the line side FlexE Group and the system side FlexE Group is defined, including:

[0028] Define the data structure of the line-side FlexE Group:

[0029] Each 50G PHY interface includes 2 Lanes, and the data of each Lane is processed in 66-bit block units; each FlexE Channel sends and receives data structures consisting of 2*66-bit data blocks, 132-bit Skip, 5-bit Channel ID, and 1-bit Sync for each 100G PHY interface; the data structure is 270 bits in total;

[0030] The data structure for defining the FlexE Group on the system side is the same as that for the 100G PHY interface.

[0031] Further, when the type of the PHY interface is a K*100G PHY interface, where K is a positive integer and K≥2; defining a data structure of a line-side FlexE Group and a system-side FlexE Group, including:

[0032] Combination processing of the definition methods under K 100G PHY interfaces.

[0033] Furthermore, the valid transceiver frame counter CNT is incremented by 1 when a valid frame without Skip is sent or received.

[0034] Furthermore, in S2, the maximum FIFO data cache capacity that can be supported by a layer of data FIFO buffer is 32*N*M*270 bits;

[0035] Among them, the depth of one layer of data FIFO buffer is 32, and each FlexE Channel caches 32 270-bit data in one layer of data FIFO buffer for each 100G PHY interface; one layer of data FIFO buffer supports a maximum of N 100GPHY interfaces, where N is a positive integer and N≤4; and each 100G PHY interface supports a maximum of M FlexE channels, where M is a positive integer and M≤20.

[0036] Furthermore, in S2, the scrambling process and the descrambling process use a linear feedback shift register LFSR to generate a pseudo-random sequence;

[0037] The state of the linear feedback shift register LFSR is given by the polynomial 1+x 39 +x 58 Determine; where x represents a shift operation.

[0038] Furthermore, in S2, the verification process includes:

[0039] Perform BIP verification and ignore data frames with abnormal verification results;

[0040] Perform Sync bit check and ignore data frames with abnormal check results;

[0041] Perform Skip check and ignore data frames with abnormal check results.

[0042] Furthermore, the BIP verification includes:

[0043] Divide the descrambled data into 7 subsets; each subset contains 8 bits of data;

[0044] Calculate the parity bits of all data bits in each subset and generate a check result;

[0045] The calculating of the parity check bits of all data bits in each subset includes: if the sum of the values ​​of all data bits in the subset is an even number, the corresponding check bit is set to 0; if the sum of the values ​​of all data bits in the subset is an odd number, the corresponding check bit is set to 1.

[0046] It can be seen from the above technical solution that compared with the prior art, the technical solution of the present invention has the following advantages:

[0047] Beneficial effects:

[0048] 1. By cross-connecting the FlexE layer 1 data and using the layer 1 data FIFO buffer to cache and forward data, multiple fragment reassembly and Interlaken channel conversion steps can be avoided, and the single-node layer 1 data exchange delay can be reduced to less than 2 microseconds. This not only meets the 3 microsecond requirement of ITU-T for access equipment, but also provides better performance, which is particularly critical for application scenarios that require low-latency communication.

[0049] 2. In the process of defining the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board, a layer of data FIFO buffer can support data cache of up to 20 FlexE channels under each 100G PHY interface, and support multiple PHY interfaces of the same type (such as 100G PHY, 50G PHY, 200G PHY). This allows the network to dynamically adjust the number of FlexE channels and their bandwidth allocation according to actual needs to adapt to different business traffic patterns.

[0050] 3. Perform data processing from the line side to the system side and from the system side to the line side, and provide an efficient data verification mechanism, including BIP (bit-by-bit verification) verification, Sync synchronization flag verification, and Skip skipping flag verification for the descrambled data. In addition, a linear feedback shift register (LFSR) is used to generate a pseudo-random sequence for data scrambling and descrambling. Together, they ensure the integrity and reliability of data during transmission, effectively reduce the error rate, and enhance the overall security level of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0052] Figure 1 A flow chart of a data processing method based on a FlexE layer 1 cross connection provided in an embodiment of the present invention;

[0053] Figure 2 A schematic diagram of a data processing process from a line side to a system side provided in an embodiment of the present invention;

[0054] Figure 3 A schematic diagram of a data processing process from a system side to a line side provided in an embodiment of the present invention;

[0055] Figure 4 A schematic diagram of an end-to-end connection structure based on a FlexE layer 1 cross connection provided in an embodiment of the present invention;

[0056] Figure 5 A schematic diagram comparing a FlexE layer-1 cross-connection provided in an embodiment of the present invention and a conventional FlexE cross-connection. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] like Figure 1 As shown, this embodiment provides a data processing method based on FlexE layer 1 cross connection, including the following steps:

[0059] S1. Build a cross connection between two FlexE boards in a network node; each FlexE board includes a line-side FlexE Group and a system-side FlexE Group; each FlexE Group includes multiple PHY interfaces of the same type; each PHY interface includes multiple Lanes and supports multiple FlexE Channels;

[0060] S2. Define the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board, and perform data processing from the line side to the system side and from the system side to the line side;

[0061] like Figure 2 As shown, the data processing from the line side to the system side includes:

[0062] S211, framing, checking, and scrambling the data of each FlexE Channel in the FlexE Group on the line side of the local FlexE board, and storing the data in a layer 1 data FIFO buffer;

[0063] S212: forward the data to the FlexE Group on the system side of the local FlexE board, and send the data to the FlexE Channel corresponding to the FlexE Group on the line side of the opposite FlexE board.

[0064] like Figure 3 As shown, data processing from the system side to the line side includes:

[0065] S221, receiving data from each FlexE Channel in the FlexE Group on the opposite FlexE board system side, performing deframing, descrambling and verification processing, and storing the data in a layer 1 data FIFO buffer;

[0066] S222: Forward the data to the FlexE Group on the line side of the local FlexE board.

[0067] This method achieves efficient data transmission and flexible network resource configuration in the Sliced ​​Packet Network (SPN). By building a cross-connection between two FlexE boards in a network node and scrambling, descrambling and verifying the data, this technical solution enhances the security and integrity of data transmission, while also improving the flexibility and bandwidth utilization of the network. Specifically, scrambling processing increases the anti-interference ability of data transmission, while descrambling and verification ensure the correctness of data during transmission. Combined with the network slicing function of SPN, resources can be dynamically allocated according to different business needs, thereby supporting diverse application scenarios and service quality requirements in the 5G era.

[0068] The above steps and related technical features are further described in detail below:

[0069] In the specific FlexE architecture, the slice transport layer (STL) acts as the basic layer and directly interacts with the IEEE 802.3 physical layer. It forms a FlexE Group by combining multiple physical Lanes and creates logical FlexE Channels to carry different types of data traffic. The slice channel layer (SCL) is responsible for mapping upper-layer traffic to these FlexE Channels, managing and coordinating bandwidth allocation to ensure that each channel obtains sufficient resources to meet service level requirements. The slice packet layer (SPL) handles higher-level protocol stacks, such as MPLS-TP, SR-TP, and SR-BE tunnels, encapsulates customer service data packets, and efficiently transmits them through the corresponding FlexE Channels.

[0070] "FlexE layer 1 cross-connection" refers to the process of data exchange and routing selection between different physical interfaces inside network devices, especially inside routers or switches. This process mainly occurs in the STL (slice transport layer) and SCL (slice channel layer) layers in the FlexE architecture, which are closer to the physical layer and data link layer of the network and are responsible for handling the low-level transmission details of data frames.

[0071] like Figure 4 As shown in the figure, data enters the FlexE Group from the FlexE Client of PE1; within the FlexE Group, the data is mapped to the corresponding FlexE Channel; the FlexE Channel is cross-connected through the FlexE L1XC module and then reaches the P3 or P4 node; at the P3 or P4 node, the data is cross-connected again through the FlexE L1XC module and finally reaches the FlexE Group of PE2; finally, the data leaves the FlexE Group of PE2 and returns to the packet switch through the FlexE Client.

[0072] PE1 and PE2 are packet switches, representing two edge routers or core routers in the network; FlexEClient is the FlexE client, responsible for encapsulating packet data into the FlexE format and decapsulating it at the other end; P3 and P4 are intermediate nodes, which are routers, switches or other network devices; FlexE L1XC (FlexE Layer 1Cross Connect) is a cross-connection module used to achieve cross-connection between FlexE boards inside the network element.

[0073] In this embodiment S1, a cross connection between two FlexE boards in a network node is established, including: determining a FlexE Channel for cross connection between the two FlexE boards, and configuring the same bandwidth for the cross-connected FlexE Channels.

[0074] Specifically, select the FlexE Channel that needs to be cross-connected in the FlexE Group of the local FlexE board and the FlexE Group of the opposite FlexE board, and assign a unique Channel ID to each selected FlexE Channel and record it. Next, determine the bandwidth of each FlexE Channel based on business requirements, and configure the same bandwidth on the line side and the system side. Finally, use a network monitoring tool or command line interface to check the bandwidth configuration of each FlexE Channel to ensure that the bandwidth of all FlexE Channels is consistent and meets expectations.

[0075] like Figure 5 As shown in the figure, for conventional FlexE cross-connection, FlexE channel data needs to be fragmented and reassembled first, and converted into Interlaken channel data, and then passed to the network processor (NP) through the Interlaken bus for further processing. It involves many conversion steps and links, so it is difficult to meet the requirement of single-node latency less than 3 microseconds.

[0076] The FlexE layer 1 cross-connection in this embodiment defines a special cross-connection module to complete data fragmentation, reorganization and switching operations. It directly processes data through the bus between the FlexE board backplanes, reducing the number of intermediate links, thereby reducing the single-node cross-connection processing delay to 2 microseconds.

[0077] In this embodiment S2, the working clock of the line side FlexE Group and the system side FlexE Group is 402 MHz. When the type of the PHY interface is a 100G PHY interface, the data structure of the line side FlexE Group and the system side FlexE Group is defined, including:

[0078] Define the data structure of the line-side FlexE Group:

[0079] Each 100G PHY interface includes 4 Lanes, and the data of each Lane is processed in 66-bit block units; each FlexE Channel sends and receives data structures consisting of 4*66-bit data blocks, 5-bit Channel ID, and 1-bit Sync for each 100G PHY interface; the data structure is 270 bits in total;

[0080] Among them, Channel id is the channel identifier, which is used to identify the unique ID of FlexE Channel; Sync is the synchronization flag, which is used to indicate the synchronization status between Lanes;

[0081] Define the data structure of the FlexE Group on the system side:

[0082] The 270-bit data of each 100G PHY interface is divided into five lanes (Lane0, Lane1, Lane2, Lane3 and Lane4) for transmission. Each lane transmits a 54-bit data frame, and the sixth lane (Lane5) is used as a control frame.

[0083] The data structure of each data frame includes 54-bit data, 1-bit SPR, 1-bit Skip, 1-bit Sync and 7-bit BIP check bit; the data structure of the control frame includes 5-bit Channel id, 10-bit valid transmit and receive frame counter CNT, 40-bit Spare, 1-bit Skip, 1-bit Sync and 7-bit BIP check bit.

[0084] Among them, SPR (Spare) is a spare bit used for filling; Skip is a skip flag bit used to indicate whether the frame needs to be ignored; Sync is a synchronization flag bit used to indicate the synchronization status between Lanes; BIP check bit is a bit-by-bit check bit used for data integrity verification.

[0085] When the PHY interface is 100G, by defining the data structure of the FlexE Group on the line side and the system side, each 100G PHY interface includes 4 Lanes, and the data is processed in 66-bit block units. The data structure of each FlexE Channel is 270 bits in total. The system side divides the 270-bit data into 5 Lanes for transmission, and uses the 6th Lane as a control frame. It significantly reduces the data transmission delay, and at the same time ensures data integrity through the BIP check bit, ensures Lane synchronization through the Sync flag, and allows invalid frames to be skipped through the Skip flag, thereby improving the reliability, flexibility and consistency of the system, and can meet and exceed the single-node delay requirements specified by ITU-T.

[0086] Furthermore, when the type of the PHY interface is a 50G PHY interface, the data structure of the line side FlexE Group and the system side FlexE Group is defined, including:

[0087] Define the data structure of the line-side FlexE Group:

[0088] Each 50G PHY interface includes 2 Lanes, and the data of each Lane is processed in 66-bit block units; each FlexE Channel sends and receives data structures consisting of 2*66-bit data blocks, 132-bit Skip, 5-bit Channel ID, and 1-bit Sync for each 100G PHY interface; the data structure is 270 bits in total;

[0089] The 132-bit Skip here is for processing the data of the two Lanes into Skips, and the data structure of the line-side FlexE Group is the same as that of the 100G PHY.

[0090] The data structure for defining the FlexE Group on the system side is the same as that for the 100G PHY interface.

[0091] Further, when the type of the PHY interface is a K*100G PHY interface, where K is a positive integer and K≥2; defining a data structure of a line-side FlexE Group and a system-side FlexE Group, including:

[0092] Combination processing of the definition methods under K 100G PHY interfaces.

[0093] Specifically, when the type of the PHY interface is a 200G PHY interface (ie, K=2), when defining the data structure of the line-side FlexEGroup and the system-side FlexE Group, each 200G PHY interface contains 2 100G instances, and the processing of each 100G Instance is the same as that of a single 100G PHY.

[0094] In this way, 200G PHY and 100G PHY adopt a unified processing method to ensure efficient, reliable and consistent data transmission solutions while meeting the requirements of low latency. Similarly, it can meet the data transmission under K*100G PHY interface.

[0095] Furthermore, the valid sending and receiving frame counter CNT is incremented by 1 when a valid frame without Skip is sent or received.

[0096] The valid frame counter CNT is a 10-bit counter used to record the number of valid frames sent or received in the control frame. By monitoring the number of valid frames, data transmission can be monitored and managed to ensure data integrity and reliability.

[0097] Specifically, at the transmitting end, whenever a valid frame without Skip bit is sent, the CNT counter of the transmitting end is incremented by 1. The transmitting end includes the current CNT value in the data structure of the control frame and sends it together with the data frame. At the receiving end, for each valid frame without Skip bit, the CNT counter of the receiving end is incremented by 1. The receiving end compares the updated CNT value with the CNT value sent by the transmitting end to ensure the consistency and integrity of data transmission.

[0098] For example, the data frame sequence sent by the sender is: Frame 1: valid frame, Skip bit = 1; Frame 2: valid frame, Skip bit = 0; Frame 3: invalid frame, Skip bit = 1; Frame 4: valid frame, Skip bit = 0;

[0099] When sending frame 1, CNT = 1; when sending frame 2, CNT = 2; when sending frame 3, Skip bit = 1, CNT is not increased, CNT = 2; when sending frame 4, CNT = 3;

[0100] When receiving frame 1, verification is correct, CNT = 1; when receiving frame 2, verification is correct, CNT = 2; when receiving frame 3, Skipbit = 1, ignore the frame, CNT = 2; when receiving frame 4, verification is correct, CNT = 3;

[0101] In this way, the valid transceiver frame counter CNT can accurately record and monitor the number of valid data frames to ensure the reliability and consistency of data transmission.

[0102] In this embodiment, the maximum FIFO data cache capacity that can be supported by a layer of data FIFO buffer is 32*N*M*270 bits;

[0103] Among them, the depth of one layer of data FIFO buffer is 32, and each FlexE Channel caches 32 270-bit data in one layer of data FIFO buffer for each 100G PHY interface; one layer of data FIFO buffer supports a maximum of N 100GPHY interfaces, where N is a positive integer and N≤4; and each 100G PHY interface supports a maximum of M FlexE channels, where M is a positive integer and M≤20.

[0104] By defining the maximum cache capacity and configuration of a layer of data FIFO buffer, it not only provides high-capacity data buffering capabilities, but also ensures low latency, high reliability and flexibility. This enables the system to efficiently handle multiple high-speed PHY interfaces and multiple FlexE channels to meet the needs of high-performance network applications.

[0105] Furthermore, the scrambling and descrambling processes use a linear feedback shift register LFSR to generate a pseudo-random sequence;

[0106] The state of the linear feedback shift register LFSR is given by the polynomial 1+x 39 +x 58 where x represents a shift operation. For example, in an LFSR, x^39 means shifting the value in the register right by 39 bits, and x^58 means shifting it right by 58 bits. These shift operations determine the feedback function of the LFSR, which in turn affects the generated pseudo-random sequence.

[0107] Specifically, the scrambling and descrambling process includes the following steps:

[0108] Scrambling process: Initialize a linear feedback shift register (LFSR) with a length of 39+58=97 bits. The state of the LFSR is determined by a polynomial. Use the LFSR to generate a pseudo-random sequence as the scrambling sequence. Perform an XOR operation on the scrambling sequence and the original data to obtain the scrambled data.

[0109] Descrambling process: The receiver receives the scrambled data and generates another pseudo-random sequence using the same LFSR polynomial. The received scrambled data is XORed with the descrambling sequence to recover the original data.

[0110] The key to scrambling and descrambling is to use the same LFSR polynomial and initial state. As long as both the transmitter and receiver follow the same rules, the correct descrambling effect can be guaranteed.

[0111] The verification process in this embodiment includes: performing BIP verification, ignoring data frames with abnormal verification results in the data; performing Sync setting verification, ignoring data frames with abnormal verification results in the data; performing Skip setting verification, ignoring data frames with abnormal verification results in the data.

[0112] Specifically, in S221, the BIP check is performed on the descrambled data, including: dividing the descrambled data into 7 subsets; each subset contains 8 bits of data; specifically: the first subset: data bit (7:0); the second subset: data bit (15:8); the third subset: data bit (23:16); the fourth subset: data bit (31:24); the fifth subset: data bit (39:32); the sixth subset: data bit (47:40); the seventh subset: data bit (56:48);

[0113] Calculate the parity bits of all data bits in each subset and generate a check result; calculate the parity bits of all data bits in each subset, including:

[0114] If the sum of the values ​​of all the data bits in the subset is an even number, the corresponding check bit is set to 0; if the sum of the values ​​of all the data bits in the subset is an odd number, the corresponding check bit is set to 1.

[0115] Generate 7 check bits, corresponding to the above 7 subsets, specifically: Bit (57) - the check result corresponding to the data bit (7:0) of the first subset; Bit (58) - the check result corresponding to the data bit (15:8) of the second subset; Bit (59) - the check result corresponding to the data bit (23:16) of the third subset; Bit (60) - the check result corresponding to the data bit (31:24) of the fourth subset; Bit (61) - the check result corresponding to the data bit (39:32) of the fifth subset; Bit (62) - the check result corresponding to the data bit (47:40) of the sixth subset; Bit (63) - the check result corresponding to the data bit (56:48) of the seventh subset;

[0116] The 57-bit data and 7-bit check bits are combined into a 64-bit data block for transmission. The receiving end verifies the integrity of the data by recalculating and comparing the received check bits. If any check bit does not match the expected value, the data is considered to be erroneous and the current data frame is ignored.

[0117] Further, a Sync setting check is performed to ignore data frames with abnormal check results in the data;

[0118] Specifically, check whether the Sync flag in the data frame is set correctly. If the Sync flag is not set (that is, 0), ignore the current data frame. This is to ensure the synchronization between Lanes. Only when all Lanes are synchronized, the receiving end considers the data to be valid.

[0119] Furthermore, a Skip bit check is performed to ignore data frames with abnormal check results, and the checked data is stored in a layer of data FIFO buffer.

[0120] Specifically, check whether the Skip flag in the data frame is set. If the Skip flag is set (i.e., 1), ignore the current data frame. If the Skip flag is not set (i.e., 0), store the verified data in a layer of data FIFO buffer. This is to skip invalid or unnecessary data frames to ensure that only valid data frames are processed.

[0121] In this step, the high integrity, synchronization and validity of the data are ensured through BIP check, Sync set check and Skip set check. BIP check detects and ignores data frames with bit errors, Sync set check ensures the synchronization status between Lanes, and Skip set check skips invalid data frames. These check steps together improve the reliability of the system, reduce data processing delays, and ensure that only valid data is stored in the FIFO buffer, thereby improving the efficiency and stability of overall data transmission.

[0122] This embodiment provides a data processing method based on a FlexE layer cross connection, which mainly includes building a cross connection between two FlexE boards in a network node, defining the data structure of the line side and the system side FlexE Group, and realizing data scrambling processing and forwarding from the line side to the system side, as well as data descrambling, verification and storage from the system side to the line side. This method enhances the security and integrity of data transmission through technical means such as scrambling, descrambling, BIP verification, Sync setting and Skip setting verification, and supports efficient cache management by configuring a layer of data FIFO buffer.

[0123] This method is applicable to the same type of PHY interfaces (such as 100G, 50G, 200G, etc.), and by defining the corresponding data structure and processing flow, it ensures low latency, high reliability and flexibility. It is suitable for efficient data transmission and flexible resource configuration in SPN networks.

[0124] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0125] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing method based on FlexE layer 1 cross connection, characterized in that: The following steps are involved: S1. Build a cross connection between two FlexE boards in a network node; each FlexE board includes a line-side FlexE Group and a system-side FlexE Group; each FlexE Group includes multiple PHY interfaces of the same type; each PHY interface includes multiple Lanes and supports multiple FlexE Channels; S2. Define the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board, and perform data processing from the line side to the system side and from the system side to the line side; The data processing from the line side to the system side includes: S211, framing, checking, and scrambling the data of each FlexE Channel in the FlexE Group on the line side of the local FlexE board, and storing the data in a layer 1 data FIFO buffer; S212: forward the data to the FlexE Group on the system side of the local FlexE board, and send the data to the FlexE Channel corresponding to the FlexE Group on the line side of the opposite FlexE board. Data processing from the system side to the line side includes: S221, receiving data from each FlexE Channel in the FlexE Group on the opposite FlexE board system side, performing deframing, descrambling and verification processing, and storing the data in a layer 1 data FIFO buffer; S222: Forward the data to the FlexE Group on the line side of the local FlexE board.

2. According to claim 1, a data processing method based on FlexE layer 1 cross connection is characterized in that: The S1 includes: Determine the FlexE Channel for cross-connection between two FlexE boards, and configure the same bandwidth for the cross-connected FlexE Channels.

3. According to claim 1, a data processing method based on FlexE layer 1 cross connection is characterized in that: In S2, when the type of the PHY interface is a 100G PHY interface, the data structure of the line-side FlexE Group and the system-side FlexE Group in each FlexE board is defined, including: Define the data structure of the line-side FlexE Group: Each 100G PHY interface includes 4 Lanes, and the data of each Lane is processed in 66-bit block units; each FlexEChannel sends and receives data structures consisting of 4*66-bit data blocks, 5-bit Channel ID, and 1-bit Sync for each 100G PHY interface; the data structure is 270 bits in total; Define the data structure of the FlexE Group on the system side: The 270-bit data of each 100G PHY interface is divided into 5 lanes for transmission. Each lane transmits a 54-bit data frame, and the sixth lane is used as a control frame. The data structure of each data frame includes 54-bit data, 1-bit SPR, 1-bit Skip, 1-bit Sync and 7-bit BIP check bit; the data structure of the control frame includes 5-bit Channel id, 10-bit valid transmit and receive frame counter CNT, 40-bit Spare, 1-bit Skip, 1-bit Sync and 7-bit BIP check bit.

4. The data processing method based on FlexE layer 1 cross connection according to claim 3 is characterized in that: When the type of the PHY interface is a 50G PHY interface, the data structure of the line-side FlexE Group and the system-side FlexE Group is defined, including: Define the data structure of the line-side FlexE Group: Each 50G PHY interface includes 2 Lanes, and the data of each Lane is processed in 66-bit block units; each FlexEChannel sends and receives each 100G PHY interface with a data structure consisting of 2*66-bit data blocks, 132-bit Skip, 5-bit Channel id, and 1-bit Sync; the data structure is 270 bits in total; the data structure for defining the system-side FlexE Group is the same as the definition under the 100G PHY interface.

5. The data processing method based on FlexE layer 1 cross connection according to claim 3 is characterized in that: When the type of the PHY interface is a K*100G PHY interface, where K is a positive integer and K≥2; the data structure of the line-side FlexE Group and the system-side FlexE Group is defined, including: Combination processing of the definition methods under K 100G PHY interfaces.

6. The data processing method based on FlexE layer 1 cross connection according to claim 3 is characterized in that: The valid transceiver frame counter CNT is incremented by 1 when a valid frame without Skip is sent or received.

7. The data processing method based on FlexE layer 1 cross connection according to claim 1 is characterized in that: In S2, the maximum FIFO data cache capacity that can be supported by a layer of data FIFO buffer is 32*N*M*270 bits; Among them, the depth of one layer of data FIFO buffer is 32, and each FlexE Channel caches 32 270-bit data in one layer of data FIFO buffer for each 100G PHY interface; one layer of data FIFO buffer supports a maximum of N 100G PHY interfaces, where N is a positive integer and N≤4; and each 100G PHY interface supports a maximum of M FlexE channels, where M is a positive integer and M≤20.

8. The data processing method based on FlexE layer 1 cross connection according to claim 1, characterized in that: In S2, the scrambling process and the descrambling process use a linear feedback shift register LFSR to generate a pseudo-random sequence; The state of the linear feedback shift register LFSR is given by the polynomial 1+x 39 +x 58 Determine; where x represents a shift operation.

9. The data processing method based on FlexE layer 1 cross connection according to claim 1, characterized in that: In S2, the verification process includes: Perform BIP verification and ignore data frames with abnormal verification results; Perform Sync bit check and ignore data frames with abnormal check results; Perform Skip check and ignore data frames with abnormal check results.

10. The data processing method based on FlexE layer 1 cross connection according to claim 9, characterized in that: The BIP verification includes: Divide the descrambled data into 7 subsets; each subset contains 8 bits of data; Calculate the parity bits of all data bits in each subset and generate a check result; The calculating of the parity check bits of all data bits in each subset includes: if the sum of the values ​​of all data bits in the subset is an even number, the corresponding check bit is set to 0; if the sum of the values ​​of all data bits in the subset is an odd number, the corresponding check bit is set to 1.

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