Conductor structure for improving crosstalk, semiconductor packaging structure and circuit board
By adding a thin line structure and a mutual capacitance module between the pads of the semiconductor package, a capacitor structure is formed to increase the signal equivalent capacitance, the problem of signal crosstalk between the LGA pads is solved, and the problem of signal crosstalk between the LGA pads is realized. The effect of effectively suppressing signal crosstalk while increasing the package size.
Patent Information
- Application Number
- CN202411521199.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-07
AI Technical Summary
In semiconductor packages, signal crosstalk between LGA pads is serious, and existing methods such as increasing pad spacing or introducing ground pads will lead to an increase in the package size, which violates the design trend of miniaturization and high integration.
By adding a thin line structure and a mutually capacitance module between the pads on each grid array package pad, and connecting the first via through the thin line structure and the via side of the mutually capacitance module between the pads, a capacitance structure is formed. Increase the signal equivalent capacitance to achieve effective coupling and mutual capacitance of signals.
Without increasing the package size, signal crosstalk between adjacent LGA pads is effectively suppressed, improving signal integrity and system performance.
Smart Images
Figure CN119403033A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a conductor structure, a semiconductor packaging structure and a circuit board for improving crosstalk. Background Art
[0002] With the rapid development of the semiconductor industry, the speed of high-speed signals continues to increase. However, in the process of signal transmission, various loss and reflection problems continue to emerge, among which the crosstalk problem is becoming increasingly serious and has become one of the key factors restricting the further improvement of signal speed.
[0003] In the signal transmission path, the crosstalk between LGA (Land Grid Array) pads and vias is particularly prominent. At present, in order to reduce the crosstalk between adjacent signals, the method of increasing the LGA pad spacing or isolating the signal pads with ground pads is usually adopted. However, in the context of high device integration today, package size is crucial. Whether it is increasing the LGA pad spacing or adding additional ground pads, the package size will increase, which is contrary to the current trend of miniaturization and high integration of package design; on the other hand, for chips with a large number of signals and compact layout, equipping each signal pad with an independent ground pad for isolation is not only technically difficult to implement, but also costly and not practically feasible.
[0004] Therefore, how to suppress signal crosstalk between adjacent LGA pads without increasing the package size is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The main purpose of the present application is to provide a conductor structure, a semiconductor packaging structure and a circuit board for improving crosstalk, aiming to effectively suppress signal crosstalk between adjacent LGA pads without increasing the package size.
[0006] To achieve the above-mentioned purpose, the present application also provides a conductor structure for improving crosstalk, wherein the conductor structure for improving crosstalk comprises a plurality of grid array package pads arranged side by side;
[0007] Each of the grid array package pads is provided with at least a first via, a fine line structure and a mutual capacitance module between pads, the first via is connected to the via side of the mutual capacitance module between pads through the fine line structure, and the mutual capacitance module between pads is arranged directly above the adjacent grid array package pads to form a capacitor structure; wherein,
[0008] The adjacent grid array package pad is the next grid array package pad of each of the grid array package pads.
[0009] In one embodiment, the pad-to-pad mutual capacitance module includes a coupling plane structure, a second via hole, and a third via hole;
[0010] The third via hole is provided on the grid array package pad and is used to connect the pad foot of the grid array package pad;
[0011] The third via hole is connected to the second via hole at a side away from the grid array package pad, and the coupling plane structure is arranged between the connected second via hole and the third via hole, and the coupling plane structure is arranged directly above the adjacent grid array package pad to form the capacitor structure; wherein,
[0012] A side of the second via hole away from the coupling plane structure constitutes a via hole side of the mutual capacitance module between pads.
[0013] In one embodiment, the pad-to-pad mutual capacitance module includes a coupling plane structure, a second via, a third via, and a fourth via;
[0014] The third via hole and the fourth via hole are arranged on the grid array package pad at a preset interval, and are used to connect the pad feet of the grid array package pad;
[0015] The coupling plane structure is disposed on a side of the third via away from the pad solder foot, and the coupling plane structure is disposed directly above the adjacent grid array package pad to form the capacitor structure;
[0016] The second via hole is connected to the fourth via hole, and a side of the second via hole that is not connected to the fourth via hole constitutes a via side of the mutual capacitance module between pads.
[0017] In one embodiment, the coupling plane structure includes a coupling plane layer, and a transmission line connecting the coupling plane layer;
[0018] In each of the grid array package pads, the extended side of the transmission line is connected to the coupling plane layer, and the coupling plane layer is arranged directly above the adjacent grid array package pad;
[0019] The connection side of the transmission line is arranged between the connected second via hole and the third via hole; or, the connection side of the transmission line is arranged on a side of the third via hole away from the pad foot, and the connection side is the opposite side of the transmission line.
[0020] In one embodiment, the aperture of the first via hole, the aperture of the second via hole, and the aperture of the third via hole in each grid array package pad are all made of the same conductive material as the coupling plane structure;
[0021] The conductive property of the conductive material is the same as the conductive property of the pad foot.
[0022] In one embodiment, each of the grid array package pads is further provided with a first integrated circuit layer, a second integrated circuit layer, a third integrated circuit layer and a fourth integrated circuit layer arranged in parallel with each other;
[0023] The first via is disposed between the first integrated circuit layer and the second integrated circuit layer to form a hole structure connecting the first integrated circuit layer and the second integrated circuit layer;
[0024] The second via is disposed between the second integrated circuit layer and the third integrated circuit layer to form a hole structure connecting the second integrated circuit layer and the third integrated circuit layer;
[0025] The third via is disposed between the third integrated circuit layer and the fourth integrated circuit layer to form a hole structure connecting the third integrated circuit layer and the fourth integrated circuit layer.
[0026] In one embodiment, the conductive properties of the first integrated circuit layer, the conductive properties of the second integrated circuit layer, the conductive properties of the third integrated circuit layer, and the conductive properties of the fourth integrated circuit layer are all the same as the conductive properties of the pad foot.
[0027] In one embodiment, the side of the first via not connected to the fine wire structure is disposed on the first integrated circuit layer; the side of the first via connected to the fine wire structure and the side of the second via connected to the fine wire structure are both disposed on the second integrated circuit layer, and the fourth integrated circuit layer is printed on the land grid array package pad;
[0028] The second via is connected to one side of the third via, the third via is connected to one side of the second via, the coupling plane structure and the side of the third via connected to the coupling plane structure are all arranged on the third integrated circuit layer, and the side of the third via connected to the pad foot is arranged on the fourth integrated circuit layer.
[0029] In addition, to achieve the above-mentioned purpose, the present application also provides a semiconductor packaging structure, which includes a substrate, and the substrate is provided with a conductor, and the conductor is configured as a conductor structure for improving crosstalk as described in any one of the above items.
[0030] In addition, to achieve the above-mentioned purpose, the present application also provides a circuit board, characterized in that the circuit board includes a substrate, the substrate is provided with a conductor, and the conductor is configured as any of the above-mentioned conductor structures for improving crosstalk.
[0031] The present application provides a conductor structure, a semiconductor packaging structure and a circuit board for improving crosstalk, so that the signal crosstalk between adjacent LGA (Land Grid Array, grid array package) pads can be effectively suppressed without increasing the package size. Specifically, the present application adds a fine wire structure and a mutual capacitance module between pads on each grid array package pad, and connects the first via provided on each grid array package pad to the via side of the mutual capacitance module between pads through the fine wire structure, so that each grid array package pad can produce a stronger signal self-inductance effect to weaken the influence of signal crosstalk between adjacent LGA pads. At the same time, by setting the additional mutual capacitance module between pads to form a capacitor structure directly above the adjacent grid array package pads to increase the equivalent capacitance of the signal between adjacent LGA pads, it is possible to achieve effective coupling mutual capacitance between the signals between adjacent LGA pads without adding additional wiring space, thereby further suppressing the signal crosstalk between adjacent LGA pads. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic diagram of the coupling of a pair of strip lines;
[0033] Figure 2 It is a structural schematic diagram of the first embodiment of the conductor structure for improving crosstalk of the present application;
[0034] Figure 3 It is a three-dimensional structural diagram of a conductor structure for improving crosstalk involved in an embodiment of the present application;
[0035] Figure 4 This application embodiment involves Figure 3 A top view of the three-dimensional structure shown;
[0036] Figure 5 This application embodiment involves Figure 3 A cross-sectional view of the three-dimensional structure shown;
[0037] Figure 6 is another three-dimensional structural diagram of a conductor structure for improving crosstalk involved in an embodiment of the present application;
[0038] Figure 7 This application embodiment involves Figure 6 A cross-sectional view of the three-dimensional structure shown.
[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings.
[0040] Description of Figure Numbers:
[0041] 10. Grid array package pad; 11. First via; 12. Fine line structure; 13. Mutual capacitance module between pads; 20. Second via; 30. Third via; 40. Coupling plane structure; 401. Transmission line; 402. Coupling plane layer; 50. Fourth via. DETAILED DESCRIPTION
[0042] The present application embodiment provides a conductor structure for improving crosstalk, referring to Figure 1 As shown, Figure 1 It is a flow chart of the first embodiment of the conductor structure for improving crosstalk of the present application.
[0043] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.
[0044] With the rapid development of semiconductor technology, high-speed signal transmission has become an indispensable key link in modern electronic systems. However, with the sharp increase in signal rate, the loss and reflection problems in the signal path have become increasingly prominent, among which the crosstalk problem is particularly serious, becoming the main bottleneck restricting the further increase of signal rate. Especially in the LGA (Land Grid Array, grid array packaging) structure, the close layout between pads and vias makes the crosstalk phenomenon particularly significant, posing a severe challenge to signal integrity and system performance.
[0045] Traditionally, in order to alleviate the crosstalk problem between adjacent signals, engineers often adopt the strategy of increasing the LGA pad spacing or introducing ground pads as isolation barriers. However, in today's era of pursuing high integration and miniaturization of devices, these methods are particularly limited. On the one hand, the expansion of the pad spacing directly leads to an increase in the package size, which runs counter to the goal of pursuing miniaturization of package size; on the other hand, for parallel interfaces such as DDR (Double Data Rate), due to the large number of signal lines and dense arrangement, it is almost impossible to configure a separate ground pad for each signal pad in a limited space for isolation, which greatly limits the flexibility and feasibility of the design.
[0046] Therefore, in order to solve the technical problem that the crosstalk between LGA (Land Grid Array) pads and vias in the current semiconductor packaging technology is serious and difficult to effectively suppress while keeping the package size unchanged, the present application provides a conductor structure, a semiconductor packaging structure and a circuit board for improving crosstalk.
[0047] Please refer to Figure 2 , Figure 2 It is a schematic diagram of the structure involved in the first embodiment of the conductor structure for improving crosstalk of the present application. The conductor structure for improving crosstalk provided in the present application includes a plurality of grid array package pads 10 arranged side by side; each of the grid array package pads 10 is provided with at least a first via 11, a fine wire structure 12 and a mutual capacitance module 13 between pads, the first via 11 is connected to the via side of the mutual capacitance module 13 between pads through the fine wire structure 12, and the mutual capacitance module 13 between pads is provided directly above the adjacent grid array package pads 10 to form a capacitor structure; wherein the adjacent grid array package pads 10 are the next grid array package pads 10 of each grid array package pad 10.
[0048] It should be noted that crosstalk is the transmission of harmful signals from one wire network to another wire network. Transmission line crosstalk is divided into near-end crosstalk and far-end crosstalk. Figure 1 , Figure 1 Figure 1 is a schematic diagram of a pair of coupled striplines, showing the fringe fields between the signal and return paths and the interaction between the two when another line network is in close proximity.
[0049]
[0050] Formula (1) is the function of far-end crosstalk for coupled transmission lines, where Len represents the length of the coupling region between the two lines, RT represents the signal rising edge, v represents the signal propagation speed on the line, and C M represents mutual capacitance per unit length, C L Represents the capacitance per unit length on the signal path, L M Represents mutual inductance per unit length, L L represents the inductance per unit length on the signal path, V0 represents the input voltage value, V FEXT It can be understood as the far-end crosstalk of coupled transmission lines. In packages or printed circuit boards, vertical communication is usually achieved through laser holes 11 / 20 / 30 / 60 or mechanical holes. Self-capacitance and mutual inductance are dominant in these vertical communication paths. is a negative number, V FEXT It is a negative value. In a package or printed circuit board, it is difficult to reduce the self-capacitance and mutual inductance in the communication circuit, and it is often necessary to add additional communication space. Therefore, the far-end crosstalk can be reduced by increasing the mutual capacitance and self-inductance between signals.
[0051] In this embodiment, the present application achieves the purpose of reducing signal crosstalk without adding additional wiring space by providing a pad mutual capacitance module 13 on each grid array package pad 10. Specifically, the present application extends the pad mutual capacitance module 13 added in each grid array package pad 10 to the top of the adjacent grid array package pad 10 to form a capacitor structure, thereby increasing the signal mutual capacitance between adjacent LGA pads, thereby making the unit length mutual capacitance C M The signal self-inductance effect of each grid array package pad 10 is increased by adding a fine wire structure 12 in each grid array package pad 10, and connecting the corresponding first via 11 and the via side of the pad mutual capacitance module 13 on each grid array package pad 10 through the fine wire structure 12, so as to increase the signal self-inductance effect of each grid array package pad 10 so that the self-inductance L on the signal path involved in each grid array package pad 10 L Increase; combined with formula (1), we can know Increasing the mutual capacitance C M And the self-inductance L in the signal path L After that, The difference decreases, so V FEXT The value of is reduced, thereby achieving the purpose of reducing signal crosstalk.
[0052] In addition, it should be noted that a plurality of grid array package pads 10 can be used Figure 2 The grid array package pad 10-1, the grid array package pad 10-2 and the grid array package pad 10-3 are shown, wherein the grid array package pad 10-1 is provided with a first via 11-1, a fine line structure 12-1 and a mutual capacitance module 13-1 between pads; the grid array package pad 10-2 is provided with a first via 11-2, a fine line structure 12-2 and a mutual capacitance module 13-2 between pads; the grid array package pad 10-3 is provided with a first via 11-3, a fine line structure 12-3 and a mutual capacitance module 13-3 between pads.
[0053] The thickness of the fine-wire structure 12 provided in the present application can be customized according to application requirements, and the thinner the fine-wire structure 12 provided on each grid array package pad 10 , the better the signal self-inductance effect on the grid array package pad 10 .
[0054] In summary, the present application provides a conductor structure, a semiconductor packaging structure and a circuit board for improving crosstalk, so that the signal crosstalk between adjacent LGA (Land Grid Array, grid array package) pads can be effectively suppressed without increasing the package size. Specifically, the present application adds a fine wire structure 12 and a mutual capacitance module between pads on each grid array package pad 10, and connects the first via 11 set on each grid array package pad 10 to the via side of the mutual capacitance module 13 between pads through the fine wire structure 12, so that each grid array package pad 10 can generate a stronger signal self-inductance effect to weaken the influence of signal crosstalk between adjacent LGA pads. At the same time, by extending the additional mutual capacitance module 13 between pads to form a capacitor structure directly above the adjacent grid array package pad 10 to increase the equivalent capacitance of the signal between adjacent LGA pads, it is possible to achieve effective coupling mutual capacitance between the signals between adjacent LGA pads without adding additional wiring space, thereby further suppressing the signal crosstalk between adjacent LGA pads.
[0055] Further, based on the first embodiment of the conductor structure for improving crosstalk of the present application, a second embodiment of the conductor structure for improving crosstalk of the present application is proposed. Figure 3 , Figure 3 It is a three-dimensional structural diagram of a conductor structure for improving crosstalk involved in the embodiment of the present application. The pad-to-pad mutual capacitance module 13 includes a coupling plane structure 40, a second via 20 and a third via 30; the third via 30 is arranged on the grid array package pad 10, and is used to connect the pad solder foot of the grid array package pad 10; the third via 30 is connected to the second via 20 on the side away from the grid array package pad 10, and the coupling plane structure 40 is arranged between the connected second via 20 and the third via 30, and the coupling plane structure 40 is arranged directly above the adjacent grid array package pad 10 to form the capacitor structure; wherein the side of the second via 20 away from the coupling plane structure 40 constitutes the via side of the pad-to-pad mutual capacitance module 13.
[0056] In this embodiment, refer to Figure 3In the present application, each LGA package pad 10 is provided with an integrated coupling plane structure 40, a second via 20 and a third via 30, thereby realizing efficient mutual capacitance of signals between adjacent LGA pads. Specifically, the present application provides the third via 30 on the LGA package pad 10, which can then connect the pad solder feet of the LGA package pad 10, ensuring the accuracy of signal transmission, and at the same time, through the connection between the third via 30 and the second via 20, a low-impedance interconnection path is constructed. At the same time, a coupling plane structure 40 is set between the connected second via 20 and the third via 30, that is, a transmission line 401 connecting the coupling plane layer 402 in the coupling plane structure 40 is set between the connected second via 20 and the third via 30, and the coupling plane layer 402 connected by the transmission line 401 is covered directly above the adjacent grid array package pad 10 to form a compact capacitor structure, thereby achieving efficient mutual capacitance of signals between adjacent LGA pads and effectively reducing signal crosstalk between adjacent LGA pads; in addition, the present application uses the side of the second via 20 away from the connected transmission line 401 as the via side of the mutual capacitance module 13 between pads, and connects the first via 11 through the fine wire structure 12, thereby enhancing the signal self-inductance effect to weaken the influence of signal crosstalk between adjacent LGA pads.
[0057] It should be noted that this application sets Figure 3 Only one case is shown in which each grid array package pad 10 is provided with a coupling plane structure 40 directly above an adjacent grid array package pad 10, that is, Figure 3 Only the case where a coupling plane structure 40 is added above another signal (the signal of each grid array package pad 10) is shown, but the coupling plane structure 40 is set on each other's grid array package pad 10 of two adjacent signals at the same time. The above is only a feasible implementation method of the present application, and the present application does not impose any limitation on this.
[0058] The first via hole 11, the second via hole 20 and the third via hole 30 provided in the present application may be laser holes or mechanical holes. The above is only a feasible implementation method of the present application, and the present application does not make any limitation here.
[0059] Exemplarily, taking the grid array package pad 10-1 and the grid array package pad 10-2 as examples, the present application provides a coupling plane structure 40 and a transmission line 40 connecting the coupling plane structure on the upper signal layer of the grid array package pad 10-1 (i.e., the integrated circuit layer where the connection node where the second via 20 and the third via 30 are connected is located, also referred to as the third integrated circuit layer). Figure 3The coupling plane structure 40 shown is a circular pad, and the transmission line 40 connected to the coupling plane structure is a normal transmission line routing, and the coupling plane structure is arranged directly above the adjacent grid array package pad 10-2, and forms a capacitor structure with the grid array package pad 10-2, which is used to increase the efficient mutual capacitance of signals between adjacent LGA pads. In addition, the fine wire structure 12 set on each grid array package pad 10 of the present application can be understood as a layer of winding on the third integrated circuit layer, which is used to increase the signal self-inductance on each grid array package pad 10.
[0060] In addition, please refer to Figures 4 to 5 , Figure 4 This application embodiment involves Figure 3 A top view of the three-dimensional structure shown, Figure 5 This application embodiment involves Figure 3 A cross-sectional view of the three-dimensional structure shown. Figure 4 The relative positions of the thin-line structure 12 and the coupling plane structure 40 shown can be adjusted arbitrarily, but the thin-line structure 12 is preferably located in the integrated circuit layer close to or near the grid array package pad 10. In addition, the size and shape of the coupling plane layer provided in the present application can be adjusted according to application requirements, and the coupling plane layer provided for each grid array package pad 10 must be provided directly above the adjacent grid array package pad 10.
[0061] In summary, the present application adds a coupling plane structure 40 to the upper signal layer of each grid array package pad 10, and sets the coupling plane structure 40 directly above the adjacent grid array package pad 10 to couple with the adjacent grid array package pad 10, thereby increasing the signal mutual capacitance between adjacent LGA pads; at the same time, a thin wire structure 12 is added above the coupling plane structure 40 added to each grid array package pad 10 to increase the signal self-inductance on each grid array package pad 10, thereby reducing V FEXT value, thereby reducing the crosstalk between adjacent signals.
[0062] Further, based on the first embodiment of the conductor structure for improving crosstalk of the present application, a third embodiment of the conductor structure for improving crosstalk of the present application is proposed. Figure 6 to Figure 7 , Figure 6 is another three-dimensional structural diagram of a conductor structure for improving crosstalk involved in an embodiment of the present application, Figure 7 This application embodiment involves Figure 6The cross-sectional view of the three-dimensional structure shown. The pad mutual capacitance module 13 includes a coupling plane structure 40, a second via 20, a third via 30 and a fourth via 50; the third via 30 and the fourth via 50 are arranged on the grid array package pad 10 at a preset interval, and are used to connect the pad solder feet of the grid array package pad 10; the coupling plane structure 40 is arranged on the side of the third via 30 away from the pad solder feet, and the coupling plane structure 40 is arranged directly above the adjacent grid array package pad 10 to form the capacitor structure; the second via 20 is arranged above the fourth via 50, and the side of the second via 20 that is not connected to the third via 30 constitutes the via side of the pad mutual capacitance module 13.
[0063] In this embodiment, the pad mutual capacitance module 13 provided in the present application realizes effective suppression of crosstalk between adjacent LGA pads by integrating the coupling plane structure 40, the second via 20, the third via 30 and the fourth via 50. Specifically, the third via 30 and the fourth via 50 provided in the present application are arranged on the pad at a preset interval, and while ensuring stable signal transmission, the coupling plane structure 40 provided on the side of the third via 30 away from the pad foot is provided directly above the adjacent grid array package pad 10. For example, the side of the third via 30 away from the pad foot is connected to the transmission line 401 in the coupling plane structure 40, and the coupling plane layer 402 connected to the transmission line 401 in the coupling plane structure 40 forms a compact capacitance structure with the adjacent grid array package pad 10, which significantly enhances the mutual capacitance effect between adjacent LGA pads and effectively reduces the signal crosstalk between adjacent LGA pads. In addition, the vertical connection design between the fourth via 50 and the second via 20, that is, the second via 20 is connected to the land grid array package pad 10 through the fourth via 50, which provides a low-impedance transmission path for the signal. At the same time, the via side of the second via 20 that is not connected to the fourth via 50, which constitutes the pad mutual capacitance module 13, is connected to the first via 11 through the fine wire structure 12, thereby increasing the self-inductance effect of the signal on the land grid array package pad 10, and further achieving the purpose of reducing the crosstalk between signals of adjacent LGA pads.
[0064] It should be noted that, refer to Figure 6 The fourth via hole 50 additionally provided in the present application is arranged at the integrated circuit layer where the grid array package pad 10 is located, and the transmission line 401 connected to the coupling plane layer 402 arranged on the upper signal layer of the grid array package pad 10 is connected through the third via hole 30 arranged on the same integrated circuit layer as the fourth via hole 50, thereby forming Figure 6 The hole structure shown connects the grid array package pad 10 and the coupling plane structure 40, thereby effectively shortening the signal path of the grid array package pad 10 and reducing the loss and delay in the signal transmission process.
[0065] Further, based on the first embodiment, the second embodiment or the third embodiment of the conductor structure for improving crosstalk of the present application, a fourth embodiment of the conductor structure for improving crosstalk of the present application is presented. Figure 4 , the coupling plane structure 40 includes a coupling plane layer 402 and a transmission line 401 connected to the coupling plane layer 402; in each of the grid array package pads 10, the extended side of the transmission line 401 is connected to the coupling plane layer 402, and the coupling plane layer 402 is arranged directly above the adjacent grid array package pads 10; the connection side of the transmission line 401 is arranged between the connected second via 20 and the third via 30; or, the connection side of the transmission line 401 is arranged on a side of the third via 30 away from the pad foot, and the connection side is the opposite side of the extended side.
[0066] In this embodiment, the present application integrates a coupling plane structure 40 with a transmission line 401 and a coupling plane layer 402, which optimizes the electromagnetic environment between adjacent LGA pads. Specifically, the extended side of the transmission line 401 set in each grid array package pad 10 is closely connected to the coupling plane layer 402, and the coupling plane layer 402 is set directly above the adjacent grid array package pad 10, which effectively reduces the crosstalk and noise between adjacent LGA pads. At the same time, the connection side of the transmission line 401 can be flexibly configured, such as Figure 3 as well as Figure 5 As shown, the second via hole 20 and the third via hole 30 are connected to each other to construct a vertical and horizontal signal transmission path; Figures 6 to 7 As shown, it is directly arranged on a side of the third via hole 30 away from the pad foot to simplify the signal flow.
[0067] Exemplarily, in another embodiment, referring to Figure 3 as well as Figure 5 As shown, the connection side of the transmission line 401 is located between the connected second via 20 and the third via 30, allowing the signal to be vertically transmitted to the transmission line 401 through the via, and then horizontally transmitted to the coupling plane layer 402 through the transmission line 401, which helps to achieve flexible signal routing while maintaining the compactness of the package.
[0068] In another embodiment, referring to Figures 6 to 7 As shown, the connection side of the transmission line 401 is directly arranged on the side of the third via 30 away from the pad solder foot, which can simplify the signal path, so that the signal can be directly transmitted from the pad to the coupling plane layer 402 through the transmission line 401 connected to the third via 30. This method reduces the intermediate links in signal transmission, helps to reduce signal loss and improve transmission efficiency.
[0069] Furthermore, in other feasible embodiments, the aperture of the first via 11, the aperture of the second via 20, and the aperture of the third via 30 in each grid array package pad 10 are all made of the same conductive material as the coupling plane structure 40; and the conductive properties of the conductive material are the same as the conductive properties of the pad foot.
[0070] In this embodiment, in each grid array package pad 10, by making the first via 11, the second via 20, the third via 30 and the aperture of the third via 30 all the same conductive material as the coupling plane structure 40, a seamless connection between the aperture and the surrounding conductive structure is achieved, which not only maintains the same conductive properties as the pad solder foot, but also ensures smooth transmission of signals in the vias and the third via 30, reducing signal loss and interference.
[0071] It should be noted that the aperture of the fourth via hole 50 is also made of the same conductive material as the coupling plane structure 40 , and the conductive material may be copper metal or other conductive metals.
[0072] Furthermore, in some feasible embodiments, each of the grid array package pads 10 is also provided with a first integrated circuit layer, a second integrated circuit layer, a third integrated circuit layer and a fourth integrated circuit layer arranged in parallel with each other; the first via 11 is provided between the first integrated circuit layer and the second integrated circuit layer to form a hole structure connecting the first integrated circuit layer and the second integrated circuit layer; the second via 20 is provided between the second integrated circuit layer and the third integrated circuit layer to form a hole structure connecting the second integrated circuit layer and the third integrated circuit layer; the third via 30 is provided between the third integrated circuit layer and the fourth integrated circuit layer to form a hole structure connecting the third integrated circuit layer and the fourth integrated circuit layer.
[0073] In this embodiment, by setting the first integrated circuit layer, the second integrated circuit layer, the third integrated circuit layer and the fourth integrated circuit layer arranged in parallel with each other in each grid array package pad 10, and setting the first via 11 between the first integrated circuit layer and the second integrated circuit layer, setting the second via 20 between the second integrated circuit layer and the third integrated circuit layer, and setting the third via 30 between the third integrated circuit layer and the fourth integrated circuit layer, an efficient connection channel between the multiple layers is formed. This multi-level, three-dimensional structural design not only optimizes the signal transmission path, reduces signal delay and loss, but also enhances the overall integration and functional diversity of the circuit board. At the same time, the setting of each via ensures the electrical interconnection between different integrated circuit layers, so that the signal can be smoothly transmitted between the layers, thereby improving the electrical performance and signal integrity of the entire grid array package pad 10.
[0074] Furthermore, in other feasible embodiments, the conductive properties of the first integrated circuit layer, the conductive properties of the second integrated circuit layer, the conductive properties of the third integrated circuit layer, and the conductive properties of the fourth integrated circuit layer are all the same as the conductive properties of the pad foot.
[0075] In this embodiment, by ensuring that the conductive properties of the first, second, third and fourth integrated circuit layers are the same as the conductive properties of the pad solder feet, the consistency of the conductive performance inside the entire grid array package pad 10 is achieved, eliminating signal transmission obstacles and electrical mismatch problems that may be caused by differences in conductivity between different layers, and further improving signal integrity and reliability.
[0076] Further, in some feasible embodiments, the side of the first via 11 that is not connected to the fine-wire structure 12 is arranged on the first integrated circuit layer; the side of the first via 11 connected to the fine-wire structure 12 and the side of the second via 20 connected to the fine-wire structure 12 are both arranged on the second integrated circuit layer, and the fourth integrated circuit layer is printed on the grid array package pad 10; the side of the second via 20 connected to the third via 30, the side of the third via 30 connected to the second via 20, the coupling plane structure 40 and the side of the third via 30 connected to the coupling plane structure 40 are all arranged on the third integrated circuit layer, and the side of the third via 30 connected to the pad foot is arranged on the fourth integrated circuit layer.
[0077] It should be noted that the side of the fourth via 50 connected to the coupling planar structure 40 is also arranged on the third integrated circuit layer, and the side of the fourth via 50 connected to the pad foot is also arranged on the fourth integrated circuit layer.
[0078] In this embodiment, the present application realizes a complex and orderly electrical connection network inside the grid array package pad 10 by carefully planning the connection structure and layout between each layer. The arrangement of the first via 11, the second via 20, and the third via 30 between different integrated circuit layers ensures that the signal can be efficiently transmitted between the integrated circuit layers, while avoiding unnecessary crossing with the fine line structure 12, reducing signal interference. The arrangement of the coupling plane structure 40 in the third integrated circuit layer provides a stable reference plane for the signal, further improving the signal integrity. The third via 30 is arranged to connect the third integrated circuit layer and the fourth integrated circuit layer, realizing the direct connection of the pad solder foot with the coupling plane layer 402 through the transmission line 401 connected to the coupling plane layer 402, thereby simplifying the signal path.
[0079] In summary, the present application provides a conductor structure, a semiconductor packaging structure and a circuit board for improving crosstalk, so that the signal crosstalk between adjacent LGA (Land Grid Array, grid array package) pads can be effectively suppressed without increasing the package size. Specifically, the present application adds a fine wire structure 12 and a mutual capacitance module between pads on each grid array package pad 10, and connects the first via 11 set on each grid array package pad 10 to the via side of the mutual capacitance module 13 between pads through the fine wire structure 12, so that each grid array package pad 10 can generate a stronger signal self-inductance effect to weaken the influence of signal crosstalk between adjacent LGA pads. At the same time, by extending the additional mutual capacitance module 13 between pads to form a capacitor structure directly above the adjacent grid array package pad 10 to increase the equivalent capacitance of the signal between adjacent LGA pads, it is possible to achieve effective coupling mutual capacitance between the signals between adjacent LGA pads without adding additional wiring space, thereby further suppressing the signal crosstalk between adjacent LGA pads.
[0080] In addition, to achieve the above-mentioned purpose, the present application also provides a semiconductor packaging structure, which includes a substrate, and the substrate is provided with a conductor, and the conductor is configured as a conductor structure for improving crosstalk as described in any one of the above items.
[0081] In addition, to achieve the above-mentioned purpose, the present application also provides a circuit board, characterized in that the circuit board includes a substrate, the substrate is provided with a conductor, and the conductor is configured as any of the above-mentioned conductor structures for improving crosstalk.
[0082] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.
[0083] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0084] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a computer-readable circuit board (such as ROM / RAM, disk, optical disk) as described above, and includes a number of instructions for a semiconductor package structure (which can be a mobile phone, computer, server, or network semiconductor package structure, etc.) to execute the methods described in each embodiment of the present application.
[0085] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A conductor structure for improving crosstalk, characterized in that: The conductor structure for improving crosstalk includes a plurality of grid array package pads arranged side by side; Each of the grid array package pads is provided with at least a first via, a fine line structure and a mutual capacitance module between pads, the first via is connected to the via side of the mutual capacitance module between pads through the fine line structure, and the mutual capacitance module between pads is arranged directly above the adjacent grid array package pads to form a capacitor structure; wherein, The adjacent grid array package pad is the next grid array package pad of each of the grid array package pads.
2. The conductor structure for improving crosstalk according to claim 1, characterized in that: The pad-to-pad mutual capacitance module includes a coupling plane structure, a second via hole and a third via hole; The third via hole is provided on the grid array package pad and is used to connect the pad foot of the grid array package pad; The third via hole is connected to the second via hole at a side away from the grid array package pad, and the coupling plane structure is arranged between the connected second via hole and the third via hole, and the coupling plane structure is arranged directly above the adjacent grid array package pad to form the capacitor structure; wherein, A side of the second via hole away from the coupling plane structure constitutes a via hole side of the mutual capacitance module between pads.
3. The conductor structure for improving crosstalk according to claim 1, characterized in that: The pad mutual capacitance module includes a coupling plane structure, a second via hole, a third via hole and a fourth via hole; The third via hole and the fourth via hole are arranged on the grid array package pad at a preset interval, and are used to connect the pad feet of the grid array package pad; The coupling plane structure is arranged on a side of the third via away from the pad solder foot, and the coupling plane structure is arranged directly above the adjacent grid array package pad to form the capacitor structure; the second via is arranged above the fourth via, and a side of the second via that is not connected to the fourth via constitutes a via side of the mutual capacitance module between pads.
4. The conductor structure for improving crosstalk according to any one of claims 2 to 3, characterized in that: The coupling plane structure includes a coupling plane layer, and a transmission line connecting the coupling plane layer; In each of the grid array package pads, the extended side of the transmission line is connected to the coupling plane layer, and the coupling plane layer is arranged directly above the adjacent grid array package pad; The connection side of the transmission line is arranged between the connected second via hole and the third via hole; or, the connection side of the transmission line is arranged on a side of the third via hole away from the pad foot, and the connection side is the opposite side of the transmission line.
5. The conductor structure for improving crosstalk according to any one of claims 2 to 3, characterized in that: The aperture of the first via hole, the aperture of the second via hole and the aperture of the third via hole in each grid array package pad are all made of the same conductive material as the coupling plane structure; The conductive property of the conductive material is the same as the conductive property of the pad foot.
6. The conductor structure for improving crosstalk according to claim 5, characterized in that: Each of the grid array package pads is also provided with a first integrated circuit layer, a second integrated circuit layer, a third integrated circuit layer and a fourth integrated circuit layer arranged in parallel with each other; The first via is disposed between the first integrated circuit layer and the second integrated circuit layer to form a hole structure connecting the first integrated circuit layer and the second integrated circuit layer; The second via is disposed between the second integrated circuit layer and the third integrated circuit layer to form a hole structure connecting the second integrated circuit layer and the third integrated circuit layer; The third via is disposed between the third integrated circuit layer and the fourth integrated circuit layer to form a hole structure connecting the third integrated circuit layer and the fourth integrated circuit layer.
7. The conductor structure for improving crosstalk according to claim 6, characterized in that: The conductive properties of the first integrated circuit layer, the conductive properties of the second integrated circuit layer, the conductive properties of the third integrated circuit layer, and the conductive properties of the fourth integrated circuit layer are all the same as the conductive properties of the pad foot.
8. The conductor structure for improving crosstalk according to claim 6, characterized in that: The side of the first via not connected to the fine wire structure is arranged on the first integrated circuit layer; the side of the first via connected to the fine wire structure and the side of the second via connected to the fine wire structure are both arranged on the second integrated circuit layer, and the fourth integrated circuit layer is printed on the grid array package pad; The second via is connected to one side of the third via, the third via is connected to one side of the second via, the coupling plane structure and the side of the third via connected to the coupling plane structure are all arranged on the third integrated circuit layer, and the side of the third via connected to the pad foot is arranged on the fourth integrated circuit layer.
9. A semiconductor packaging structure, characterized in that: The semiconductor package structure includes a substrate, wherein the substrate is provided with a conductor, and the conductor is provided as the conductor structure for improving crosstalk according to any one of claims 1 to 8.
10. A circuit board, characterized in that: The circuit board includes a substrate, the substrate is provided with a conductor, and the conductor is configured as a conductor structure for improving crosstalk according to any one of claims 1 to 8.