Manufacturing method of three-dimensional memory and three-dimensional memory

Abstract

The invention discloses a manufacturing method of a three-dimensional memory and the three-dimensional memory, relates to the technical field of semiconductor manufacturing, and aims to solve the problem of relatively high thermal budget of a single-crystal semiconductor channel formed in the prior art. The manufacturing method of the three-dimensional memory comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a laminated structure, a semiconductor active layer and an inter-electrode dielectric layer; a through hole is formed in the laminated structure, and the bottom of the through hole is filled with the semiconductor active layer; forming a cylindrical induction structure and a semiconductor structure on the side wall of the through hole; the induction structure and the semiconductor structure are sequentially arranged on the semiconductor active layer along the thickness direction of the substrate; filling a second type of dielectric isolation layer in the through hole; performing induced annealing on the semiconductor structure and the induction structure to crystallize and modify the semiconductor structure into a single-crystal semiconductor layer; after induced annealing, the induction structure is located at the top of the single-crystal semiconductor layer. The manufacturing method of the three-dimensional memory provided by the invention is used for forming the single-crystal semiconductor channel with lower thermal budget.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a manufacturing method of a three-dimensional memory and a three-dimensional memory. Background Art

[0002] With the development of science and technology, traditional two-dimensional memory cannot meet the storage speed and density requirements, so three-dimensional memory is designed and developed. In order to improve the density and speed of three-dimensional memory, it is necessary to increase the number of stacked layers of its storage unit, so that the vertical channel in the three-dimensional memory becomes longer, and then the resistance increases and the current decreases. In addition, the vertical semiconductor channel resistance of the traditional non-single crystal phase is large, which further reduces the on-current, and its grain boundaries cause random telegraph noise fluctuations and carrier mobility to decrease, causing read or write errors. Although the error correction code algorithm can reduce the impact of errors, the error correction circuit occupies a large area, which will reduce the storage density of the three-dimensional memory, so the three-dimensional memory of the single crystal semiconductor channel has become an inevitable choice.

[0003] However, in the prior art, the semiconductor channel of the non-single-crystal phase is usually converted into a single-crystal semiconductor channel by heating and melting the semiconductor channel of the non-single-crystal phase and then cooling it to form a single-crystal semiconductor channel. This method places high demands on the thermal budget of the entire three-dimensional memory. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a three-dimensional memory and a three-dimensional memory, which is used to provide a method for manufacturing a single crystal semiconductor channel with a lower thermal budget in a three-dimensional memory.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a method for manufacturing a three-dimensional memory, which method comprises: providing a substrate, the substrate comprising a substrate, a laminated structure, a semiconductor active layer and an inter-electrode dielectric layer. The laminated structure is arranged on the substrate. The laminated structure comprises a first-class dielectric isolation layer and a sacrificial layer which are arranged alternately in sequence along the thickness direction of the substrate. In the laminated structure, the film layers located at the bottom layer and the top layer are both first-class dielectric isolation layers. A through hole is provided in the laminated structure, and the semiconductor active layer is filled at the bottom of the through hole. The inter-electrode dielectric layer is arranged on the semiconductor active layer and covers the side wall surface of the through hole.

[0006] Next, a cylindrical inductive structure and a semiconductor structure are formed on the sidewall of the through hole. The inductive structure and the semiconductor structure are sequentially arranged on the semiconductor active layer along the thickness direction of the substrate. The projection of the semiconductor structure on the semiconductor active layer covers the projection of the inductive structure on the semiconductor active layer. The material of the inductive structure is a compound of the semiconductor and the metal in the semiconductor active layer. The crystal phase of the material of the semiconductor structure is a non-single crystal phase.

[0007] Next, a second type dielectric isolation layer is filled in the through hole, and one end of the second type dielectric isolation layer away from the bottom of the through hole is flush with the stacked structure.

[0008] Next, the semiconductor structure and the induced structure are subjected to an induction annealing treatment to crystallize the semiconductor structure and transform it into a single crystal semiconductor layer. After the induction annealing treatment, the induced structure is located on top of the single crystal semiconductor layer.

[0009] In the case of adopting the above scheme, in the manufacturing method provided by the present invention, the stacked structure includes at least two first-class dielectric isolation layers and at least one sacrificial layer. In the through hole of the stacked structure, a cylindrical induction structure and a semiconductor structure are sequentially formed on the side wall of the through hole along the thickness direction of the substrate, and the top of the semiconductor structure is flush with the top of the inter-electrode dielectric layer. The induction structure can crystallize and induce the semiconductor structure of the non-single-crystal phase to be a single-crystal semiconductor layer during the induction annealing process, that is, a single-crystal channel is formed on the side wall of the through hole. Moreover, after the induction annealing treatment, the cylindrical induction structure is located on the top of the cylindrical single-crystal semiconductor layer, and the cylindrical single-crystal semiconductor layer is located on the cylindrical semiconductor active layer, and the two exchange positions, that is, the induction structure crystallizes and modifies all semiconductor structures of the non-single-crystal phase, and the crystallization modification of this process is complete and sufficient, and there will be no residual polycrystalline components, so that the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the present invention has all the advantages of using a single-crystal channel. Moreover, under the induced catalysis of the induced structure, it is helpful to reduce the temperature of crystallization modification and shorten the time of crystallization modification. The thermal budget of the present invention is greatly reduced compared with the solution used in the prior art of heating the channel to melt and then cooling to crystallize and modify the polycrystalline channel into a single crystal channel. The structure of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the present invention is less affected, and the three-dimensional memory manufactured by the present invention can have better performance.

[0010] Furthermore, the projection of the semiconductor structure on the semiconductor active layer covers the projection of the induced structure on the semiconductor active layer, that is, the ring width of the semiconductor structure along the cross section parallel to the substrate direction is greater than or equal to the ring width of the induced structure along the cross section parallel to the substrate direction. In this case, it can be ensured that after the induced annealing treatment, no induced structure will remain under the single crystal semiconductor layer and / or between the single crystal semiconductor layer and the second type of dielectric isolation layer, and the induced structure is located at the top of the single crystal semiconductor layer, that is, the top of the through hole, and is no longer wrapped by the structure of the three-dimensional memory.

[0011] As a possible implementation, the annealing temperature of the induced annealing treatment is greater than or equal to 450° C. and less than or equal to 600° C. In this way, the semiconductor structure and the induced structure are subjected to the induced annealing treatment at this temperature, which can avoid the three-dimensional memory manufactured by the present invention from accumulating too much internal stress, causing warping or cracking due to the annealing temperature being too high, and the thermal budget requirement is low.

[0012] As a possible implementation scheme, the annealing time of the induced annealing treatment is greater than or equal to 0.5 hours and less than or equal to 30 hours. In this case, the semiconductor structure and the induced structure are subjected to the induced annealing treatment within this time range, which can avoid the incomplete crystallization modification of the semiconductor structure due to too short an annealing time, and can also avoid the three-dimensional memory manufactured by the present invention from accumulating too much internal stress, warping or generating cracks due to too long an annealing time, thereby ensuring better performance and higher yield of the three-dimensional memory.

[0013] As a possible implementation scheme, the annealing temperature of the induced annealing treatment is greater than or equal to 900° C. and less than or equal to 1200° C., and the annealing time of the induced annealing treatment is greater than or equal to 2s and less than or equal to 20s. In this case, the semiconductor structure and the induced structure are induced to anneal at a higher temperature and in a shorter time to achieve the crystallization modification of the induced semiconductor structure. On the premise that the semiconductor structure is fully crystallized and modified into a single crystal semiconductor layer, the thermal budget is low.

[0014] As a possible implementation scheme, a cylindrical inductive structure and a semiconductor structure are formed on the side wall of a through hole, including: first, forming an inductive metal layer on a laminated structure, on the side wall of the through hole and at the bottom of the through hole. Next, removing the inductive metal layer on the laminated structure and the inductive metal layer at the bottom of the through hole, and retaining the inductive metal layer on the side wall of the through hole. Next, performing a reaction annealing treatment on the remaining inductive metal layer and the semiconductor active layer, so that the remaining inductive metal layer in contact with the semiconductor active layer is converted into an inductive structure. Next, removing the inductive metal layer that has not been converted into an inductive structure. Next, forming a semiconductor structure on the laminated structure, on the side wall of the through hole and at the bottom of the through hole. Next, removing the semiconductor structure on the laminated structure and the semiconductor structure at the bottom of the through hole, and retaining the semiconductor structure on the side wall of the through hole. In this case, the cylindrical inductive structure is formed first, and then the cylindrical semiconductor structure is formed, and there is no need to etch the inductive structure whose material is a compound of semiconductor and metal, thereby avoiding the need to etch the compound of semiconductor and metal that is difficult to etch, thereby improving the manufacturing speed of the manufacturing method provided by the present invention and improving the yield.

[0015] As a possible implementation scheme, a cylindrical inductive structure and a semiconductor structure are formed on the side wall of a through hole, including: first, forming an inductive metal layer on the laminated structure, on the side wall of the through hole and at the bottom of the through hole. Next, the inductive metal layer and the semiconductor active layer are subjected to reaction annealing treatment to convert the portion of the inductive metal layer in contact with the semiconductor active layer into an inductive structure. Next, the inductive metal layer that has not been converted into an inductive structure is removed. Next, a semiconductor structure is formed on the laminated structure, on the side wall of the through hole and at the bottom of the through hole. Next, the semiconductor structure located on the laminated structure and the semiconductor structure located on the bottom of the through hole are removed, and only the semiconductor structure located on the side wall of the through hole is retained; the inductive metal layer located on the bottom of the through hole is removed, and the inductive metal layer located on the side wall of the through hole is retained. In this case, a thin sheet-shaped inductive structure is first formed on the semiconductor active layer at the bottom of the through hole and then a semiconductor structure is formed, and then the inductive structure and the semiconductor structure are patterned. The two patternings can share a mask, which can reduce the cost of the manufacturing method provided by the present invention.

[0016] As a possible implementation scheme, the annealing temperature of the reaction annealing treatment is greater than or equal to 180°C and less than or equal to 300°C. In this case, the reaction annealing treatment of the induced metal layer within this temperature range can ensure that the induced metal layer effectively reacts with the semiconductor active layer to form a semiconductor and metal compound, avoiding the situation where the induced metal layer and the semiconductor active layer cannot effectively react due to too low a temperature, thereby ensuring the effect of subsequent induced crystallization modification. It can also prevent the influence of other structures due to excessively high temperature, causing the accumulation of internal stress in other structures, which may cause damage to other structures.

[0017] As a possible implementation scheme, the annealing time of the reaction annealing treatment is greater than or equal to 15 s and less than or equal to 300 s.

[0018] In this way, the induced metal layer is subjected to reaction annealing within this time range, which can ensure that the induced metal layer effectively reacts with the semiconductor active layer to form a semiconductor-metal compound, and avoids the situation where the non-induced metal layer and the semiconductor active layer cannot effectively react due to too short a time, thereby ensuring the effect of subsequent induced crystallization modification. It can also prevent the thermal budget from increasing due to too long a time, thereby affecting other structures.

[0019] As a possible implementation scheme, the thickness of the induced metal layer is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, it is possible to avoid problems such as the induced metal layer not reacting effectively with the semiconductor active layer due to the induced metal layer being too thin, the height of the formed induced structure along the thickness direction of the laminated structure and the height perpendicular to the thickness direction of the laminated structure being uneven, and the height of the formed induced structure along the thickness direction of the laminated structure and the height perpendicular to the thickness direction of the laminated structure being too low, thereby ensuring that the subsequent induced annealing treatment is carried out effectively. It is also possible to avoid the excessive material cost and time cost of forming the induced metal layer due to the induced metal layer being too thick, which is beneficial to controlling costs and improving yields. In addition, an overly thick induced metal layer may crack due to stress and damage the three-dimensional memory. The thickness of the induced metal layer within the aforementioned range can also improve yields and reduce costs.

[0020] As a possible implementation scheme, a wet etching process or a dry etching process is used to remove the inductive metal layer that has not been converted into an inductive structure. In this case, wet etching is used, and the temperature is relatively low. Selective removal is performed through wet processing. While being able to effectively remove the portion that needs to be removed, it can also prevent dry etching from increasing the thermal budget in the processing flow due to high temperature. The use of a dry etching process to remove the inductive metal layer that has not been converted into an inductive structure can be removed more accurately, and dry etching has little effect on other structures of the three-dimensional memory manufactured by the present invention, and the performance of the three-dimensional memory manufactured by the present invention can be guaranteed.

[0021] As a possible implementation, the material of the induced metal layer includes at least one of nickel, palladium, aluminum, copper, iron or tungsten. In this case, the aforementioned materials and semiconductor structures can form an induced structure after reaction annealing, and can effectively induce the semiconductor structure to crystallize into a single crystal semiconductor layer. In the manufacturing method of the three-dimensional memory provided by the present invention, different induced metal layers can be selected according to the material of the semiconductor structure, the width and depth of the through hole and the thermal budget, so as to achieve the best effect under the respective conditions.

[0022] As a possible implementation, the height of the induced structure along the thickness direction of the stacked structure is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, it is possible to ensure that the induced structure has a suitable height so that it can effectively induce annealing to crystallize the semiconductor structure into a single crystal semiconductor layer, avoiding the inability to achieve the effect due to the height being too small. It is also possible to prevent the induced structure from being too high, which makes it difficult to completely remove the structure in the future, and to prevent a large gap from being left on the inner wall of the through hole after removal, thereby affecting the performance of the top three-dimensional memory unit.

[0023] As a possible implementation, after the semiconductor structure and the inductive structure are subjected to inductive annealing, the manufacturing method of the three-dimensional memory provided by the present invention further includes: removing the inductive structure. Removing the inductive structure can avoid adverse effects on the yield and performance of the three-dimensional memory formed by subsequent processing, and the single crystal channel without inductive metal contamination can improve the working performance of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the present invention.

[0024] In a second aspect, the present invention further provides a three-dimensional memory, which is manufactured by the manufacturing method of the three-dimensional memory provided in the first aspect.

[0025] The beneficial effects of the second aspect of the present invention and its various embodiments can be analyzed by referring to the beneficial effects of the three-dimensional memory manufactured by the first aspect and its various embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 A flow chart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0028] Figure 2 A flow chart of an implementation method of forming a cylindrical inductive structure and a semiconductor structure on the sidewall of a through hole in a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0029] Figure 3 A flow chart of another implementation of forming a cylindrical inductive structure and a semiconductor structure on the sidewall of a through hole in a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of forming a stacked structure on a substrate in an embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of forming a through hole at least penetrating the stacked structure in the stacked structure according to an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of forming a semiconductor active layer at the bottom of a through hole in an embodiment of the present invention;

[0033] Figure 7 It is a schematic diagram of forming an inter-electrode dielectric layer covering the side wall of the through hole on the semiconductor active layer in an embodiment of the present invention;

[0034] Figure 8It is a schematic diagram of forming a cylindrical inductive structure and a semiconductor structure on the side wall of a through hole in an embodiment of the present invention;

[0035] Fig. 9 A schematic diagram of filling a second type of dielectric isolation layer in a through hole according to an embodiment of the present invention;

[0036] Fig.10 It is a schematic diagram of performing an induced annealing treatment on a semiconductor structure and an induced structure in an embodiment of the present invention;

[0037] Fig.11 A schematic diagram of removing the inducing structure in an embodiment of the present invention;

[0038] Figures 12 to 17 A schematic process diagram of a first implementation method of forming a cylindrical inductive structure and a semiconductor structure on the sidewall of a through hole in a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0039] Figures 18 to 22 A schematic process diagram of a second implementation method of forming a cylindrical inductive structure and a semiconductor structure on the sidewall of a through hole in a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0040] Fig.23 It is a schematic diagram of forming a second type of dielectric isolation layer in a through hole and on a stacked structure in an embodiment of the present invention;

[0041] Reference numerals:

[0042] 100-substrate, 200-laminated structure,

[0043] 201-first type dielectric isolation layer, 202-sacrificial layer,

[0044] 300-through hole, 301-semiconductor active layer,

[0045] 302-inter-electrode dielectric layer, 410-induction metal layer,

[0046] 420-Induced structure, 510-Semiconductor structure,

[0047] 520- single crystal semiconductor layer, 600- second type dielectric isolation layer. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0050] In addition, the terms "first category" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first category" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0051] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0052] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] With the development of science and technology, traditional two-dimensional memory cannot meet the increasing demand for memory storage speed and storage density, so three-dimensional memory that vertically "stacks" traditional two-dimensional memory is designed and developed. With the increase in the total number of word lines in the three-dimensional memory device, that is, the increase in the number of stacking layers, the vertical channel in the stacking structure becomes longer, thereby increasing the resistance of the vertical channel and reducing the current of the channel. The vertical semiconductor channel of the traditional non-single crystal phase has a larger resistance, which further reduces the conduction current of the vertical channel. In addition, the grain-to-grain boundary in the semiconductor channel of the non-single crystal phase acts as a charge trapping site, resulting in additional random telegraph noise fluctuations and decreased carrier mobility. This random instability may cause significant read / write errors. A known technology for partially mitigating the impact of read / write errors is to use an error correction code (ECC) algorithm. However, the circuit required to execute the ECC algorithm occupies a relatively large chip area, thereby offsetting the benefits of using a three-dimensional memory. Therefore, using a single crystal channel with lower resistance becomes an inevitable choice.

[0054] In the prior art, the semiconductor channel of non-single crystal phase is usually converted into a single crystal semiconductor channel by heating and melting the semiconductor channel of non-single crystal phase and then cooling it to form a single crystal semiconductor channel. This method places high demands on the thermal budget of the entire three-dimensional memory. In addition, due to uneven heating, non-single crystal phase components may still remain in the channel, which will still increase the resistance of the channel, reduce the on-current of the channel and cause random instability.

[0055] To solve the above problems, first of all, please refer to Figure 1 The present invention provides a method for manufacturing a three-dimensional memory. The method comprises: first, referring to Figure 7 , providing a substrate, the substrate comprising a substrate 100, a stacked structure 200, a semiconductor active layer 301 and an inter-electrode dielectric layer 302. The stacked structure 200 is arranged on the substrate 100. The stacked structure 200 comprises a first-type dielectric isolation layer 201 and a sacrificial layer 202 which are alternately arranged in sequence along the thickness direction of the substrate 100. In the stacked structure 200, the film layers at the bottom layer and the top layer are both the first-type dielectric isolation layer 201; a through hole 300 is provided in the stacked structure 200, and the semiconductor active layer 301 is filled at the bottom of the through hole 300. The inter-electrode dielectric layer 302 is arranged on the semiconductor active layer 301 and covers the side wall surface of the through hole 300.

[0056] Next, please refer to Figure 8, a cylindrical induction structure 420 and a semiconductor structure 510 of non-single crystal phase are formed on the sidewall of the through hole 300. The induction structure 420 and the semiconductor structure 510 are sequentially arranged on the semiconductor active layer 301 along the thickness direction of the substrate. The projection of the semiconductor structure 510 on the semiconductor active layer 301 covers the projection of the induction structure 420 on the semiconductor active layer 301. The material of the induction structure is a compound of the semiconductor and the metal in the semiconductor active layer. The crystal phase of the material of the semiconductor structure is a non-single crystal phase.

[0057] Next, please refer to Fig. 9 , a second type dielectric isolation layer 600 is filled in the through hole 300 , and one end of the second type dielectric isolation layer 600 away from the bottom of the through hole 300 is flush with the stacked structure 200 .

[0058] Next, please refer to Fig.10 , the semiconductor structure 510 and the induction structure 420 are subjected to an induction annealing treatment, so that the semiconductor structure 510 is crystallized and modified into a single crystal semiconductor layer 520. After the induction annealing treatment, the induction structure 420 is located on the top of the single crystal semiconductor layer 520.

[0059] In the case of adopting the above technical solution, in the manufacturing method provided in the embodiment of the present invention, the stacked structure includes at least two first-type dielectric isolation layers and at least one sacrificial layer. In the through hole 300 of the stacked structure 200, a cylindrical induction structure 420 and a semiconductor structure 510 are sequentially formed on the side wall of the through hole 300 along the thickness direction of the substrate, and the top of the semiconductor structure 510 is flush with the top of the inter-electrode dielectric layer 302. The induction structure 420 can crystallize and modify the semiconductor structure 510 in a non-single-crystalline phase into a single-crystalline semiconductor layer 520, that is, a single-crystalline channel is formed on the side wall of the through hole 300. Specifically, when the semiconductor structure 510 and the induction structure 420 are subjected to an induction annealing treatment, the induction structure 420 will crystallize and modify the semiconductor structure 510 in a non-single-crystalline phase into a single-crystalline semiconductor layer 520, thereby realizing the preparation of a single-crystalline channel. After the induction annealing treatment, the cylindrical induction structure 420 is located on the top of the cylindrical single crystal semiconductor layer 520, and the cylindrical single crystal semiconductor layer 520 is located on the cylindrical semiconductor active layer 301, and the two have exchanged positions, that is, the induction structure 420 has crystallized and modified all the semiconductor structures 510 of the non-single crystal phase. The crystallization modification of this process is complete and sufficient, and there will be no residual polycrystalline components, so that the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention has all the advantages of using a single crystal channel. Compared with the prior art, the method of heating the non-single crystal phase channel and then cooling it to form a single crystal phase channel is used to convert the non-single crystal phase channel into a single crystal phase channel, which is easy to cause non-single crystal phase components to remain in the channel due to uneven heating, and the operation is more stable. In addition, the temperature of the induced annealing treatment is low and the time is short. The thermal budget of the induced annealing treatment is greatly reduced compared with the solution used in the prior art of heating the channel to melt and then cooling to crystallize and modify the polycrystalline channel into a single crystal channel. The structure of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention is less affected, and the three-dimensional memory manufactured by the embodiment of the present invention can have better performance. In addition, the projection of the semiconductor structure 510 on the semiconductor active layer 301 covers the projection of the induced structure 420 on the semiconductor active layer 301, that is, the ring width of the semiconductor structure 510 along the cross section parallel to the substrate 100 is greater than or equal to the ring width of the induced structure 420 along the cross section parallel to the substrate 100. In this case, it can be ensured that after the induced annealing treatment, there will be no induced structure 420 remaining under the single crystal semiconductor layer 520 and / or between the single crystal semiconductor layer 520 and the second type of dielectric isolation layer 600. The induced structure 420 is located at the top of the single crystal semiconductor layer 520, that is, the top of the through hole 300, and is no longer wrapped by the structure of the three-dimensional memory, and can be directly removed.

[0060] The following will be based on Figures 1 to 22 The manufacturing process is described by referring to the cross-sectional view of the operation shown in FIG. 1 . Specifically, the manufacturing method of the three-dimensional memory includes the following steps:

[0061] First, please refer to Figure 4 , providing a substrate 100. The embodiment of the present invention does not specifically limit the material and thickness of the substrate 100, as long as it can be applied to the manufacturing method of the three-dimensional memory provided in the embodiment of the present invention. The substrate 100 can be used to support the device structure thereon. Exemplarily, the material of the substrate 100 includes at least one of silicon, germanium, germanium silicon, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Preferably, the material of the substrate 100 is silicon.

[0062] Next, please refer to Figure 4 The method for forming a stacked structure in an embodiment of the present invention may include a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, to form a stacked structure 200 on a substrate 100, wherein the stacked structure 200 includes at least two first-type dielectric isolation layers 201 and at least one sacrificial layer 202 alternately arranged along the thickness direction of the substrate 100.

[0063] Regarding the sacrificial layer 202, it plays a role of pre-occupying in the stacked structure 200. After the floating gate structure and word line in the through hole are manufactured in the subsequent process, the sacrificial layer 202 is removed and the structure of the storage unit is formed at the original sacrificial layer 202. The thickness of the sacrificial layer 202 is determined by the size of the storage unit included in the three-dimensional memory manufactured by the embodiment of the present invention, and the embodiment of the present invention does not specifically limit it. The material of the sacrificial layer 202 should be as easy to remove as possible while meeting the requirements of its place-occupying function. Exemplarily, the material of the sacrificial layer 202 can be selected from at least one of polymer, nitride and germanium silicon; the thickness of the sacrificial layer 202 is greater than or equal to 5nm and less than or equal to 500nm.

[0064] Regarding the first type of isolation dielectric layer, it serves as an insulating layer between the stacked storage units of the three-dimensional memory formed by subsequent processes, and is used to separate the stacked storage units included in the three-dimensional memory manufactured by the embodiment of the present invention, so that the stacked storage units are isolated from each other and reduce interference between each other. The thickness of the first type of isolation dielectric layer can be determined according to the size of the storage unit and the leakage parameters between the stacked storage units. The embodiment of the present invention does not specifically limit the thickness of the first type of isolation dielectric layer. The material of the first type of isolation dielectric layer can be at least one of silicon oxide, hafnium oxide, silicon carbide or silicon nitride, or other materials that can meet the insulation performance requirements of the three-dimensional memory manufactured by the embodiment of the present invention. Optionally, the material of the first type of isolation dielectric layer is silicon oxide, because the process of silicon oxide used in three-dimensional memory is relatively mature and widespread, and the selection of silicon oxide as the material of the first type of isolation dielectric layer can make the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention have a higher yield and lower cost.

[0065] Exemplarily, the thickness of at least two first-type dielectric isolation layers 201 formed are the same, and the thickness of at least one sacrificial layer 202 formed is the same. In this case, the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention has the same size of storage units, and the voltage and current conditions for operating the storage units are also the same, which is convenient for other electronic systems to use the three-dimensional memory manufactured by the embodiment of the present invention. In addition, the thickness of the first-type isolation dielectric layer formed can be different, and the thickness of the sacrificial layer 202 formed can also be different. The thickness of the first-type isolation dielectric layer formed and the thickness of the sacrificial layer 202 formed can be determined according to the performance requirements of the three-dimensional memory manufactured by the embodiment of the present invention and the design requirements of the storage unit.

[0066] It should be noted that in the stacked structure 200, the film layers at the bottom and top are both the first type dielectric isolation layer 201. In this case, the film layer at the bottom in the stacked structure 200 is the first type dielectric isolation layer 201, which can prevent the transistor formed at the bottom layer of the stacked structure 200 from leaking to the substrate 100, thereby ensuring the performance of the transistor formed at the bottom layer of the stacked structure 200. At the same time, the film layer at the top in the stacked structure 200 is the first type dielectric isolation layer 201, which can prevent the transistor formed at the bottom layer of the stacked structure 200 from leaking to other structures subsequently formed on the stacked structure 200, thereby ensuring the performance of the transistor formed at the bottom layer of the stacked structure 200. The first type of dielectric isolation layer 201 can also serve as a protective layer to prevent the storage unit formed on the top layer of the stacked structure 200 of the three-dimensional memory manufactured by the embodiment of the present invention from being damaged during subsequent processing, thereby ensuring performance; and if a planarization process is used in a subsequent process to remove the inducing structure 420, the first type of dielectric isolation layer 201 can be appropriately thickened and gradually removed along the thickness direction of the substrate together with the inducing structure 420 until the inducing structure 420 is completely removed.

[0067] Next, please refer to Figure 5 , photolithography and etching processes can be used to form a through hole 300 in the stacked structure 200. The through hole 300 can only penetrate the stacked structure 200, or extend into the substrate 100. The manufacturing method provided in the embodiment of the present invention does not specifically limit the depth of the through hole 300, which can reduce the precision requirements for the process of forming the through hole 300 and reduce the cost of the manufacturing method provided in the embodiment of the present invention. For example, when the through hole 300 is formed by an etching process, if the etcher used or the type of etching process selected has low precision, the through hole 300 that only penetrates the stacked structure 200 cannot be formed, and the through hole 300 that extends into the substrate 100 can be formed, and then the through hole 300 is backfilled to only penetrate the stacked structure 200 by epitaxy, or the part of the through hole 300 extending into the substrate 100 is filled when the semiconductor active layer 301 is subsequently formed.

[0068] In addition, the embodiment of the present invention does not limit the size and shape of the through hole 300, as long as it can meet the performance requirements of the three-dimensional memory manufactured by the embodiment of the present invention and the precision requirements of the process for manufacturing the through hole 300. For example, the through hole 300 can be cylindrical, quadrangular, hexagonal, etc.

[0069] As for the number of through holes 300 , the embodiment of the present invention does not impose any limitation thereon, and the number can be determined according to the number of stacked layers and the number of memory cells to be manufactured.

[0070] Next, please refer to Figure 6 , an epitaxial process can be used to form a semiconductor active layer 301 at the bottom of the through hole 300, and the thickness of the formed semiconductor active layer 301 is at least the sum of the thickness of a first type dielectric isolation layer 201 and a sacrificial layer 202. The material of the semiconductor active layer 301 includes silicon, germanium, and germanium silicon. In the subsequent steps, the semiconductor active layer 301 can be used as a part of the selection tube structure of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention. If the top morphology of the formed semiconductor active layer 301 is uneven, such as a diamond morphology, a semiconductor active layer 301 thicker than the designed thickness can be formed first, and then the semiconductor active layer 301 can be back-etched to make the top of the semiconductor active layer 301 relatively flat, so as to facilitate the subsequent formation of the induced metal layer 410 and the semiconductor structure 510 on the semiconductor active layer 301.

[0071] Next, please refer to Figure 7 , the method of forming the inter-electrode dielectric layer 302 covering the side wall of the through hole 300 on the semiconductor active layer 301 may adopt a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The inter-electrode dielectric layer 302 may include a charge blocking layer, a charge trapping layer and a tunneling layer. Specifically, the tunneling layer is formed on the side wall of the through hole 300, the charge trapping layer is formed on the tunneling layer, and the charge blocking layer is formed on the charge trapping layer. In this step, the tunneling layer, the charge trapping layer, and the charge blocking layer are sequentially deposited along the inner wall of each through hole 300. The material of the charge blocking layer may be silicon oxide, the material of the charge trapping layer may be silicon nitride or SiON, and the material of the tunneling layer may be silicon oxide to form an "ONO" (Oxide-Nitride-Oxide) structure.

[0072] Next, please refer to Figure 8, a cylindrical induction structure 420 and a semiconductor structure 510 are formed on the sidewall of the through hole 300. Along the thickness direction of the substrate, the induction structure 420 and the semiconductor structure 510 are sequentially arranged on the semiconductor active layer 301. The top of the semiconductor structure 510 is flush with the top of the inter-electrode dielectric layer 302, and the projection of the semiconductor structure 510 on the semiconductor active layer 301 covers the projection of the induction structure 420 on the semiconductor active layer 301, that is, the ring width of the semiconductor structure 510 along the cross section parallel to the substrate 100 is greater than or equal to the ring width of the induction structure 420 along the cross section parallel to the substrate 100. In this case, it can be ensured that after the induction annealing treatment, no induction structure 420 will remain under the single crystal semiconductor layer 520 and / or between the single crystal semiconductor layer 520 and the second type dielectric isolation layer 600, and the induction structure 420 is located at the top of the single crystal semiconductor layer 520, that is, the top of the through hole 300, and is no longer wrapped by the structure of the three-dimensional memory, and can be directly removed.

[0073] In addition, the material of the semiconductor structure 510 includes silicon, germanium, and germanium silicon. The material of the semiconductor structure 510 is the same as that of the semiconductor active layer 301, so that the semiconductor structure 510 is subsequently induced to be catalyzed into a single crystal semiconductor layer 520, that is, a single crystal channel.

[0074] The embodiment of the present invention provides two implementations for forming the cylindrical inducing structure 420 and the semiconductor structure 510 on the sidewall of the through hole 300. It should be noted that the method for forming the cylindrical inducing structure 420 and the semiconductor structure 510 on the sidewall of the through hole 300 is not limited to these two implementations, and a more appropriate method can be selected according to actual needs.

[0075] The first implementation method: please refer to Figure 2 , forming a cylindrical inductive structure 420 and a semiconductor structure 510 on the sidewall of the through hole 300 includes:

[0076] First, please refer to Fig.12 , an induced metal layer 410 is formed on the stacked structure 200, the sidewall of the through hole 300 and the bottom of the through hole 300 by, for example, isotropic deposition. The embodiment of the present invention does not impose any specific restrictions on the thickness of the induced metal layer 410 and the material of the induced metal layer 410, and a suitable method and thickness of the induced metal layer 410 can be selected according to actual needs.

[0077] Specifically, the material of the induction metal layer 410 includes at least one of nickel, palladium, aluminum, copper, iron or tungsten. The aforementioned materials can form an induction structure 420 after reaction annealing, and can effectively induce the semiconductor structure 510 to crystallize into a single crystal semiconductor layer 520. In the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention, the induction metal layer 410 of different materials can be selected according to the material of the semiconductor structure 510, the width and depth of the channel and the thermal budget, so as to achieve the best effect under the respective conditions.

[0078] Exemplarily, when the material of the semiconductor structure 510 is silicon, the material of the inductive metal layer 410 is nickel, iron, copper, palladium, tungsten or aluminum. When the material of the semiconductor structure 510 is germanium, the material of the inductive metal layer 410 is nickel, iron or copper. When the material of the semiconductor structure 510 is silicon germanium, the material of the inductive metal layer 410 is nickel.

[0079] Optionally, the material of the inducing metal layer 410 is nickel, because nickel has a better effect of inducing crystallization modification on the semiconductor structure 510 .

[0080] Exemplarily, the thickness of the inductive metal layer 410 beyond the surface of the stacked structure 200 , the surface of the sidewall of the through hole 300 , and the surface of the semiconductor active layer 301 is greater than or equal to 3 nm and less than or equal to 30 nm.

[0081] In this case, it is possible to avoid the problems that the induced metal layer 410 and the semiconductor active layer 301 do not react effectively due to the induction metal layer 410 being too thin, the induction structure 420 is not formed after the induction metal layer 410, the height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and the height along the direction perpendicular to the thickness of the stacked structure 200 are uneven, and the height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and the height along the direction perpendicular to the thickness of the stacked structure 200 are too low, so as to ensure that the subsequent induced annealing treatment is carried out effectively. It is also possible to avoid the excessive material cost and time cost of forming the induced metal layer 410 due to the induced metal layer 410 being too thick, which is conducive to controlling costs and improving yields. In addition, an overly thick induced metal layer 410 may crack due to stress and damage the three-dimensional memory. The thickness of the induced metal layer 410 within the aforementioned range can also improve the yield and reduce costs.

[0082] Next, please refer to Fig.13 The induced metal layer 410 on the stacked structure and the induced metal layer 410 at the bottom of the through hole can be removed by dry etching, such as reactive ion etching (RIE) and ion beam etching (IBE), leaving only the induced metal layer 410 on the sidewall of the through hole 300.

[0083] Next, please refer to Fig.14, the induced metal layer 410 and the semiconductor active layer 301 are subjected to reaction annealing treatment, so that the portion of the induced metal layer 410 in contact with the semiconductor active layer 301 is transformed into the induced structure 420. It should be noted that the induced structure 420 formed in this step can penetrate into the semiconductor active layer 301. In addition, the embodiment of the present invention does not specifically limit the annealing time and annealing temperature of the reaction annealing in this step, and the thickness of the formed induced structure 420. The annealing time and annealing temperature of the reaction annealing and the thickness of the formed induced structure 420 can be selected according to actual needs.

[0084] Exemplarily, the annealing time of the reaction annealing treatment is greater than or equal to 15s and less than or equal to 300s. In this case, the reaction annealing treatment of the induced metal layer within this time range can ensure that the induced metal layer 410 effectively reacts with the semiconductor active layer 301 to form a semiconductor and metal compound, avoiding the situation where the induced metal layer 410 and the semiconductor active layer 301 cannot effectively react due to too short a time, thereby ensuring the effect of subsequent induced crystallization modification. It can also prevent the thermal budget from being increased due to too long a time, thereby affecting other structures.

[0085] Exemplarily, the annealing temperature of the reaction annealing treatment is greater than or equal to 180° C. and less than or equal to 300° C. Performing the reaction annealing treatment on the induced metal layer 410 within this temperature range can ensure that the induced metal layer 410 effectively reacts with the semiconductor active layer 301 to form a semiconductor and metal compound, and avoid the situation where the induced metal layer 410 and the semiconductor active layer 301 cannot effectively react due to too low a temperature, thereby ensuring the effect of subsequent induced crystallization modification. In addition, it can prevent unnecessary increase in thermal budget due to too high a temperature.

[0086] Exemplarily, the thickness of the induced metal layer 410 is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, it can be avoided that the induced metal layer 410 is too thin, resulting in the ineffective reaction between the induced metal layer 410 and the semiconductor active layer 301, the height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and the height along the direction perpendicular to the thickness of the stacked structure 200 are uneven, and the height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and the height along the direction perpendicular to the thickness of the stacked structure 200 are too low, which affects whether the subsequent induced annealing process can be effectively performed.

[0087] Exemplarily, the height of the inducing structure 420 along the thickness direction of the stacked structure 200 is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, within this height range, it is possible to ensure that the inducing structure 420 has a suitable height, so that it can effectively induce annealing to crystallize and modify the semiconductor structure 510 into a single crystal semiconductor layer 520, thereby avoiding the ineffectiveness due to the height being too small. It is also possible to prevent the inducing structure 420 from being too high, which makes it difficult to completely remove the structure in the future, and to prevent a large gap from being left on the inner wall of the through hole 300 after removal, thereby affecting the performance of the top three-dimensional memory unit.

[0088] Next, please refer to Fig.15 , use a wet etching process or a dry etching process to selectively remove the inductive metal layer 410 that has not been converted into the inductive structure 420. The temperature of wet etching is low, and wet processing is used for selective removal. Under the premise of effectively removing the required part, the high temperature of dry etching can be avoided to increase the thermal budget in the processing flow. The inductive metal layer that has not been converted into the inductive structure can be removed more accurately by using a dry etching process, and dry etching has little effect on other structures of the three-dimensional memory manufactured by the embodiment of the present invention, which can ensure the performance of the three-dimensional memory manufactured by the embodiment of the present invention.

[0089] Exemplarily, when the material of the induced metal layer 410 is nickel, a mixture solution of concentrated sulfuric acid and hydrogen peroxide, i.e., SPM semiconductor cleaning solution, is used to remove the induced metal layer 410; a cleaning solution such as aqua regia formed by a mixture of concentrated hydrochloric acid and concentrated nitric acid can also be used to remove the induced metal layer 410; and plasma etching can also be used to remove the induced metal layer 410.

[0090] Next, please refer to Fig.16 , a deposition process such as chemical vapor deposition, physical vapor deposition, electroplating, spin coating or evaporation is used to form a semiconductor structure 510 on the stacked structure 200, the sidewall of the through hole 300 and the semiconductor active layer 301. It should be noted that the embodiment of the present invention does not limit the thickness of the semiconductor structure 510, and the thickness of the semiconductor structure 510 can be selected appropriately according to actual needs.

[0091] Next, please refer to Fig.17, the semiconductor structure 510 located on the stacked structure 200 and the semiconductor structure 510 located on the bottom of the through hole 300 are removed by a process such as anisotropic etching, and only the semiconductor structure 510 located on the sidewall of the through hole 300 is retained, except for the inducing structure 420 located on the sidewall of the through hole 300 and the semiconductor structure 510 located on the sidewall of the through hole 300, and the projection of the semiconductor structure 510 on the semiconductor active layer 301 covers the projection of the inducing structure 420 on the semiconductor active layer 301, that is, the ring width of the semiconductor structure 510 along the cross section parallel to the substrate 100 is greater than or equal to the ring width of the inducing structure 420 along the cross section parallel to the substrate 100. Specifically, the ring width of the semiconductor structure 510 along the cross section parallel to the substrate 100 is 0nm to 1nm larger than the ring width of the inducing structure 420 along the cross section parallel to the substrate 100.

[0092] In this case, the tubular inducing structure 420 is formed first, and then the tubular semiconductor structure 510 is formed. There is no need to etch the inducing structure whose material is a compound of semiconductor and metal, thereby avoiding the need to etch the compound of semiconductor and metal that is more difficult to etch, thereby improving the manufacturing speed of the manufacturing method provided in the embodiment of the present invention and improving the yield.

[0093] The second implementation method: please refer to Figure 3 , a cylindrical inductive structure 420 and a semiconductor structure 510 are formed on the sidewall of the through hole 300, including:

[0094] First, physical vapor deposition or other processes can be used to form an induced metal layer 410 on the stacked structure 200, on the sidewalls of the through hole 300 and on the semiconductor active layer 301 at the bottom of the through hole 300. The material and thickness of the induced metal layer can be found in the above text and will not be described here.

[0095] Next, the induction metal layer 410 and the semiconductor active layer 301 are subjected to reaction annealing treatment to convert the contacting portion of the induction metal layer 410 and the semiconductor active layer 301 into the induction structure 420. The annealing time and annealing temperature of the reaction annealing can be referred to above and will not be described again.

[0096] Next, the inductive metal layer 410 that has not been transformed into the inductive structure 420 is removed by using a process such as dry etching.

[0097] Next, a deposition process, such as chemical vapor deposition, physical vapor deposition, electroplating or evaporation process, is used to form a semiconductor structure 510 on the stacked structure 200, on the sidewalls of the through hole 300 and on the semiconductor active layer 301 at the bottom of the through hole 300. It should be noted that the embodiment of the present invention does not limit the thickness of the semiconductor structure 510, and the thickness of the semiconductor structure 510 can be selected appropriately according to actual needs.

[0098] Next, the semiconductor structure 510 located on the stacked structure 200 and the semiconductor structure 510 located on the bottom of the through hole 300 are removed using a process such as anisotropic etching, leaving only the semiconductor structure 510 located on the side wall of the through hole 300; the induced metal layer 410 located on the bottom of the through hole 300 is removed, leaving only the induced metal layer 410 located on the side wall of the through hole 300.

[0099] In this case, the projection of the semiconductor structure 510 on the semiconductor active layer 301 overlaps with the projection of the inducing structure 420 on the semiconductor active layer, that is, the ring width of the semiconductor structure 510 along the cross section parallel to the substrate 100 is equal to the ring width of the inducing structure along the cross section parallel to the substrate. First, a thin sheet-like inducing structure 420 is formed on the semiconductor active layer 301 at the bottom of the through hole 300, and then the semiconductor structure 510 is formed, and then the inducing structure 420 and the semiconductor structure 510 are patterned. The two patternings can share the same mask, which can reduce the cost of the manufacturing method provided by the embodiment of the present invention. In addition, the inducing structure 420 and the semiconductor structure 510 form a self-alignment in the process, which is conducive to reducing the process complexity of the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention and improving the yield of the three-dimensional memory manufactured by the embodiment of the present invention.

[0100] Next, please refer to Fig.23 and Fig. 9 The method of forming the second dielectric isolation layer 600 in the through hole 300 and on the stacked structure 200 may include a thin film deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof, and the second dielectric isolation layer 600 is filled in the through hole 300, and one end of the second dielectric isolation layer 600 away from the bottom of the through hole 300 is flush with the stacked structure 200. For details, please refer to Fig.23 , firstly, a second type dielectric isolation layer 600 is formed in the through hole 300 and on the stacked structure 200; please refer to Fig. 9 The method for removing the second type of dielectric isolation layer 600 higher than the stacked structure 200 includes at least one of chemical mechanical polishing, reverse etching or other known planarization processes, and then removing the second type of dielectric isolation layer 600 higher than the stacked structure 200, leaving only the second type of dielectric isolation layer 600 located in the through hole 300.

[0101] It should be noted that, to ensure that the second dielectric isolation layer 600 can completely fill the through hole 300 , an excess of the second dielectric isolation layer 600 may be formed first, and then the second dielectric isolation layer 600 higher than the stacked structure 200 may be removed.

[0102] It should be noted that the embodiment of the present invention does not limit the material of the second type dielectric isolation layer 600 , and a suitable material can be selected according to actual needs.

[0103] Exemplarily, the material of the second type of isolation dielectric layer includes at least one of silicon oxide, hafnium oxide, silicon carbide or silicon nitride. Preferably, the material of the second type of isolation dielectric layer is silicon oxide, because silicon oxide is the most mature and widely used in three-dimensional memory, and the use of silicon oxide can make the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention have high yield and lower cost.

[0104] Next, please refer to Fig.10 , the semiconductor structure 510 and the induction structure 420 are subjected to induction annealing treatment, so that the semiconductor structure 510 is crystallized and modified into a single crystal semiconductor layer 520. After the induction annealing treatment, the induction structure 420 is located on the top of the single crystal semiconductor layer 520. In this case, after the induction annealing treatment, the induction structure 420 is located at the top of the single crystal semiconductor layer 520, that is, the top of the through hole 300, and is no longer wrapped by the structure of the three-dimensional memory manufactured by the embodiment of the present invention, but is directly exposed to the outside, and can be directly removed in the subsequent steps, which is conducive to avoiding the residual induction structure 420 from adversely affecting the yield and performance of the three-dimensional memory formed by subsequent processing. The single crystal channel without induction metal contamination can improve the working performance of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention. Compared with forming the induction structure on the top of the semiconductor structure and then performing the induction annealing treatment, which will remain in the through hole, and removing the induction structure requires etching from the substrate direction and then backfilling, the manufacturing method provided by the embodiment of the present invention is easier to remove the induction structure, which is conducive to reducing the process complexity.

[0105] It should be noted that the embodiment of the present invention does not impose any specific restrictions on the annealing time and annealing temperature of the reaction annealing in this step, and a suitable annealing time and annealing temperature of the reaction annealing can be selected according to actual needs.

[0106] As a possible implementation, the annealing temperature of the induced annealing treatment is greater than or equal to 450°C and less than or equal to 600°C, and the annealing time of the induced annealing treatment is greater than or equal to 0.5h and less than or equal to 30h. Performing the induced annealing treatment on the semiconductor structure 510 and the induced structure 420 at this temperature has little impact on other structures and low thermal budget requirements. Performing the induced annealing treatment on the semiconductor structure 510 and the induced structure 420 within this time range can avoid the incomplete crystallization modification of the semiconductor structure 510 due to too short annealing time, and can also avoid the increase of the thermal budget due to too long annealing time, thereby affecting the structural integrity of the three-dimensional memory, thereby ensuring better performance and higher yield of the three-dimensional memory.

[0107] Please note that when the annealing temperature of the induced annealing treatment is greater than or equal to 450°C and less than or equal to 600°C, the annealing time of the induced annealing treatment can also be determined according to the crystallization rate of the semiconductor structure from the bottom to the top from the non-single crystal phase to the single crystal phase and the length of the semiconductor structure along the thickness direction of the substrate. For example, when the induced structure is nickel silicide, the length of the semiconductor structure along the thickness direction of the substrate is 2000nm, and the crystallization rate of nickel silicide to the semiconductor structure is 500nm / h, the annealing time of the induced annealing treatment is greater than or equal to 4h and less than or equal to 30h.

[0108] As a possible implementation, the annealing temperature of the induced annealing treatment is greater than or equal to 900° C. and less than or equal to 1200° C., and the annealing time of the induced annealing treatment is greater than or equal to 2s and less than or equal to 20s. In this case, through the aforementioned rapid annealing, the semiconductor structure 510 is induced to crystallize and modify at a higher temperature and in a shorter time. On the premise that the semiconductor structure 510 is fully crystallized and modified into a single crystal semiconductor layer 520, the thermal budget is low.

[0109] Next, please refer to Fig.11 After the induction annealing is completed, that is, after the semiconductor structure 510 is crystallized and modified, the induction structure 420 is located above the single crystal semiconductor layer 520, that is, at the top of the channel, and the induction structure 420 is removed by a method such as a planarization process or an etching process.

[0110] In this way, the thermal budget of removing the inducing structure 420 by the planarization process is low, and the top layer of the stacked structure 200 can be planarized at the same time when the inducing structure 420 is removed, thereby reducing the process steps and improving the yield. Removing the inducing structure 420 by the etching process can achieve accurate removal of only the inducing structure 420, reduce the impact on other structures of the three-dimensional memory manufactured by the embodiment of the present invention, and ensure the structural integrity of the three-dimensional memory manufactured by the embodiment of the present invention.

[0111] In addition, removing the inductive structure 420 can avoid adverse effects on the yield and performance of the three-dimensional memory formed through subsequent processing, and the single crystal channel without induced metal contamination can improve the working performance of the three-dimensional memory manufactured using the manufacturing method of the three-dimensional memory provided by the embodiment of the present invention.

[0112] It should be noted that after the induction annealing is completed, that is, after the semiconductor structure 510 is crystallized and modified, the induction structure 420 is located above the single crystal semiconductor layer 520, that is, at the top of the channel, and the induction structure 420 may not be removed. The induction structure 420 may be removed when the three-dimensional memory manufactured by the embodiment of the present invention is subsequently processed after the manufacturing method provided by the embodiment of the present invention is applied, or the induction structure 420 may be retained according to performance requirements or processing needs.

[0113] Second, please refer to Fig.11 The embodiment of the present invention further provides a three-dimensional memory. The three-dimensional memory is manufactured by the manufacturing method of the three-dimensional memory provided in the first aspect.

[0114] The beneficial effects of the second aspect and its various implementation schemes in the embodiments of the present invention can be analyzed by referring to the beneficial effects of the three-dimensional memory manufactured by the first aspect and its various implementation schemes, and will not be repeated here.

[0115] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0116] The above are only specific implementations of the embodiments of the present invention, but the protection scope of the embodiments of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiments of the present invention, which should be included in the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: include: A substrate is provided, the substrate comprising a substrate, a stacked structure, a semiconductor active layer and an inter-electrode dielectric layer; the stacked structure is arranged on the substrate; the stacked structure comprises a first-type dielectric isolation layer and a sacrificial layer which are arranged alternately in sequence along the thickness direction of the substrate; in the stacked structure, the film layers located at the bottom layer and the top layer are both the first-type dielectric isolation layer; a through hole is provided in the stacked structure, the semiconductor active layer is filled at the bottom of the through hole; the inter-electrode dielectric layer is arranged on the semiconductor active layer and covers the side wall surface of the through hole; A cylindrical inductive structure and a semiconductor structure are formed on the sidewall of the through hole; the inductive structure and the semiconductor structure are sequentially arranged on the semiconductor active layer along the thickness direction of the substrate; The projection of the semiconductor structure on the semiconductor active layer covers the projection of the inductive structure on the semiconductor active layer; The material of the induced structure is a compound of the semiconductor and the metal in the semiconductor active layer; the crystal phase of the material of the semiconductor structure is a non-single crystal phase; Filling a second type of dielectric isolation layer in the through hole, wherein one end of the second type of dielectric isolation layer away from the bottom of the through hole is flush with the stacked structure; Performing an induction annealing treatment on the semiconductor structure and the induction structure to crystallize and transform the semiconductor structure into a single crystal semiconductor layer; After the induction annealing treatment, the induction structure is located on the top of the single crystal semiconductor layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The annealing temperature of the induced annealing treatment is greater than or equal to 450° C. and less than or equal to 600° C.; and / or the annealing time of the induced annealing treatment is greater than or equal to 0.5 h and less than or equal to 30 h; Alternatively, the annealing temperature of the induction annealing treatment is greater than or equal to 900° C. and less than or equal to 1200° C., and the annealing time of the induction annealing treatment is greater than or equal to 2s and less than or equal to 20s.

3. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The cylindrical inductive structure and the semiconductor structure formed on the sidewall of the through hole include: forming an induction metal layer on the stacked structure, on the sidewalls of the through hole and on the bottom of the through hole; removing the inductive metal layer located on the stacked structure and the inductive metal layer located at the bottom of the through hole, and retaining the inductive metal layer located on the side wall of the through hole; Performing a reaction annealing treatment on the remaining induction metal layer and the semiconductor active layer, so that the remaining portion of the induction metal layer in contact with the semiconductor active layer is converted into the induction structure; removing the inductive metal layer that has not been transformed into the inductive structure; forming the semiconductor structure on the stacked structure, on the sidewalls of the through hole and on the bottom of the through hole; The semiconductor structure on the stacked structure and the semiconductor structure on the bottom of the through hole are removed, and the semiconductor structure on the sidewall of the through hole is retained.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The cylindrical inductive structure and the semiconductor structure formed on the sidewall of the through hole include: forming an induction metal layer on the stacked structure, on the sidewalls of the through hole and on the bottom of the through hole; Performing a reaction annealing treatment on the induction metal layer and the semiconductor active layer, so that the portion of the induction metal layer in contact with the semiconductor active layer is converted into the induction structure; removing the inductive metal layer that has not been transformed into the inductive structure; forming the semiconductor structure on the stacked structure, on the sidewalls of the through hole and on the bottom of the through hole; The semiconductor structure located on the stacked structure and the semiconductor structure located on the bottom of the through hole are removed, and only the semiconductor structure located on the side wall of the through hole is retained; the induced metal layer located on the bottom of the through hole is removed, and the induced metal layer located on the side wall of the through hole is retained.

5. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, wherein the annealing temperature of the reaction annealing treatment is greater than or equal to 180° C. and less than or equal to 300° C.; and / or the annealing time of the reaction annealing treatment is greater than or equal to 15 s and less than or equal to 300 s. 6 . The method for manufacturing a three-dimensional memory according to claim 3 , wherein the thickness of the induction metal layer is greater than or equal to 0.5 nm and less than or equal to 30 nm. 7 . The method for manufacturing a three-dimensional memory according to claim 3 or claim 4 , wherein a wet etching process or a dry etching process is used to remove the inducing metal layer that has not been transformed into the inducing structure.

8. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, characterized in that: The material of the inductive metal layer includes at least one of nickel, palladium, aluminum, copper, iron and tungsten. 9 . The method for manufacturing a three-dimensional memory according to claim 3 or claim 4 , wherein a height of the inducing structure along a thickness direction of the stacked structure is greater than or equal to 0.5 nm and less than or equal to 30 nm.

10. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: After performing the induction annealing process on the semiconductor structure and the induction structure, the method for manufacturing the three-dimensional memory further includes: removing the induction structure.

11. A three-dimensional memory, characterized in that: The three-dimensional memory is manufactured by the manufacturing method described in any one of claims 1 to 10.

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