Formation method of semiconductor structure

Abstract

The embodiment of the invention provides a forming method of a semiconductor structure, the semiconductor structure is applied to a flash memory device, and the forming method of the semiconductor structure comprises the following steps: providing a substrate; forming a first oxide layer on the substrate; forming a seed layer on the first oxide layer; forming a nitride layer on the seed layer; and forming a second oxide layer on the nitride layer. By adopting the technical scheme, the data read-write speed of the flash memory device can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As a non-volatile memory device, flash memory devices are widely used because of their excellent erasure resistance, low operating voltage and low power consumption, simple process and compatibility with standard complementary metal oxide semiconductor (CMOS) process.

[0003] The flash memory device includes a flash memory cell, each of which includes a floating gate electrode for storing charge, and the floating gate electrode generally includes a dielectric for storing charge. The data reading and writing process of the flash memory device is realized by applying a voltage to the floating gate electrode.

[0004] However, the data reading and writing speed of existing flash memory devices is slow. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the data reading and writing speed of a flash memory device.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, which is applied to a flash memory device. The method for forming the semiconductor structure includes: providing a substrate; forming a first oxide layer on the substrate; forming a seed layer on the first oxide layer; forming a nitride layer on the seed layer; and forming a second oxide layer on the nitride layer.

[0007] Optionally, forming a first oxide layer on the substrate comprises:

[0008] introducing a silicon source gas and an oxygen source gas into a chamber where the substrate is located;

[0009] The first oxide layer is formed by reaction on the substrate based on the silicon source gas and the oxygen source gas.

[0010] Optionally, the concentration ratio of the silicon source gas to the oxygen source gas is 20% to 50%.

[0011] Optionally, a residual layer is formed on the first oxide layer, and the residual layer is silicon source gas remaining on the first oxide layer;

[0012] The step of forming a seed layer on the first oxide layer comprises:

[0013] Based on the silicon source gas remaining on the first oxide layer, an initial silicon nitride layer is generated by reaction on the first oxide layer, and the initial silicon nitride layer serves as the seed layer.

[0014] Optionally, the generating an initial silicon-nitrogen layer by reacting on the first oxide layer based on the silicon source gas remaining on the first oxide layer comprises:

[0015] Introducing a nitrogen source gas into the chamber where the substrate is located, wherein the nitrogen source gas is used to react with silicon in the silicon source gas remaining on the first oxide layer;

[0016] Based on the nitrogen source gas and the silicon source gas remaining on the first oxide layer, an initial silicon nitrogen layer is generated by reaction on the first oxide layer.

[0017] Optionally, the silicon source gas includes dichlorosilane; the oxygen source gas includes nitrogen oxide; and the nitrogen source gas includes ammonia.

[0018] Optionally, forming a seed layer on the first oxide layer includes:

[0019] Introducing a silicon source gas and a nitrogen source gas into a chamber where the substrate is located, wherein the nitrogen source gas is used to react with silicon in the silicon source gas;

[0020] Based on the nitrogen source gas and the silicon source gas, an initial silicon nitrogen layer is generated by reaction on the first oxide layer, and the initial silicon nitrogen layer serves as the seed layer.

[0021] Optionally, a thermal oxidation process is used to form the seed layer on the first oxide layer; and a low-pressure chemical vapor deposition process is used to form the nitride layer on the seed layer.

[0022] Optionally, the first oxide layer and the second oxide layer are made of the same material, both of which are silicon oxide;

[0023] The material of the nitride layer and the seed layer is the same, both are silicon nitride.

[0024] Optionally, the seed layer has a thickness of 0 angstroms to 40 angstroms;

[0025] The thickness of the nitride layer is 20 angstroms to 40 angstroms.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a seed layer is formed on the first oxide layer before forming the nitride layer. The seed layer can improve the adhesion between the nitride layer and the first oxide layer, solve the problem of unstable initial growth of the nitride layer, and thus improve the formation quality of the nitride layer (for example, reduce the thickness of the nitride layer, and the interface quality of the nitride layer). When the formed semiconductor structure is applied to a flash memory device, the programming speed of the flash memory device can be improved, thereby improving the data reading and writing speed of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the reading and writing speeds of existing flash memory devices are relatively slow.

[0030] Specifically, when forming a flash memory device, a step of forming a nitride layer using a furnace tube machine is included. Currently, a low pressure chemical vapor deposition (LPCVD) process is generally used to form the nitride layer in a furnace tube machine. In this process, the growth of the initially deposited nitride layer is unstable, resulting in the inability to form a nitride layer that meets the requirements (for example, the nitride layer has a thicker thickness, or the interface of the nitride layer is rougher), which will cause the data reading and writing speed of the flash memory device to slow down.

[0031] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, which is applied to a flash memory device. The method for forming the semiconductor structure includes: providing a substrate; forming a first oxide layer on the substrate; forming a seed layer on the first oxide layer; forming a nitride layer on the seed layer; and forming a second oxide layer on the nitride layer.

[0032] In the present invention, a seed layer is formed on the first oxide layer before forming the nitride layer. The seed layer can improve the adhesion between the nitride layer and the first oxide layer, solve the problem of unstable initial growth of the nitride layer, and thus improve the formation quality of the nitride layer (for example, reduce the thickness of the nitride layer so that the nitride layer has a preset thickness, and the interface quality of the nitride layer). When the formed semiconductor structure is applied to a flash memory device, the programming speed of the flash memory device can be improved, thereby improving the data reading and writing speed of the flash memory device.

[0033] For example, the semiconductor structure formed in the present embodiment can be an oxide-nitride-oxide (ONO) structure, and the ONO structure can be used as a dielectric for storing charge in a flash memory device. By applying a voltage to the floating gate electrode in the flash memory device, electrons can be stored in the nitride layer through the oxide layer to realize the data reading and writing process of the flash memory device. Since the present embodiment can improve the formation quality of the nitride layer, the equivalent thickness of the ONO structure can be reduced, and the smaller the equivalent thickness of the ONO structure, the faster the programming speed of the flash memory device, so when the ONO structure is applied to the flash memory device, the data reading and writing speed of the flash memory device can be improved.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0035] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0036] See also Figure 1 , providing a substrate 100.

[0037] In this embodiment, the substrate 100 may provide a process operation basis for a formation process of a semiconductor structure, wherein the semiconductor structure may include a fin field effect transistor (FinFET) or a gate all around transistor (GAA).

[0038] In this embodiment, the material of the substrate 100 includes silicon. In other embodiments, the material of the substrate 100 may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0039] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover a portion of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.

[0040] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0041] In some embodiments, the material of the isolation structure may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0042] In this embodiment, the material of the isolation structure may be silicon oxide.

[0043] See also Figure 2 , a first oxide layer 102 is formed on the substrate 100 .

[0044] The first oxide layer 102 can be used as a buffer layer to improve the interface state of the substrate 100. In addition, the first oxide layer 102 can suppress the injection of charges into the substrate 100, thereby improving the reliability of the ONO structure.

[0045] In this embodiment, a thermal oxidation process may be used to form the first oxide layer 102 on the substrate 100. In addition, the first oxide layer 102 formed by thermal oxidation has a denser structure, which can further improve the data reading speed of the flash memory device.

[0046] In a specific embodiment, the step of forming the first oxide layer 102 on the substrate 100 may include:

[0047] A silicon source gas and an oxygen source gas (such as Figure 2 Based on the silicon source gas and the oxygen source gas, a first oxide layer 102 is formed on the substrate 100 by reaction.

[0048] In this embodiment, when the silicon source gas and the oxygen source gas are introduced into the chamber where the substrate 100 is located, the silicon ions in the silicon source gas can be ionized under the excitation of the excitation source, and the free silicon can be attached to the surface of the substrate 100; and the oxygen ions in the oxygen source gas can be ionized. The oxygen ions can oxidize the silicon ions, thereby realizing the chemical bond between silicon and oxygen, and solidifying the silicon on the surface of the substrate 100 to form the first oxide layer 102.

[0049] That is, the material of the first oxide layer 102 may include silicon oxide. By selecting silicon oxide as the material of the first oxide layer 102, process compatibility can be improved and process risk can be reduced; moreover, compared with organic materials, silicon oxide materials have greater hardness and density, which is conducive to improving the protective effect of the first oxide layer 102 on the surface of the substrate 100.

[0050] In a specific embodiment, the material of the first oxide layer 102 includes silicon oxide. The silicon oxide material has good adhesion to the substrate 100, which is conducive to improving the stability and process treatment effect of subsequent processes; moreover, silicon oxide is a silicon oxide commonly used in semiconductor processes, which can reduce the difficulty and process cost of forming the first oxide layer 102 and improve process compatibility.

[0051] In this embodiment, the ratio of silicon source gas to oxygen source gas should not be too large or too small. If the ratio of silicon source gas to oxygen source gas is too small, the thickness of the first oxide layer 102 formed is too thin, which will reduce the critical electric field strength of the ONO structure, and there is a probability of charge injection into the substrate 100; if the ratio of silicon source gas to oxygen source gas is too large, the thickness of the first oxide layer 102 formed is too thick, resulting in a larger equivalent thickness of the formed ONO structure, which will reduce the programming speed of the flash memory device, and further reduce the data reading and writing speed. Based on this, in this embodiment, the concentration ratio of silicon source gas to oxygen source gas is 20% to 50%.

[0052] In this embodiment, the silicon source gas may include dichlorosilane; and the oxygen source gas may include nitrogen oxide.

[0053] In this embodiment, by adjusting the ratio of the silicon source gas to the oxygen source gas, the first oxide layer 102 that meets the requirements of the flash memory device can be obtained.

[0054] For example, the thickness of the first oxide layer 102 can increase the critical electric field strength of the flash memory device while reducing the equivalent thickness of the ONO structure and increasing the coupling rate of the ONO structure, thereby increasing the data reading and writing speed of the flash memory device.

[0055] In a specific embodiment, the thickness of the first oxide layer 102 may be 20 angstroms to 50 angstroms.

[0056] In some other embodiments, the thickness uniformity of the first oxide layer 102 can be improved by adjusting the gas flow rates of the silicon source gas and the oxygen source gas; and the problem that too much silicon adheres to the surface of the substrate 100 and part of the silicon cannot be solidified, resulting in a decrease in the density of the formed first oxide layer 102 and an increase in the surface roughness, can be avoided.

[0057] In some other embodiments, a low pressure chemical vapor deposition process may be used to form the first oxide layer 102 on the substrate 100 .

[0058] In the actual production process, the inventors found that in the step of forming the first oxide layer 102 on the substrate 100, by configuring the ratio between the silicon source gas and the oxygen source gas, when the first oxide layer 102 is formed, there is a residual layer on the first oxide layer 102, and the residual layer can be the silicon source gas remaining on the first oxide layer 102, and the silicon source gas can be used to form a seed layer.

[0059] In this embodiment, see Figure 3 The step of forming the seed layer 104 on the first oxide layer 102 may include:

[0060] Based on the silicon source gas (not shown) remaining on the first oxide layer 102 , an initial silicon nitride layer is generated by reaction on the first oxide layer 102 , and the initial silicon nitride layer serves as the seed layer 104 .

[0061] In a specific embodiment, based on the silicon source gas remaining on the first oxide layer 102 (not shown), the step of reacting and generating an initial silicon nitrogen layer on the first oxide layer 102 includes:

[0062] A nitrogen source gas (such as Figure 3 As shown by the arrow in the figure, the nitrogen source gas is used to react with the silicon in the silicon source gas remaining on the first oxide layer 102; based on the nitrogen source gas and the silicon source gas remaining on the first oxide layer 102, an initial silicon nitrogen layer 104 is generated on the first oxide layer 102 by reaction (the specific process is to be supplemented).

[0063] In this embodiment, the seed layer 104 may be formed on the first oxide layer 102 by using a thermal oxidation process in an atmosphere of nitrogen source gas and silicon source gas.

[0064] By pre-forming the seed layer 104 on the first oxide layer 102 , the adhesion between the subsequently formed nitride layer and the first oxide layer 102 can be improved, and the problem of unstable initial growth of the nitride layer can be solved, thereby improving the formation quality of the nitride layer.

[0065] In this embodiment, when the nitrogen source gas is introduced into the chamber where the substrate 100 is located, the gas flow rate of the nitrogen source gas should not be too small or too large. If the gas flow rate of the nitrogen source gas is too small, the density of the nitrogen source gas is low, which is easy to reduce the thickness uniformity of the seed layer 104, and the required process time is longer; if the gas flow rate of the nitrogen source gas is too large, it is easy to reduce the process stability, and it is also easy to reduce the distribution uniformity of the nitrogen source gas, and correspondingly reduce the thickness uniformity of the seed layer 104. For this reason, in this embodiment, when forming the seed layer 104, the gas flow rate of the nitrogen source gas is 10sccm to 100sccm.

[0066] In this embodiment, the thickness of the seed layer 104 should not be too large or too small. If the thickness of the seed layer 104 is too large, it is easy to cause the equivalent thickness of the formed ONO structure to be larger, which will reduce the programming speed of the flash memory device; if the thickness of the seed layer 104 is too small, it may not be able to improve the adhesion between the nitride layer and the first oxide layer 102. Based on this, in this embodiment, the thickness of the seed layer 104 is 0 angstroms to 40 angstroms (it should be noted that the thickness of the seed layer 104 must be at least greater than 0 angstroms).

[0067] In this embodiment, the nitrogen source gas may include ammonia NH3, and the nitrogen in the ammonia NH3 may react with the silicon in the dichlorodihydrogen silicon DCS to form a nitrogen silicon compound. That is, in the atmosphere of dichlorodihydrogen silicon DCS and ammonia NH3, a thermal oxidation process is used to form the seed layer 104 on the first oxide layer 102.

[0068] In this embodiment, by associating the formation process of the seed layer 104 with the first oxide layer 102 and taking into account the mutual influence between different layers in the ONO structure, the formation quality of the seed layer 104 can be improved, thereby improving the quality of the finally formed ONO structure.

[0069] In some other embodiments, the first oxide layer may be formed by other methods.

[0070] As an example, a germanium source gas and an oxygen source gas are introduced into a chamber where the substrate is located; based on the germanium source gas and the oxygen source gas, the first oxide layer is formed by reaction on the substrate.

[0071] Next, based on the germanium source gas remaining on the first oxide layer, an initial germanium nitride layer is generated by reaction on the first oxide layer, and the initial germanium nitride layer serves as the seed layer.

[0072] In other words, the present invention can form the seed layer in a variety of ways, and the material of the seed layer is not unique.

[0073] See also Figure 4 , a nitride layer 106 is formed on the seed layer 104 .

[0074] The nitride layer 106 can be used as a charge storage layer. By adjusting the composition and thickness of the nitride layer 106 , different charge storage capacities and charge retention times can be achieved.

[0075] In this embodiment, low pressure chemical vapor deposition is used to form the nitride layer 106 on the seed layer 104. Since the pre-formed seed layer 104 has the effect of improving the adhesion between the nitride layer 106 and the first oxide layer 102, even if low pressure chemical vapor deposition is used, the problem of unstable initial growth of the nitride layer 106 can still be solved.

[0076] In this embodiment, the material of the nitride layer 106 and the seed layer 104 is the same. For example, the nitride layer 106 and the seed layer 104 are both silicon nitride.

[0077] In some embodiments, the seed layer 104 serves as a charge storage layer and is used together with the nitride layer 106 to store charges.

[0078] As mentioned above, the charge storage capacity and charge retention time of the flash memory device are different depending on the thickness of the nitride layer 106. To meet the data reading requirements of the flash memory device, the thickness of the nitride layer 106 can be 20 angstroms to 40 angstroms.

[0079] It should be noted that when the nitride layer 106 and the seed layer 104 are used together as a nitride layer, the total height of the two should be less than 40 angstroms.

[0080] See also Figure 5 , a second oxide layer 108 is formed on the nitride layer 106 .

[0081] The second oxide layer 108 may serve as a protective layer to prevent the surface of the nitride layer 106 from being directly exposed to the air, thereby improving the surface quality of the nitride layer 106 .

[0082] In this embodiment, the second oxide layer 108 may be formed on the nitride layer 106 by using the same process as that for forming the first oxide layer 102 .

[0083] For example, the second oxide layer 108 may be formed on the nitride layer 106 by using a thermal oxidation process or a low pressure chemical vapor deposition process.

[0084] In this embodiment, the second oxide layer 108 and the first oxide layer 102 may be made of the same material. For example, the second oxide layer 108 and the first oxide layer 102 may both include silicon oxide.

[0085] In this embodiment, the thickness of the second oxide layer 108 can be set according to the needs of the flash memory device. For example, the thickness of the second oxide layer 108 can reduce the equivalent thickness of the ONO structure while increasing the critical electric field strength of the flash memory device, thereby increasing the coupling rate of the ONO structure and improving the data read and write speed of the flash memory device.

[0086] In a specific embodiment, the thickness of the second oxide layer 108 may be 20 angstroms to 50 angstroms.

[0087] It should be noted that, in this embodiment, the thickness is determined along a direction perpendicular to the substrate surface.

[0088] This embodiment further provides another method for forming a semiconductor structure. The similarities between this embodiment and the above-mentioned embodiment will not be repeated here.

[0089] The difference between this embodiment and the aforementioned embodiment is that: silicon source gas and nitrogen source gas are introduced into the chamber where the substrate is located, and the nitrogen source gas is used to react with the silicon in the silicon source gas; based on the nitrogen source gas and the silicon source gas, an initial silicon nitrogen layer is generated by reaction on the first oxide layer, and the initial silicon nitrogen layer serves as a seed layer.

[0090] That is, the silicon source gas and the nitrogen source gas are directly introduced into the chamber where the substrate is located to form a seed layer on the first oxide layer, rather than using the silicon source gas remaining on the surface of the first oxide layer.

[0091] In this embodiment, after the ONO structure is formed on the substrate, various device structures and functional structures may also be formed. For example, a gate structure and source-drain doping regions may also be formed on the substrate.

[0092] When the device is working, the gate structure is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure is a metal gate structure, and the gate structure may include a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0093] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0094] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0095] In this embodiment, the gate electrode layer may include one or both of a work function layer and an electrode layer.

[0096] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and silicon titanium nitride.

[0097] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0098] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0099] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0100] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0101] In this embodiment, the gate structure is described by taking a metal gate structure as an example. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0102] In some embodiments, a gate sidewall is formed on the sidewall of the gate structure, and the gate sidewall can be used to protect the gate structure.

[0103] In this embodiment, the material of the gate spacer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbon oxynitride, boron nitride or boron carbon nitride.

[0104] As an example, the material of the gate spacer is silicon nitride.

[0105] In this embodiment, the source-drain doped region can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped region can provide a carrier source.

[0106] The process of forming the source-drain doped regions includes: forming grooves in the substrate on both sides of the gate structure; forming a stress layer that fills the grooves; in the process of forming the stress layer, in-situ doping the stress layer to form the source-drain doped regions; or, after forming the stress layer, doping the stress layer to form the source-drain doped regions.

[0107] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, wherein the semiconductor structure is applied to a flash memory device, characterized in that: The method of forming a semiconductor structure includes: providing a substrate; forming a first oxide layer on the substrate; forming a seed layer on the first oxide layer; forming a nitride layer on the seed layer; A second oxide layer is formed on the nitride layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a first oxide layer on the substrate comprises: introducing a silicon source gas and an oxygen source gas into a chamber where the substrate is located; The first oxide layer is formed by reaction on the substrate based on the silicon source gas and the oxygen source gas.

3. The method for forming a semiconductor structure according to claim 2, wherein: The concentration ratio of the silicon source gas to the oxygen source gas is 20% to 50%.

4. The method for forming a semiconductor structure according to claim 2, wherein: The first oxide layer is formed to have a residual layer, and the residual layer is the silicon source gas remaining on the first oxide layer; The step of forming a seed layer on the first oxide layer comprises: Based on the silicon source gas remaining on the first oxide layer, an initial silicon nitride layer is generated by reaction on the first oxide layer, and the initial silicon nitride layer serves as the seed layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The step of reacting the residual silicon source gas on the first oxide layer to generate an initial silicon nitrogen layer on the first oxide layer comprises: Introducing a nitrogen source gas into the chamber where the substrate is located, wherein the nitrogen source gas is used to react with silicon in the silicon source gas remaining on the first oxide layer; Based on the nitrogen source gas and the silicon source gas remaining on the first oxide layer, an initial silicon nitrogen layer is generated by reaction on the first oxide layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: The silicon source gas includes dichlorosilane; the oxygen source gas includes nitrogen oxide; and the nitrogen source gas includes ammonia.

7. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a seed layer on the first oxide layer comprises: Introducing a silicon source gas and a nitrogen source gas into a chamber where the substrate is located, wherein the nitrogen source gas is used to react with silicon in the silicon source gas; Based on the nitrogen source gas and the silicon source gas, an initial silicon nitrogen layer is generated by reaction on the first oxide layer, and the initial silicon nitrogen layer serves as the seed layer.

8. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that: forming the seed layer on the first oxide layer by a thermal oxidation process; A nitride layer is formed on the seed layer by using a low pressure chemical vapor deposition process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The first oxide layer and the second oxide layer are made of the same material, which is silicon oxide; The material of the nitride layer and the seed layer is the same, both are silicon nitride.

10. The method for forming a semiconductor structure according to claim 1, wherein: The seed layer has a thickness of 0 angstroms to 40 angstroms; The thickness of the nitride layer is 20 angstroms to 40 angstroms.

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