Variable capacitance diode and preparation method thereof

Abstract

The invention provides a variable capacitance diode and a preparation method thereof, and relates to the technical field of microelectronics, the variable capacitance diode comprises a substrate, a buffer layer, a channel layer, a barrier layer, a cap layer and a passivation layer which are arranged in a stacked mode, a groove is formed from the passivation layer to the channel layer, the groove side wall of the groove in the stacking direction is nonlinear on the section passing through the central axis of the groove, and the groove side wall of the groove in the stacking direction is perpendicular to the central axis of the groove. A two-dimensional electron gas area is formed on the contact interface of the channel layer and the barrier layer, in the direction from the passivation layer to the channel layer, the groove bottom, close to the channel layer, of the groove is located below the two-dimensional electron gas area, a cathode is further arranged on the cap layer on the periphery of the groove, and anodes are arranged on the groove side wall and the groove bottom of the groove and the passivation layer on the periphery of the groove. The non-vertical groove structure is utilized, so that the problem of insufficient capacitance changing capability is solved, the capacitance changing range of the variable capacitance diode is enlarged, and large-range stable capacitance change is realized; the capacitance characteristic of the capacitor changes in a non-linear manner, and the capacitor can show a fixed capacitance value within a certain range under different negative pressure bias.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a varactor diode and a method for preparing the same. Background Art

[0002] At present, most of the groove anode gallium nitride (GaN) diodes are microwave diodes, which require the capacitance to be as small as possible. This structure introduces an etched groove under the anode. Since the heterojunction structure is destroyed, the capacitance in the etched groove area is eliminated, and the device capacitance is greatly reduced. Its structure can refer to patent CN110729362B. Conventional groove anode GaN diodes have a certain capacitance change capability under negative voltage bias, but the capacitance of existing GaN diodes changes rapidly, often dropping sharply when the voltage value at which the two-dimensional electron gas is depleted is reached, and the controllability is very poor, affecting the normal performance of the device. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a varactor diode and a method for preparing the same, which can increase the varactor range and achieve a wide range of stable capacitance changes.

[0004] According to one aspect of an embodiment of the present application, a varactor diode is provided, comprising: a stacked substrate, a buffer layer, a channel layer, a barrier layer, a cap layer and a passivation layer, wherein a groove is formed from the passivation layer to the channel layer, and the groove sidewalls of the groove along the stacking direction are non-straight lines in a cross section passing through the central axis of the groove, and a two-dimensional electron gas region is formed at an interface where the channel layer contacts the barrier layer, and in a direction from the passivation layer to the channel layer, a groove bottom of the groove close to the channel layer is located below the two-dimensional electron gas region, a cathode is further arranged on the cap layer at the periphery of the groove, and an anode is arranged on the groove sidewalls, the groove bottom and the passivation layer at the periphery of the groove.

[0005] Optionally, the groove sidewalls along the stacking direction are arranged in at least two steps.

[0006] Optionally, in a direction from the passivation layer to the channel layer, a step surface of the groove close to the channel layer is located 5 nm to 25 nm below the two-dimensional electron gas region.

[0007] Optionally, in a direction from the passivation layer to the channel layer, the groove is located in the barrier layer or the cap layer or the passivation layer, close to a step surface of the passivation layer.

[0008] Optionally, the width of the groove at the multi-step position gradually decreases from the passivation layer to the channel layer.

[0009] Optionally, the anode forms an anode field plate on the passivation layer, and along a length direction perpendicular to the stacking direction, the length of the anode field plate is 0.5 μm to 50 μm.

[0010] Optionally, the thickness of the passivation layer along the stacking direction is 50 nm to 500 nm.

[0011] Another aspect of the embodiment of the present application provides a method for preparing a varactor diode, which is used to prepare the varactor diode, comprising: sequentially forming a buffer layer, a channel layer, a barrier layer, a cap layer and a cathode on a substrate; forming an outer mesa groove at the edge of the cap layer, so that the outer mesa groove extends from the cap layer to the channel layer; forming a passivation layer on the cathode, wherein the passivation layer covers the cap layer and the outer mesa groove; In a region corresponding to the anode, a groove having multiple steps is formed from the passivation layer to the channel layer; Depositing metal in the groove to form an anode; A hole is opened from the passivation layer to the cathode.

[0012] Optionally, forming a groove having multiple steps from the passivation layer to the channel layer in a region corresponding to the anode includes: Etching a first groove from the passivation layer into the passivation layer, the cap layer or the barrier layer; A second groove and a third groove with gradually decreasing groove width are etched step by step from the bottom of the first groove into the channel layer, so that the groove forms three steps, and the step surface of the third groove close to the channel layer is located 5nm to 25nm below the interface where the barrier layer and the channel layer contact.

[0013] Optionally, depositing metal in the groove to form an anode comprises: Depositing a first metal layer with a thickness of 30 nm to 200 nm in the groove; A second metal layer with a thickness of 0 to 200 nm is deposited on the first metal layer; wherein the first metal layer at least includes a molybdenum layer, a tungsten layer or a nickel layer, and the second metal layer at least includes a gold layer.

[0014] The varactor diode and its preparation method provided by the embodiment of the present application, the groove sidewall of the groove along the stacking direction is non-linear in the cross section passing through the central axis of the groove. When the groove sidewall is a straight line in the cross section passing through the central axis of the groove, the capacitance of the varactor diode will change rapidly, resulting in poor controllability of the varactor diode. The present application sets the groove sidewall of the groove to be non-linear in the cross section passing through the central axis of the groove, which can gradually deplete the two-dimensional electron gas of the varactor diode, so that the capacitance of the varactor diode has a non-linear change, that is, the capacitance does not change linearly, and a fixed capacitance within a certain voltage variation range is achieved under a certain negative voltage bias. By using a non-vertical groove structure, the problem of insufficient capacitance variation of the existing groove anode GaN diode is overcome, the capacitance variation range of the varactor diode is increased, and a large range of stable capacitance variation is achieved; the capacitance characteristics of the varactor diode show non-linear changes, and a fixed capacitance value can be shown within a certain range under different negative voltage biases. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 is a schematic diagram of the structure of a varactor diode provided in this embodiment; Figure 2 to Figure 8 It is a schematic diagram of the varactor diode preparation process provided in this embodiment.

[0017] Icons: 11-substrate; 12-buffer layer; 13-channel layer; 14-barrier layer; 15-cap layer; 16-cathode; 17-passivation layer; 18-groove; 181-first groove; 182-second groove; 183-third groove; 19-anode; 190-anode field plate; 191-anode top; 192-anode bottom; 20-through hole; A-two-dimensional electron gas region; F-stacking direction; L-length; d1, d2, d3-slot width. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0019] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0020] It should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0021] Reference Figure 1 As shown, an embodiment of the present application provides a varactor diode, comprising: a stacked substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15 and a passivation layer 17, a groove 18 is formed from the passivation layer 17 to the channel layer 13, the groove sidewalls of the groove 18 along the stacking direction F are non-linear in a cross section passing through the central axis of the groove 18, a two-dimensional electron gas region A is formed at an interface where the channel layer 13 contacts the barrier layer 14, in a direction from the passivation layer 17 to the channel layer 13, the groove bottom of the groove 18 close to the channel layer 13 is located below the two-dimensional electron gas region A, a cathode 16 is further arranged on the cap layer 15 outside the groove 18, and an anode 19 is arranged on the groove sidewalls, the groove bottom and the passivation layer 17 outside the groove 18.

[0022] The substrate 11, buffer layer 12, channel layer 13, barrier layer 14, cap layer 15, cathode 16 and passivation layer 17 are arranged in sequence from bottom to top; there is a groove 18 on the channel layer 13, barrier layer 14, cap layer 15 and passivation layer 17, and the groove sidewall of the groove 18 along the stacking direction F is non-straight in the cross section passing the central axis of the groove 18, which means that when the groove 18 is etched, the etching direction is not parallel to the stacking direction F. At this time, the groove sidewall of the groove 18 formed in the cross section passing the central axis of the groove 18 can be a slant line, a curve, a step line, etc., as long as it is not a straight line.

[0023] This is because when the groove sidewall is a straight line in the cross section of the central axis of the groove 18, the capacitance of the varactor diode will change rapidly, resulting in poor controllability of the varactor diode. The present application sets the groove sidewall of the groove 18 to be a non-linear line in the cross section of the central axis of the groove 18, which can gradually deplete the two-dimensional electron gas of the varactor diode, so that the capacitance of the varactor diode has a non-linear change, that is, the capacitance does not change linearly, and a fixed capacitance within a certain voltage variation range is achieved under a certain negative voltage bias. The existing groove anode GaN diode has insufficient capacitance variation capability. The varactor diode of the present application can increase its capacitance variation range and achieve a wide range of stable capacitance variation.

[0024] For example, the varactor diode can be a GaN varactor diode. GaN material has great electrical performance advantages. The AlGaN (nitride semiconductor material composed of aluminum Al and gallium Ga) / GaN heterojunction structure will induce a high concentration of two-dimensional electron gas on the GaN side near the interface due to its strong spontaneous polarization and piezoelectric polarization effect. Since the electrons are confined in the potential well and there is very little impurity doping in this area, the ionized impurity scattering and alloy disorder scattering are small, and the two-dimensional electron gas has extremely high mobility and electron saturation rate. And due to the inherent wide bandgap properties of GaN materials, its critical breakdown field strength is extremely large, which is suitable for making high-power withstand voltage diodes.

[0025] In the present application, a two-dimensional electron gas region A is formed at the interface where the channel layer 13 contacts the barrier layer 14, and the bottom of the groove 18 close to the channel layer 13 is located below the two-dimensional electron gas region A. In other words, the groove 18 extends from the passivation layer 17 along the stacking direction F into the channel layer 13; specifically, it is located 5nm to 25nm below the two-dimensional electron gas region A, that is, 5nm to 25nm below the interface where the channel layer 13 contacts the barrier layer 14.

[0026] In the embodiment of the present application, the groove 18 is set to be a stepped groove 18, and the groove sidewall of the groove 18 along the stacking direction F is set in at least two steps; Figure 1 In the example, the groove 18 is arranged in a three-step shape.

[0027] In the direction from the passivation layer 17 to the channel layer 13, the stepped groove 18 is connected and extended from the first step to the last step. The step surface of the groove 18 close to the channel layer 13, that is, the step surface of the last step, is located 5nm to 25nm below the two-dimensional electron gas region A, and the step surface of the groove 18 close to the passivation layer 17 is located in the barrier layer 14, that is, the step surface of the first step close to the passivation layer 17 is located in the barrier layer 14. Figure 1It can be seen that, among the steps of the groove 18 , except for the step surface of the last step located in the channel layer 13 , the step surfaces of the remaining steps are all located in the barrier layer 14 , or the step surfaces of the remaining steps are all located in the cap layer 15 , or in the passivation layer 17 .

[0028] When the groove 18 is set to at least two steps, when a negative pressure is applied to the anode 19, as the negative pressure gradually increases, the two-dimensional electron gas can be gradually depleted along the steps multiple times in a discontinuous manner, which is equivalent to the area facing the capacitance of the anode field plate 190 being reduced by a part each time, and being reduced multiple times until depletion. Therefore, step-like control of the capacitance can be achieved, and a stable fixed capacitance can be achieved within a larger variable voltage range.

[0029] In some embodiments, the width of the groove 18 at the multi-step position gradually increases from the passivation layer 17 to the channel layer 13 .

[0030] In some embodiments, for example Figure 1 As shown, the width of the groove 18 at the multi-step position gradually decreases from the passivation layer 17 to the channel layer 13. Figure 7 The passivation layer 17 gradually forms a first groove 181, a second groove 182 and a third groove 183 toward the channel layer 13, the step surface of the first step is the bottom of the first groove 181, the step surface of the second step is the bottom of the second groove 182, and the step surface of the third step, which is the last step, is the bottom of the third groove 183, and the groove width d1 of the first groove 181 is greater than the groove width d2 of the second groove 182 and the groove width d3 of the third groove 183.

[0031] On the other hand, due to the requirement of process stability during the preparation of traditional groove anode GaN diodes, the range of the anode metal when evaporated is slightly larger than the anode groove. The edge of the anode metal is placed on the AlGaN to form a field plate structure, introducing the capacitance generated by the overlap of the Schottky anode and the two-dimensional electron gas.

[0032] The groove sidewalls, groove bottom and passivation layer 17 of the groove 18 in the present application are provided with an anode 19 to correspond to the cathode 16. The area where the anode 19 covers the passivation layer 17 forms an anode field plate 190, and the length L of the anode field plate 190 is 0.5μm to 50μm along the length direction perpendicular to the stacking direction F. The length L is longer than the field plate length in the prior art. When the length L is small, the capacitance formed is not large, and its variable capacitance range is limited, and it cannot be used as a varactor diode.

[0033] The main source of the capacitance of the varactor diode is the flat plate capacitance generated by the overlap of the anode field plate 190 and the two-dimensional electron gas. The present application lengthens the length L of the anode field plate 190 to effectively increase the capacitance.

[0034] In addition, the anode field plate 190 covers the passivation layer 17, and the passivation layer 17 serves as a medium, which is equivalent to filling the passivation layer 17 as a medium under the anode field plate 190. The filling of the medium increases the distance between the anode field plate 190 and the two-dimensional electron gas region A, and the control ability of the anode field plate 190 over the two-dimensional electron gas region A is weakened, so the capacitance change of the varactor diode can be made smoother and more stable; and when the thickness of the passivation layer 17 along the stacking direction F is changed, the size of the varactor diode capacitance can be modulated, and the length L of the anode field plate 190 and the thickness of the passivation layer 17 can be used to jointly adjust the capacitance change range. For example, the thickness of the passivation layer 17 of the present application can be adjusted between 50nm and 500nm.

[0035] In addition, in the stacking direction F, the anode 19 forms at least two steps in the groove 18 near the bottom of the substrate 11, and metal is filled in the groove 18 to form the anode 19. Therefore, the anode bottom 192 of the anode 19 needs to match the stepped groove 18, and the anode bottom 192 also forms at least two steps; and the anode top 191 of the anode 19 away from the substrate 11 forms steps corresponding to the anode bottom 192, for example, the step side walls of each level of the anode top 191 in the stacking direction F are basically located on the same vertical line as the step side walls of each level of the anode bottom 192.

[0036] In summary, the varactor diode provided in the embodiment of the present application utilizes a groove 18 structure with at least two steps to overcome the problem of insufficient varactor capability of the existing groove anode GaN diode, increase the varactor range of the varactor diode, and achieve a wide range of stable capacitance changes; the capacitance characteristics of the varactor diode change in a step-like manner, and can show a fixed capacitance value within a certain range under different negative voltage biases. The capacitance is also effectively increased by increasing the length L of the anode field plate 190, and the dielectric filling of the passivation layer 17 is performed under the anode field plate 190, so as to achieve a stable and controllable high-power varactor diode.

[0037] On the other hand, an embodiment of the present application further provides a method for preparing a varactor diode, which is used to prepare the above-mentioned varactor diode, and the method includes: Step 200 : A buffer layer 12 , a channel layer 13 , a barrier layer 14 , a cap layer 15 and a cathode 16 are sequentially formed on a substrate 11 .

[0038] like Figure 2 As shown, taking the AlGaN / GaN varactor diode as an example, a buffer layer 12, a channel layer 13, a barrier layer 14, and a cap layer 15 are sequentially formed on a substrate 11 as an epitaxial wafer.

[0039] The substrate 11 may be a SiC substrate 11 with a thickness of 100 μm to 600 μm, a sapphire substrate 11 with a thickness of 100 μm to 600 μm, a Si substrate 11 with a thickness of 100 μm to 1000 μm, or a GaN substrate 11 with a thickness of 100 μm to 600 μm.

[0040] The buffer layer 12 may be a GaN buffer layer 12 with a thickness of 1 μm to 6 μm, an AlGaN graded buffer layer 12 with a thickness of 1 μm to 6 μm, or an AlN buffer layer 12 with a thickness of 0.2 μm to 1 μm.

[0041] The channel layer 13 may be a non-intentionally doped GaN channel layer 13 having a thickness of 100 nm to 400 nm.

[0042] The barrier layer 14 may be an AlGaN barrier layer 14 , and the cap layer 15 may be a GaN cap layer 15 .

[0043] The epitaxial wafer is then cleaned by first soaking the AlGaN / GaN structure epitaxial wafer in HF acid solution or HCl acid solution for 30 seconds, then sequentially placed in acetone solution, isopropanol solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 5 minutes each, and then blown dry with nitrogen.

[0044] Then, the cathode 16 is made, such as Figure 3 As shown, photolithography, photolithography and development of the device cathode 16 region are sequentially performed on a clean epitaxial wafer, and a Ti / Al / Ni / Au metal stack is deposited on the epitaxial wafer using an electron beam evaporation device.

[0045] First, the epitaxial wafer deposited with Ti / Al / Ni / Au metal stack is soaked in acetone solution to peel off the metal in the photoresist area. Then, the epitaxial wafer is placed in acetone, isopropanol, anhydrous ethanol, and deionized water solution in turn for ultrasonic cleaning for 5 minutes each. After being blown dry with nitrogen, it is placed in a rapid annealing furnace for annealing to form the device cathode 16.

[0046] Step 201 : forming an outer mesa groove at the edge of the cap layer 15 , so that the outer mesa groove extends from the cap layer 15 to the channel layer 13 .

[0047] like Figure 4 As shown, the mesa isolation is made: the epitaxial wafer with 16 ohm cathode contact is coated, baked, and the mesa isolation photolithography and development and hardening are performed; an ICP (Inductively Coupled Plasma) etcher is used to etch the outer area of ​​the GaN mesa to form an outer mesa groove; the etched epitaxial wafer is placed in clean acetone, isopropanol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and blown dry with nitrogen to form device isolation.

[0048] Step 202: forming a passivation layer 17 on the cathode 16, wherein the passivation layer 17 covers the cap layer 15 and the outer mesa groove.

[0049] Refer to Figure 5 , perform dielectric deposition: a plasma enhanced chemical vapor deposition device can be used to deposit a SiN or SiO2 dielectric with a thickness of 50nm to 500nm on the epitaxial wafer after the mesa isolation as a passivation layer 17, and a double-layer composite passivation layer 17 of 10nm to 40nm Al2O3 and 50nm to 500nm SiN can also be deposited.

[0050] Step 203 : forming a groove 18 with multiple steps from the passivation layer 17 to the channel layer 13 in a region corresponding to the anode 19 .

[0051] like Figure 6 As shown, a first groove 181 is etched from the passivation layer 17 into the passivation layer 17 or the cap layer 15 or the barrier layer 14 .

[0052] like Figure 7 As shown, a second groove 182 and a third groove 183 with gradually decreasing groove widths are etched step by step from the bottom of the first groove 181 into the channel layer 13, so that the groove 18 forms three steps, and the step surface of the third groove 183 close to the channel layer 13 is located 5nm to 25nm below the interface where the barrier layer 14 and the channel layer 13 contact.

[0053] The notch width d1 of the first notch 181 is greater than the notch width d2 of the second notch 182 and greater than the notch width d3 of the third notch 183 .

[0054] Step 203 is a process for preparing the groove 18: 203-a), coating, baking, photolithography and development of the groove 18, and hardening are sequentially performed on the epitaxial wafer on which the passivation layer 17 has been deposited. 203-b), first use RIE (Reactive Ion Etching) etcher to slowly etch the SiN or SiO2 passivation layer 17 in the opening area of ​​the epitaxial wafer anode 19 to the surface of the barrier layer 14, and then use ICP etcher to slowly etch the required step height to form a first-level step groove 18 (first groove 181), and then put it into acetone, isopropanol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, blow dry with nitrogen to complete the production of the first-level step groove 18.

[0055] 203-c), gradually reduce (or increase) the lithography range of the groove 18, repeat 203-a) and 203-b), repeatedly perform lithography and etching to form a step groove 18. Note that after multiple etchings, the bottom of the lowest step must be 5nm to 25nm below the contact surface of the AlGaN barrier layer 14 and the GaN channel layer 13.

[0056] Step 204 : depositing metal in the groove 18 to form the anode 19 .

[0057] like Figure 8 The anode 19 of the varactor diode is made as shown: 204-a), on the epitaxial wafer after etching the step groove 18, the photolithography and development of the device anode 19 area are carried out in sequence, and a magnetron sputtering device or an electron beam evaporation device is used to first deposit a low work function metal Mo or W or Ni with a thickness of 30nm to 200nm on the epitaxial wafer as the first metal layer, and then a metal Au with a thickness of 0 to 200nm is deposited as the second metal layer to form a metal stack; the first metal layer is close to the channel layer 13, and the second metal layer is close to the passivation layer 17, or according to the different thicknesses of the metal layers, the first metal layer can also be close to the channel layer 13 and the passivation layer 17, and the second metal layer is located above the first metal layer.

[0058] 204-b), soak the epitaxial wafer after the operation 204-a) in an acetone solution so that the metal on the photoresist area is stripped off to form an anode field plate 190 of 0.5μm to 50μm, and then put the epitaxial wafer into clean acetone, isopropanol, anhydrous ethanol, and deionized water solution in turn for ultrasonic cleaning for 5 minutes each, and blow dry with nitrogen.

[0059] Step 205 : Open a through hole 20 from the passivation layer 17 to the cathode 16 .

[0060] Opening holes in the cathode 16 medium: 205-a), on the epitaxial wafer after the anode 19 is made, the photolithography of the through hole 20, development and hardening are carried out in sequence, and the through hole 20 area is etched to the cathode 16 metal surface using an RIE etcher. 205-b), the epitaxial wafer after the operation of 205-a) is placed in acetone, isopropanol, anhydrous ethanol, and deionized water solution for ultrasonic cleaning for 5 minutes each, and blown dry with nitrogen to complete the production of multi-level step groove 18 anode 19 varactor diode to obtain Figure 1 The structure shown.

[0061] The present application is a method for preparing a varactor diode provided in an embodiment. After the cathode 16 ohmic contact and the mesa isolation are completed and the passivation layer 17 dielectric is grown, the anode 19 is gradually increased or reduced multiple times, and multiple photolithography and slow etching are performed to form at least two steps of step grooves 18. The step groove 18 can gradually and stage-by-stage exhaust the two-dimensional electron gas of the device, so that the device capacitance has a step-like change, and a fixed capacitance within a certain voltage variation range is achieved under a certain negative voltage bias. The number of terraces determines the number of variable fixed capacitors. In addition, a larger anode field plate 190 is formed after the metal of the anode 19 is evaporated, and finally the passivation layer 17 dielectric on the ohmic contact is etched to open a hole, and the preparation of a high-power varactor diode with a multi-step groove 18 anode 19 is completed. The passivation layer 17 dielectric is filled under the anode field plate 190 to achieve the regulation of the capacitance variation range of the varactor diode. In addition, the present application also increases the length L of the anode field plate 190, and the anode field plate 190 with a larger length L can increase the device capacitance and change the capacitance variation range. The preparation method of the varactor diode is simple, has strong feasibility and high yield.

[0062] The method for preparing the varactor diode has the same structure and beneficial effects as the varactor diode in the aforementioned embodiment. The structure and beneficial effects of the varactor diode have been described in detail in the aforementioned embodiment and will not be repeated here.

[0063] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A varactor diode, characterized in that: include: A substrate, a buffer layer, a channel layer, a barrier layer, a cap layer and a passivation layer are stacked, a groove is formed from the passivation layer to the channel layer, the groove sidewalls of the groove along the stacking direction are non-straight lines on the cross section through the central axis of the groove, a two-dimensional electron gas region is formed at the interface where the channel layer contacts the barrier layer, and in the direction from the passivation layer to the channel layer, the groove bottom close to the channel layer is located below the two-dimensional electron gas region, a cathode is also arranged on the cap layer at the periphery of the groove, and an anode is arranged on the groove sidewalls, the groove bottom and the passivation layer at the periphery of the groove.

2. The varactor diode according to claim 1, characterized in that: The groove sidewalls of the groove along the stacking direction are arranged in at least two steps.

3. The varactor diode according to claim 2, characterized in that: In the direction from the passivation layer to the channel layer, the step surface of the groove close to the channel layer is located 5 nm to 25 nm below the two-dimensional electron gas region.

4. The varactor diode according to claim 3, characterized in that: In a direction from the passivation layer to the channel layer, the groove is located in the barrier layer or the cap layer or the passivation layer near the step surface of the passivation layer.

5. The varactor diode according to claim 4, characterized in that: The width of the groove at the multi-step position gradually decreases from the passivation layer to the channel layer.

6. The varactor diode according to any one of claims 1 to 5, characterized in that: The anode forms an anode field plate on the passivation layer. Along a length direction perpendicular to the stacking direction, the length of the anode field plate is 0.5 μm to 50 μm.

7. The varactor diode according to claim 6, characterized in that: The thickness of the passivation layer along the stacking direction is 50nm-500nm.

8. A method for preparing a varactor diode, used for preparing the varactor diode according to any one of claims 1 to 7, characterized in that: The method comprises: A buffer layer, a channel layer, a barrier layer, a cap layer and a cathode are sequentially formed on the substrate; forming an outer mesa groove at the edge of the cap layer, so that the outer mesa groove extends from the cap layer to the channel layer; forming a passivation layer on the cathode, wherein the passivation layer covers the cap layer and the outer mesa groove; In a region corresponding to the anode, a groove having multiple steps is formed from the passivation layer to the channel layer; Depositing metal in the groove to form an anode; A hole is opened from the passivation layer to the cathode.

9. The method for preparing a varactor diode according to claim 8, characterized in that: The forming of a groove having multiple steps from the passivation layer to the channel layer in a region corresponding to the anode includes: Etching a first groove from the passivation layer into the passivation layer, the cap layer or the barrier layer; A second groove and a third groove with gradually decreasing groove width are etched step by step from the bottom of the first groove into the channel layer, so that the groove forms three steps, and the step surface of the third groove close to the channel layer is located 5nm to 25nm below the interface where the barrier layer and the channel layer contact.

10. The method for preparing a varactor diode according to claim 8, characterized in that: The step of depositing metal in the groove to form an anode comprises: Depositing a first metal layer with a thickness of 30 nm to 200 nm in the groove; A second metal layer with a thickness of 0 to 200 nm is deposited on the first metal layer; wherein the first metal layer at least includes a molybdenum layer, a tungsten layer or a nickel layer, and the second metal layer at least includes a gold layer.

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