Insulated gate bipolar transistor and preparation method thereof

Abstract

The invention provides an insulated gate bipolar transistor and a preparation method thereof. According to the preparation method of the insulated gate bipolar transistor, a first interlayer dielectric layer is formed on the surface of a substrate and the surface of a protruding structure, and then the protruding part of the first interlayer dielectric layer is removed, so that the remaining first interlayer dielectric layer has a flat surface; therefore, the second interlayer dielectric layer and the third interlayer dielectric layer which are sequentially formed subsequently also have flat surfaces. Due to the fact that the flat surface can avoid metal etching residues, in the process of preparing the metal plug, the preparation method effectively avoids the problem of device short circuit caused by the metal residues, and the performance and the yield of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an insulated gate bipolar transistor and a preparation method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET). IGBT combines the advantages of MOS and BJT. It has the advantages of MOS, such as high input impedance, low control power, simple drive circuit, fast switching speed, and low switching loss, and it also has the advantages of BJT, such as high current density, low saturation voltage drop, and strong current handling capability.

[0003] See also Figure 1 and Figure 2 , the IGBT includes a cell region C and a terminal region T. The key structure of the IGBT is formed in the cell region C, involving the gate 101 and the emitter, etc. A field plate 102 is formed in the terminal region T to achieve the voltage division of the planar electric field and improve the device performance. However, since the field plate 102 is formed on the oxide layer 103 and its edge is a right-angle structure, the interlayer dielectric layer 104 covering the field plate 102 and the oxide layer 103 has a corner A or a concave morphology, which results in the metal etching residue 105a being easily present at the corner A when etching the metal material layer 105 used to form the tungsten through hole 106. The metal etching residue 105a is easily directly connected to the metal layer of the field plate 102 and / or the emitter, resulting in a short circuit problem, which seriously affects the yield of the device.

[0004] Therefore, a new preparation method is urgently needed to solve the above technical problems. Summary of the invention

[0005] The object of the present invention is to provide an insulated gate bipolar transistor and a method for manufacturing the same, so as to solve at least one of the problems of how to avoid metal residue on the interlayer dielectric layer of the IGBT and how to avoid device short circuit.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an insulated gate bipolar transistor, comprising:

[0007] A substrate is provided; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;

[0008] forming a first interlayer dielectric layer on the surfaces of the substrate and the protruding structure, wherein a portion of the first interlayer dielectric layer covering the surface of the protruding structure is in a protruding shape;

[0009] Removing a portion of the first interlayer dielectric layer in a protruding shape and exposing a top surface of the protruding structure to planarize the first interlayer dielectric layer;

[0010] A second interlayer dielectric layer and a third interlayer dielectric layer are sequentially formed on top surfaces of the first interlayer dielectric layer and the protrusion structure.

[0011] Optionally, in the method for preparing the insulated gate bipolar transistor, the process of removing the protruding portion of the first interlayer dielectric layer and exposing the top surface of the protruding structure to planarize the first interlayer dielectric layer includes:

[0012] coating a first photoresist layer on the first interlayer dielectric layer;

[0013] Using a first photomask to expose the first photoresist layer and form a patterned first photoresist layer to expose a portion of the first interlayer dielectric layer in a convex shape;

[0014] The patterned first photoresist layer is used as a barrier to etch and remove a portion of the first interlayer dielectric layer in a protruding shape, and expose a top surface of the protruding structure to planarize the first interlayer dielectric layer.

[0015] Optionally, in the method for preparing the insulated gate bipolar transistor, the process of forming the protruding structure on the terminal region includes:

[0016] forming a polysilicon layer on the substrate;

[0017] coating a second photoresist layer on the polysilicon layer;

[0018] Using the first photomask to expose the second photoresist layer and form a patterned second photoresist layer to cover a portion of the polysilicon layer located on the terminal region and expose the remaining portion of the polysilicon layer;

[0019] The patterned second photoresist layer is used as a barrier to etch and remove the exposed portion of the polysilicon layer; and the remaining portion of the polysilicon layer is the protruding structure.

[0020] Optionally, in the method for preparing the insulated gate bipolar transistor, the first photoresist layer is a positive photoresist, the second photoresist layer is a negative photoresist, and the opening width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; or, the first photoresist layer is a negative photoresist, the second photoresist layer is a positive photoresist, and the shielding width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; and,

[0021] The photosensitivity of the first photoresist layer is different from the photosensitivity of the second photoresist layer, so that the width of the portion of the polysilicon layer covered by the patterned second photoresist layer is equal to the width of the top surface of the protruding structure; and the width of the portion of the first interlayer dielectric layer exposed by the patterned first photoresist layer is a first width, and the first width D satisfies the following formula:

[0022] D = d1 + 2d2;

[0023] Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

[0024] Optionally, in the method for preparing the insulated gate bipolar transistor, the protruding structure includes a field plate and / or a temperature sensor.

[0025] Optionally, in the method for preparing the insulated gate bipolar transistor, the process of removing the protruding portion of the first interlayer dielectric layer and exposing the top surface of the protruding structure to planarize the first interlayer dielectric layer includes:

[0026] coating a third photoresist layer on the first interlayer dielectric layer;

[0027] Using a second photomask to expose the third photoresist layer and form a patterned third photoresist layer to expose a portion of the first interlayer dielectric layer in a protruding shape;

[0028] Using the patterned third photoresist layer as a barrier, etching and removing the protruding portion of the first interlayer dielectric layer, and exposing the top surface of the protruding structure, so as to planarize the first interlayer dielectric layer;

[0029] The third photoresist layer is a positive photoresist, and the opening width of the second photomask toward the protruding structure is a first width D; or the third photoresist layer is a negative photoresist, and the shielding width of the second photomask toward the protruding structure is a first width D; and the first width D satisfies the following formula:

[0030] D = d1 + 2d2;

[0031] Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

[0032] Optionally, in the method for preparing the insulated gate bipolar transistor, a chemical mechanical polishing process is used to remove a protruding portion of the first interlayer dielectric layer and expose a top surface of the protruding structure to planarize the first interlayer dielectric layer.

[0033] Optionally, in the method for preparing the insulated gate bipolar transistor, the material of the first interlayer dielectric layer and the material of the second interlayer dielectric layer both include USG; and the material of the third interlayer dielectric layer includes BPSG or BSG.

[0034] Optionally, in the method for preparing the insulated gate bipolar transistor, the thickness of the first interlayer dielectric layer is less than or equal to the thickness of the protruding structure.

[0035] Optionally, in the method for preparing the insulated gate bipolar transistor, after forming the second interlayer dielectric layer, the method for preparing the insulated gate bipolar transistor further comprises:

[0036] A metal plug is formed at least on the side of the trench gate, and the metal plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer.

[0037] Based on the same inventive concept, the present invention also provides an insulated gate bipolar transistor, comprising:

[0038] A substrate; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;

[0039] A first interlayer dielectric layer; the first interlayer dielectric layer covers the surface of the substrate and surrounds the sidewalls of the protruding structure;

[0040] A second interlayer dielectric layer; the second interlayer dielectric layer covers the first interlayer dielectric layer and the exposed surface of the protruding structure;

[0041] A third interlayer dielectric layer; the third interlayer dielectric layer covers the surface of the second interlayer dielectric layer.

[0042] Optionally, in the insulated gate bipolar transistor, the material of the first interlayer dielectric layer and the material of the second interlayer dielectric layer both include USG; and the material of the third interlayer dielectric layer includes BPSG or BSG.

[0043] Optionally, in the insulated gate bipolar transistor, the thickness of the first interlayer dielectric layer is less than or equal to the thickness of the protruding structure.

[0044] Optionally, in the insulated gate bipolar transistor, the protruding structure includes a field plate and / or a temperature sensor.

[0045] Optionally, in the insulated gate bipolar transistor, the insulated gate bipolar transistor also includes: a plurality of metal plugs; at least some of the metal plugs are located on the sides of the trench gate and penetrate the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer.

[0046] In summary, the present invention provides an insulated gate bipolar transistor and a method for preparing the same. Compared with the prior art, the preparation method first forms a first interlayer dielectric layer on the surface of the substrate and the protruding structure, and then removes the protruding portion of the first interlayer dielectric layer, so that the remaining first interlayer dielectric layer has a flat surface, and then the second interlayer dielectric layer and the third interlayer dielectric layer formed in sequence subsequently also have a flat surface. Since the flat surface can avoid metal etching residues, the preparation method effectively avoids the problem of device short circuit caused by metal residues in the process of preparing the metal plug, thereby improving the performance and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0048] Figure 1 It is a schematic diagram of the structure in which the surface of the interlayer dielectric layer is uneven in the prior art.

[0049] Figure 2 It is a schematic diagram of a structure in which metal etching residues exist at corners in the prior art.

[0050] Figure 3 It is a flow chart of a method for preparing an insulated gate bipolar transistor in an embodiment of the present invention.

[0051] Figure 4 Flow chart of the method for preparing the protruding structure in an embodiment of the present invention.

[0052] Figure 5 It is a schematic diagram of using a first photomask to expose a second photoresist layer in an embodiment of the present invention.

[0053] Figure 6 Schematic diagram of the structure of the patterned second photoresist layer in an embodiment of the present invention.

[0054] Figure 7Schematic diagram of etching a polysilicon layer using a patterned second photoresist layer in an embodiment of the present invention.

[0055] Figure 8 It is a schematic diagram of a polysilicon layer synchronously covering the trench gate trench and the substrate surface in an embodiment of the present invention.

[0056] Fig. 9 Schematic diagram of forming a first interlayer dielectric layer in an embodiment of the present invention.

[0057] Fig.10 The present invention is a flowchart of a method for removing a protruding first interlayer dielectric layer according to an embodiment of the present invention.

[0058] Fig.11 It is a schematic diagram of using a first mask to expose a first photoresist layer in an embodiment of the present invention.

[0059] Fig.12 It is a schematic diagram of etching the first interlayer dielectric layer using a patterned first photoresist layer in an embodiment of the present invention.

[0060] Fig.13 Schematic diagram of the structure of a first interlayer dielectric layer having a flat surface in an embodiment of the present invention.

[0061] Fig.14 It is a schematic diagram of using a second mask to expose a third photoresist layer in an embodiment of the present invention.

[0062] Fig.15 It is a schematic diagram of etching the first interlayer dielectric layer using a patterned third photoresist layer in an embodiment of the present invention.

[0063] Fig.16 Schematic diagram of forming a second interlayer dielectric layer in an embodiment of the present invention.

[0064] Fig.17 Schematic diagram of forming a third interlayer dielectric layer in an embodiment of the present invention.

[0065] Fig.18 Schematic diagram of forming a contact hole in an embodiment of the present invention.

[0066] Fig.19 Schematic diagram of forming a metal material layer in an embodiment of the present invention.

[0067] Fig. 20 Schematic diagram of forming a metal plug in an embodiment of the present invention.

[0068] And, in the attached drawings:

[0069] 101 - gate; 102 - field plate; 103 - oxide layer; 104 - interlayer dielectric layer; 105 - metal material layer; 105a - metal etching residue; 106 - tungsten through hole;

[0070] 200-first drift region; 201-polysilicon gate; 202-gate oxide layer; 203-second drift region; 204-oxide layer; 205-polysilicon layer; 206-second photoresist layer; 207-patterned second photoresist layer; 208-protruding structure; 209-first interlayer dielectric layer; 210-first photoresist layer; 211-patterned first photoresist layer; 212-third photoresist layer; 213-patterned third photoresist layer; 214-second interlayer dielectric layer; 215-third interlayer dielectric layer; 216-contact hole; 217-metal material layer; 218-metal plug;

[0071] C-cell region; T-terminal region; A-corner; D-first width; d1-width of the top surface of the protruding structure; d2-width of the first interlayer dielectric layer covering one side wall of the protruding structure. DETAILED DESCRIPTION

[0072] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0073] See also Figure 3 This embodiment provides a method for preparing an insulated gate bipolar transistor, comprising:

[0074] Step 1 S10: providing a substrate; the substrate comprises a cell region and a terminal region, wherein a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region;

[0075] Step 2 S20: forming a first interlayer dielectric layer on the surfaces of the substrate and the protruding structure, wherein a portion of the first interlayer dielectric layer covering the surface of the protruding structure is in a protruding shape;

[0076] Step three S30: removing the protruding portion of the first interlayer dielectric layer and exposing the top surface of the protruding structure to planarize the first interlayer dielectric layer;

[0077] Step 4 S40: forming a second interlayer dielectric layer and a third interlayer dielectric layer in sequence on the top surfaces of the first interlayer dielectric layer and the protrusion structure.

[0078] Based on this, the preparation method provided in this embodiment removes the first interlayer dielectric layer that is in a protruding shape, so that the remaining first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer have a flat surface. The flat surface can avoid metal etching residues and thus avoid the problem of device short circuit, thereby effectively improving the performance and yield of the device.

[0079] The following is combined with Figures 3 to 20 , specifically describing the method for preparing the insulated gate bipolar transistor provided in this embodiment.

[0080] Step 1 S10: Please refer to Figures 4 to 8 , providing a substrate; the substrate includes a cell region C and a terminal region T, and a trench gate is formed in the cell region C, and a protrusion structure 208 is formed on the terminal region T.

[0081] It should be noted that the structure of the IGBT is mainly divided into a cell region C and a terminal region T, and the terminal region T surrounds the cell region C. The cell region C is a key device region, in which a gate, an emitter and various well regions are arranged; a field plate, a temperature sensor and a floating field ring are arranged in the terminal region T to improve the performance of the IGBT. The collector of the IGBT is generally arranged on the other side of the substrate. Based on this, the cell region C includes a first drift region 200, and a plurality of trench gates, a P well region and an N well region are arranged in the first drift region 200. The trench gate includes a polysilicon gate 201 and a gate oxide layer 202 formed on the periphery of the polysilicon gate 201. In other embodiments, the gate of the IGBT can also be a planar gate. And the terminal region T includes a second drift region 203, and a doping structure such as a floating field ring is arranged in the second drift region 203, and a field plate and / or a temperature sensor and other structures are arranged on the surface of the second drift region 203. Since structures such as field plates and temperature sensors have morphological features protruding from the surface of the substrate, they are collectively referred to as protruding structures 208 in this embodiment. It should be noted that each of the protruding structures 208 located on the terminal region T may be a field plate, or may be partially a field plate and partially a temperature sensor, which is not specifically limited in this embodiment, and this embodiment is only described by taking the simultaneous formation of a field plate and a temperature sensor as an example.

[0082] For details, please refer to Figure 4 The process of forming a field plate and / or a temperature sensor on the surface of the second drift region 203 comprises the following steps:

[0083] Sub-step 1 S101: Please refer to Figure 5 , a polysilicon layer 205 is formed on the substrate.

[0084] After forming trench gates, various well regions and various field rings in the first drift region 200 and the second drift region 203, respectively, an oxide layer 204 is formed on the surface of the substrate to protect the substrate structure and prevent doping ions from diffusing. Subsequently, a polysilicon layer 205 is formed on the substrate for subsequent preparation of a protruding structure of a field plate and / or a temperature sensor.

[0085] Sub-step 2 S102: Please refer to Figure 5 , a second photoresist layer 206 is coated on the polysilicon layer 205 .

[0086] This embodiment does not limit whether the second photoresist layer 206 is a positive photoresist or a negative photoresist. If the second photoresist layer 206 is a positive photoresist, a cross-linking reaction will occur after exposure, so that the exposed part is dissolved and the unexposed part is insoluble. If the second photoresist layer 206 is a negative photoresist, the exposed part becomes insoluble after exposure, while the unexposed part is dissolved.

[0087] Sub-step 3 S103: Please refer to Figure 5 , Figure 6 and Figure 7 The first mask M1 is used to expose the second photoresist layer 206 and form a patterned second photoresist layer 207 to cover a portion of the polysilicon layer 205 located on the terminal region T and expose the remaining portion of the polysilicon layer 205 .

[0088] Exemplarily, the second photoresist layer 206 is a negative photoresist, so the opening of the first mask M1 faces the terminal region T, and during the exposure process, the light beam is irradiated through the opening onto a portion of the photoresist layer 206 in the terminal region T, so that the portion of the photoresist layer 206 is retained, while the remaining photoresist layer 206 not irradiated by the light beam is dissolved, and a portion of the polysilicon layer 205 is exposed. Figure 7 A patterned second photoresist layer 207 is shown.

[0089] Sub-step 4 S104: Please refer to Figure 6 and Figure 7 , using the patterned second photoresist layer 207 as a barrier, etching and removing the exposed portion of the polysilicon layer 205 ; and the remaining portion of the polysilicon layer 205 is the protruding structure 208 .

[0090] Because the patterned second photoresist layer 207 exposes the polysilicon layer 205 located in the cell area C and also exposes part of the polysilicon layer 205 located in the terminal area T, the polysilicon layer 205 is etched with the patterned second photoresist layer 207 as a barrier, and the exposed part of the polysilicon layer 205 is removed, while the part of the polysilicon layer 205 covered by the patterned second photoresist layer 207 is retained. The polysilicon layer 205 retained at last can be used as a field plate in subsequent processes, and / or formed into a protruding structure 208 such as a temperature sensor with a PN junction through ion doping. In addition, after the protruding structure 208 is formed, the patterned second photoresist layer 207 is removed. It should be noted that the above-mentioned process for preparing the protruding structure 208 provided in this embodiment is only an example. And in other examples, the trench gate and the protruding structure 208 can be formed simultaneously. As Figure 8 As shown, the formed polysilicon layer 205 not only covers the surface of the substrate in the cell region C and the terminal region T, but also fills and covers the trench for forming the trench gate in the cell region C. Then, under the blocking of the patterned second photoresist layer 207, the polysilicon layer 205 is etched until the oxide layer 204 on the substrate is exposed, and the polysilicon material filling of the trench gate and the formation of the protruding structure 208 are completed simultaneously. Therefore, this embodiment does not limit the specific process of forming the protruding structure 208.

[0091] Step 2 S20: Please refer to Fig. 9 A first interlayer dielectric layer 209 is formed on the surfaces of the substrate and the protruding structure 208, and a portion of the first interlayer dielectric layer 209 covering the surface of the protruding structure 208 is in a protruding shape.

[0092] It should be noted that after the trench gate and various well regions are formed in the first drift region 200, a metal interconnection structure needs to be formed on the surface thereof to realize the electrical extraction of the gate and the emitter. Therefore, a dielectric layer needs to be formed on the surface of the substrate and the protruding structure 208 to achieve electrical isolation. However, since the protruding structure 208 protrudes from the surface of the oxide layer 204, the formed dielectric layer will have an uneven surface, which is prone to etching residues when a metal plug or metal line is subsequently formed, resulting in a short circuit of the device.

[0093] Therefore, in order to avoid the uneven morphology on the surface of the dielectric layer, the preparation method provided in this embodiment first forms a first interlayer dielectric layer 209 on the surface of the oxide layer 204 and the protruding structure 208, and the thickness of the first interlayer dielectric layer 209 is less than or equal to the thickness of the protruding structure 208. Preferably, the thickness of the first interlayer dielectric layer 209 is equal to the thickness of the protruding structure 208, so that after the execution of step three S30, the surface of the remaining first interlayer dielectric layer 209 and the top surface of the protruding structure 208 are on the same plane, which is conducive to the second interlayer dielectric layer and the third interlayer dielectric layer formed subsequently having a top surface with better flatness, thereby avoiding the problem of metal etching residue. Among them, the thickness referred to in this embodiment is the distance in the direction perpendicular to the substrate surface in the figure.

[0094] Furthermore, since the protruding structure 208 is located on the oxide layer 204 of the terminal region T, the portion of the first interlayer dielectric layer 209 located in the cell region C has a flat surface, while the portion of the first interlayer dielectric layer 209 located in the terminal region T has an uneven morphology, and the portion of the first interlayer dielectric layer 209 covering the protruding structure 208 is in a protruding shape. Also, the width of the portion of the first interlayer dielectric layer 209 in a protruding shape on each protruding structure 208 is a first width D; and the first width D satisfies the following formula: D=d1+2d2; wherein d1 is the width of the top surface of the protruding structure 208, and d2 is the width of the portion of the first interlayer dielectric layer 209 covering the side wall of the protruding structure 208. The width referred to in this embodiment is the distance in the direction parallel to the substrate surface in the figure.

[0095] Preferably, the material of the first interlayer dielectric layer 209 includes undoped silicate glass (Usable Size Grown, USG) material. Based on the characteristic of the material being ion-free, the substrate structure can be further protected to prevent diffusion of doped ions in the substrate.

[0096] Step 3 S30: Please refer to Figures 9 to 12 , removing the protruding portion of the first interlayer dielectric layer 209 and exposing the top surface of the protruding structure 208 to planarize the first interlayer dielectric layer 209 .

[0097] In one example, if Fig.10 As shown, the step three S30 specifically includes:

[0098] Sub-step one S301 : coating a first photoresist layer 210 on the first interlayer dielectric layer 209 .

[0099] Sub-step 2 S302 : using a first mask M1 to expose the first photoresist layer 210 and form a patterned first photoresist layer 211 to expose a portion of the first interlayer dielectric layer 209 that is in a protruding shape.

[0100] according to Figure 5 , Figure 6 , Fig.11 and Fig.12 It can be seen that the exposed and covered areas of the patterned first photoresist layer 211 and the patterned second photoresist layer 207 are opposite. Therefore, if the same first photomask M1 is used to reduce costs, the polarities of the first photoresist layer 210 and the second photoresist layer 206 are opposite. That is, if the first photoresist layer 210 is a positive photoresist, the second photoresist layer 206 is a negative photoresist; or, if the first photoresist layer 210 is a negative photoresist, the second photoresist layer 206 is a positive photoresist.

[0101] Further, according to Fig. 9 As shown, the width D of the protruding portion of the first interlayer dielectric layer 209 to be removed by etching is greater than the width d1 of the top surface of the protruding structure 208. If the same first photomask M1 is used to obtain different exposure widths, the light sensitivity of the first photoresist layer 210 should be different from the light sensitivity of the second photoresist layer 206. For example, Figure 5 , Figure 6 , Fig.11 and Fig.12 As shown, the first photoresist layer 210 is a positive photoresist, the second photoresist layer 206 is a negative photoresist, and the opening width of the first mask M1 toward the protruding structure 208 is equal to the width d1 of the top surface of the protruding structure 208, and the light sensitivity of the first photoresist layer 210 should be greater than the light sensitivity of the second photoresist layer 206. Under the same exposure adjustment, the width of the portion of the polysilicon layer 205 covered by the patterned second photoresist layer 207 is equal to the width d1 of the top surface of the protruding structure 208. The width of the portion of the first interlayer dielectric layer 209 exposed by the patterned first photoresist layer 211 is equal to the width of the portion of the first interlayer dielectric layer 209 in a protruding shape, that is, the first width D; and D=d1+2d2. Alternatively, when the first photoresist layer 206 is a negative photoresist, the second photoresist layer 210 is a positive photoresist, and the blocking width of the first mask M1 toward the protruding structure 208 is equal to the width d1 of the top surface of the protruding structure 208, the photosensitivity of the first photoresist layer 210 is less than the photosensitivity of the second photoresist layer 206, different exposure widths of the above-mentioned patterned first photoresist layer 211 and the patterned second photoresist layer 207 can also be obtained.

[0102] Sub-step three S303 : using the patterned first photoresist layer 211 as a barrier, etching away the protruding portion of the first interlayer dielectric layer 209 , and exposing the top surface of the protruding structure 208 , so as to planarize the first interlayer dielectric layer 209 .

[0103] See also Fig.12 and Fig.13 After the first interlayer dielectric layer 209 in the protruding shape is removed by etching, the first interlayer dielectric layer 209 located on the oxide layer 204 has a flat surface. Preferably, the thickness of the first interlayer dielectric layer 209 is equal to the thickness of the protruding structure 208, so the surface of the first interlayer dielectric layer 209 and the surface of the protruding structure 208 together constitute a flat surface. Based on this, the flat surface can avoid the presence of metal residues when the metal plug is subsequently formed, thereby avoiding problems such as short circuits in the device. And, after the first interlayer dielectric layer 209 in the protruding shape is removed by etching, the patterned first photoresist layer 211 is cleaned and removed.

[0104] In another example, Fig.14 and Fig.15 As shown, in order to remove the protruding portion of the first interlayer dielectric layer 209, a third photoresist layer 212 is first coated on the first interlayer dielectric layer 209, and the third photoresist layer 212 can be a positive photoresist or a negative photoresist. Then, a second photomask M2 is used to expose the third photoresist layer 212 and form a patterned third photoresist layer 213 to expose the protruding portion of the first interlayer dielectric layer 209. The light sensitivity of the third photoresist layer 212 can be equal to the light sensitivity of the second photoresist layer 216. Based on this, when the third photoresist layer 212 is a positive photoresist, the opening width of the second photomask M2 toward the protruding structure 208 is the first width D; or, when the third photoresist layer 212 is a negative photoresist, the shielding width of the second photomask M2 toward the protruding structure 208 can be the first width D. Therefore, the morphology of the patterned third photoresist layer 213 is consistent with the morphology of the patterned first photoresist layer 211. Then, the patterned third photoresist layer 213 is used as a barrier to etch away the protruding portion of the first interlayer dielectric layer 209, and the same Fig.13 The topographical features shown are: the top surface of the protruding structure 208 is exposed, and the remaining first interlayer dielectric layer 209 has a flat surface.

[0105] In another example, in order to remove the protruding portion of the first interlayer dielectric layer 209, a chemical mechanical polishing process can be directly used to remove the protruding portion of the first interlayer dielectric layer 209 and expose the top surface of the protruding structure 208, so that the remaining first interlayer dielectric layer 209 has a flat surface.

[0106] Step 4 S40: Please refer to Fig.16 and Fig.17 , a second interlayer dielectric layer 214 and a third interlayer dielectric layer 215 are sequentially formed on the top surfaces of the first interlayer dielectric layer 209 and the protruding structure 208 .

[0107] It is understandable that after performing the step three S30, the top surface of the protruding structure 208 will be exposed, or the top surface of the protruding structure 208 and part of its sidewall will be exposed. Therefore, it is necessary to deposit a second interlayer dielectric layer 214 to cover the protruding structure 208 to ensure electrical isolation of the protruding structure 208. And since the first interlayer dielectric layer 209 has a flat surface and its thickness is equal to or close to the thickness of the protruding structure 208, the second interlayer dielectric layer 214 covering the first interlayer dielectric layer 209 and the top surface of the protruding structure 208 also has a flat top surface. It should be noted that in the actual process, if a thicker interlayer dielectric layer is formed to completely cover the protruding structure 208 and keep the interlayer dielectric layer with a flat surface, the thickness of the interlayer dielectric layer needs to be as high as 2 to 3 times the thickness of the protruding structure 208, which is much thicker than the thickness of the first interlayer dielectric layer 209 and the second interlayer dielectric layer 214 in this embodiment. Based on this, the preparation method of the first interlayer dielectric layer 209 and the second interlayer dielectric layer 214 provided in this embodiment can not only obtain a flat dielectric layer surface, but also help reduce the preparation cost, which meets the development needs of device miniaturization. Preferably, the material of the second interlayer dielectric layer 214 is consistent with the material of the first interlayer dielectric layer 209, both including USG.

[0108] Furthermore, in order to optimize the electrical performance of the IGBT and enhance its durability and radial uniformity, the third interlayer dielectric layer 215 is formed on the surface of the second interlayer dielectric layer 214, and boron ions are doped in the third interlayer dielectric layer 215. Preferably, the material of the third interlayer dielectric layer 215 includes borophospho-silicate glass (BPSG) or boron-silicate glass (BSG).

[0109] It should be noted that if Fig.17As shown, since the first interlayer dielectric layer 209 and the second interlayer dielectric layer 214 have flat surfaces, the third interlayer dielectric layer 215 also has a flat surface.

[0110] Furthermore, after forming the third interlayer dielectric layer 215 , the preparation method further includes: forming a metal plug 218 at least on the side of the trench gate, and the metal plug 218 penetrates the first interlayer dielectric layer 209 , the second interlayer dielectric layer 214 and the third interlayer dielectric layer 215 .

[0111] Specifically, Fig.18 As shown, a plurality of contact holes 216 are formed by etching process. In the cell region C, in order to lead out the emitter, the contact hole 216 can be formed on the side of the trench gate, and the contact hole 216 extends into the first drift region 200 and penetrates the first interlayer dielectric layer 209, the second interlayer dielectric layer 214 and the third interlayer dielectric layer 215. In the terminal region T, the contact hole 216 can also be formed on the protruding structure 208 used as a temperature sensor, and the contact hole 216 extends into the protruding structure 208 and penetrates the second interlayer dielectric layer 214 and the third interlayer dielectric layer 215. Then, as Fig.19 As shown, a metal material layer 217 is formed on the flat surface of the third interlayer dielectric layer 215, and the metal material layer 217 fills and covers each of the contact holes 216. Finally, as shown in FIG. Fig. 20 As shown, an etching process is used to remove part of the metal material layer 217 on the surface of the third interlayer dielectric layer 215, and the metal material layer 217 in the contact hole 216 is retained to form each metal plug 218. Optionally, the metal material layer 217 is made of metal tungsten.

[0112] It can be understood that, since the top surface of the third interlayer dielectric layer 215 is flat, the problem of etching residues in the process of etching away part of the metal material layer 217 is effectively avoided, thereby avoiding the problem of device short circuit due to metal residues, which is beneficial to improving device performance.

[0113] Optionally, the etching process used in the above-mentioned method for preparing the insulated gate bipolar transistor can be a dry etching process or a wet etching process; and the deposition method used includes but is not limited to physical vapor deposition or chemical vapor deposition.

[0114] Based on the same concept, this embodiment also provides an insulated gate bipolar transistor. Fig. 20The semiconductor device includes: a substrate, a first interlayer dielectric layer 209 , a second interlayer dielectric layer 214 , a third interlayer dielectric layer 215 and a plurality of metal plugs 218 .

[0115] Specifically, the substrate includes a cell region C and a terminal region T; the cell region C is a main device region, and a trench gate is formed in the cell region C; the terminal region T surrounds the cell region C, and a protruding structure 208 is formed on the terminal region T. Preferably, a plurality of protruding structures 208 are formed on the terminal region T, and each of the protruding structures 208 is a field plate and / or a temperature sensor. Furthermore, an oxide layer 204 is formed on the surface of the substrate to protect the substrate; and the protruding structure 208 can be located on the oxide layer 204.

[0116] The first interlayer dielectric layer 209 covers the substrate surface and surrounds the sidewalls of the protruding structure 208. It can be understood that the first interlayer dielectric layer 209 does not cover the top surface of the protruding structure 208, but is only laid on the substrate surface and the peripheral sidewalls of the protruding structure 208. If the thickness of the first interlayer dielectric layer 209 is less than or equal to the thickness of the protruding structure 208, the first interlayer dielectric layer 209 has a flat surface.

[0117] The second interlayer dielectric layer 214 covers the exposed surfaces of the first interlayer dielectric layer 209 and the protruding structure 208. In view of the fact that the first interlayer dielectric layer 209 has a flat surface and the thickness of the first interlayer dielectric layer 209 is less than or equal to the thickness of the protruding structure 208, the second interlayer dielectric layer 214 also has a flat surface, or the part of the second interlayer dielectric layer 214 located on the protruding structure 208 is only slightly higher than the surface of the remaining part of the second interlayer dielectric layer 214. Preferably, the material of the first interlayer dielectric layer 209 and the material of the second interlayer dielectric layer 214 both include USG to have a good electrical isolation effect. Compared with directly forming a dielectric layer covering the protruding structure 208 on the protruding structure 208, the combination of the first interlayer dielectric layer 209 and the second interlayer dielectric layer 214 provided in this embodiment not only makes the overall undulation of the film layer lower and the flatness better, but also can ensure the electrical isolation effect of the protruding structure 208.

[0118] The third interlayer dielectric layer 215 covers the surface of the second interlayer dielectric layer 214. Since the second interlayer dielectric layer 214 has a flat surface, the third interlayer dielectric layer 215 also has a flat surface. The material of the third interlayer dielectric layer 215 includes BPSG or BSG, which is conducive to optimizing device performance.

[0119] A plurality of metal plugs 218 are used to realize electrical lead-out. Fig. 20 As shown, the metal plug 218 located in the cell region C is located at the side of the trench gate, and sequentially penetrates the third interlayer dielectric layer 215, the second interlayer dielectric layer 214 and the first interlayer dielectric layer 209, and extends into the substrate. When part of the protruding structure 208 in the terminal region T is a temperature sensor, part of the metal plug 215 sequentially penetrates the third interlayer dielectric layer 215 and the second interlayer dielectric layer 214, and extends into the protruding structure 208.

[0120] Preferably, the insulated gate bipolar transistor is prepared by the above-mentioned method for preparing the insulated gate bipolar transistor.

[0121] In summary, the insulated gate bipolar transistor and the preparation method thereof provided in this embodiment divide the process of the interlayer dielectric layer into three steps, firstly forming the first interlayer dielectric layer 209, and removing the protruding part of the first interlayer dielectric layer 209 located on the protruding structure 208, so that the top surface of the remaining first interlayer dielectric layer 209 has a flat morphology. Then, the second interlayer dielectric layer 214 and the third interlayer dielectric layer 215 are sequentially formed on the surface of the first interlayer dielectric layer 209 and the protruding structure 208. Among them, because the first interlayer dielectric layer 209 has a flat top surface, and the first interlayer dielectric layer 209 is close to the thickness of the protruding structure 208, the second interlayer dielectric layer 214 and the third interlayer dielectric layer 215 also have a flat surface. Based on this, in the process of forming the metal plug 218, it is not easy for metal material to remain on the flat surface, which effectively avoids the problem of device short circuit caused by metal residue, and is conducive to improving the performance and yield of the device.

[0122] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing an insulated gate bipolar transistor, characterized in that: include: A substrate is provided; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region; forming a first interlayer dielectric layer on the surfaces of the substrate and the protruding structure, wherein a portion of the first interlayer dielectric layer covering the surface of the protruding structure is in a protruding shape; Removing a portion of the first interlayer dielectric layer in a protruding shape and exposing a top surface of the protruding structure to planarize the first interlayer dielectric layer; A second interlayer dielectric layer and a third interlayer dielectric layer are sequentially formed on top surfaces of the first interlayer dielectric layer and the protrusion structure.

2. The method for preparing an insulated gate bipolar transistor according to claim 1, characterized in that: The process of removing the protruding portion of the first interlayer dielectric layer and exposing the top surface of the protruding structure to planarize the first interlayer dielectric layer includes: coating a first photoresist layer on the first interlayer dielectric layer; Using a first photomask to expose the first photoresist layer and form a patterned first photoresist layer to expose a portion of the first interlayer dielectric layer in a convex shape; The patterned first photoresist layer is used as a barrier to etch and remove a portion of the first interlayer dielectric layer in a protruding shape, and expose a top surface of the protruding structure to planarize the first interlayer dielectric layer.

3. The method for preparing an insulated gate bipolar transistor according to claim 2, characterized in that: The process of forming the protruding structure on the terminal region includes: forming a polysilicon layer on the substrate; coating a second photoresist layer on the polysilicon layer; Using the first photomask to expose the second photoresist layer and form a patterned second photoresist layer to cover a portion of the polysilicon layer located on the terminal region and expose the remaining portion of the polysilicon layer; The patterned second photoresist layer is used as a barrier to etch and remove the exposed portion of the polysilicon layer; and the remaining portion of the polysilicon layer is the protruding structure.

4. The method for preparing an insulated gate bipolar transistor according to claim 3, characterized in that: The first photoresist layer is a positive photoresist, the second photoresist layer is a negative photoresist, and the opening width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; Alternatively, the first photoresist layer is a negative photoresist, the second photoresist layer is a positive photoresist, and the shielding width of the first photomask toward the protruding structure is equal to the width of the top surface of the protruding structure; as well as, The photosensitivity of the first photoresist layer is different from the photosensitivity of the second photoresist layer, so that the width of the portion of the polysilicon layer covered by the patterned second photoresist layer is equal to the width of the top surface of the protruding structure; and the width of the portion of the first interlayer dielectric layer exposed by the patterned first photoresist layer is a first width, and the first width D satisfies the following formula: D = d1 + 2d2; Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

5. The method for preparing an IGBT device according to claim 1 or 3, characterized in that: The raised structure includes a field plate and / or a temperature sensor.

6. The method for preparing an insulated gate bipolar transistor according to claim 1, characterized in that: The process of removing the protruding portion of the first interlayer dielectric layer and exposing the top surface of the protruding structure to planarize the first interlayer dielectric layer includes: coating a third photoresist layer on the first interlayer dielectric layer; Using a second photomask to expose the third photoresist layer and form a patterned third photoresist layer to expose a portion of the first interlayer dielectric layer in a protruding shape; Using the patterned third photoresist layer as a barrier, etching and removing the protruding portion of the first interlayer dielectric layer, and exposing the top surface of the protruding structure, so as to planarize the first interlayer dielectric layer; The third photoresist layer is a positive photoresist, and the opening width of the second photomask toward the protruding structure is a first width D; or the third photoresist layer is a negative photoresist, and the shielding width of the second photomask toward the protruding structure is a first width D; and the first width D satisfies the following formula: D = d1 + 2d2; Wherein, d1 is the width of the top surface of the protruding structure, and d2 is the width of the first interlayer dielectric layer covering a side wall of the protruding structure.

7. The method for preparing an insulated gate bipolar transistor according to claim 1, characterized in that: A chemical mechanical polishing process is used to remove a portion of the first interlayer dielectric layer in a protruding shape and expose a top surface of the protruding structure to planarize the first interlayer dielectric layer.

8. The method for preparing an insulated gate bipolar transistor according to claim 1, characterized in that: The material of the first interlayer dielectric layer and the material of the second interlayer dielectric layer both include USG; the material of the third interlayer dielectric layer includes BPSG or BSG.

9. The method for preparing an insulated gate bipolar transistor according to claim 1, characterized in that: The thickness of the first interlayer dielectric layer is less than or equal to the thickness of the protruding structure.

10. The method for manufacturing an insulated gate bipolar transistor according to claim 1, after forming the second interlayer dielectric layer, the method for manufacturing an insulated gate bipolar transistor further comprises: A metal plug is formed at least on the side of the trench gate, and the metal plug penetrates the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer.

11. An insulated gate bipolar transistor, characterized in that: include: A substrate; the substrate comprises a cell region and a terminal region, a trench gate is formed in the cell region, and a protrusion structure is formed on the terminal region; a first interlayer dielectric layer; The first interlayer dielectric layer covers the surface of the substrate and surrounds the sidewalls of the protruding structure; a second interlayer dielectric layer; The second interlayer dielectric layer covers the first interlayer dielectric layer and the exposed surface of the protruding structure; a third interlayer dielectric layer; The third interlayer dielectric layer covers a surface of the second interlayer dielectric layer.

12. The insulated gate bipolar transistor according to claim 11, characterized in that: The material of the first interlayer dielectric layer and the material of the second interlayer dielectric layer both include USG; the material of the third interlayer dielectric layer includes BPSG or BSG.

13. The insulated gate bipolar transistor according to claim 11, characterized in that: The thickness of the first interlayer dielectric layer is less than or equal to the thickness of the protruding structure.

14. The insulated gate bipolar transistor according to claim 11, wherein: The raised structure includes a field plate and / or a temperature sensor.

15. The insulated gate bipolar transistor according to claim 11, characterized in that: The insulated gate bipolar transistor further includes: a plurality of metal plugs; at least some of the metal plugs are located on the sides of the trench gate and penetrate the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer.

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