A low on-resistance trench gate silicon carbide VDMOS and a preparation method thereof

Abstract

The invention provides a low on-resistance trench gate silicon carbide VDMOS and a preparation method thereof, which comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; ion implanting to form a low resistance region; forming a barrier layer, etching, and ion implanting to form a P+ well region, a P-type well region, and an N-type source region; reforming the barrier layer, etching, and depositing an insulating medium; reforming the barrier layer, etching, and depositing metal to form a suspended gate; reforming the barrier layer, etching the barrier layer, and depositing an insulating medium layer; reforming the barrier layer, etching, and depositing metal to form a gate metal layer; reforming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the P-type well region, depositing metal to form a source metal layer, and removing the barrier layer to complete the preparation, thereby reducing the gate-drain capacitance, improving the switching speed of the device, and reducing the switching loss.

Description

Technical Field

[0001] The invention relates to a low on-resistance trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a low on-resistance trench gate silicon carbide VDMOS and a preparation method thereof, so as to reduce gate-drain capacitance, increase the switching speed of the device and reduce switching loss.

[0004] In a first aspect, the present invention provides a method for preparing a low on-resistance trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2, forming a low resistance region by ion implantation into the drift layer;

[0007] Step 3, forming a barrier layer, etching the barrier layer to form a through hole, and forming a first well region by ion implantation into the low resistance region;

[0008] Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a second well region, wherein the P+ well region includes the first well region and the second well region;

[0009] Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the low resistance area, forming a groove in the low resistance area, and depositing an insulating medium;

[0012] Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating medium, and then deposit metal to form a suspended gate;

[0013] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer;

[0014] Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer to form a groove, deposit metal, and form a gate metal layer;

[0015] Step 11: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0016] In a second aspect, the present invention provides a low on-resistance trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a low on-resistance trench gate silicon carbide VDMOS according to the first aspect.

[0017] The advantages of the present invention are:

[0018] 1. The present invention adopts the structure of the P-type well region and the P+ well region, wherein the P-type well region wraps the N-type source region, completes the inversion of the device gate to the region, and realizes the gate function; the P+ well region wraps the P-type well region, and the doping concentration of the P+ well region is higher than that of the P-type well region, thereby ensuring the voltage withstand capability of the pn junction inside the device;

[0019] Second, the present invention constructs a floating gate structure, which can avoid the gate reliability problem caused by the electric field concentration at the corner of the device trench gate. At the same time, the floating gate can shield the parasitic capacitance of the gate and drain of the device, thereby reducing the gate-drain capacitance of the device, improving the switching speed of the device, and reducing the switching loss;

[0020] 3. Low resistance regions are constructed on the left and right sides and bottom of the floating gate of the device. The low resistance regions are distributed throughout the entire layer below the insulating dielectric layer, which can effectively realize the current equalization inside the device and reduce the on-resistance of the device. The low resistance regions distributed on the left and right sides of the insulating dielectric layer can effectively reduce the on-resistance from the N-type source region through the inversion region of the P-type well region to the bottom of the insulating dielectric when the device is turned on;

[0021] 4. The low resistance regions on both sides of the insulating dielectric layer are only distributed in a very small width and do not affect the voltage withstand capability of the device constructed by the P+ well region of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0023] Figure 1 The schematic diagram of a low on-resistance trench gate silicon carbide VDMOS of the present invention is shown.

[0024] Figure 2 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 1 .

[0025] Figure 3 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 2 .

[0026] Figure 4 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 3 .

[0027] Figure 5 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 4 .

[0028] Figure 6 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 5 .

[0029] Figure 7 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 6 .

[0030] Figure 8 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 7 .

[0031] Fig. 9 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 8 .

[0032] Fig.10 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 9 .

[0033] Fig.11 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 10 .

[0034] Fig.12 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 10 one.

[0035] Fig.13 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 10 two.

[0036] Fig.14 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 10 three.

[0037] Fig.15 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 10 Four.

[0038] Fig.16 A cross-sectional view of the process of manufacturing a low on-resistance trench gate silicon carbide VDMOS according to the present invention Figure 10 five. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] like Figures 1 to 16 As shown, the embodiment of the present application provides a method for preparing a low on-resistance trench gate silicon carbide VDMOS, comprising the following steps:

[0045] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0046] Step 2, forming a low resistance region 3 by performing ion implantation on the drift layer 2;

[0047] Step 3, forming a barrier layer a, etching the barrier layer a to form a through hole, and forming a first well region 41 by ion implantation into the low resistance region 3;

[0048] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the drift layer 2 to form a second well region 42, the P+ well region 4 includes a first well region 41 and a second well region 42;

[0049] Step 5, removing the original barrier layer a, re-forming the barrier layer, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 5;

[0050] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the P-type well region 5 to form an N-type source region 51;

[0051] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the drift layer 2 and the low resistance region 3, forming a groove 311 in the low resistance region 3, and depositing an insulating medium;

[0052] Step 8: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the insulating medium, and then deposit metal to form a floating gate 61;

[0053] Step 9, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and depositing to form an insulating dielectric layer 6;

[0054] Step 10, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the insulating dielectric layer 6 to form a groove 62, and depositing metal to form a gate metal layer 7;

[0055] Step 11, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 2 to the upper side of the P-type well region 5, deposit metal to form a source metal layer 8, remove the barrier layer a, and complete the preparation.

[0056] In this embodiment, preferably, the doping concentration of the P+ well region 4 is greater than the doping concentration of the P-type well region 5 .

[0057] In this embodiment, preferably, the width of the gate metal layer 7 is greater than the width of the floating gate 61 .

[0058] In this embodiment, preferably, the lower side surface of the gate metal layer 7 and the lower side surface of the P-type well region 5 are located in the same plane.

[0059] In this embodiment, preferably, the distance between the floating gate 61 and the lower side of the gate metal layer 7 is 200-500 nm.

[0060] In this embodiment, preferably, the doping concentration of the low resistance region 3 is greater than the doping concentration of the drift layer 2 .

[0061] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0062] Silicon carbide substrate 1,

[0063] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0064] A low resistance region 3, wherein the lower side of the low resistance region 3 is connected to the drift layer 2, a protrusion 31 is provided on the low resistance region 3, and a groove 311 is provided in the protrusion 31;

[0065] A P+ well region 4, wherein the lower side of the P+ well region 4 is connected to the upper side of the low resistance region 3, and the inner side of the P+ well region 4 is connected to the outer side of the protrusion 31;

[0066] A P-type well region 5, wherein the outer side of the P-type well region 5 is connected to the P+ well region 4, and the lower side of the P-type well region 5 is connected to the upper side of the protrusion 31 and the P+ well region 4; an N-type source region 51 is provided on the P-type well region 5;

[0067] an insulating dielectric layer 6, the insulating dielectric layer 6 passes through the N-type source region 51 and the P-type well region 5, and the lower part of the insulating dielectric layer 6 is arranged in the groove 311; a floating gate 61 and a trench 62 are arranged in the insulating dielectric layer 6, and the trench 62 is located above the floating gate 61;

[0068] A gate metal layer 7, wherein the gate metal layer 7 is disposed in the groove 62;

[0069] A source metal layer 8, wherein the source metal layer 8 is respectively connected to the N-type source region 51, the P-type well region 5 and the P+ well region 4;

[0070] And, a drain metal layer 9 , wherein the upper side of the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0071] In another embodiment, the silicon carbide substrate 1, the drift layer 2 and the low resistance region 3 are all N-type, the doping concentration of the silicon carbide substrate 1 is 2-8e18cm-3, the doping concentration of the n-type drift layer 2 is 1-5e16cm-3, the doping concentration of the n-type low resistance region 3 is 1-5e17cm-3, the doping concentration of the P+ well region 4 is 1-2e18cm-3, the doping concentration of the P-type well region 5 is 1-5e17cm-3, the insulating dielectric layer 6 is silicon dioxide, and the doping concentration of the N-type source region 51 is 2-8e18cm-3; the doping concentration of the silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 9 to reduce the overall on-resistance of the device; the doping concentration of the n-type drift layer 2 is the device A compromise between reverse withstand voltage and on-resistance; the doping concentration design of the n-type low resistance region 3 has two considerations. One is to achieve current equalization in the device body and reduce the on-resistance of the device; the other is to ensure the formation of a pn junction with the P+ well region 4. Since the device adopts a floating gate 61, the thickness of the insulating medium on the left and right sides of the floating gate 61 is large, and the gate reliability of the device is high, so there is no need for an additional p-type shielding area, so that high doping of the n-type low resistance region 3 can be set on the left and right sides and below the floating gate 61 to reduce the on-resistance of the device; the P+ well region 4 can effectively achieve the pn junction withstand voltage of the device and construct the device body diode; the relatively low doping of the P-type well region 5 can reduce the gate inversion voltage of the device, thereby reducing the driving loss of the device.

[0072] The thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the n-type drift layer 2 is 30-100 μm, and it is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the contact part of the n-type low resistance region 3 and the P+ well region 4 is 500 nm, the thickness of the low resistance region 3 is 1500 nm, the thickness of the P+ well region 4 is 1500 nm, the thickness of the P-type well region 5 is 500 nm, the thickness of the N-type source region is 200 nm, the width of the N-type source region 51 is 50-70% of the width of the P-type well region 5, and the width of the P-type well region 5 accounts for 10% of the device cell. 50-60%, the width of the contact portion between the P+ well region 4 and the source metal layer 8 is 20-40% of the width of the device cell, the width of the insulating dielectric layer accounts for 10% of the device cell, the width of the device cell is 100-500 μm, the total width of the insulating dielectric on the left and right sides of the gate metal layer 7 is 50 nm, the distance between the gate metal layer 7 and the floating gate 61 is 200-500 nm, the total width of the insulating dielectric on the left and right sides of the floating gate 61 is 500-1000 nm, and the thickness of the insulating dielectric at the bottom of the floating gate 61 is 100-200 nm;

[0073] The P-type well region 5 of this embodiment wraps the bottom and side of the N-type source region 51, completes the inversion of the device gate metal layer 7 to this region, and realizes the gate function. Since the doping concentration of the P-type well region 5 is low, it is easier for the gate metal layer 7 to control the inversion, and the gate capacitance is smaller, which can reduce the driving loss of the device and improve the switching speed of the device. The P+ well region 4 wraps the side and part of the bottom of the P-type well region 5, and ensures the pn junction withstand voltage capability inside the device by increasing the doping concentration;

[0074] The device has a floating gate 61 structure, and there is a thicker insulating medium under the device gate metal layer 7, which can withstand higher voltages and avoid gate reliability issues caused by electric field concentration at the corners of the device trench gate. At the same time, the floating gate 61 can shield the parasitic capacitance of the gate and drain of the device, thereby reducing the gate-drain capacitance of the device, increasing the switching speed of the device, and reducing switching losses.

[0075] An n-type low-resistance region 3 is constructed on the left and right sides and bottom of the floating gate 61 of the device. The low-resistance region 3 is distributed throughout the bottom layer of the device's insulating dielectric, which can effectively achieve current equalization within the device and reduce the on-resistance of the device. The low-resistance region 3 distributed on the left and right sides of the gate insulating dielectric layer 6 can effectively reduce the on-resistance from the N-type source region 51 through the inversion region of the P-type well region 5 to the bottom of the insulating dielectric layer 6 when the device is turned on. The n-type low-resistance region 3 distributed on both sides of the device's gate insulating dielectric layer 6 is only distributed in a very small width, which does not affect the device's voltage resistance capability constructed by the P+ well region 4 of the device.

[0076] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a low on-resistance trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a low resistance region by ion implantation into the drift layer; Step 3, forming a barrier layer, etching the barrier layer to form a through hole, and forming a first well region by ion implantation into the low resistance region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a second well region, wherein the P+ well region includes the first well region and the second well region; Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the low resistance area, forming a groove in the low resistance area, and depositing an insulating medium; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating medium, and then deposit metal to form a suspended gate; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer to form a groove, deposit metal, and form a gate metal layer; Step 11, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation; The silicon carbide substrate, the drift layer and the low resistance region are all N-type; the doping concentration of the low resistance region is greater than the doping concentration of the drift layer.

2. The method for preparing a low on-resistance trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P+ well region is greater than the doping concentration of the P-type well region.

3. The method for preparing a low on-resistance trench gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the gate metal layer is greater than the width of the floating gate.

4. The method for preparing a low on-resistance trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the gate metal layer and the lower side surface of the P-type well region are located in the same plane.

5. The method for preparing a low on-resistance trench gate silicon carbide VDMOS according to claim 1, characterized in that: The distance between the floating gate and the lower side of the gate metal layer is 200-500 nm.

6. A low on-resistance trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods described in claim 1 to claim 5.

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