A heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof

Abstract

The invention provides a heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof, which comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, etching, and ion implanting to form a P-type well region, an N-type source region, and a shielding region; reforming the barrier layer, etching, and depositing an insulating medium to form a first insulating medium region; reforming the barrier layer, etching, and forming a groove; reforming the barrier layer, etching, and depositing metal to form a suspended gate; reforming the barrier layer, etching, and depositing an insulating medium to form a second insulating medium region; reforming the barrier layer, etching, and depositing metal to form a gate metal layer; reforming the barrier layer, etching, and depositing metal to form a source metal layer, and removing the barrier layer to complete the preparation, thereby achieving the characteristics of low switching loss, high switching speed, and low on-resistance.

Description

Technical Field

[0001] The invention relates to a heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion, etc. For silicon carbide VDMOS, the device performance requirements in different fields have different emphases, but the overall requirements are lower on-resistance, faster switching speed, and higher reliability. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof, which achieves the characteristics of low switching loss, high switching speed and low on-resistance.

[0004] In a first aspect, the present invention provides a method for preparing a heterogeneous trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type well region;

[0007] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region;

[0008] Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a masking area;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the masking area to the drift layer, depositing an insulating medium, and forming a first insulating medium area;

[0010] Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the masking area to form a groove;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a suspended gate;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing an insulating medium, forming a second insulating medium region, wherein the insulating medium layer includes a first insulating medium region and a second insulating medium region;

[0013] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a groove, depositing metal, and forming a gate metal layer;

[0014] Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a heterogeneous trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a heterogeneous trench gate silicon carbide VDMOS according to the first aspect.

[0016] The advantages of the present invention are:

[0017] 1. The gate metal layer of the present invention increases the gate dielectric thickness from the middle region of the device gate to the drain without affecting the characteristics of the device gate to the P-type well region, thereby reducing the gate-drain capacitance of the device, reducing the Maitreya capacitance of the device, and improving the switching speed of the device;

[0018] Second, the gate metal layer reduces the gate-drain capacitance of the device, but it will affect the carrier concentration at the bottom of the device's insulating medium, and thus affect the device's on-resistance. Therefore, a floating gate is designed. The floating gate can form electrons under the insulating medium corresponding to the floating gate of the device through the charge effect of the capacitor, thereby achieving the effect of reducing the device's on-resistance.

[0019] 3. The bottom of the masking area is located in the same plane as the bottom of the insulating medium, and the top is located in the same plane as the bottom of the floating gate. This can effectively improve the gate reliability of the device while reducing the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 The schematic diagram of a heterogeneous trench gate silicon carbide VDMOS of the present invention.

[0022] Figure 2 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0023] Figure 3 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0024] Figure 4 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 3.

[0025] Figure 5 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0026] Figure 6 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0027] Figure 7 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0028] Figure 8 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0029] Fig. 9 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0030] Fig.10 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0031] Fig.11 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0032] Fig.12 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 10 one.

[0033] Fig.13 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 10 two.

[0034] Fig.14 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 10 three.

[0035] Fig.15 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 10 Four.

[0036] Fig.16 A cross-sectional view of the process of a heterogeneous trench gate silicon carbide VDMOS of the present invention Figure 10 five. DETAILED DESCRIPTION

[0037] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0041] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] like Figures 1 to 16 As shown, the embodiment of the present application provides a method for preparing a heterogeneous trench gate silicon carbide VDMOS, comprising the following steps:

[0043] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0044] Step 2, forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 4;

[0045] Step 3, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the P-type well region 4 to form an N-type source region 41;

[0046] Step 4, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the drift layer 2 to form a masking area 3;

[0047] Step 5, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the masking area 3 to the drift layer, depositing an insulating medium, and forming a first insulating medium area 53;

[0048] Step 6, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer to form a through hole, and etching the drift layer 2 to the upper side of the masking area 3 to form a groove 21;

[0049] Step 7, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing metal, and forming a floating gate 51;

[0050] Step 8, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing an insulating dielectric to form a second insulating dielectric region 54, the insulating dielectric layer 5 includes a first insulating dielectric region 53 and a second insulating dielectric region 54;

[0051] Step 9, removing the original barrier layer 9, reforming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the insulating dielectric layer 5 to form a first channel 521, depositing metal to form a first gate metal region 61; removing the original barrier layer 9, reforming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the insulating dielectric layer 5 to form a second channel 522, depositing metal to form a second gate metal region 62, the trench 52 includes the first channel 521 and the second channel 522, and the gate metal layer 6 includes the first gate metal region 61 and the second gate metal region 62;

[0052] Step 10, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and etch the drift layer 2 to the upper side of the P-type well region 4, deposit metal to form a source metal layer 7, remove the barrier layer 9, and complete the preparation.

[0053] In this embodiment, preferably, the groove 52 is in an inverted concave shape, and the lower side surface of the gate metal layer 6 and the upper side surface of the floating gate 51 are located in the same plane.

[0054] In this embodiment, preferably, the lower side of the floating gate 51 and the upper side of the masking area 3 are located in the same plane.

[0055] In this embodiment, preferably, the thickness of the masking area 3 is greater than the thickness of the floating gate 51 .

[0056] In this embodiment, preferably, the upper side surface of the floating gate 51 is lower than the lower side surface of the P-type well region 4 .

[0057] In this embodiment, preferably, the doping concentration of the masking region 3 is greater than the doping concentration of the drift layer 2 .

[0058] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0059] Silicon carbide substrate 1,

[0060] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a groove 21 is provided in the drift layer 2;

[0061] A masking region 3, wherein the masking region 3 is disposed in the groove 21, and the lower side surface and the outer side surface of the masking region 3 are both connected to the drift layer 2;

[0062] A P-type well region 4, the lower side of the P-type well region 4 is connected to the upper side of the drift layer 2; an N-type source region 41 is provided on the P-type well region 4;

[0063] An insulating dielectric layer 5, wherein the lower portion of the insulating dielectric layer 5 is disposed in the groove 21, and the insulating dielectric layer 5 is connected to the upper side and the inner side of the masking area 3, and the outer side of the insulating dielectric layer 5 is respectively connected to the inner side of the P-type well area 4 and the inner side of the N-type source area 41, a floating gate 51 is disposed in the insulating dielectric layer 5, and a groove 52 is disposed on the insulating dielectric layer 5, and the floating gate 51 is located above the masking area 3;

[0064] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 52;

[0065] A source metal layer 7, wherein the source metal layer 7 is connected to the P-type well region 4 and the N-type source region 41 respectively;

[0066] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0067] In another embodiment, the silicon carbide substrate 1 and the drift layer 2 are N-type; the masking region 3 is P-type; the doping concentration of the silicon carbide substrate 1 is 2-8e18cm -3 The doping concentration of the drift layer 2 is 1-5e17cm -3 The doping concentration of the P-type well region 4 is 1-5e18cm -3 The doping concentration of the masking area 3 is 3-6e17cm -3 The material of the insulating dielectric layer 5 can be silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm -3 ; The concentration of the silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the masking area 3 is to protect the electric field concentration at the gate corner of the device and improve the gate reliability of the device; the P-type well area 4 is to form the gate switching characteristics of the device and form an ohmic contact with the source metal layer to construct the body diode of the device; the concentration of the N-type source area 41 is to reduce the source contact resistance of the device and reduce the on-resistance of the device.

[0068] The thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the drift layer 2 is 30-100 μm, and it is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The width of the N-type source region 41 is 40-60% of the width of the P-type well region 4; the width of the P-type well region 4 accounts for 80-90% of the width of the device cell, the width of the device cell is 100-500 μm, the thickness of the source metal layer 7 is 300 nm, the thickness of the N-type source region 41 is 200 nm, the thickness of the P-type well region 4 is 500 nm, the thickness of the gate metal layer 6 is 850 nm, and the top thickness of the gate metal layer 6 is 2 00nm, the thickness of the insulating medium from the top of the inner side of the gate metal layer 6 to the top of the floating gate 51 is 650nm, the thickness of the floating gate 51 is 200nm, the thickness of the masking area 3 is 300nm, and the distance between the outer side of the gate metal layer 6 and the inner side of the P-type well region 4 is 50nm; the gate metal layer 6 of the present invention increases the thickness of the insulating medium from the middle area of ​​the device gate to the drain without affecting the characteristics of the device gate to the P-type well region 4, thereby reducing the gate-drain capacitance of the device, reducing the Maitreya capacitance of the device, reducing the switching loss of the device, and improving the switching speed of the device;

[0069] The gate metal layer 6 reduces the gate-drain capacitance of the device, but it will affect the carrier concentration at the bottom of the device insulating medium, thereby affecting the device on-resistance. Therefore, a floating gate is designed. The floating gate 51 can form electrons under the insulating medium corresponding to the floating gate 51 of the device through the charge effect of the capacitor, thereby achieving the effect of reducing the device on-resistance. The floating gate 51 can increase the carrier concentration at its bottom and at the same time increase the carrier concentration from the N-type source region 41 to the shielding region 3 of the device through the insulating medium on the left and right sides, thereby reducing the device on-resistance.

[0070] In order to improve the reliability of the trench gate of the device, a masking area 3 is designed. The lower side of the masking area 3 is located in the same plane as the lower side of the insulating dielectric layer 5, and the upper side of the masking area 3 is located in the same plane as the lower side of the floating gate 51. This can effectively improve the gate reliability of the device while reducing the process difficulty.

[0071] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a heterogeneous trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type well region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a masking area; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the masking area to the drift layer, depositing an insulating medium, and forming a first insulating medium area; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the masking area to form a groove; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a floating gate, wherein the lower side of the floating gate and the upper side of the masking area are located in the same plane; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing an insulating medium, forming a second insulating medium region, wherein the insulating medium layer includes a first insulating medium region and a second insulating medium region; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a groove, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a heterogeneous trench gate silicon carbide VDMOS according to claim 1, characterized in that: The step 9 is specifically as follows: removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a first channel, depositing metal to form a first gate metal region; removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a second channel, depositing metal to form a second gate metal region, the groove includes the first channel and the second channel, the gate metal layer includes the first gate metal region and the second gate metal region, the gate metal layer is an inverted concave shape, and the lower side surface of the gate metal layer and the upper side surface of the floating gate are located in the same plane.

3. The method for preparing a heterogeneous trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the masking region is greater than the thickness of the floating gate.

4. The method for preparing a heterogeneous trench gate silicon carbide VDMOS according to claim 1, characterized in that: The upper side surface of the floating gate is lower than the lower side surface of the P-type well region.

5. The method for preparing a heterogeneous trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the masking region is greater than the doping concentration of the drift layer.

6. A heterogeneous trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods described in claim 1 to claim 5.

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