A trench gate silicon carbide VDMOS with suppressed bipolar degradation and a preparation method thereof

Abstract

This invention provides a trench-gate silicon carbide VDMOS for suppressing bipolar degradation and its fabrication method, comprising: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a first drift layer; epitaxially growing above the first drift layer to form a second drift layer; forming a barrier layer, etching, and ion implantation to form a buffer zone, a P-type well region, and an N-type source region; reforming the barrier layer, etching, and depositing an insulating dielectric; reforming the barrier layer, etching, and depositing metal to form a floating gate; reforming the barrier layer, etching, and depositing to form a gate dielectric layer; reforming the barrier layer, etching, and depositing metal to form a gate metal layer; reforming the barrier layer, etching, and forming a source metal layer; removing the barrier layer to complete the fabrication; by designing the gate structure and body diode structure, the feature of suppressing the bipolar degradation effect of the device is achieved.

Description

Technical Field

[0001] The invention relates to a trench gate silicon carbide VDMOS capable of suppressing bipolar degradation and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields. The suppression of bipolar degradation of VDMOS (vertical double diffused metal oxide semiconductor) refers to a degradation phenomenon that may occur in the body diode of VDMOS devices under certain conditions. This degradation phenomenon mainly refers to the propagation of stacking faults at the basal plane dislocation (BPD) under bipolar operating conditions due to the energy released by the recombination of electrons and holes. This propagation eventually leads to a reduction in the effective active area of ​​the chip, thereby affecting the performance of the device. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a trench gate silicon carbide VDMOS that suppresses bipolar degradation and a preparation method thereof, and the characteristic of suppressing the bipolar degradation effect of the device is achieved by designing the gate structure and the body diode structure.

[0004] In a first aspect, the present invention provides a method for preparing a trench gate silicon carbide VDMOS for suppressing bipolar degradation, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a first drift layer;

[0006] Step 2, epitaxially growing on the first drift layer to form a second drift layer;

[0007] Step 3, forming a barrier layer on the second drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a buffer zone;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second drift layer to form a P-type well region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the second drift layer to the buffer zone, and deposit an insulating medium;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating medium to form a groove, and depositing metal to form a suspended gate;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing an insulating dielectric, and forming a gate dielectric layer;

[0013] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the gate dielectric layer to form a groove, depositing metal, and forming a gate metal layer;

[0014] Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift layer, depositing metal, and forming a first source metal region;

[0015] Step 11, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the second drift layer to the upper side of the P-type well area, deposit metal to form a second source metal area, the source metal layer includes the first source metal area and the second source metal area, remove the barrier layer, and complete the preparation.

[0016] In a second aspect, the present invention provides a trench gate silicon carbide VDMOS for suppressing bipolar degradation, wherein the silicon carbide VDMOS is prepared by the method for preparing a trench gate silicon carbide VDMOS for suppressing bipolar degradation described in the first aspect.

[0017] The advantages of the present invention are:

[0018] 1. The source metal layer of the present invention is parallel in the contact area with the top of the N-type source region and the top of the P-type well region, connected to the side of the P-type well region, and the bottom surface of the source metal layer is flush with the bottom surface of the P-type well region. This structure can effectively reduce the pn junction area between the P-type well region and the second drift layer inside the device, thereby reducing the energy release caused by the recombination of electrons and holes, thereby inhibiting bipolar degradation;

[0019] Second, the present invention constructs a Schottky diode, which is a single-carrier conductive diode, thereby suppressing the parasitic pn junction diode of the traditional silicon carbide VDMOS, and the energy release of reverse recovery caused by bipolar conduction, thereby suppressing the bipolar effect;

[0020] 3. A buffer zone is constructed under the floating gate of the present invention, and the outer side surface of the buffer zone is flush with the outer side surface of the P-type well region. By increasing the doping concentration in the buffer zone, the energy generated by the electron-hole recombination between the P-type well region and the second drift layer can be consumed, thereby avoiding the energy from moving to the silicon carbide substrate, thereby inhibiting the defects of the silicon carbide substrate from extending upward and inhibiting the bipolar degradation effect of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0022] Figure 1 The schematic diagram of the trench gate silicon carbide VDMOS for suppressing bipolar degradation is provided in the present invention.

[0023] Figure 2 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 1 .

[0024] Figure 3 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 2 .

[0025] Figure 4 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 3 .

[0026] Figure 5 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 4 .

[0027] Figure 6 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 5 .

[0028] Figure 7 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 6 .

[0029] Figure 8 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 7 .

[0030] Fig. 9 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 8 .

[0031] Fig.10 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 9 .

[0032] Fig.11 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 .

[0033] Fig.12 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 one.

[0034] Fig.13A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 two.

[0035] Fig.14 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 three.

[0036] Fig.15 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 Four.

[0037] Fig.16 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 five.

[0038] Fig.17 A cross-sectional view of the process of a trench gate silicon carbide VDMOS for suppressing bipolar degradation according to the present invention Figure 10 six. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] like Figures 1 to 17 As shown, the embodiment of the present application provides a method for preparing a trench gate silicon carbide VDMOS that suppresses bipolar degradation, comprising the following steps:

[0045] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially growing on the side of the silicon carbide substrate 1 to form a first drift layer 2;

[0046] Step 2, epitaxially growing on the first drift layer 2 to form a second drift layer 3;

[0047] Step 3, forming a barrier layer 9 on the second drift layer 3, etching the barrier layer 9 to form a through hole, and performing ion implantation into the second drift layer 3 to form a buffer zone 31;

[0048] Step 4, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the second drift layer 3 to form a P-type well region 4;

[0049] Step 5, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the P-type well region 4 to form an N-type source region 41;

[0050] Step 6, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the second drift layer 3 to the buffer zone 31, and depositing an insulating medium;

[0051] Step 7, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the insulating medium to form a groove 53, and depositing metal to form a floating gate 51;

[0052] Step 8, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing an insulating dielectric, and forming a gate dielectric layer 5;

[0053] Step 9, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the gate dielectric layer 5 to form a groove 52, and depositing metal to form a gate metal layer 6;

[0054] Step 10, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, etching the second drift layer 3, depositing metal, and forming a first source metal region 71;

[0055] Step 11, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and etch the second drift layer 3 to the upper side of the P-type well area 4, deposit metal to form a second source metal area 72, the source metal layer 7 includes the first source metal area 71 and the second source metal area 72, remove the barrier layer, and complete the preparation.

[0056] In this embodiment, preferably, the width of the buffer region 31 is equal to the sum of the width of the P-type well region 4 and the width of the gate dielectric layer 5 .

[0057] In this embodiment, preferably, the width of the floating gate 51 is smaller than the width of the gate metal layer 6 .

[0058] In this embodiment, preferably, the lower side surface of the gate metal layer 6 and the lower side surface of the P-type well region 4 are located in the same plane.

[0059] In this embodiment, preferably, a groove 311 is provided in the buffer region 31 , and the lower portion of the gate dielectric layer 5 is provided in the groove 311 .

[0060] In this embodiment, preferably, the source metal layer 7 is respectively connected to the upper side of the second drift layer 3 , the outer side of the P-type well region 4 , the upper side of the P-type well region 4 and the upper side of the N-type source region 41 .

[0061] like Figure 1 As shown, the trench gate silicon carbide VDMOS obtained by the above manufacturing method includes:

[0062] Silicon carbide substrate 1,

[0063] A first drift layer 2, wherein the lower side of the first drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0064] A second drift layer 3, wherein the lower side of the second drift layer 3 is connected to the upper side of the first drift layer 2, and a buffer zone 31 is provided in the second drift layer 3, and the lower side of the buffer zone 31 is connected to the upper side of the first drift layer 2;

[0065] A P-type well region 4, wherein the lower side of the P-type well region 4 is connected to the upper side of the second drift layer 3, and an N-type source region 41 is disposed on the P-type well region 4;

[0066] a gate dielectric layer 5, the gate dielectric layer 5 passing through the second drift layer 3 and connected to the upper side of the buffer region 31, a floating gate 51 is provided in the gate dielectric layer 5, a groove 52 is provided on the gate dielectric layer 5, the groove 52 is located above the floating gate 51, and the outer side of the gate dielectric layer 5 is respectively connected to the inner side of the P-type well region 4 and the inner side of the N-type source region 41;

[0067] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 52;

[0068] A source metal layer 7, wherein the source metal layer 7 is respectively connected to the upper side of the second drift layer 3, the P-type well region 4 and the N-type source region 41;

[0069] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0070] In another embodiment of the present invention, the silicon carbide substrate 1, the first drift layer 2, the second drift layer 3 and the buffer zone 31 are all N-type; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the first drift layer 2 is 1-5e16cm -3 , the doping concentration of the second drift layer 3 is 1-5e17cm -3 , the doping concentration of the P-type well region 4 is 1-2e18cm -3 , the doping concentration of the N-type buffer region 31 is 3-6e17cm -3 The gate dielectric layer 5 is silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type first drift layer 2 and the second drift layer 3 is a compromise between the reverse withstand voltage and the on-resistance of the device. In order to suppress the rapid diffusion of defects in the silicon carbide substrate 1, the diffusion of substrate defects is suppressed through the structure of the first drift layer 2 and the second drift layer 3, thereby achieving the goal of suppressing the bipolar degradation effect; since the device adopts a floating gate 51 structure, the insulating dielectric thickness of the floating gate 51 is large, and the gate reliability of the device is high, so no additional shielding area is required; the P-type well region 4 is to form the gate switching characteristics of the device, and the concentration of the N-type source region 41 is to reduce the source contact resistance of the device and reduce the on-resistance of the device.

[0071] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the first drift layer 2 is 30-90 μm, and the thickness of the second drift layer 3 is 10-20 μm. The thickness is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The width of the N-type source region 41 is 60-80% of the width of the P-type well region 4, and the width of the P-type well region 4 accounts for 50-60% of the device cell. The width of the device cell is 100-500 μm, the thickness of the source metal layer 7 is 800 nm, the thickness of the P-type well region 4 is 500 nm, the thickness of the N-type source region 41 is 200 nm, the total width of the insulating medium on the left and right sides of the gate metal layer 6 is 50 nm, the thickness of the insulating medium between the gate metal layer 6 and the floating gate 51 is 100-300 nm, the total width of the insulating medium on the left and right sides of the floating gate 51 is 200-500 nm, and the thickness of the insulating medium at the bottom of the floating gate 51 is 100-200 nm;

[0072] The gate metal layer 6 needs to completely invert the P-type well regions 4 on the left and right sides of the device and increase the electron concentration of the conductive channel to reduce the on-resistance of the device. Therefore, the width of the insulating medium in this area is small, which can ensure the gate control ability of the device. The thickness of the insulating medium between the gate metal layer 6 and the floating gate 51 only affects the characteristics of the floating gate. The function of the floating gate 51 is to form an inversion region in the device body to reduce the on-resistance of the device, and has little effect on the overall characteristics of the device.

[0073] In this embodiment, the source metal layer 7 is respectively connected to the upper side of the second drift layer 3, the outer side of the P-type well region 4, the upper side of the P-type well region 4 and the upper side of the N-type source region 41; the source metal layer 7 is parallel in the contact area with the top of the N-type source region 41 and the top of the P-type well 4 region, and the source metal layer 7 is convex on one side of the P-type well region 4, and the bottom end of the convex part of the source metal layer 7 is flush with the bottom end of the P-type well region 4. This structure can effectively reduce the pn junction area between the P-type well region 4 and the second drift layer 3 inside the device, thereby reducing the energy release caused by the recombination of electrons and holes, thereby inhibiting bipolar degradation;

[0074] The source metal layer 7 and the second drift layer 3 form a Schottky diode, which is single-carrier conductive, thereby suppressing the reverse recovery energy release caused by the parasitic pn junction diode of the traditional silicon carbide VDMOS due to bipolar conductivity, thereby suppressing the bipolar effect;

[0075] An N-type buffer zone 31 is constructed under the floating gate 51 of the device. By increasing the doping concentration in this area, the energy generated by the electron-hole recombination between the P-type well region 4 and the second drift layer 3 can be consumed, thereby avoiding the energy from moving to the silicon carbide substrate, thereby inhibiting the upward extension of the silicon carbide substrate defects and inhibiting the bipolar degradation effect of the device. At the same time, the N-type buffer zone 31 will also form a gate-drain capacitance shield, thereby reducing the gate-drain capacitance of the device and improving the switching speed of the device.

[0076] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a trench gate silicon carbide VDMOS with suppressed bipolar degradation, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a first drift layer; Step 2, epitaxially growing on the first drift layer to form a second drift layer; Step 3, forming a barrier layer on the second drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a buffer zone; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the second drift layer to the buffer zone, and deposit an insulating medium; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating medium to form a groove, and depositing metal to form a suspended gate; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing an insulating dielectric, and forming a gate dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the gate dielectric layer to form a groove, depositing metal, and forming a gate metal layer; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift layer, depositing metal, and forming a first source metal region; Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the second drift layer to the upper side of the P-type well region, depositing metal to form a second source metal region, the source metal layer includes the first source metal region and the second source metal region, removing the barrier layer, and completing the preparation; The width of the buffer zone is equal to the sum of the width of the P-type well region and the width of the gate dielectric layer; the width of the floating gate is smaller than the width of the gate metal layer.

2. The method for preparing a trench gate silicon carbide VDMOS with suppressed bipolar degradation according to claim 1, characterized in that: The lower side surface of the gate metal layer and the lower side surface of the P-type well region are located in the same plane.

3. The method for preparing a trench gate silicon carbide VDMOS with suppressed bipolar degradation according to claim 1, characterized in that: A groove is arranged in the buffer zone, and the lower part of the gate dielectric layer is arranged in the groove.

4. The method for preparing a trench gate silicon carbide VDMOS with suppressed bipolar degradation according to claim 1, characterized in that: The source metal layer is respectively connected to the upper side of the second drift layer, the outer side of the P-type well region, the upper side of the P-type well region and the upper side of the N-type source region.

5. A trench gate silicon carbide VDMOS for suppressing bipolar degradation, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods described in claim 1 to claim 4.

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