SiC MOSFET device and preparation method thereof

Abstract

The SiC MOSFET device is characterized in that a current diffusion layer of a first doping type is arranged between a lightly doped first epitaxial layer of the first doping type and a gate dielectric layer, and a well region of a second doping type, a source region of the first doping type and a contact region of the second doping type are arranged in the current diffusion layer; the bottom end of the well region of the second doping type is provided with a deeply-buried electric field shielding region of the second doping type, which is used for reducing the intensity of an electric field below the Schottky electrode of the source electrode and improving the short-circuit current impact resistance of the device, thereby effectively reducing the intensity of the electric field below the Schottky electrode and improving the short-circuit current impact resistance of the device. The short-circuit tolerance time of the device is prolonged; the shape, width or depth of the deeply-buried electric field shielding area is changed, and the influence of the deeply-buried electric field shielding area on the normal working performance of the device is balanced; a current diffusion layer is additionally arranged to maintain the through-current capability and the voltage endurance capability of the device; the device is simple in structure and preparation method, has high compatibility with a traditional SiC MOSFET preparation process, and is easy for batch production.

Description

Technical Field

[0001] The present invention relates to a switching device, and in particular to a SiC MOSFET device and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) is a third-generation semiconductor material with excellent characteristics such as large bandgap, high critical breakdown electric field strength, and high thermal conductivity. Power devices based on SiC materials have excellent performance such as high breakdown voltage, high power density, and high operating frequency. SiC MOSFET is a voltage-controlled switching device that is competitive in high-temperature, high-frequency, high-voltage, and high-power applications. Using it to replace silicon-based devices can reduce the system volume to 1 / 3 of the original. However, the high operating junction temperature and power density of SiCMOSFET place strict requirements on its reliability. As a switching tube device, short-circuit conditions are an extreme condition that SiC MOSFET is very likely to experience. In the conduction mode where the gate is kept on, the device will directly face the impact of bus voltage and short-circuit current. Improving the short-circuit tolerance of the device can ensure the reliability and stability of the device. There is a parasitic PiN body diode in SiC MOSFET. In power frequency applications, the body diode can be used as a freewheeling diode. However, due to the bipolar conduction characteristics of the body diode, there is a reverse recovery phenomenon when it is turned off, so the switching is slow and the loss is high, which is not suitable for higher frequency applications. Integrating Schottky diodes (SBDs) in cells is a solution that can reduce the reverse turn-on voltage drop of the device from 2.7V to 0.9V and eliminate the tail current, which greatly reduces the switching loss of the device. However, due to the cell structure, the integrated Schottky diode is very easy to be exposed to high electric fields, which affects the reliability of the device. Compared with silicon-based devices (short-circuit withstand time ≥ 10μs), the short-circuit withstand time of SiC MOSFET is inherently shorter, about 3μs, due to its shorter channel and lower on-resistance. The short-circuit withstand time of SiC MOSFET with integrated Schottky diode does not even exceed 2μs. The lower short-circuit withstand time is not conducive to the feedback control of the drive signal, affecting the reliability of the system. How to improve the short-circuit withstand capability without affecting the current-carrying capacity of the device is an urgent problem to be solved in device design. Summary of the invention

[0003] Purpose of the invention: The purpose of the present invention is to provide a SiC MOSFET device in order to improve the short-circuit withstand capability of the device without affecting the current conduction capability; another purpose of the present invention is to provide a method for preparing the device.

[0004] Technical solution: The SiC MOSFET device described in the present invention includes a drain electrode, a drain ohmic contact layer, a heavily doped substrate of a first doping type, a lightly doped first epitaxial layer of a first doping type, a gate dielectric layer, a polysilicon layer of a first doping type, a passivation layer, a source ohmic contact layer, a source Schottky contact layer, a source electrode and a gate electrode, which are arranged in sequence from bottom to top; a current diffusion layer of a first doping type is arranged between the lightly doped first epitaxial layer of the first doping type and the gate dielectric layer, and a pair of well regions of a second doping type are symmetrically arranged on the top of the current diffusion layer of the first doping type; a source region of a first doping type and a contact region of a second doping type are arranged on the top of the well region of the second doping type; a second doping type buried electric field shielding region for reducing the electric field strength below the source Schottky electrode and improving the device's ability to resist short-circuit current impact is arranged at the bottom of the well region of the second doping type.

[0005] Furthermore, a current diffusion layer of the first doping type is added between the lightly doped first epitaxial layer of the first doping type and the gate dielectric layer, and a well region of the second doping type, a source region of the first doping type and a contact region of the second doping type are arranged in the current diffusion layer to maintain the current flow capacity and voltage resistance of the device.

[0006] Furthermore, the first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

[0007] Furthermore, the second doping type deep buried electric field shielding region is a rectangular structure, the width of the second doping type deep buried electric field shielding region is greater than, equal to or less than the width of the second doping type well region, and its bottom extends to the inside of the first doping type current diffusion layer, the bottom of the first doping type current diffusion layer or the inside of the first doping type lightly doped first epitaxial layer. By adjusting the area of ​​the deep buried electric field shielding region, the electric field strength under the source Schottky electrode is reduced and the ability of the device to resist short-circuit current shocks is improved.

[0008] Furthermore, the second doping type deep buried electric field shielding area is an inverted right-angled trapezoidal structure with the hypotenuse close to the source Schottky contact layer, the width of the second doping type deep buried electric field shielding area is greater than, equal to or less than the width of the second doping type well area, and its bottom extends to the inside of the first doping type current diffusion layer, the bottom of the first doping type current diffusion layer or the inside of the first doping type lightly doped first epitaxial layer, and the inverted right-angled trapezoidal structure has a small source shielding area, which is conducive to the source Schottky diode current conduction and reduces the device third quadrant turn-on voltage. Alternatively, by adjusting the width and depth of the second doping type deep buried electric field shielding area, while satisfying its ability to enhance the device's ability to resist short-circuit current impact, the source shielding area is minimized as much as possible to ensure the source Schottky diode current conduction capability, thereby reducing the device conduction and switching losses.

[0009] Furthermore, the doping concentration of the second doping type deep electric field shielding region is greater than the doping concentration of the second doping type well region, and the ability of the device to resist short-circuit current impact is improved by adjusting the doping concentration of the shielding region.

[0010] Furthermore, the concentration of the current diffusion layer of the first doping type is positively correlated with the area of ​​the deep buried electric field shielding zone of the second doping type, and its doping concentration is adjusted according to the area of ​​the deep buried electric field shielding zone of the second doping type: when the area of ​​the deep buried electric field shielding zone of the second doping type is larger, the concentration of the current diffusion layer of the first doping type is increased; when the area of ​​the deep buried electric field shielding zone of the second doping type is smaller, the concentration of the current diffusion layer of the first doping type is reduced.

[0011] The present invention also provides a method for preparing a SiC MOSFET device, comprising the following steps:

[0012] Step 1, preparing a heavily doped substrate of a first doping type, and forming a lightly doped first epitaxial layer of the first doping type and a lightly doped current diffusion layer of the first doping type on the upper surface of the substrate;

[0013] Step 2, forming a well region of a second doping type on the upper surface of the first epitaxial layer lightly doped with the first doping type by an ion implantation process;

[0014] Step 3, forming a buried electric field shielding region of the second doping type in the lightly doped current diffusion layer of the first doping type and below the well region of the second doping type by an ion implantation process;

[0015] Step 4, forming a source region of the first doping type and a contact region of the second doping type in the well region of the second doping type by an ion implantation process;

[0016] Step 5, forming a gate dielectric layer on the upper surface of the first epitaxial layer of the first doping type and lightly doped, and growing a polysilicon layer on the gate dielectric layer;

[0017] Step 6, using photolithography and etching processes, a passivation layer is formed on the upper surface of the lightly doped current diffusion layer of the first doping type, two source windows are formed in the passivation layer and on both sides of the polysilicon layer, a source ohmic contact layer and a source Schottky contact layer are formed in the source windows, and a source electrode is generated on the source ohmic contact layer and the source Schottky contact layer; a gate window is formed in the middle of the passivation layer and at a position corresponding to the polysilicon layer, and a gate electrode is formed in the gate window;

[0018] Step 7: forming a drain ohmic contact layer on the bottom surface of the heavily doped substrate of the first doping type, and generating a drain electrode on the drain ohmic contact layer.

[0019] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: 1. Introducing a deeply buried electric field shielding area to effectively reduce the electric field strength under the Schottky electrode, thereby improving the device's ability to resist short-circuit current shocks and increasing the device's short-circuit withstand time; 2. Changing the shape, width or depth of the deeply buried electric field shielding area to balance the impact of the deeply buried electric field shielding area on the normal working performance of the device; 3. Adding a current diffusion layer to maintain the device's current carrying capacity and voltage resistance; 4. The structure and preparation method are simple, highly compatible with the traditional SiC MOSFET preparation process, and easy to mass produce. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of Example 3 of the present invention. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0024] Example 1

[0025] like Figure 1A SiC MOSFET device is shown, comprising a drain electrode 116, a drain ohmic contact layer 111, a heavily doped substrate 101 of a first doping type, a lightly doped first epitaxial layer 102 of a first doping type, a current diffusion layer 103 of a first doping type, a gate dielectric layer 107, a polysilicon layer 108 of a first doping type, a passivation layer 113, a source ohmic contact layer 109, a source Schottky contact layer 110, a source electrode 114 and a gate electrode 115, which are arranged in sequence from bottom to top; a pair of well regions 104 of a second doping type are symmetrically arranged on the top of the current diffusion layer 103 of the first doping type, a source region 105 of a first doping type and a contact region 106 of a second doping type are arranged on the top of the well region 104 of the second doping type, and a buried electric field shielding region 112 of a second doping type is arranged at the bottom of the well region 104 of the second doping type. The second doping type of buried electric field shielding region 112 is a rectangular parallelepiped structure, whose width is equal to the width of the second doping type of well region 104, and whose bottom extends to the interior of the first doping type of current diffusion layer 103 (the bottom of the second doping type of buried electric field shielding region 112 can also be set to extend to the bottom of the first doping type of current diffusion layer 103 according to the electric field shielding requirements). The first doping type is N-type, and the second doping type is P-type. The doping concentration of the second doping type of buried electric field shielding region 112 is greater than the doping concentration of the second doping type of well region 104.

[0026] The above-mentioned SiC MOSFET device generates a current diffusion layer 103 of the first doping type above the lightly doped first epitaxial layer 102 of the first doping type, and its doping concentration is determined according to the area of ​​the designed shape of the deep buried electric field shielding area 112 of the second doping type. The well region 104 of the second doping type, the source region 105 of the first doping type, and the contact region 106 of the second doping type are arranged inside the current diffusion layer 103 of the first doping type to increase the conduction capacity of the current in each functional area and maintain the current flow capacity and withstand voltage of the device. The deep buried electric field shielding area 112 of the second doping type is arranged inside the current diffusion layer 103 of the first doping type and at the bottom of the well region 104 of the second doping type, which effectively reduces the electric field strength below the Schottky electrode, improves the ability of the device to resist the impact of short-circuit current, and increases the short-circuit withstand time of the device.

[0027] Example 2

[0028] like Figure 2 As shown, the difference from Embodiment 1 is that the second doping type buried electric field shielding region 112 is an inverted right-angle trapezoidal structure with the oblique side close to the source Schottky contact layer 110. The first doping type is P type, and the second doping type is N type.

[0029] Compared with Example 1, the above SiC MOSFET device is advantageous for the conduction of the source Schottky diode current and reduces the third quadrant turn-on voltage of the device by changing the shape of the second doping type deep electric field shielding region 112 to an inverted right-angled trapezoid; at the same time, the shielding area below the source Schottky contact layer 110 is reduced to ensure the current conduction capability of the source Schottky diode, thereby reducing the conduction and switching losses of the device. The shape and area of ​​the second doping type deep electric field shielding region 112 are changed, and the doping concentration of the first doping type current diffusion layer 103 is adjusted for suitability.

[0030] Example 3

[0031] like Figure 3 As shown, what is different from Example 1 is that the width of the second doping type deep buried electric field shielding region 112 is smaller than the width of the second doping type well region 104 (the width of the second doping type deep buried electric field shielding region 112 can also be set to be larger than the width of the second doping type well region 104 according to the electric field shielding requirements), and its bottom extends to the interior of the lightly doped first epitaxial layer 102 of the first doping type.

[0032] Compared with Example 1, the above SiC MOSFET device is changed to have a width of the second doping type buried electric field shielding region 112 smaller than the width of the second doping type well region 104, thereby reducing the shielding area of ​​the first doping type current diffusion layer 103 to a greater extent, further reducing the electric field strength under the source electrode and improving the device's ability to resist short-circuit current impact; at the same time, the bottom of the second doping type buried electric field shielding region 112 extends to the inside of the first doping type lightly doped first epitaxial layer 102, and by adjusting the width, depth or doping concentration of the second doping type buried electric field shielding region, while satisfying its ability to enhance the device's ability to resist short-circuit current impact, the shielding area of ​​the source is minimized as much as possible, ensuring the device's current conduction capability, thereby reducing the device's conduction and switching losses. The shape and area of ​​the second doping type buried electric field shielding region 112 are changed, and the doping concentration of the first doping type current diffusion layer 103 is adjusted for suitability.

[0033] The method for preparing the above SiC MOSFET device comprises the following steps:

[0034] Step 1, preparing a heavily doped substrate 101 of a first doping type, and forming a lightly doped first epitaxial layer 102 of a first doping type and a lightly doped current diffusion layer 103 of a first doping type on the upper surface thereof;

[0035] Step 2, forming a well region 104 of a second doping type on the upper surface of the first epitaxial layer 102 which is lightly doped with a first doping type by an ion implantation process;

[0036] Step 3, forming a buried electric field shielding region 112 of the second doping type in the lightly doped current diffusion layer 103 of the first doping type and below the well region 104 of the second doping type by an ion implantation process;

[0037] Step 4, forming a source region 105 of the first doping type and a contact region 106 of the second doping type in the well region 104 of the second doping type by an ion implantation process;

[0038] Step 5, forming a gate dielectric layer 107 on the upper surface of the first epitaxial layer 102 with a light doping type of the first doping type, and growing a polysilicon layer 108 on the gate dielectric layer 107;

[0039] Step 6, using photolithography and etching processes, a passivation layer 113 is formed on the upper surface of the lightly doped current diffusion layer 103 of the first doping type, two source windows are formed in the passivation layer 113 and on both sides of the polysilicon layer 108, a source ohmic contact layer 109 and a source Schottky contact layer 110 are formed in the source windows, and a source electrode 114 is generated on the source ohmic contact layer 109 and the source Schottky contact layer 110; a gate window is formed in the middle of the passivation layer 113 and at a position corresponding to the polysilicon layer 108, and a gate electrode 115 is formed in the gate window;

[0040] Step 7: forming a drain ohmic contact layer 111 on the bottom surface of the heavily doped substrate 101 of the first doping type, and generating a drain electrode 116 on the drain ohmic contact layer 111 .

[0041] In the above-mentioned manufacturing method, the ability of the second doping type deep buried electric field shielding area 112 to resist short-circuit current impact is adjusted by adjusting the width, depth or shape of the second doping type deep buried electric field shielding area 112 according to the requirements of device performance. The doping concentration of the first doping type lightly doped current diffusion layer 103 is adjusted according to the design requirements of the second doping type deep buried electric field shielding area 112: when the area of ​​the second doping type deep buried electric field shielding area 112 is large, the concentration of the first doping type current diffusion layer 103 is increased; when the area of ​​the second doping type deep buried electric field shielding area 112 is small, the concentration of the first doping type current diffusion layer 103 is reduced.

Claims

1. A SiC MOSFET device, comprising, arranged in sequence from bottom to top, a drain electrode (116), a drain ohmic contact layer (111), a heavily doped substrate (101) of a first doping type, a lightly doped first epitaxial layer (102) of a first doping type, a gate dielectric layer (107), a polysilicon layer (108) of a first doping type, a passivation layer (113), a source ohmic contact layer (109), a source Schottky contact layer (110), a source electrode (114) and a gate electrode (115); characterized in that: A current diffusion layer (103) of the first doping type is arranged between the lightly doped first epitaxial layer (102) of the first doping type and the gate dielectric layer (107); a pair of well regions (104) of the second doping type are symmetrically arranged on the top of the current diffusion layer (103) of the first doping type; a source region (105) of the first doping type and a contact region (106) of the second doping type are arranged on the top of the well region (104) of the second doping type; and a second doping type buried electric field shielding region (112) for reducing the electric field strength below the source Schottky electrode and improving the device's ability to resist short-circuit current impact is arranged at the bottom of the well region (104) of the second doping type.

2. The SiC MOSFET device according to claim 1, characterized in that: The first doping type is N-type, and the second doping type is P-type.

3. The SiC MOSFET device according to claim 1, characterized in that: The first doping type is P type, and the second doping type is N type.

4. The SiC MOSFET device according to claim 1, characterized in that: The second doping type buried electric field shielding region (112) is a rectangular parallelepiped structure.

5. The SiC MOSFET device according to claim 1, characterized in that: The second doping type buried electric field shielding region (112) is an inverted right-angled trapezoidal structure with its oblique side close to the source Schottky contact layer (110).

6. The SiC MOSFET device according to claim 4 or 5, characterized in that: The bottom of the second doping type buried electric field shielding region (112) extends to the inside of the first doping type current diffusion layer (103), the bottom of the first doping type current diffusion layer (103), or the inside of the first doping type lightly doped first epitaxial layer (102).

7. The SiC MOSFET device according to claim 1, characterized in that: The doping concentration of the second doping type buried electric field shielding region (112) is greater than the doping concentration of the second doping type well region (104).

8. The SiC MOSFET device according to claim 1 or 7, characterized in that: The concentration of the first doping type current diffusion layer (103) is positively correlated with the area of ​​the second doping type deep buried electric field shielding region (112).

9. A method for preparing a SiC MOSFET device according to any one of claims 1 to 8, characterized in that: The steps include: A heavily doped substrate (101) of a first doping type is prepared, and a lightly doped first epitaxial layer (102) of a first doping type and a lightly doped current diffusion layer (103) of a first doping type are formed on the upper surface of the substrate; Forming a well region (104) of a second doping type on the upper surface of a lightly doped first epitaxial layer (102) of a first doping type by an ion implantation process; Forming a second doping type buried electric field shielding region (112) in a first doping type lightly doped current diffusion layer (103) and below a second doping type well region (104) by an ion implantation process; Forming a source region (105) of the first doping type and a contact region (106) of the second doping type in a well region (104) of the second doping type by an ion implantation process; Forming a gate dielectric layer (107) on the upper surface of a lightly doped first epitaxial layer (102) of a first doping type, and growing a polysilicon layer (108) on the gate dielectric layer (107); Using photolithography and etching processes, a passivation layer (113) is formed on the upper surface of a lightly doped current diffusion layer (103) of a first doping type, two source windows are formed in the passivation layer (113) and on both sides of the polysilicon layer (108), a source ohmic contact layer (109) and a source Schottky contact layer (110) are formed in the source windows, and a source electrode (114) is generated on the source ohmic contact layer (109) and the source Schottky contact layer (110); a gate window is formed in the middle of the passivation layer (113) and at a position corresponding to the polysilicon layer (108), and a gate electrode (115) is formed in the gate window; A drain ohmic contact layer (111) is formed on the bottom surface of a heavily doped substrate (101) of a first doping type, and a drain electrode (116) is generated on the drain ohmic contact layer (111).

10. The method for preparing a SiC MOSFET device according to claim 9, characterized in that: In the step of preparing the second doping type deep buried electric field shielding region (112), the area is adjusted by adjusting its width, depth or shape, thereby adjusting the ability of the second doping type deep buried electric field shielding region (112) to resist short-circuit current impact.

11. The method for preparing a SiC MOSFET device according to claim 9 or 10, characterized in that: In the step of preparing the first doping type current diffusion layer (103), the concentration of the first doping type current diffusion layer (103) is adjusted according to the area of ​​the second doping type deep buried electric field shielding region (112): when the area of ​​the second doping type deep buried electric field shielding region (112) is large, the concentration of the first doping type current diffusion layer (103) is increased; when the area of ​​the second doping type deep buried electric field shielding region (112) is small, the concentration of the first doping type current diffusion layer (103) is reduced.

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