Silicon carbide transistor, manufacturing method thereof and electronic device

Abstract

The present invention discloses a silicon carbide transistor, a manufacturing method thereof and an electronic device, comprising: a substrate, and a silicon carbide layer arranged on the substrate; the silicon carbide layer comprises: an N-drift layer, a P well, an N+ source layer and a source electrode stacked in sequence on the substrate; the silicon carbide transistor also comprises a P-protection structure, a surface of the silicon carbide layer away from the substrate is provided with a gate groove, at least part of the P-protection structure is provided at the bottom of the gate groove, a gate insulating layer and a gate are also provided in the gate groove, the gate insulating layer is respectively isolated from the P-protection structure and the gate, and the silicon carbide layer and the gate; the P-protection structure is connected to the source electrode. In this way, by providing the P-protection structure at the bottom of the gate groove, the electric field strength of the gate insulating layer can be reduced, thereby reducing the probability of the gate insulating layer being broken down, and improving the reliability of the silicon carbide transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide transistor, a manufacturing method thereof and an electronic device. Background Art

[0002] As a semiconductor material with a wide bandgap, high breakdown field strength, high thermal conductivity, and mobility similar to that of silicon, silicon carbide has broad prospects in power electronics applications and is widely used in new energy vehicles, charging piles, photovoltaics and other fields.

[0003] When silicon carbide transistors are used in high-power working scenarios, the gate insulation layer between the gate and the silicon carbide layer is easily broken down, which leads to reduced reliability of the silicon carbide transistor. Therefore, how to improve the reliability of silicon carbide transistors has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0004] Embodiments of the present invention provide a silicon carbide transistor, a manufacturing method thereof, and an electronic device, so as to improve the reliability of the silicon carbide transistor.

[0005] In a first aspect, an embodiment of the present invention provides a silicon carbide transistor, comprising: a substrate, and a silicon carbide layer disposed on the substrate; the silicon carbide layer comprises: an N-drift layer, a P well, an N+ source layer and a source electrode stacked in sequence on the substrate;

[0006] The silicon carbide transistor further comprises a P-protection structure, a gate trench is arranged on a surface of the silicon carbide layer on one side away from the substrate, at least a portion of the P-protection structure is arranged at the bottom of the gate trench, a gate insulating layer and a gate are further arranged in the gate trench, and the gate insulating layer isolates the P-protection structure from the gate, and the silicon carbide layer from the gate, respectively;

[0007] The P-guard structure is connected to the source electrode.

[0008] In a second aspect, an embodiment of the present invention provides a method for manufacturing a silicon carbide transistor as described in the first aspect above, comprising:

[0009] A silicon carbide layer is formed on the substrate; the silicon carbide layer comprises: an N-drift layer, a P well, and an N+ source layer stacked in sequence on the substrate;

[0010] Etching a gate trench on a surface of the silicon carbide layer away from the substrate;

[0011] Backfilling P-doped silicon carbide in the gate trench to form a P-protection structure; at least a portion of the P-protection structure is disposed at the bottom of the gate trench;

[0012] A gate insulating layer and a gate are sequentially formed in the gate trench; the gate insulating layer isolates the P-protection structure from the gate, and the silicon carbide layer from the gate;

[0013] A source electrode is formed on the silicon carbide layer, and the P-protection structure is connected to the source electrode.

[0014] In a third aspect, an embodiment of the present invention provides an electronic device, including: a silicon carbide transistor as described in the first aspect above.

[0015] The beneficial effects of the present invention are as follows:

[0016] A silicon carbide transistor, a manufacturing method thereof, and an electronic device provided by an embodiment of the present invention include: a substrate, and a silicon carbide layer disposed on the substrate; the silicon carbide layer includes: an N-drift layer, a P well, an N+ source layer, and a source electrode stacked in sequence on the substrate; the silicon carbide transistor also includes a P-protection structure, a gate groove is disposed on the surface of the silicon carbide layer away from the substrate, at least part of the P-protection structure is disposed at the bottom of the gate groove, a gate insulating layer and a gate are also disposed in the gate groove, and the gate insulating layer isolates the P-protection structure from the gate, and the silicon carbide layer from the gate; the P-protection structure is connected to the source electrode. In this way, by arranging the P-protection structure at the bottom of the gate groove, the electric field strength of the gate insulating layer can be reduced, thereby reducing the probability of the gate insulating layer being broken down, and improving the reliability of the silicon carbide transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a cross-sectional view of a first silicon carbide transistor provided in an embodiment of the present invention;

[0018] Figure 2 is a cross-sectional view of a second silicon carbide transistor provided in an embodiment of the present invention;

[0019] Figure 3 is a cross-sectional view of a third silicon carbide transistor provided in an embodiment of the present invention;

[0020] Figure 4 is a cross-sectional view of a fourth silicon carbide transistor provided in an embodiment of the present invention;

[0021] Figure 5 A flowchart of a method for manufacturing a silicon carbide transistor provided in an embodiment of the present invention;

[0022] Figure 6 A schematic diagram of a process for manufacturing a silicon carbide transistor provided in an embodiment of the present invention;

[0023] Figure 7A simulation diagram of the on-current streamline distribution of the silicon carbide transistor provided in an embodiment of the present invention;

[0024] Figure 8 A simulation diagram of the electron current density distribution of a silicon carbide transistor provided in an embodiment of the present invention;

[0025] Fig. 9 A graph showing the relationship between the current density and the drain electrode voltage of the silicon carbide transistor provided in an embodiment of the present invention;

[0026] Fig.10 A graph showing the relationship between the reduction ratio of the on-current of the silicon carbide transistor and the drain electrode voltage provided in an embodiment of the present invention;

[0027] Fig.11 A simulation diagram of the electric field distribution of the silicon carbide transistor under the reverse breakdown voltage provided in an embodiment of the present invention;

[0028] Fig.12 A simulation diagram of the potential distribution of the silicon carbide transistor under the reverse breakdown voltage provided in an embodiment of the present invention;

[0029] Fig.13 A graph showing the relationship between the drain current density and the reverse voltage of the silicon carbide transistor provided in an embodiment of the present invention;

[0030] Fig.14 The figure is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings to describe in detail a specific implementation of a silicon carbide transistor, a method for manufacturing the same, and an electronic device provided by an embodiment of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] An embodiment of the present invention provides a silicon carbide transistor, such as Figure 1 As shown, it includes: a substrate 100, and a silicon carbide layer 200 disposed on the substrate 100; the silicon carbide layer 200 includes: an N-drift layer 201, a P well 202, an N+ source layer 203 and a source electrode 600 which are sequentially stacked on the substrate 100;

[0033] The silicon carbide transistor also includes a P-protection structure. Figure 1 The structures shown in the dashed box B, the dashed box L1, and the dashed box L2 constitute a P-protection structure, and Figure 1The area filled with sparse black dots in the figure represents the P-protection structure. A gate trench G1 is provided on the surface of the silicon carbide layer 200 away from the substrate 100. The gate trench G1 passes through the N+ source layer 203 and the P well 202 and extends into the N-drift layer 201. At least part of the P-protection structure is provided at the bottom of the gate trench G1. Figure 1 The P-protection structure in the area shown in the dotted box B is arranged at the bottom of the gate trench G1. A gate insulating layer 400 and a gate 500 are also arranged in the gate trench G1. The gate insulating layer 400 isolates the P-protection structure from the gate 500, and the silicon carbide layer 200 from the gate 500 respectively; the P-protection structure is connected to the source electrode 600.

[0034] In this way, by setting a P-protection structure at the bottom of the gate trench, the electric field strength of the gate insulating layer can be reduced, thereby reducing the probability of the gate insulating layer being broken down, and improving the reliability of the silicon carbide transistor; in addition, the P-protection structure is connected to the source electrode, and the P-protection structure can be clamped by the source electrode, and then when the source electrode is grounded, the charge accumulated in the P-protection structure can be drawn away, thereby avoiding charge accumulation in the P-protection structure, improving the protection effect of the P-protection structure on the gate insulating layer, and can further improve the reliability of the silicon carbide transistor.

[0035] It should be understood that the P-protection structure can be made by first etching to obtain a gate trench, and then epitaxially growing P-doped silicon carbide in the gate trench, so that the side of the P-protection structure obtained is a plane, and the side of the gate trench and the side of the P-protection structure are located in the same plane. In this way, the P-protection structure is formed by first etching and then epitaxial backfilling, so that the formation area of ​​the protection structure is easier to control, and the damage to the silicon carbide layer is small, thereby improving the stability of the silicon carbide transistor.

[0036] Alternatively, if Figure 1 As shown, the P-protection structure includes: a protection part B, a first connection part L1, a second connection part L2, a first top structure D1 and a second top structure D2; the gate trench G1 includes a first side wall and a second side wall opposite to each other; the protection part B is located at the bottom of the gate trench; the protection part B extends a first connection part L1 along the first side wall on a surface of a side away from the substrate 100, and extends a second connection part L2 along the second side wall; the first top structure D1 and the second top structure D2 are both located on the silicon carbide layer 200; the first top structure D1 is respectively connected to the first connection part L1 and the source electrode 600, and the second top structure D2 is respectively connected to the second connection part L2 and the source electrode 600; the first connection part L1 and the second connection part L2 are both located between the gate insulating layer 400 and the silicon carbide layer 200.

[0037] In this way, the first connecting part and the first top structure as well as the second connecting part and the second top structure can all connect the source electrode with the protection part, and then the protection part can be clamped by the source electrode. When the source electrode is grounded, the charges accumulated in the protection part can be led away, thereby avoiding the accumulation of charges in the protection part, improving the protection effect of the protection part on the gate insulating layer, and further improving the reliability of the silicon carbide transistor.

[0038] In addition, in addition to being achieved through the first connecting part, the first top structure, the second connecting part, and the second top structure, the P-protection structure and the source electrode may also be connected in other ways, such as but not limited to: directly connecting the protection part and the source electrode by providing an additional conductive structure; or only providing the first connecting part and the second connecting part, and both the first connecting part and the second connecting part are connected to the N+ source layer, thereby connecting the source electrode and the protection part through the N+ source layer.

[0039] Furthermore, the first connection portion connects the protection portion and the N+ source layer, and the second connection portion connects the protection portion and the N+ source layer. In this way, since the protection portion is part of the P-protection structure, it is P-type silicon carbide, and the N+ source layer is N-type silicon carbide, so that the protection portion and the N+ source layer can form a diode, which can play a freewheeling role when the silicon carbide transistor is reversely conducted, and can enhance the reverse conduction current of the silicon carbide transistor, improve the reverse conduction capability of the silicon carbide transistor, and enhance the performance of the silicon carbide transistor.

[0040] Optionally, the first connecting portion and / or the second connecting portion can be set to be thicker, for example, the thickness can be set to 100nm. In this way, the thicker first connecting portion and / or the second connecting portion has a smaller resistance and a higher conductivity, so that the first connecting portion and / or the second connecting portion can realize the electrical connection between the protection portion and the N+ source layer, and then clamp the protection portion, which is beneficial to the protection of the gate insulation layer by the protection portion and improves the reliability of the silicon carbide transistor.

[0041] Of course, the first connection portion and / or the second connection portion can be set to be thinner, for example, the thickness can be set to 10nm. In this way, the thinner first connection portion and / or the second connection portion has a larger resistance and a lower conductivity. At this time, the protection portion can be clamped by a parasitic PMOS. The parasitic PMOS can be specifically as follows: Figure 2As shown, the P-well 202 (equivalent to the source of the parasitic PMOS), the N-drift layer 201 (equivalent to the inversion channel of the parasitic PMOS), the protection part B (equivalent to the drain of the parasitic PMOS), the gate insulating layer 400 (equivalent to the gate insulating layer of the parasitic PMOS), and the gate 500 (equivalent to the gate of the parasitic PMOS) constitute an equivalent PMOS. When the silicon carbide transistor is reversely withstand voltage, the gate 500 and the P-well 202 are grounded, and the potential of the N-drift layer 201 is relatively high, so that the parasitic PMOS is turned on, and the protection part B is grounded and clamped, so that the protection part B further protects the gate insulating layer 400, thereby improving the reliability of the silicon carbide transistor.

[0042] Alternatively, if Figure 1 As shown, the thickness of the first connection portion L1 at one end close to the protection portion B (such as the bottom end of the first connection portion L1) is smaller than the thickness at the end away from the protection portion B (such as the top end of the first connection portion L1); or, the thickness of the second connection portion L2 at one end close to the protection portion B (such as the bottom end of the second connection portion L2) is smaller than the thickness at the end away from the protection portion B (such as the top end of the second connection portion L2).

[0043] Wherein, the first connection portion L1 is a P-doped silicon carbide layer covering the first side wall, and the second connection portion L2 is a P-doped silicon carbide layer covering the second side wall. Then the thickness of the first connection portion L1 and the second connection portion L2 is: the length of the P-doped silicon carbide layer along the arrangement direction of the first side wall and the second side wall. The arrangement direction of the first side wall and the second side wall can be as follows Figure 1 The direction indicated by x.

[0044] In this way, the thickness of the first connection part and / or the second connection part near one end of the protection part is set to be smaller, which can reduce the thickness of the PN junction formed by the first connection part and / or the second connection part near one end of the protection part and the N+ drift layer, so that when the silicon carbide transistor is forward-conducted, only the thinner PN junction needs to be overcome, thereby improving the on-state current of the silicon carbide transistor and enhancing the forward conduction performance of the silicon carbide transistor; setting the thickness of the first connection part and / or the second connection part away from one end of the protection part to be larger is conducive to the flow of the freewheeling current to the protection part during reverse conduction, improving the freewheeling capability during reverse conduction, and enhancing the reverse conduction performance of the silicon carbide transistor.

[0045] Of course, if any one of the first connecting part and the second connecting part is called a connecting part, the thickness of the connecting part close to the end of the protecting part is set to be smaller, and the thickness of the connecting part away from the protecting part is set to be larger, which is called a thickness distribution of wide at the top and narrow at the bottom. The first connecting part and the second connecting part can be set to be wide at the top and narrow at the bottom at the same time, and of course they can also be set to be wide at the top and narrow at the bottom at different times. The thickness distribution of the first connecting part and the second connecting part can be set according to actual needs, and is not limited here.

[0046] Optionally, the first connecting portion is close to one end of the protection portion (eg Figure 1 The thickness of the first connecting portion L1 in the bottom end is not greater than 100 nm, so that the thickness of the first connecting portion close to the end of the protection portion is thinner; or the thickness of the second connecting portion close to the end of the protection portion (for example Figure 1 The bottom end of the second connection portion L2 in the circuit is not greater than 100 nm, so that the thickness of the second connection portion close to the end of the protection portion is relatively thin. In this way, the thickness of the first connection portion and / or the second connection portion close to the end of the protection portion is set to be relatively thin, so that when the silicon carbide transistor is forward-conducted, it only needs to overcome a relatively thin PN junction, thereby increasing the on-current of the silicon carbide transistor and enhancing the forward conduction performance of the silicon carbide transistor.

[0047] Alternatively, if Figure 1 As shown, the thickness of the first top structure D1 or the second top structure D2 is greater than 0 and not greater than 5 μm, and the thickness of the first top structure D1 and the second top structure D2 are both the lengths along the direction shown by y. In this way, setting the thickness of the first top structure D1 or the second top structure D2 within a suitable range can not only improve the protection effect of the protection portion B on the gate insulating layer 400, further improve the reliability of the silicon carbide transistor, but also reduce the volume of the silicon carbide transistor.

[0048] Alternatively, if Figure 1 As shown, the silicon carbide transistor also includes a source electrode 600 located on the silicon carbide layer 200, and the source electrode 600 is connected to the N+ source layer 203; the source electrode 600 passes through the N+ source layer 203 and is connected to the P-well 202. Among them, the side surface A1 of the source electrode 600 close to the substrate 100 is located in the P-well 202, or the side surface A1 of the source electrode 600 close to the substrate 100 is located on the side surface of the P-well 202 away from the substrate 100. In this way, the silicon carbide transistor can be freewheeled through the diode formed by the P-well 202 and the N-drift layer 201, which can improve the reverse conduction performance of the silicon carbide transistor.

[0049] Alternatively, if Figure 2 As shown, when the source electrode 600 is connected to the N+ source layer 203, the source electrode 600 may not pass through the N+ source layer 203. The side surface A1 of the source electrode 600 close to the substrate 100 is located in the N+ source layer 203, or the side surface A1 of the source electrode 600 close to the substrate 100 is located on the side surface of the N+ source layer 203 away from the substrate 100. In this way, the difficulty of manufacturing the source electrode 600 can be reduced, and the manufacturing cost of the silicon carbide transistor can be reduced.

[0050] Alternatively, if Figure 2As shown, a P+ contact region 204 may also be provided in the silicon carbide transistor. The P+ contact region 204 is provided in the N+ source layer 203 and the P well 202. The surface of the P+ contact region 204 on the side away from the N-drift layer is connected to the source electrode 600. The surface of the P+ contact region 204 on the side close to the N-drift layer 201 is located in the P well 202, or the surface of the P+ contact region 204 on the side close to the N-drift layer 201 is located on the surface of the P well 202 away from the N-drift layer 201. In this way, by providing the P+ contact region 204, the P+ contact region 204 can electrically connect the source electrode 600 and the P well 202, so that the source electrode 600 can control the potential of the P well 202 through the P+ contact region 204, thereby improving the reliability of the silicon carbide transistor.

[0051] Alternatively, if Figure 3 As shown, the N-drift layer 201 includes: a first N-drift layer 201a and a second N-drift layer 201b, the doping concentration of the second N-drift layer 201b is greater than the doping concentration of the first N-drift layer 201a, and the first N-drift layer 201a is located between the substrate 100 and the second N-drift layer 201b; the surface of the P-protection structure facing the substrate 100 is located in the interface M2 between the first N-drift layer 201a and the second N-drift layer 201b. The doping concentration of the first N-drift layer 201a can be, but is not limited to, 1×10 14 / cm 3 Up to 1×10 16 / cm 3 The doping concentration of the second N-drift layer 201b may be, but is not limited to, 1×10 16 / cm 3 Up to 5×10 17 / cm 3 .

[0052] Furthermore, the second N-drift layer and the P-protection structure form a super junction, that is, the protection portion in the P-protection structure and the second N-drift layer form a super junction. Figure 3 The area shown in the dotted box C is the super junction structure.

[0053] In this way, the second N-drift layer can achieve charge balance with the P-protection structure, and then a super junction structure is formed between the second N-drift layer and the P-protection structure. The super junction structure can adjust the electric field distribution in the N-drift layer of the silicon carbide transistor and reduce the peak electric field strength, so that the N-drift layer can be doped with a higher concentration, reducing the on-resistance of the silicon carbide transistor and improving the performance of the silicon carbide transistor.

[0054] It should be understood that Figure 3 As shown, the region X1 between the vertical dotted lines is a cell of the silicon carbide transistor, that is, the structure included in the region X1 can be repeatedly extended to both sides.

[0055] Alternatively, if Figure 4 As shown, a protection groove G2 is also provided on the surface of the silicon carbide layer 200 away from the substrate 100, and the protection groove G2 is provided on opposite sides of the gate groove G1; the P-protection structure is also provided at the bottom of the protection groove G2. Among them, a protection insulating layer B400 and a conductive layer B500 are provided in the protection groove G2. In this way, by providing a protection groove, the electric field strength of the gate insulating layer at the bottom of the gate groove can be reduced, and the probability of the gate insulating layer being broken down can be reduced, thereby improving the reliability of the silicon carbide transistor.

[0056] Optionally, the protective insulating layer and the gate insulating layer can be made of the same insulating material through the same process steps, and the conductive layer and the gate can also be made of the same insulating material through the same process steps. This can simplify the manufacturing process steps of the silicon carbide transistor and reduce the manufacturing cost.

[0057] Alternatively, if Figure 4 As shown, a through hole K may be provided in the protection insulating layer B400 in the protection trench G2, and the conductive layer B500 in the protection trench G2 is connected to the P-protection structure in the protection trench G2 through the through hole K, so that the P-protection structure in the protection trench G2 is clamped by the conductive layer B500 in the protection trench G2, which can effectively control the electric field strength of the gate insulating layer 400 at the bottom of the gate trench G1, further reduce the probability of the gate insulating layer 400 in the gate trench G1 being broken down, and improve the reliability of the silicon carbide transistor.

[0058] Optionally, one protection trench may be provided in one cell of the silicon carbide transistor, or two protection trenches may be provided in one cell of the silicon carbide transistor. Figure 4 As shown, when the area X2 between the vertical dotted lines is a cell of a silicon carbide transistor, one cell of the silicon carbide transistor includes one protection groove G2, and the manufacturing process is relatively simple at this time; when the area X3 between the vertical dotted lines is a cell of a silicon carbide transistor, one cell of the silicon carbide transistor includes two protection grooves G2, and the protection effect on the gate insulating layer 400 is relatively good at this time. Of course, the number of protection grooves G2 in each cell can be set according to actual needs, including but not limited to one, two, three or more, and is not limited here.

[0059] Optionally, a P-buried layer is provided at the bottom of the protection groove, and a surface of the P-buried layer on one side away from the substrate contacts the P-protection structure at the bottom of the protection groove, and the length of the P-buried layer along the first direction is greater than the length of the protection groove along the first direction, and the first direction is the arrangement direction of the protection groove and the gate groove. In this way, the P-buried layer can further reduce the electric field strength at the gate groove, enhance the protection of the gate groove, and improve the reliability of the silicon carbide transistor.

[0060] Alternatively, if Figure 1 As shown, the silicon carbide transistor may further include: a dielectric layer 700 disposed between the source electrode 600 and the silicon carbide layer 200, a drain electrode 800 disposed on the surface of the substrate 100 away from the silicon carbide layer 200, and a buffer layer 900 disposed between the silicon carbide layer 200 and the substrate 100. In this way, by providing the dielectric layer 700, the drain electrode 800, and the buffer layer 900, the structure of the silicon carbide transistor is improved, and the performance of the silicon carbide transistor is improved.

[0061] Based on the same inventive concept, an embodiment of the present invention also provides a method for manufacturing a silicon carbide transistor, such as Figure 5 As shown, including:

[0062] S501, forming a silicon carbide layer on a substrate; the silicon carbide layer includes: an N-drift layer, a P well, and an N+ source layer stacked in sequence on the substrate;

[0063] S502, etching a gate trench on a surface of the silicon carbide layer away from the substrate;

[0064] S503, backfilling the gate trench with P-doped silicon carbide to form a P-protection structure; at least a portion of the P-protection structure is disposed at the bottom of the gate trench;

[0065] S504, sequentially forming a gate insulating layer and a gate in the gate trench; the gate insulating layer isolates the P-protection structure from the gate, and the silicon carbide layer from the gate;

[0066] S505 , forming a source electrode on the silicon carbide layer, and connecting the P-protection structure to the source electrode.

[0067] In this way, a P-protection structure is formed by etching the gate trench and then backfilling P-doped silicon carbide. The P-protection structure is formed at the bottom of the gate trench, which can reduce the electric field strength of the gate insulating layer, thereby reducing the probability of the gate insulating layer being broken down, and improving the reliability of the silicon carbide transistor; in addition, the P-protection structure is connected to the source electrode, and the P-protection structure can be clamped through the source electrode, and then when the source electrode is grounded, the charge accumulated in the P-protection structure can be led away, thereby avoiding charge accumulation in the P-protection structure, improving the protection effect of the P-protection structure on the gate insulating layer, and can further improve the reliability of the silicon carbide transistor.

[0068] The method for manufacturing a silicon carbide transistor provided in an embodiment of the present invention is explained below in conjunction with specific embodiments.

[0069] S1, such as Figure 6As shown in (a), a buffer layer, an N-drift layer, a P well, and an N+ source layer are sequentially formed on the substrate.

[0070] The specific process may include: using a CVD process to sequentially epitaxially grow a first layer of N-doped silicon carbide, a second layer of N-doped silicon carbide, a P-doped silicon carbide, and an N+ doped silicon carbide on a substrate, wherein the first layer of N-doped silicon carbide is used as a buffer layer, the second layer of N-doped silicon carbide is used as an N-drift layer, the P-doped silicon carbide is used as a P-well, the N+ doped silicon carbide is used as an N+ source layer, and the N-drift layer, the P-well, and the N+ source layer constitute a silicon carbide layer.

[0071] Of course, the P well and N+ source layer can also be formed by ion implantation. The specific process may include: after forming the N-drift layer, ion implantation of different energies is performed on the surface of the N-drift layer away from the substrate, thereby forming the P well and N+ source layer at different depths.

[0072] S2, such as Figure 6 As shown in (b), a gate trench G1 is formed.

[0073] The specific process may include: forming a first mask layer with a predetermined pattern on the surface of the silicon carbide layer; then, etching the area exposed by the first mask layer, etching into the N-drift layer, and stopping the etching to form a gate trench at a specific position; finally, removing the first mask layer and cleaning it to facilitate the production of other structures. Figure 6 As shown in (b), the opening width d of the gate trench can be, but is not limited to, set to 0.5 μm to 5 μm, and the depth h of the gate trench can be, but is not limited to, set to 1 μm to 25 μm.

[0074] Wherein, forming a first mask layer having a predetermined pattern may specifically include:

[0075] Silicon nitride is deposited on the surface of the first doped layer and used as an etching barrier layer; a silicon oxide layer is produced on the surface of the etching barrier layer and used as a first mask layer by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method; photoresist is spin-coated on the surface of the first mask layer, and the photoresist is patterned to obtain a photoresist with a predetermined pattern; the area exposed by the photoresist is etched to transfer the predetermined pattern to the first mask layer, thereby forming a first mask layer with a predetermined pattern.

[0076] It should be noted that since there is a silicon nitride layer between the first mask layer and the silicon carbide layer, when etching is performed using the first mask layer, the silicon nitride layer is etched first, and then the silicon carbide layer is etched.

[0077] Furthermore, when removing the first mask layer and performing cleaning, it may specifically include: performing wet etching using hydrofluoric acid to remove the first mask layer and the etching stop layer, and then performing SPM wet cleaning.

[0078] In addition, the direction of the gate trench obtained by etching is The crystal direction is symmetrical, and the error is within 0.2°, so as to facilitate the subsequent epitaxial growth of the P-protection structure; the acute angle between the sidewall of the gate trench obtained by etching and the horizontal direction can be, but not limited to, 85° to 90°, so as to reduce the difficulty of process implementation, wherein the horizontal direction can be as follows Figure 7 The direction shown by F1 in (b).

[0079] S3, such as Figure 6 As shown in (c), a P-protection structure is formed ( Figure 6 The area filled with sparse black dots in the figure represents the P-protection structure).

[0080] The specific process may include: using silane and propane as growth gases, and the ratio of carbon element to silicon element in the growth gas is 1:1, hydrogen is used as a carrier gas, trimethylaluminum is used as a P-type doping source gas, and hydrogen chloride gas is introduced to grow P-doped silicon carbide, so that the P-doped silicon carbide serves as a P-protective structure.

[0081] The effect of introducing hydrogen chloride gas is: it has a certain etching effect on P-doped silicon carbide. By controlling the flow rate of hydrogen chloride gas, it is possible to prevent the gate trench from closing too quickly during the process of epitaxial growth of P-doped silicon carbide, and at the same time, the thickness of the first connecting portion, the second connecting portion, and the top structure can be controlled. For example, when the epitaxial growth temperature is 1650° C., the epitaxial growth pressure is 60 kPa, the flow rate of silane is 36 sccm, the flow rate of propane is 12 sccm, and the flow rate of hydrogen is 40,000 sccm, the flow rate of hydrogen chloride gas can be, but is not limited to, 1800 sccm.

[0082] S4, such as Figure 6 As shown in (d), a gate insulating layer 400 and a gate 500 are sequentially formed in the gate trench G1.

[0083] The specific process may include: performing a thermal oxidation treatment at 800°C to 1000°C on the structure obtained in step S3, so that a silicon oxide layer is generated in the gate trench and other locations; or, using a low-pressure chemical vapor deposition method, depositing a silicon oxide layer on the surface of the structure obtained in step S3, and performing high-temperature annealing in a nitrogen monoxide environment, and the gaseous precursors of the reaction include but are not limited to ethyl orthosilicate and oxygen. Then, a conductive material is deposited on the silicon oxide layer so that the gate trench is filled; wherein the conductive material may be, but is not limited to, an in-situ doped polysilicon material. Thereafter, the silicon oxide layer and the conductive material outside the gate trench are removed to form a gate insulating layer and a gate. The thickness of the silicon oxide layer may be, but is not limited to, set to 50nm to 110nm.

[0084] Among them, the silicon oxide layer and the conductive material outside the gate trench can be removed by dry etching or CMP (Chemical Mechanical Polish). Of course, the silicon oxide layer outside the gate trench may not be removed in step S4 to simplify the process steps.

[0085] S5, such as Figure 6 As shown in (e), a dielectric layer and a dielectric layer through hole ( Figure 6 not shown).

[0086] The specific process may include: using a CVD method to deposit a whole layer of silicon dioxide on the surface of the silicon carbide layer away from the substrate; using the same process as in the above step S2 to obtain a second mask layer with a predetermined pattern, and then etching the exposed position of the second mask layer to form a dielectric layer covering the gate and a dielectric layer through hole penetrating the dielectric layer, wherein the dielectric layer through hole is used to connect the outside world with the gate. The dielectric layer is used to isolate the source electrode from the gate.

[0087] S6, such as Figure 6 As shown in (f), a source electrode and a drain electrode are formed to obtain a silicon carbide transistor.

[0088] The specific process of forming the source electrode may include: adopting the same process as in the above step S2, after obtaining a third mask layer with a predetermined pattern, etching the exposed position of the third mask layer, etching into the P well, and stopping etching; after the etching is completed, a metal layer is deposited on the entire surface of the structure, and the metal layer serves as a source electrode, and the source electrode is connected to the N+ source layer and the P well.

[0089] The specific process of forming the drain electrode may include: after thinning the substrate, forming a back metal on the surface of the substrate away from the silicon carbide layer, and the back metal serves as the drain electrode.

[0090] After forming the source electrode and the drain electrode, laser annealing is performed so that the source electrode forms an ohmic contact with the N+ source layer and the P well, and the drain electrode forms an ohmic contact with the substrate.

[0091] The performance of the silicon carbide transistor is simulated below, and the corresponding P-protection structure does not include the first top structure and the second top structure during the simulation.

[0092] like Figure 7 As shown, Figure 7 The simulation diagram of the on-current streamline distribution of the silicon carbide transistor is shown in FIG. Figure 7 (not shown) have uniform and equal thickness, Figure 7 The thicknesses of the first connecting portion and the second connecting portion in (a), (b) and (c) are 10 nm, 20 nm and 40 nm respectively. Figure 7 It can be seen that when the thickness of the first connection part and the second connection part changes, the on-current streamline distribution of the silicon carbide transistor remains basically unchanged, indicating that the thickness of the first connection part L1 and the second connection part has little effect on the on-current streamline.

[0093] like Figure 8 As shown, Figure 8 This is a simulation diagram of the electron current density distribution of the silicon carbide transistor. During the simulation, the drain electrode ( Figure 8 The voltage of the gate electrode 500 is +60V, the voltage of the gate electrode 500 is +20V, and the first connection part and the second connection part ( Figure 8 (not shown) have uniform and equal thickness, Figure 8 The thicknesses of the first connecting portion and the second connecting portion in (a), (b) and (c) are 10 nm, 20 nm and 40 nm respectively. Figure 8 It can be seen that as the thickness of the first connection part and the second connection part decreases, the electron current density of the silicon carbide transistor becomes larger and larger, which means that the on-resistance of the silicon carbide transistor gradually decreases and the on-performance is improved. Therefore, the thickness of the first connection part and the second connection part can be set according to actual needs.

[0094] like Fig. 9 As shown, Fig. 9 is the relationship between current density and drain electrode voltage, Fig. 9 Curve 91, curve 92 and curve 93 are curves corresponding to the case where the thickness of the first connecting portion and the second connecting portion is 10 nm, 20 nm and 40 nm respectively. Fig. 9 It can be seen that, under the same drain electrode voltage, as the thickness of the first connecting part and the second connecting part decreases, the current density gradually increases, the on-resistance of the silicon carbide transistor gradually decreases, and the on-performance gradually increases.

[0095] like Fig.10 As shown, Fig.10is a relationship diagram between the reduction ratio of the on-current and the drain electrode voltage, wherein the on-current when the thickness of the first connecting portion and the second connecting portion is 10 nm is referred to as the first on-current, the on-current when the thickness of the first connecting portion and the second connecting portion is 20 nm is referred to as the second on-current, and the on-current when the thickness of the first connecting portion and the second connecting portion is 40 nm is referred to as the third on-current, Fig.10 The middle curve 10a is the reduction ratio of the second conduction current compared to the first conduction current, and the curve 10b is the reduction ratio of the third conduction current compared to the first conduction current. Fig.10 It can be seen that the third on-current has a larger reduction ratio at low drain electrode voltage. This is because the thickness of the PN junction formed by the first connecting part and the second connecting part close to the end of the protection part and the N+ drift layer is larger, which makes it more difficult to overcome the PN junction and increases the on-resistance, resulting in a larger reduction ratio of the third on-current. However, when the drain electrode voltage is high, the PN junction is penetrated, and the reduction ratio of the third on-current is greatly reduced. When the drain electrode voltage is +60V, the reduction ratio of the third on-current is about 0.67, so that the on-current of the silicon carbide transistor can be increased by setting a thinner first connecting part and second connecting part.

[0096] like Fig.11 and Fig.12 As shown, Fig.11 This is a simulation diagram of the electric field distribution of a silicon carbide transistor under reverse breakdown voltage. Fig.12 This is a simulation diagram of the potential distribution of a silicon carbide transistor under reverse breakdown voltage. Fig.11 and Fig.12 In the above formula, source means source electrode, gate means gate electrode, and drain means drain electrode. Fig.11 As can be seen in FIG. 1 , the P-protection structure is close to one side of the substrate 100 (i.e. Fig.11 The electric field strength in the area indicated by the dashed line Q1 is relatively large. Fig.12 , the P-protection structure is close to the side of the substrate 100 (ie Fig.12 The potential change of the area (shown in the dotted box Q2) is also large, so setting a P-protection structure can make the high electric field strength area close to the side of the P-protection structure close to the substrate 100, reducing the electric field strength and potential at the gate insulating layer, realizing the protection of the gate insulating layer, and improving the reliability of the silicon carbide transistor.

[0097] like Fig.13 As shown, Fig.13 The relationship between the drain current density and the reverse voltage of the silicon carbide transistor is shown in Figure 2. The doping concentration of the N-drift layer of the silicon carbide transistor is about 1×10 16 / cm 3 The thickness of the N-drift layer is about 7 μm. Fig.13It can be seen that when the reverse voltage is about 1174V, the silicon carbide transistor breaks down, that is, the reverse breakdown voltage of the silicon carbide transistor is about 1174V. The reverse breakdown voltage is relatively high, so the silicon carbide crystal has a strong voltage resistance.

[0098] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, the implementation principle of which is similar to the implementation principle of the aforementioned silicon carbide transistor. The specific implementation method of the electronic device can refer to the embodiment of the aforementioned silicon carbide transistor, and the repeated parts will not be repeated.

[0099] Specifically, an electronic device provided by an embodiment of the present invention is Fig.14 As shown, it includes: the silicon carbide transistor 1401 as described above. Among them, the application scenarios of the electronic device include but are not limited to: vehicle-mounted chips, high-voltage inverters, distribution networks, microgrids, high-voltage photovoltaics, etc.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A silicon carbide transistor, characterized in that: include: A substrate, and a silicon carbide layer disposed on the substrate; the silicon carbide layer comprises: an N-drift layer, a P well, an N+ source layer and a source electrode stacked in sequence on the substrate; The silicon carbide transistor further comprises a P-protection structure, a gate trench is arranged on a surface of the silicon carbide layer on one side away from the substrate, at least a portion of the P-protection structure is arranged at the bottom of the gate trench, a gate insulating layer and a gate are further arranged in the gate trench, and the gate insulating layer isolates the P-protection structure from the gate, and the silicon carbide layer from the gate, respectively; The P-protection structure is connected to the source electrode, and the P-protection structure is connected to the N+ source layer.

2. The silicon carbide transistor according to claim 1, wherein: The P-protection structure comprises: a protection portion, a first connection portion, a second connection portion, a first top structure and a second top structure; The gate trench comprises a first side wall and a second side wall which are opposite to each other; the protection portion is located at the bottom of the gate trench; the protection portion extends the first connection portion along the first side wall and extends the second connection portion along the second side wall on a surface of a side away from the substrate; The first top structure and the second top structure are both located on the silicon carbide layer; The first top structure is connected to the first connection portion and the source electrode respectively, and the second top structure is connected to the second connection portion and the source electrode respectively; The first connecting portion and the second connecting portion are both located between the gate insulating layer and the silicon carbide layer.

3. The silicon carbide transistor according to claim 2, characterized in that The thickness of the first connecting portion close to the protecting portion is smaller than the thickness of the first connecting portion away from the protecting portion; Alternatively, a thickness of the second connecting portion at an end close to the protecting portion is smaller than a thickness of an end away from the protecting portion.

4. The silicon carbide transistor according to claim 2, wherein: The thickness of the first connecting portion close to one end of the protecting portion is not greater than 100 nm; Alternatively, the thickness of the second connecting portion close to one end of the protecting portion is not greater than 100 nm.

5. The silicon carbide transistor according to claim 2, wherein: The thickness of the first top structure or the second top structure is greater than 0 and not greater than 5 μm.

6. The silicon carbide transistor according to claim 1, wherein: The source electrode is connected to the N+ source layer; The source electrode passes through the N+ source layer and is connected to the P well.

7. The silicon carbide transistor according to claim 1, wherein: The N-drift layer includes: a first N-drift layer and a second N-drift layer, the doping concentration of the second N-drift layer is greater than the doping concentration of the first N-drift layer, and the first N-drift layer is located between the substrate and the second N-drift layer; A surface of the P-protection structure facing the substrate is located within an interface between the first N-drift layer and the second N-drift layer.

8. The silicon carbide transistor according to claim 7, characterized in that The second N-drift layer and the P-protection structure form a super junction.

9. The silicon carbide transistor according to any one of claims 1 to 8, characterized in that: A protection groove is also provided on a surface of the silicon carbide layer away from the substrate, and the protection groove is provided on two opposite sides of the gate groove; The P-protection structure is also arranged at the bottom of the protection trench.

10. A method for manufacturing a silicon carbide transistor according to any one of claims 1 to 9, characterized in that: include: A silicon carbide layer is formed on the substrate; the silicon carbide layer comprises: an N-drift layer, a P well, and an N+ source layer stacked in sequence on the substrate; Etching a gate trench on a surface of the silicon carbide layer away from the substrate; Backfilling P-doped silicon carbide in the gate trench to form a P-protection structure; at least a portion of the P-protection structure is disposed at the bottom of the gate trench; A gate insulating layer and a gate are sequentially formed in the gate trench; the gate insulating layer isolates the P-protection structure from the gate, and the silicon carbide layer from the gate; A source electrode is formed on the silicon carbide layer, and the P-protection structure is connected to the source electrode.

11. An electronic device, characterized in that: include: A silicon carbide transistor as claimed in any one of claims 1 to 9.

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