Formation method of semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure, and relates to the technical field of semiconductors. The forming method comprises the following steps: forming an initial semiconductor structure which comprises a plurality of channels; a laminated structure is formed in each channel, the laminated structure extends to the surface of the initial semiconductor structure, and the laminated structure comprises an insulating layer, an oxide layer and a sacrificial layer; protective gas and auxiliary gas are introduced into the channels and react, so that a protective layer is formed on the surface of the sacrificial layer in a conformal mode, the protective gas comprises silicon ions, and the auxiliary gas comprises oxygen ions; and etching the laminated structure with the protective layer, removing a part of the laminated structure at the bottom of the channel and removing the laminated structure on the surface of the functional layer so as to expose the surfaces of the substrate and the functional layer. According to the invention, the protection layers are formed on the film layers in the channel of the etching device, so that the integrity of the morphology of the etched film layers and the etching contour is ensured, and a good structural basis is provided for the subsequent technological process of the device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] Memory is widely used in smart devices such as mobile phones and tablets due to its small size, fast transmission speed, and high integration. With the evolution of semiconductor process technology and the continuous reduction in the size of terminal devices, the size of memory is also shrinking, and the feature size of the device is also decreasing.

[0003] At present, the characteristic size of devices can reach more than ten nanometers or even smaller, which increases the difficulty of the manufacturing process. Especially in the etching process, as the characteristic size decreases, defects in the etching profile will occur, which will affect the function of subsequent devices.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, a method for forming a semiconductor structure is provided. The method ensures the integrity and alignment of the etching profile by forming a protective layer when etching a film layer on a device channel.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate, a functional layer, and a plurality of spaced channels formed on the functional layer;

[0009] Forming a stacked structure on the bottom wall and the side wall of each of the trenches, and the stacked structure extends to the surface of the initial semiconductor structure, wherein the stacked structure includes an insulating layer, an oxide layer and a sacrificial layer formed in sequence along the surface away from the initial semiconductor structure;

[0010] Introducing a protective gas and an auxiliary gas into each of the channels and reacting them to conformally form a protective layer on the surface of the sacrificial layer, wherein the protective gas includes silicon ions and the auxiliary gas includes oxygen ions;

[0011] The stacked structure with the protective layer is etched to remove a portion of the stacked structure located at the bottom of the trench and the stacked structure located on the surface of the functional layer to expose the surfaces of the substrate and the functional layer.

[0012] In an exemplary embodiment of the present disclosure, within the same channel, the orthographic projection area of ​​the protection layer on the substrate is one tenth to one fifth of the orthographic projection area of ​​the opening of the channel on the substrate.

[0013] In an exemplary embodiment of the present disclosure, the protective gas includes at least one of silicon tetrachloride, monosilane, silylene, disilane or silicate.

[0014] In an exemplary embodiment of the present disclosure, the auxiliary gas includes at least one of oxygen, methanol or ethanol.

[0015] In an exemplary embodiment of the present disclosure, the gas flow rate of the protective gas is 10 sccm to 100 sccm, and the gas flow rate of the auxiliary gas is 100 sccm to 500 sccm.

[0016] In an exemplary embodiment of the present disclosure, the method includes:

[0017] Under the condition of a pressure of 5 mT to 30 mT, the auxiliary gas reacts with the protective gas.

[0018] In an exemplary embodiment of the present disclosure, the method includes:

[0019] Under the condition that the bias voltage is 1000W-1500W, the auxiliary gas reacts with the protective gas.

[0020] In an exemplary embodiment of the present disclosure, the forming of the initial semiconductor structure further comprises:

[0021] forming a conductive layer on the substrate;

[0022] A plurality of channels are formed in the conductive layer, so that the conductive layer forms a plurality of conductive parts distributed at intervals.

[0023] In an exemplary embodiment of the present disclosure, the method further includes:

[0024] A first source and drain are formed on the substrate, wherein an orthographic projection of the first source and drain on the bottom surface of the substrate does not overlap with an orthographic projection of the conductive portion on the bottom surface of the substrate.

[0025] In an exemplary embodiment of the present disclosure, the method further includes:

[0026] The remaining protection layer is removed to expose the sidewall of the sacrificial layer, so that the opening sidewall of the channel is aligned with the substrate.

[0027] In an exemplary embodiment of the present disclosure, the method further includes:

[0028] Removing the remaining sacrificial layer to expose a first side wall, a second side wall and a third side wall, wherein the first side wall and the second side wall are two non-coplanar side surfaces on the oxide layer, the third side wall is a side surface of the insulating layer, and the second side wall is coplanar with the third side wall;

[0029] A semiconductor layer is conformally formed on a surface formed by the first side wall, the second side wall and the third side wall, and the semiconductor layer is connected to the first source and drain.

[0030] In an exemplary embodiment of the present disclosure, the method further includes:

[0031] Filling the remaining opening portion of the trench with an insulating material layer, wherein the surface of the insulating material layer is flush with the surface of the initial semiconductor structure;

[0032] A second source and drain are formed on a surface jointly formed by the insulating material layer and the semiconductor layer to obtain a target semiconductor structure, wherein an orthographic projection of the second source and drain on the substrate does not overlap with an orthographic projection of the conductive portion on the substrate.

[0033] In an exemplary embodiment of the present disclosure, the initial semiconductor structure further includes a barrier layer, wherein the barrier layer is formed between the conductive layer and the substrate, and the barrier layer is used to block the conductive layer from diffusing into the substrate.

[0034] The present invention provides a method for forming a semiconductor structure. By introducing a protective gas and an auxiliary gas into a channel, the protective gas and the auxiliary gas react to form a protective layer, which can protect the film layer on the side wall of the channel when the channel is subsequently etched, and can form a contour with a complete morphology after etching, thereby reducing structural defects caused by the etching process and improving the collimation of the etching side wall. In addition, the protective layer formed by the protective gas and the auxiliary gas is easy to remove, does not increase the complexity of the process, does not have an adverse effect on the subsequent process, and the protective layer is universal and can be applied to the etching process of various film layers. The formation method can improve the overall yield of the device.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0037] Figure 1 The present invention discloses a flow chart of a method for forming a semiconductor structure in an exemplary embodiment.

[0038] Figure 2 It is a schematic structural diagram of a semiconductor structure in the prior art in an exemplary embodiment of the present disclosure.

[0039] Figure 3 It is a schematic structural diagram of a substrate and a first source and drain of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0040] Figure 4 It is a schematic structural diagram of a conductive layer of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0041] Figure 5 It is a schematic structural diagram of a sub-conductive layer of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0042] Figure 6 It is a schematic structural diagram of a channel of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0043] Figure 7 It is a schematic structural diagram of a stacked structure of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0044] Figure 8 It is a schematic structural diagram of a protective layer of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0045] Fig. 9 It is a schematic structural diagram of a semiconductor structure after etching in an exemplary embodiment of the present disclosure.

[0046] Fig.10 It is a schematic structural diagram of a semiconductor structure after removing a sacrificial layer in an exemplary embodiment of the present disclosure.

[0047] Fig.11 It is a schematic structural diagram of a semiconductor structure for forming a semiconductor layer in an exemplary embodiment of the present disclosure.

[0048] Fig.12 It is a schematic structural diagram of a semiconductor structure in which an insulating material layer is formed in an exemplary embodiment of the present disclosure.

[0049] Fig.13It is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0050] The reference numerals are described as follows:

[0051] 1000, defect; 2000, channel; 100, substrate; 120, stacked structure; 121, insulating layer; 122, oxide layer; 1221, first side wall; 1222, second side wall; 123, sacrificial layer; 1231, third side wall; 200, protective layer; 310, first source and drain; 320, second source and drain; 400, conductive layer; 410, sub-conductive layer; 420, conductive part; 401, blocking layer; 500, semiconductor layer; 600, insulating material layer; 700, isolation layer. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0053] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0054] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0055] In the related art, transistors, as a semiconductor device, are an indispensable component of storage units. They are widely used in electronic circuits and have functions such as switch control, signal amplification, and voltage stabilization. Junction Field-Effect Transistor (JFET), as a voltage-controlled semiconductor device, can control the current between the source and the drain by changing the voltage between the gate and the source, thereby achieving the purpose of controlling the circuit.

[0056] In the process of manufacturing transistors, a gate oxide layer is formed in the channel of the transistor to isolate the gate and source and drain of the transistor. However, due to the small feature size of existing devices, the opening size of the channel is also small, which increases the difficulty of the deposition process and etching process in the channel opening. At present, when etching the gate oxide layer, due to the different etching selectivity between the gate oxide layer and other film layers in the etching process, defects 1000 are formed on the sidewalls of the etched channel structure, such as Figure 2 As shown, a larger opening is formed on the side of the channel away from the substrate, resulting in an incomplete etching profile, affecting subsequent process steps, and even increasing the leakage current of the device, affecting the threshold voltage of the device, and reducing the overall performance of the device.

[0057] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, combined Figures 3 to 13 The forming method includes: step S10 to step S40.

[0058] Wherein, step S10: forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate 100, a functional layer and a plurality of channels 2000 formed on the functional layer and distributed at intervals;

[0059] Step S20: forming a stacked structure 120 on the bottom wall and the side wall of each trench 2000, and the stacked structure 120 extends to the surface of the initial semiconductor structure, wherein the stacked structure 120 includes an insulating layer 121, an oxide layer 122 and a sacrificial layer 123 sequentially formed along the surface away from the initial semiconductor structure;

[0060] Step S30: introducing a protective gas and an auxiliary gas into each channel 2000 and reacting them to conformally form a protective layer 200 on the surface of the sacrificial layer 123 , wherein the protective gas includes silicon ions and the auxiliary gas includes oxygen ions;

[0061] Step S40: etching the stacked structure 120 with the protection layer 200 to remove a portion of the stacked structure 120 at the bottom of the trench 2000 and the stacked structure 120 at the surface of the functional layer to expose the surfaces of the substrate 100 and the functional layer.

[0062] The method for forming a semiconductor structure provided by the present disclosure introduces a protective gas and an auxiliary gas into a channel 2000, and the protective gas and the auxiliary gas react to form a protective layer 200. When etching the stacked structure 120 in the channel 2000, the protective layer 200 can form a protective effect on the film layer on the side wall of the channel 2000, thereby ensuring the etching integrity between the side wall of the channel 2000 and the surface of the initial semiconductor structure, avoiding etching defects at the connection, so as to form an etching profile with a complete morphology, reduce structural defects caused by the etching process, and improve the collimation of the etching side wall; in addition, the protective layer 200 formed by the protective gas and the auxiliary gas is easy to remove, does not increase the complexity of the process, and does not have an adverse effect on subsequent process steps. Moreover, this protective layer 200 is universal and can be applied to etching processes of various film layers, thereby solving the problem of device performance degradation caused by the cumulative effect of etching defects in multiple processes.

[0063] The following will describe in detail the steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0064] In the embodiments provided in the present disclosure, Figures 3 to 6 As shown, in step S10, an initial semiconductor structure is formed, and the initial semiconductor structure includes a substrate 100, a functional layer, and a plurality of channels 2000 formed on the functional layer and distributed at intervals.

[0065] Wherein, the substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs). The embodiments provided in the present disclosure are described by taking the substrate 100 as a substrate including silicon (Si) ions as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the protection scope of the present disclosure.

[0066] Before forming the channel 2000 on the substrate 100, as Figure 3As shown, the formation method also includes: forming a first source and drain 310 on the substrate 100. The substrate 100 may include an epitaxial layer, and the first source and drain 310 may be formed by doping the epitaxial layer. For example, a trivalent element such as boron (B), gallium (Ga), indium (In), etc. may be doped on the substrate 100 to form a P-type source and drain region on the substrate 100, and a P-type source and drain may be formed by etching or other processes; or a pentavalent element such as phosphorus (P), arsenic (As), antimony (Sb), etc. may be doped on the substrate 100 to form an N-type source and drain region on the substrate 100, and an N-type source and drain may be formed by etching or other processes. The type of the first source and drain 310 may be selected according to the actual structure of the device. Of course, in order to isolate multiple first source and drain electrodes 310, an insulating structure may be formed between two adjacent first source and drain electrodes 310, such as a silicon dioxide insulating structure. This insulating structure is made of an insulating material commonly used in the art, and will not be described in detail here.

[0067] The functional layer may include a conductive layer 400 formed on the substrate 100. After forming the first source and drain electrodes 310, as shown in FIG. Figure 4 As shown, the formation method further includes: forming a conductive layer 400 on the substrate 100. Forming a plurality of isolation grooves in the conductive layer 400 to divide the conductive layer 400 into a plurality of sub-conductive layers 410; filling the plurality of isolation grooves with isolation materials to form an isolation layer 700, as shown in FIG. Figure 5 As shown; a channel 2000 is formed in each sub-conductive layer 410 to form a plurality of conductive portions 420 distributed at intervals, such as Figure 6 Each conductive portion 420 can be used as a gate in subsequent devices.

[0068] The conductive layer 400 may be made of metal materials, such as one or more of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), etc. The conductive layer 400 may be formed by chemical vapor deposition (CVD), such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD); or physical vapor deposition (PVD), such as sputtering, electron beam evaporation (E-beam Evaporation); or atomic layer epitaxy (ALE); or chemical vapor infiltration (CVI).

[0069] Before forming the conductive layer 400, Figures 3 to 13 As shown, a barrier layer 401 may also be formed in the initial semiconductor structure, and the barrier layer 401 is used to block the diffusion of the conductive layer 400 into the substrate 100. Specifically, when the conductive layer 400 is metal tungsten, the barrier layer 401 can prevent the diffusion of tungsten and other metal atoms in the semiconductor device. The barrier layer 401 may be formed of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicide (TiSi2), and tantalum silicide (TaSi2). It may be formed by methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and electrochemical deposition (Electrochemical Deposition). In some embodiments, the barrier layer 401 may be a one-layer structure or a multi-layer structure, and the material, formation method, and number of layers of the barrier layer 401 may be selected according to the actual structure and functional requirements of the device.

[0070] The channel 2000 is formed in each sub-conductive layer 410, comprising: etching the sub-conductive layer 410 from a direction away from the substrate 100 to a direction close to the substrate 100 in a direction perpendicular to the substrate 100 until the surface of the substrate 100 is exposed, so as to form a channel 2000 in each sub-conductive layer 410, wherein each channel 2000 separates each sub-conductive layer 410 into two conductive parts 420. The orthographic projection of the conductive part 420 on the bottom surface of the substrate 100 does not overlap with the orthographic projection of the first source and drain 310 on the bottom surface of the substrate 100, that is, each first source and drain 310 is located at the bottom of the channel 2000, and the conductive part 420 is located at the side wall of the channel 2000, so as to isolate the conductive part 420 from the first source and drain 310 in a direction perpendicular to the substrate 100.

[0071] Each sub-conductive layer 410 may be etched by dry etching methods such as plasma etching, ion beam etching, chemical vapor etching (CVE), laser etching, etc., or wet etching may be used.

[0072] In the embodiments provided in the present disclosure, Figure 7 As shown, in step S20, a stacked structure 120 is formed on the bottom wall and side wall of each trench 2000, and the stacked structure 120 extends to the surface of the initial semiconductor structure, wherein the stacked structure 120 includes an insulating layer 121, an oxide layer 122 and a sacrificial layer 123 formed in sequence along the surface away from the initial semiconductor structure.

[0073] The insulating layer 121 in the stacked structure 120 covers the sidewalls and bottom walls of each channel 2000 and extends to the top surface of the initial semiconductor structure. It covers the sidewalls of the conductive portion 420 to provide insulation for the conductive portion 420. The insulating layer 121 can be formed by one or more of materials such as silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), tantalum oxide (Ta2O5) or hafnium oxide (HfO2). The insulating layer 121 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical solution deposition (Chemical Solution Deposition) and the like.

[0074] The oxide layer 122 is conformally formed on the insulating layer 121, and can be formed as a gate oxide layer 122 on the initial semiconductor structure to form electrical insulation, electric field control and other functions in the semiconductor structure. The oxide layer 122 can be formed by one or more of silicon dioxide (SiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), hafnium silicon oxide (HfSiO), and zirconium silicon oxide (ZrSiO). The oxide layer 122 can be formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, epitaxial growth, sol-gel method and other methods.

[0075] The sacrificial layer 123 is conformally formed on the oxide layer 122, and the sacrificial layer 123 can provide a basis for the electrical connection structure of the subsequent structure. The sacrificial layer 123 can be formed of materials such as amorphous silicon (Amorphous Silicon, A-Si), silicon (Si), etc. The sacrificial layer 123 can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering or other thin film deposition techniques.

[0076] It should be noted that conformal formation in the embodiments of the present disclosure refers to the formation of one film layer on the surface of another film layer, and the cross-sectional shapes of the two film layers in the direction perpendicular to the substrate 100 are the same or substantially the same, and the coverage areas and formation positions of the two film layers are also the same or substantially the same. In addition, in the present disclosure, the materials and formation processes of the sacrificial layer 123, the oxide layer 122, and the insulating layer 121 can be adaptively selected and adjusted according to actual structural requirements and process requirements.

[0077] In the embodiments provided in the present disclosure, Figure 8 and Fig. 9 As shown, in step S30 and step S40, a protective gas and an auxiliary gas are introduced into each channel 2000 and reacted to conformally form a protective layer 200 on the surface of the sacrificial layer 123, wherein the protective gas includes silicon ions and the auxiliary gas includes oxygen ions; the stacked structure 120 with the protective layer 200 is etched to remove a portion of the stacked structure 120 located at the bottom of the channel 2000 and the stacked structure 120 located on the surface of the functional layer to expose the surfaces of the substrate 100 and the functional layer.

[0078] After forming the stacked structure 120, the stacked structure 120 needs to be etched to form a subsequent structure of the semiconductor structure. However, the inventors have found that when etching the stacked structure 120, especially when etching the stacked structure 120 located at the junction of the sidewall of the channel 2000 and the surface of the initial semiconductor structure, due to the etching anisotropy of each film layer in the stacked structure 120, a profile defect will be generated when etching the stacked structure 120, and a structure with a wide opening at the top and a narrow opening at the bottom will be formed in the channel 2000. Here, the width and narrowness refer to the size of the opening on the cross section of the channel 2000. When other film layers are subsequently deposited, it is difficult to ensure the formation quality of the film layer, which affects the overall performance of the device, such as increasing the leakage current, affecting the threshold voltage, and reducing the reliability. Therefore, before etching the stacked structure 120, a protective gas and an auxiliary gas are introduced into each channel 2000 to form a protective layer 200 on the surface of the sacrificial layer 123.

[0079] The protective gas may be at least one of silicon tetrachloride (SiCl4), monosilane (SiH4), silylene (SiH2), disilane (Si2H6) or silicate, wherein silicate is a salt containing silicon ions, and its composition can be determined according to actual use requirements. The auxiliary gas may be at least one of oxygen (O2), methanol (CH3OH) or ethanol (C2H5OH).

[0080] Taking the case where the protective gas is silicon tetrachloride (SiCl4) and the auxiliary gas is oxygen (O2) as an example, the protective gas and the auxiliary gas react to form a protective layer 200, and the protective layer 200 is attached to the surface of the sacrificial layer 123, wherein the reaction process is SiCl4+O2→SiO2+Cl2↑, wherein silicon dioxide forms the protective layer 200, and the chlorine gas is drawn away. In the subsequent etching process, the protective layer 200 can ensure that the etching profile shape at the interface between the side wall of the stacked structure 120 and the surface of the initial semiconductor structure is not destroyed, thereby ensuring the integrity of the structural profile after etching. Of course, the chlorine gas can also be separated and recycled.

[0081] Similarly, if the shielding gas and auxiliary gas are other gases, the reaction process includes Si + +O - →SiO2, and the byproducts generated can be pumped away or vaporized, so that silicon dioxide is deposited on the surface of the sacrificial layer 123 to form the protective layer 200. For example, when the protective gas is monosilane (SiH4), the reaction process is SiH4+O2→SiO2+H2O↑, wherein the reaction byproduct water is pumped away in gaseous form, or the structure can be dried to a certain extent during the process of forming the protective layer 200.

[0082] After the protective layer 200 is formed, during the etching of the stacked structure 120, due to etching anisotropy, the etching speed of the stacked structure 120 on the sidewall of the trench 2000 is lower than that of the stacked structure 120 located on the surface of the initial semiconductor structure, so that the protective layer 200 ensures that the sidewall of the structure after etching is aligned with the surface of the substrate 100. Alignment refers to the strict verticality (the angle between the two is 90 degrees) or approximately verticality between the sidewall of the structure and the surface of the substrate 100, and the alignment in the embodiments provided herein all has this meaning.

[0083] In the embodiments provided in the present disclosure, the reaction conditions of the auxiliary gas and the protective gas are as follows:

[0084] The gas flow rate of the shielding gas is 10 sccm (cubic centimeters per minute) to 100 sccm, for example, it can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc. The gas flow rate of the auxiliary gas is 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, etc. The flow rates of the shielding gas and the auxiliary gas can be adaptively adjusted within the above range according to actual process requirements.

[0085] The reaction pressure is 5 mT (milliton force per square meter) to 30 mT, for example, 5 mT, 10 mT, 15 mT, 20 mT, 25 mT, 30 mT, etc. The reaction pressure can be selected and adjusted according to actual process requirements.

[0086] The reaction bias voltage is 1000W (watt) to 1500W, for example, it can be 1000W, 1100W, 1200W, 1300W, 1400W, 1500W, etc. The reaction bias voltage can be adaptively selected and adjusted according to actual process requirements.

[0087] In the embodiments provided in the present disclosure, when forming the protective layer 200, in the same channel 2000, the orthographic projection area of ​​the protective layer 200 on the substrate 100 is one tenth to one fifth of the orthographic projection area of ​​the opening of the channel 2000 on the substrate 100, that is, the area ratio of the two can be 10% to 20%, such as 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%. For example, in some embodiments, the size of the opening of the channel 2000 is 60nm (nanometers), the thickness of the protective layer 200 formed on one side wall of the channel 2000 can be 4.5nm, and the thickness of the protective layer 200 formed on both side walls of the channel 2000 in one channel 2000 is 9nm, and the thickness of the protective layer 200 is 15% of the size of the opening of the channel 2000. The size of the channel 2000 refers to the maximum distance (or minimum distance) between the two side walls of the opening of the channel 2000, and the thickness of the protective layer 200 refers to the maximum thickness (or minimum thickness) of the protective layer 200 in a direction parallel to the substrate 100. When the thickness of the protective layer 200 is within this range, the best etching effect of the stacked structure 120 can be ensured, the profile alignment and integrity of the structure after etching can be ensured, and a good structural foundation can be provided for forming a subsequent semiconductor structure.

[0088] In addition, the protective layer 200 provided by the present disclosure can be applied before etching other film layers according to actual process requirements to ensure the integrity and alignment of the etching profile. The protective layer 200 is versatile and can be applied to etching processes of various film layers, solving the problem of device performance degradation caused by the cumulative effect of etching defects in multiple processes.

[0089] In the embodiment provided by the present disclosure, after etching the stacked structure 120, the formation method further includes: removing the remaining protective layer 200 to expose the side wall of the sacrificial layer 123, so that the opening side wall of the channel 2000 is aligned with the substrate 100. After etching the stacked structure 120 with the protective layer 200, there will be a residual or residue of the protective layer 200. In order to avoid the influence of the protective layer 200 on the subsequent film formation or process, it is necessary to remove the remaining protective layer 200. The protective layer 200 can be removed by wet chemical etching, dry chemical etching, chemical mechanical polishing (CMP), ion milling, etc. For example, when wet chemical etching is used, hydrofluoric acid (HF) or its mixed solution (such as buffered hydrofluoric acid, BHF) can be used to etch silicon dioxide; if dry etching is used, carbon tetrafluoride (CF4) or octafluorocyclobutane (C4F8) can be used to convert it into a plasma state, and then react with the surface of silicon dioxide to etch it away. The specific removal method can be adaptively selected according to the process requirements and structural performance.

[0090] In the embodiments provided in the present disclosure, Fig.10 and Fig.11 As shown, after removing the remaining protective layer 200, the formation method further includes: removing the remaining sacrificial layer 123 to expose the first side wall 1221, the second side wall 1222 and the third side wall 1231, wherein the first side wall 1221 and the second side wall 1222 are two non-coplanar side surfaces on the oxide layer 122, the third side wall 1231 is the side surface of the insulating layer 121, and the second side wall 1222 is coplanar with the third side wall 1231; conformally forming a semiconductor layer 500 on the surface jointly formed by the first side wall 1221, the second side wall 1222 and the third side wall 1231, and the semiconductor layer 500 is connected to the first source and drain 310.

[0091] Among them, the semiconductor layer 500 can extend to the first source and drain 310. In the structure, the semiconductor layer 500 is electrically connected to the first source and drain 310. The semiconductor layer 500 can provide a conductive path for the channel 2000, so that the current can flow between the first source and drain 310 and the second source and drain 320. The semiconductor layer 500 can be made of materials such as polysilicon (poly), strained silicon, silicon germanium alloy (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium silicide (GaSi), indium silicide (InSi), etc. It can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), ion implantation, etc.

[0092] In the embodiments provided in the present disclosure, Fig.12 and Fig.13 As shown, after forming the semiconductor layer 500, the formation method also includes: filling the remaining opening portion of the channel 2000 with an insulating material layer 600, wherein the surface of the insulating material layer 600 is flush with the surface of the initial semiconductor structure; forming a second source and drain 320 on the surface jointly formed by the insulating material layer 600 and the semiconductor layer 500 to obtain a target semiconductor structure, wherein the orthographic projection of the second source and drain 320 on the substrate 100 does not overlap with the orthographic projection of the conductive portion 420 on the substrate 100.

[0093] The insulating material layer 600 is filled in the remaining openings in the trench 2000 to form an isolation and insulation effect for different conductive parts 420 (gates). The insulating material layer 600 can be formed of silicon dioxide (SiO2), silicon nitride (Si3N4), high dielectric constant (High-k) materials (such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3)), organic dielectric materials (such as polyimide (PI)), etc. The formation method can be similar to the formation method of the insulating layer 121, which will not be repeated here.

[0094] After forming the insulating material layer 600, it is necessary to form the second source-drain electrode 320 on the surface formed by the insulating material layer 600 and the semiconductor layer 500, and the semiconductor layer 500 is electrically connected to the first source-drain electrode 310 and the second source-drain electrode 320. In order to avoid leakage between the second source-drain electrode 320 and the conductive part 420, the orthographic projection of the second source-drain electrode 320 on the substrate 100 may not overlap with the orthographic projection of the conductive part 420 on the substrate 100, that is, the second source-drain electrode 320 is located at the top of the opening of the channel 2000, the first source-drain electrode 310 is located at the bottom of the opening of the channel 2000, and the first source-drain electrode 310 and the second source-drain electrode 320 are arranged opposite to each other.

[0095] In the embodiments provided in the present disclosure, the target semiconductor structure may be applied in a junction field effect transistor (JFET), or may be a transistor with a vertical structure or other applicable types of transistors.

[0096] The method for forming a semiconductor structure provided by the present disclosure introduces a protective gas and an auxiliary gas into a channel 2000, and the protective gas and the auxiliary gas react to form a protective layer 200. When etching the stacked structure 120 in the channel 2000, the protective layer 200 can form a protective effect on the film layer on the side wall of the channel 2000, thereby ensuring the etching integrity between the side wall of the channel 2000 and the surface of the initial semiconductor structure, avoiding etching defects at the connection, so as to form an etching profile with a complete morphology, reduce structural defects caused by the etching process, and improve the collimation of the etching side wall; in addition, the protective layer 200 formed by the protective gas and the auxiliary gas is easy to remove, does not increase the complexity of the process, and does not have an adverse effect on the subsequent process.

[0097] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0098] The present disclosure provides a semiconductor structure, such as Fig.13 As shown, the semiconductor structure is prepared by the above-mentioned formation method.

[0099] In an embodiment provided in the present disclosure, the semiconductor structure may include a gate and a first source-drain 310 and a second source-drain 320 formed on both sides of the gate.

[0100] Among them, a pair of source and drain electrodes can be shared between two adjacent gates, which saves the occupied space of the device and improves the arrangement density of the device. A channel 2000 structure is included between two adjacent gates, and the channel 2000 structure includes a channel 2000, and an insulating layer 121, an oxide layer 122 and a semiconductor layer 500 formed on both side walls of the channel 2000 in sequence, and an insulating material layer 600 is filled in the opening of the channel 2000.

[0101] The semiconductor structure provided by the present disclosure can be prepared by the above-mentioned semiconductor structure forming method. Among them, the materials, forming methods and process steps of each film layer structure are as described in the above-mentioned forming method part, and will not be described in detail here.

[0102] The semiconductor structure provided by the present disclosure has a formation profile of each film layer having good integrity and high alignment, and the overall structural performance of the formed device is good.

[0103] The semiconductor structure provided by the present disclosure may be a junction field effect transistor (JFET) or a transistor with a vertical structure, etc., which is applied to memories such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. Of course, it can also be applied to other storage devices not listed here, which will not be listed one by one.

[0104] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate, a functional layer, and a plurality of spaced channels formed on the functional layer; Forming a stacked structure on the bottom wall and the side wall of each of the trenches, and the stacked structure extends to the surface of the initial semiconductor structure, wherein the stacked structure includes an insulating layer, an oxide layer and a sacrificial layer formed in sequence along the surface away from the initial semiconductor structure; Introducing a protective gas and an auxiliary gas into each of the channels and reacting them to conformally form a protective layer on the surface of the sacrificial layer, wherein the protective gas includes silicon ions and the auxiliary gas includes oxygen ions; The stacked structure with the protective layer is etched to remove a portion of the stacked structure located at the bottom of the trench and the stacked structure located on the surface of the functional layer to expose the surfaces of the substrate and the functional layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the same channel, the orthographic projection area of ​​the protection layer on the substrate is one tenth to one fifth of the orthographic projection area of ​​the opening of the channel on the substrate.

3. The method for forming a semiconductor structure according to claim 2, wherein: The protective gas includes at least one of silicon tetrachloride, monosilane, silylene, disilane or silicate.

4. The method for forming a semiconductor structure according to claim 2, wherein: The auxiliary gas includes at least one of oxygen, methanol or ethanol.

5. The method for forming a semiconductor structure according to claim 2, wherein: The gas flow rate of the protective gas is 10 sccm to 100 sccm, and the gas flow rate of the auxiliary gas is 100 sccm to 500 sccm.

6. The method for forming a semiconductor structure according to claim 2, wherein: The method comprises: Under the condition of a pressure of 5 mT to 30 mT, the auxiliary gas reacts with the protective gas.

7. The method for forming a semiconductor structure according to claim 2, wherein: The method comprises: Under the condition that the bias voltage is 1000W-1500W, the auxiliary gas reacts with the protective gas.

8. The method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that: The forming of the initial semiconductor structure, the method further comprises: forming a conductive layer on the substrate; A plurality of channels are formed in the conductive layer, so that the conductive layer forms a plurality of conductive parts distributed at intervals.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The method further comprises: A first source and drain are formed on the substrate, wherein an orthographic projection of the first source and drain on the bottom surface of the substrate does not overlap with an orthographic projection of the conductive portion on the bottom surface of the substrate.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: The method further comprises: The remaining protection layer is removed to expose the sidewall of the sacrificial layer, so that the opening sidewall of the channel is aligned with the substrate.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The method further comprises: Removing the remaining sacrificial layer to expose a first side wall, a second side wall and a third side wall, wherein the first side wall and the second side wall are two non-coplanar side surfaces on the oxide layer, the third side wall is a side surface of the insulating layer, and the second side wall is coplanar with the third side wall; A semiconductor layer is conformally formed on a surface formed by the first side wall, the second side wall and the third side wall, and the semiconductor layer is connected to the first source and drain.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: The method further comprises: Filling the remaining opening portion of the trench with an insulating material layer, wherein a surface of the insulating material layer is flush with a surface of the initial semiconductor structure; A second source and drain are formed on a surface jointly formed by the insulating material layer and the semiconductor layer to obtain a target semiconductor structure, wherein an orthographic projection of the second source and drain on the substrate does not overlap with an orthographic projection of the conductive portion on the substrate.

13. The method for forming a semiconductor structure according to claim 8, wherein: The initial semiconductor structure further includes a barrier layer formed between the conductive layer and the substrate, and the barrier layer is used to block the conductive layer from diffusing into the substrate.

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