Method for forming dummy pattern and method for improving defect by using dummy pattern
By forming a dummy pattern during semiconductor manufacturing, a source region is added to the edge of the medium voltage device region, the problem of oxide trench defects between the medium voltage and high voltage device regions is solved, and a higher polysilicon etching is achieved and lower risk of peeling defects.
Patent Information
- Application Number
- CN202411547614.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-07
AI Technical Summary
During semiconductor manufacturing, oxide trench defects are easily formed between the medium voltage and high voltage device regions, resulting in the risk of insufficient etching of polysilicon and peeling defects.
By forming a dummy pattern, a source region is added to the periphery of the shallow trench isolation structure at the edge of the medium voltage device region, so that after the gate oxide layer forms a film, the surface of the shallow trench isolation structure in the medium voltage device region and the low voltage device region are added to the surface of the shallow trench isolation structure in the medium voltage device region and the low voltage device region after the gate oxide layer is formed. The semiconductor substrate surface is flush, thereby avoiding the formation of oxide trenches.
The oxide groove defects between the medium and low voltage device regions are effectively avoided, ensuring the integrity of polysilicon etching in subsequent processes, and reducing the risk of peeling defects.
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Figure CN119403211A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, in particular to a method for forming a dummy pattern and a method for improving defects by using the same. Background Art
[0002] In the high-voltage process flow specified based on the metal gate process platform, the gate oxide thickness of medium-voltage and high-voltage devices is much greater than that of low-voltage devices. In order to ensure that the thickness of the metal gates of different devices is consistent after the metal gate grinding process, it is necessary to ensure that the gate oxide surface heights of different devices are flush. Therefore, in the process flow, before the growth of the medium-voltage and high-voltage gate oxide layers, the active areas and shallow trench isolation areas of the medium-voltage and high-voltage regions will be etched down to a certain depth at the same time, so that the relative horizontal heights of the medium-voltage and high-voltage regions are reduced, ensuring that the gate oxide surfaces of each region are at the same height after the gate oxide layer is deposited and before the polysilicon gate is deposited. In this way, after the medium-voltage gate oxide layer is formed, there will be a height difference on the boundary line between the medium-voltage and low-voltage regions.
[0003] The medium voltage gate oxide layer is formed into an oxide film by sequentially using two processes of in-situ water vapor growth and high temperature oxide layer deposition. After the high temperature oxide layer deposition is completed, the medium voltage gate oxide layer will maintain the step shape caused by the downward etching of the medium voltage region on the boundary between the medium voltage and low voltage regions. Then, a double-gate wet etching process using photoresist to shield the medium voltage region is performed to achieve the purpose of removing the gate oxide layer outside the medium voltage region. Due to the isotropic effect of wet etching, the side of the step will be etched. As the etching proceeds, the edge of the gate oxide step gradually moves away from the edge of the etched photoresist, causing the gate oxide layer outside the edge of the photoresist to gradually become the bottom of the step and be exposed to the wet etching solution and etched, and finally an oxide groove (such as Figure 1 This trench may cause insufficient polysilicon etching in subsequent processes, resulting in polysilicon residues and the risk of becoming a source of peeling defects (such as Figure 2 shown).
[0004] The conventional method to solve this problem is to increase the critical size of the photoresist exposure before the dual-gate wet etching process, compensatingly increase the coverage area of the photoresist, and avoid the bottom of the step from being etched too early, thereby reducing the width and depth of the oxide groove caused by wet etching. However, the disadvantage of the above method is that due to the increase in the coverage area of the photoresist, the photoresist may cover the step or the top of the step, resulting in the oxide layer on the step covered by the photoresist not being etched, thereby forming a protruding oxide residue, and because the photoresist pattern of the medium-voltage area etching process and the exposure pattern of the dual-gate wet etching process are difficult to be completely consistent, in actual situations, there will be a situation where oxide grooves and oxide residues appear at the same time. In this case, the only way is to weigh the two and make an adjustment to the critical size of the photoresist exposure. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for forming a dummy pattern and a method for improving defects using the same, so as to solve the problem of trench defects being easily formed between the low-voltage device area and the medium-voltage device area.
[0006] To achieve the above object and other related objects, the present invention provides a method for forming a virtual pattern, the method comprising:
[0007] Providing a target layer pattern, which includes a first pattern and a second pattern, wherein the first pattern is formed in a medium voltage device area, and the second pattern is formed in a low voltage device area;
[0008] Enlarging the first graphic for the first time to obtain a first enlarged graphic;
[0009] Enlarging the first figure for a second time to obtain a second enlarged figure, wherein the degree of the second enlargement is smaller than the degree of the first enlargement;
[0010] Subtracting the second enlarged figure from the first enlarged figure to obtain a ring-shaped virtual figure;
[0011] Adding the virtual graphic to the periphery of the first graphic to obtain a new target layer graphic;
[0012] The dummy pattern is used to form an active area on the wafer, and the formed active area is located between the medium voltage device area and the low voltage device area.
[0013] Optionally, the first enlarged graphic and the second enlarged graphic are both obtained by enlarging the first graphic in the first direction and in the second direction in equal proportions.
[0014] Optionally, the first direction is perpendicular to the second direction.
[0015] Optionally, the active area formed according to the dummy pattern is separated from the medium voltage device area and the low voltage device area by a shallow trench isolation structure.
[0016] Accordingly, the present invention also provides a method for improving defects according to the dummy pattern provided above, the method comprising:
[0017] A semiconductor substrate is provided, which is divided into a medium voltage device area, a low voltage device area and a dummy active area located therebetween, wherein the medium voltage device area is used to form a first pattern, the low voltage device area is used to form a second pattern, and the dummy active area is a region obtained on the semiconductor substrate according to the dummy pattern;
[0018] A shallow trench isolation structure is formed in the semiconductor substrate at both sides of the dummy active area, and the surface of the shallow trench isolation structure is higher than the surface of the semiconductor substrate, including a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure is located in the medium voltage device area, and the second shallow trench isolation structure is located in the low voltage device area;
[0019] forming a hard mask layer in the low voltage device area and the dummy active area;
[0020] Etching the first shallow trench isolation structure and the semiconductor substrate located in the medium voltage device area;
[0021] forming the gate oxide layer on the surfaces of the medium voltage device area, the low voltage device area and the dummy active area after etching;
[0022] forming a photoresist layer on the surface of the gate oxide layer, and patterning the photoresist layer to expose the gate oxide layer formed in the low voltage device area and the dummy active area;
[0023] Using the photoresist layer as a mask, wet-etching the gate oxide layer until the semiconductor substrate and the second shallow trench isolation structure thereunder are exposed;
[0024] Wherein, the surface of the first shallow trench isolation structure after etching is flush with the surface of the semiconductor substrate in the low-voltage device area.
[0025] Optionally, a surface of the first shallow trench isolation structure in the medium voltage device region after etching is higher than a surface of the semiconductor substrate.
[0026] Optionally, the gate oxide layer is formed by an in-situ water vapor growth process and a high temperature oxidation process.
[0027] Optionally, the gate oxide layer is made of silicon oxide.
[0028] Optionally, the material of the hard mask layer includes silicon nitride.
[0029] Optionally, a width of the first shallow trench isolation structure is greater than a width of the second shallow trench isolation structure.
[0030] As described above, the method for forming a virtual pattern of the present invention and the method for improving defects using the same, by adding an active area on the periphery of the shallow trench isolation structure at the edge of the medium voltage device area, so that after the gate oxide layer is formed, the surface of the shallow trench isolation structure in the medium voltage device area and the surface of the semiconductor substrate in the low voltage device area are at the same level, so that in the subsequent wet etching process, since the outside of the edge of the photoresist after patterning is a flat gate oxide layer, after etching with a wet etching solution, the remaining surface is still flat, and there will be only one step between the medium voltage device area and the low voltage device area, and no oxide trench will appear, thereby avoiding the production of defective products. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 The diagram shows a cross-sectional structure of a conventional semiconductor structure having trench defects.
[0032] Figure 2 Display as Figure 1 Electron micrograph of the structure shown.
[0033] Figure 3 Shown are schematic diagrams of the new target layer graphics and dummy graphics of the present invention.
[0034] Figures 4 to 10 It is a schematic cross-sectional structure diagram of the process of forming a gate oxide layer according to the present invention.
[0035] Description of Figure Numbers
[0036] 10: semiconductor substrate; 20: shallow trench isolation structure; 21: first shallow trench isolation structure; 22: second shallow trench isolation structure; 30: hard mask layer; 40: gate oxide layer; 50: photoresist layer; 60: first photoresist layer DETAILED DESCRIPTION
[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0039] Embodiment 1
[0040] like Figure 3 As shown, this embodiment provides a method for forming a virtual pattern, the method comprising:
[0041] A target layer pattern 100 is provided, which includes a first pattern 110 and a second pattern 120, wherein the first pattern 110 is formed in a medium voltage device area, and the second pattern 120 is formed in a low voltage device area;
[0042] The first graphic 110 is enlarged for the first time to obtain a first enlarged graphic 110A;
[0043] The first graphic 110 is enlarged for a second time to obtain a second enlarged graphic 110B, and the degree of the second enlargement is smaller than that of the first enlargement;
[0044] Subtracting the second enlarged pattern 110B from the first enlarged pattern 110A to obtain a ring-shaped virtual pattern CC;
[0045] Add the virtual graphic CC to the periphery of the first graphic 110 to obtain a new target layer graphic 200;
[0046] The dummy pattern CC is used to form an active area on the wafer, and the formed active area is located between the medium voltage device area and the low voltage device area.
[0047] Specifically, the first enlarged graphic 110A and the second enlarged graphic 110B are obtained by enlarging the first graphic 110 in the first direction and in the second direction in equal proportions.
[0048] Specifically, the first direction is perpendicular to the second direction.
[0049] like Figure 3 As shown, in this embodiment, the first figure shown is a square figure, X represents the first direction, and Y represents the second direction.
[0050] Specifically, the active area formed according to the dummy pattern CC is separated from the medium voltage device area and the low voltage device area by a shallow trench isolation structure.
[0051] Embodiment 2
[0052] This embodiment provides a method for improving defects of a dummy pattern according to the first embodiment, the method comprising:
[0053] A semiconductor substrate 10 is provided, which is divided into a medium voltage device area A, a low voltage device area B and a dummy active area C located therebetween, wherein the medium voltage device area A is used to form a first pattern, the low voltage device area B is used to form a second pattern, and the dummy active area C is a region obtained on the semiconductor substrate 10 according to the dummy pattern;
[0054] A shallow trench isolation structure 20 is formed in the semiconductor substrate 10 on both sides of the dummy active area C, and the surface of the shallow trench isolation structure 20 is higher than the surface of the semiconductor substrate 10, including a first shallow trench isolation structure 21 and a second shallow trench isolation structure 22, wherein the first shallow trench isolation structure 21 is located in the medium voltage device area A, and the second shallow trench isolation structure 22 is located in the low voltage device area B;
[0055] forming a hard mask layer 30 in the low voltage device region B and the dummy active region C;
[0056] Etching the first shallow trench isolation structure 21 and the semiconductor substrate 10 located in the medium voltage device area A;
[0057] Forming the gate oxide layer 40 on the surfaces of the medium voltage device area A, the low voltage device area B and the dummy active area C after etching;
[0058] Forming a photoresist layer 50 on the surface of the gate oxide layer 40, and patterning the photoresist layer 50 to expose the gate oxide layer 40 formed in the low voltage device region B and the dummy active region C;
[0059] Using the photoresist layer 50 as a mask, wet-etching the gate oxide layer 40 until the semiconductor substrate 10 and the second shallow trench isolation structure 22 thereunder are exposed;
[0060] The surface of the first shallow trench isolation structure 21 after etching is flush with the surface of the semiconductor substrate 10 in the low-voltage device area B.
[0061] like Figure 5 and Figure 6 As shown, in this embodiment, the method for forming a hard mask layer 30 in the low voltage device area B and the dummy active area C includes: forming the hard mask layer 30 on the surface of the low voltage device area B, the dummy active area C and the high voltage device area A; forming a first photoresist layer 60 on the surface of the hard mask layer 30, and patterning it; using the patterned first photoresist layer 60 as a mask to etch the hard mask layer 30 formed in the medium voltage device area A.
[0062] Moreover, if Fig.10As shown, in this embodiment, the surface of the gate oxide layer 40 formed in the medium voltage device area A is flush with the surface of the semiconductor substrate 10 in the low voltage device area B.
[0063] Specifically, the surface of the first shallow trench isolation structure 21 in the medium voltage device area A after etching is higher than the surface of the semiconductor substrate 10 .
[0064] Specifically, the gate oxide layer 40 is formed by an in-situ water vapor growth process and a high temperature oxidation process.
[0065] Specifically, the material of the gate oxide layer 40 includes silicon oxide.
[0066] Specifically, the material of the hard mask layer 30 includes silicon nitride.
[0067] Specifically, the width of the first shallow trench isolation structure 21 is greater than the width of the second shallow trench isolation structure 22 .
[0068] In summary, the method for forming a dummy pattern of the present invention and the method for improving defects using the same, by adding an active area to the periphery of the shallow trench isolation structure at the edge of the medium voltage device area, so that after the gate oxide layer is formed, the surface of the shallow trench isolation structure in the medium voltage device area and the surface of the semiconductor substrate in the low voltage device area are at the same level, so that in the subsequent wet etching process, since the outside of the edge of the photoresist after patterning is a flat gate oxide layer, after etching with a wet etching solution, the remaining surface is still flat, and there will be only one step between the medium voltage device area and the low voltage device area, and no oxide trench will appear, thereby avoiding the production of defective products. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for forming a virtual pattern, characterized in that: The method comprises: Providing a target layer pattern, which includes a first pattern and a second pattern, wherein the first pattern is formed in a medium voltage device area, and the second pattern is formed in a low voltage device area; Enlarging the first graphic for the first time to obtain a first enlarged graphic; Enlarging the first figure for a second time to obtain a second enlarged figure, wherein the degree of the second enlargement is smaller than the degree of the first enlargement; Subtracting the second enlarged figure from the first enlarged figure to obtain a ring-shaped virtual figure; Adding the virtual graphic to the periphery of the first graphic to obtain a new target layer graphic; The dummy pattern is used to form an active area on the wafer, and the formed active area is located between the medium voltage device area and the low voltage device area.
2. The method for forming a virtual pattern according to claim 1, wherein: The first enlarged graphic and the second enlarged graphic are both obtained by enlarging the first graphic in the first direction and in the second direction at equal proportions.
3. The method for forming a virtual pattern according to claim 2, wherein: The first direction is perpendicular to the second direction.
4. The method for forming a virtual pattern according to claim 1, wherein: The active area formed according to the dummy pattern is separated from the medium voltage device area and the low voltage device area by a shallow trench isolation structure.
5. A method for improving defects by using a dummy pattern according to claim 1, characterized in that: The method comprises: A semiconductor substrate is provided, which is divided into a medium voltage device area, a low voltage device area and a dummy active area located therebetween, wherein the medium voltage device area is used to form a first pattern, the low voltage device area is used to form a second pattern, and the dummy active area is a region obtained on the semiconductor substrate according to the dummy pattern; A shallow trench isolation structure is formed in the semiconductor substrate at both sides of the dummy active area, and the surface of the shallow trench isolation structure is higher than the surface of the semiconductor substrate, including a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure is located in the medium voltage device area, and the second shallow trench isolation structure is located in the low voltage device area; forming a hard mask layer in the low voltage device area and the dummy active area; Etching the first shallow trench isolation structure and the semiconductor substrate located in the medium voltage device area; forming the gate oxide layer on the surfaces of the medium voltage device area, the low voltage device area and the dummy active area after etching; forming a photoresist layer on the surface of the gate oxide layer, and patterning the photoresist layer to expose the gate oxide layer formed in the low voltage device area and the dummy active area; Using the photoresist layer as a mask, wet-etching the gate oxide layer until the semiconductor substrate and the second shallow trench isolation structure thereunder are exposed; Wherein, the surface of the first shallow trench isolation structure after etching is flush with the surface of the semiconductor substrate in the low-voltage device area.
6. The defect improvement method according to claim 5, characterized in that: After etching, the surface of the first shallow trench isolation structure in the medium voltage device area is higher than the surface of the semiconductor substrate.
7. The defect improvement method according to claim 5, characterized in that: The gate oxide layer is formed by an in-situ water vapor growth process and a high temperature oxidation process.
8. The defect improvement method according to claim 5, characterized in that: The material of the gate oxide layer includes silicon oxide.
9. The defect improvement method according to claim 5, characterized in that: The material of the hard mask layer includes silicon nitride.
10. The defect improvement method according to claim 5, characterized in that: The width of the first shallow trench isolation structure is greater than the width of the second shallow trench isolation structure.