Semiconductor device

Abstract

A semiconductor device is described. The semiconductor device includes a lower channel layer and an upper channel layer over an active region on a substrate. The semiconductor device also includes an intermediate insulating structure disposed between the lower channel layer and the upper channel layer. The semiconductor device comprises: a gate structure surrounding the channel layer; and a lower source / drain region and an upper source / drain region disposed on the active region on at least one side of the gate structure. A blocking structure is between the lower source / drain region and the upper source / drain region. The lower source / drain region and the upper source / drain region may each fill the lower recessed region or the upper recessed region, respectively. These recessed regions are defined by respective channel layers, the gate structures, and the blocking structures. Side surface slopes of the upper and lower recessed regions may vary, and the side surface slopes of the recessed regions may be different from each other.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] There is a high demand for technology for reducing the size of semiconductor devices. Summary of the invention

[0003] In general, in some aspects, the subject matter of the present application relates to a semiconductor device, the semiconductor device comprising: an active region, the active region extending along a first direction on a substrate; a device isolation layer, the device isolation layer being disposed on the substrate and defining the active region; a lower channel layer, the lower channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; an upper channel layer, the upper channel layer being disposed on the lower channel layer and spaced apart from each other in the vertical direction; an intermediate insulating structure, the intermediate insulating structure being disposed between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers; a gate structure, the gate structure intersecting the active region, surrounding each of the lower channel layers and each of the upper channel layers, and extending in a second direction; a lower source / drain region, the lower source / drain region being disposed between the gate At least one side of the structure is arranged on the active area and connected to the lower channel layer; an upper source / drain region, the upper source / drain region is connected to each of the upper channel layers on at least one side of the gate structure and is spaced apart from the lower source / drain region in the vertical direction; and a blocking structure, the blocking structure is arranged between the lower source / drain region and the upper source / drain region, wherein the lower source / drain region fills a lower recessed region defined by a side surface of the lower channel layer, a side surface of the gate structure and an upper surface of the active area, wherein the upper source / drain region fills an upper recessed region defined by a side surface of the upper channel layer, a side surface of the gate structure, and a lower surface and a side surface of the blocking structure, and wherein a slope of the side surface of the lower recessed region and a slope of the side surface of the upper recessed region have opposite signs.

[0004] In general, in some aspects, the subject matter of the present application relates to a semiconductor device, the semiconductor device comprising: an active region, the active region extending along a first direction on a substrate; a device isolation layer, the device isolation layer being disposed on the substrate and defining the active region; lower channel layers, the lower channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; upper channel layers, the upper channel layers being disposed on the lower channel layers and spaced apart from each other in the vertical direction; an intermediate insulating structure, the intermediate insulating structure being disposed between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers; a lower gate structure, the lower gate structure intersecting the active region, surrounding each of the lower channel layers, extending in the second direction, and disposed below a lower surface of the intermediate insulating structure; an upper gate structure, the upper gate structure surrounding each of the upper channel layers, The substrate includes a first gate structure and a second gate structure, wherein the first gate structure is provided on the active region and connected to each of the lower channel layers; a second gate structure and a second gate structure are ... source / drain region and a second source / drain region

[0005] In general, in some aspects, the subject matter of the present application relates to a semiconductor device, the semiconductor device comprising: an active region extending along a first direction on a substrate; a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure intersecting the active region, surrounding each of the plurality of channel layers and extending in a second direction; a lower source / drain region disposed on at least one side of the gate structure on the active region and connected to one of the plurality of channel layers; a portion; an upper source / drain region, the upper source / drain region being connected to another portion of the plurality of channel layers on at least one side of the gate structure and being spaced apart from the lower source / drain region in the vertical direction; and a blocking structure, the blocking structure being disposed between the lower source / drain region and the upper source / drain region, wherein the lower source / drain region includes a first lower inclined surface and a second lower inclined surface, the first lower inclined surface having a first slope, and the second lower inclined surface having a second slope different from the first slope of the first lower inclined surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a top view showing an example of a semiconductor device;

[0008] Figure 2A A cross-sectional view showing an example of a semiconductor device;

[0009] Figure 2B is an enlarged cross-sectional view showing a portion of an example of a semiconductor device;

[0010] Figures 3 to 15 is an enlarged cross-sectional view showing a portion of an example of a semiconductor device;

[0011] Fig.16A A cross-sectional view showing an example of a semiconductor device;

[0012] Fig. 16B is an enlarged cross-sectional view showing a portion of an example of a semiconductor device;

[0013] Fig.17 is an enlarged cross-sectional view showing a portion of an example of a semiconductor device;

[0014] Fig.18 A cross-sectional view showing a portion of an example of a semiconductor device;

[0015] FIG. 19A to FIG. 19His a cross-sectional view illustrating an example method of manufacturing a semiconductor device;

[0016] FIG. 20A to FIG. 20J is a cross-sectional view illustrating an example method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0017] Hereinafter, implementations of the present disclosure will be described as follows with reference to the accompanying drawings.

[0018] Figure 1 is a top view showing a semiconductor device.

[0019] Figure 2A Shows the Figure 1 sectional views of the semiconductor device taken along line II', line II-II' and line III-III'.

[0020] Figure 2B is an enlarged cross-sectional view showing a portion of a semiconductor device to show Figure 2A Area "A" in the.

[0021] For ease of description, Figures 1 to 2B Only the main components of the semiconductor device are shown.

[0022] refer to Figures 1 to 2B , the semiconductor device 100 may include: a substrate 101; an active region 105 located on the substrate 101; a device isolation layer 110 defining the active region 105; a channel structure 140 including a plurality of channel layers 141A, 142A, 141B and 142B disposed on the active region 105 and vertically spaced apart from each other; an intermediate insulating structure MDI disposed between the lower channel layers 141A and 142A and the upper channel layers 141B and 142B; a gate structure 160 extending by intersecting the active region 105; a source / drain region 150 contacting the plurality of channel layers 141A, 142A, 141B and 142B; and a blocking structure 170 disposed between the lower source / drain region 150A and the upper source / drain region 150B.

[0023] The semiconductor device 100 may further include a contact structure 180 and an interlayer insulating layer 190. In addition, although not shown for ease of description, the semiconductor device 100 may further include a contact plug connected to the lower source / drain region 150A.

[0024] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer.

[0025] The active region 105 may be defined by the device isolation layer 110 in the substrate 101, and may be arranged to extend in a first direction (e.g., the X direction). The active region 105 may have a structure protruding from the substrate 101. The upper end of the active region 105 may be arranged to protrude from the upper surface of the device isolation layer 110 at a predetermined height. The active region 105 may be formed as a part of the substrate 101, or may include an epitaxial layer grown from the substrate 101. However, the active region 105 located on the substrate 101 may be partially recessed on both sides of the gate structure 160, and the source / drain region 150 may be arranged on the recessed active region 105. The active region 105 may include impurities, or may include a doped region having impurities.

[0026] In the semiconductor device 100, the active region 105 may have a fin structure, and the gate structure 160 may be disposed between the active region 105 and the channel structure 140, between the lower channel structure 140A and the upper channel structure 140B of the channel structure 140, and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET). TM ) structure, which is a full-surround gate field effect transistor. In some implementations, the semiconductor device may include a transistor of a complementary FET (CFET) structure. The example implementation may also be applicable to a transistor having a three-dimensional stacked FET (3D-SFET) structure in which a plurality of transistors are vertically stacked.

[0027] like Figure 2A As shown, the semiconductor device 100 according to the example implementation may include a first transistor structure TR1 and a second transistor structure TR2 stacked on the active region 105. The first transistor structure TR1 and the second transistor structure TR2 used in the example implementation may be a multi-bridge channel FET (MBCFET) including a gate structure 160. TM), the gate structure 160 surrounds the lower channel layers 141A and 142A and the upper channel layers 141B and 142B disposed on the active region 105. Each first transistor structure TR1 may be one of an N-type MOSFET and a P-type MOSFET, and the second transistor structure TR2 may be one of a P-type MOSFET and an N-type MOSFET. In some example implementations, each of the first transistor structure TR1 and the second transistor structure TR2 may be a P-type MOSFET and an N-type MOSFET, respectively.

[0028] The device isolation layer 110 may define an active region 105 in the substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. In an example implementation, the device isolation layer 110 may also include a region that further extends downward to a region below the substrate 101 while having a step difference. The device isolation layer 110 may partially expose an upper portion of the active region 105. In an example implementation, the device isolation layer 110 may have a curved upper surface having a height that increases toward the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0029] In example implementations, the first transistor structure TR1 and the second transistor structure TR2 may be configured as a shared gate structure 160 .

[0030] Specifically, the first transistor structure TR1 may include lower channel layers 141A and 142A stacked on the active region 105, a gate electrode 165 surrounding the lower channel layers 141A and 142A, a lower source / drain region 150A connected to the lower channel layers 141A and 142A on one side of the gate electrode 165, and a gate dielectric layer 162 disposed between the lower channel layers 141A and 142A and the gate electrode 165.

[0031] Similarly, the second transistor structure TR2 may include upper channel layers 141B and 142B, a gate electrode 165 surrounding the upper channel layers 141B and 142B, upper source / drain regions 150B connected to the upper channel layers 141B and 142B on both sides of the gate electrode 165, and a gate dielectric layer 162 disposed between the upper channel layers 141B and 142B and the gate electrode 165.

[0032] The channel structure 140 may include two or more of a plurality of channel layers 141A, 142A, 141B, and 142B spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 (e.g., in the Z direction) on the active region 105, that is, a lower channel structure 140A including lower channel layers 141A and 142A and an upper channel structure 140B including upper channel layers 141B and 142B. The plurality of channel layers 141A, 142A, 141B, and 142B may be connected to the source / drain region 150 and may be spaced apart from the upper surface of the active region 105. The upper channel layers 141B and 142B may be disposed on the intermediate insulating structure MDI and may be spaced apart from each other in the Z direction.

[0033] The plurality of channel layers 141A, 142A, 141B, and 142B may have a width in the Y direction that is the same as or similar to the width of the active region 105. In an example implementation, the width of the plurality of channel layers 141A, 142A, 141B, and 142B in the Y direction may decrease in a direction away from the upper surface of the substrate 101. The width of the plurality of channel layers 141A, 142A, 141B, and 142B in the X direction may increase toward the upper surface of the substrate 101 and decrease thereafter. For example, the width of the upper channel layers 141B and 142B in the X direction may increase toward the upper surface of the substrate 101, and the width of the lower channel layers 141A and 142A in the X direction may decrease toward the upper surface of the substrate 101, which may be due to the shapes of the lower recessed region RCB and the upper recessed region RCU.

[0034] The plurality of channel layers 141A, 142A, 141B, and 142B may be formed of a semiconductor material, and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the plurality of channel layers 141A, 142A, 141B, and 142B may be formed of the same material as the substrate 101. The plurality of channel layers 141A, 142A, 141B, and 142B may be disposed on the active region 105 and vertically spaced apart from each other. In an example implementation, the number of the plurality of channel layers 141A, 142A, 141B, and 142B included in the channel structure 140 and their shapes may vary.

[0035] The intermediate insulating structure MDI may be disposed between the uppermost lower channel layer 142A among the lower channel layers 141A and 142A and the lowermost upper channel layer 141B among the upper channel layers 141B and 142B. The intermediate insulating structure MDI may include an intermediate insulating pattern 300. The intermediate insulating pattern 300 may include insulating materials such as oxides, nitrides, and oxynitrides. The intermediate insulating structure MDI may space the lower channel layers 141A and 142A from the upper channel layers 141B and 142B. The intermediate insulating structure MDI may include a protrusion 300P protruding toward the blocking structure 170. In an example implementation, the protrusion 300P may also be referred to as a middle portion 300P. The protrusion 300P may be in a pointed shape, but its example implementation is not limited thereto. In another example implementation, the protrusion 300P may be in a rounded shape with rounded corners toward the blocking structure 170.

[0036] The gate structure 160 may intersect the active region 105, may surround the lower channel layers 141A and 142A and the upper channel layers 141B and 142B, respectively, and may extend in the second direction Y. The lower gate structure 160A may intersect the active region 105, may surround the lower channel layers 141A and 142A, respectively, may extend in the second direction Y, and may be disposed below the lower surface of the intermediate insulating structure MDI. The upper gate structure 160B may surround the upper channel layers 141B and 142B, respectively, may extend in the second direction Y, and may be disposed on the upper surface of the intermediate insulating structure MDI. In an example implementation, as described above, the first transistor structure TR1 and the second transistor structure TR2 may share the gate structure 160. The gate electrode 165 employed in the example implementation may be used as a common gate electrode surrounding the plurality of channel layers 141A, 142A, 141B, and 142B. The gate dielectric layer 162 may be disposed between the lower channel layers 141A and 142A and the gate electrode 165, and also disposed between the upper channel layers 141B and 142B and the gate electrode 165. The gate dielectric layer 162 may surround the intermediate insulating pattern 300 in the second direction (e.g., the Y direction). The gate structure 160 may further include a gate spacer layer 164. The gate spacer layer 164 may be disposed on both sidewalls of an electrode portion extending along the second direction (e.g., the Y direction) on the uppermost upper channel layers 141B and 142B among the gate electrodes 165. A gate capping layer 166 may be formed on the gate spacer layer 164 and the gate electrode 165.

[0037] The gate electrode 165 used in the example implementation may include a conductive material. For example, the gate electrode 165 may include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN and TaAlC. The gate electrode 165 may include a semiconductor material such as doped polysilicon. The common gate electrode 165 may include two or more layers. Although not shown, in another example implementation, an inter-gate insulating layer may be further included to isolate the upper gate structure 160B from the lower gate structure 160A at a height substantially the same as the height of the intermediate insulating structure MDI. At least a portion of the inter-gate insulating layer may be arranged to overlap the intermediate insulating structure MDI in the horizontal direction. Due to the inter-gate insulating layer, the gate electrode 165 of the upper gate structure 160B and the gate electrode 165 of the lower gate structure 160A may include different conductive materials. Considering the desired threshold voltage, the gate electrode 165 of the upper gate structure 160B and the gate electrode 165 of the lower gate structure 160A may be formed of a material having an appropriate work function. Similarly, the gate dielectric layer 162 of the upper gate structure 160B and the gate dielectric layer 162 of the lower gate structure 160A may include different dielectric layers or a combination thereof.

[0038] For example, each gate dielectric layer 162 may include oxide, nitride, or high-k material. High-k material may refer to a material having a dielectric constant higher than that of silicon oxide (SiO 2 ) dielectric material with a high dielectric constant. The high-k material can be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ).

[0039] For example, the gate spacer layer 164 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some example implementations, the gate spacer layer 164 may include a multilayer structure. The gate cap layer 166 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide.

[0040] In some embodiments, the slope of the side surface of the lower source / drain region 150A and the slope of the side surface of the upper source / drain region 150B may have slopes of opposite signs. For example, the first lower inclined surface 150A1 and the second lower inclined surface 150A2 may have a positive slope and a negative slope, respectively, and the first upper inclined surface 150B1 and the second upper inclined surface 150B2 may have a negative slope and a positive slope, respectively. Therefore, the width of the lower gate structure 160A in the first direction X may decrease toward the upper surface of the substrate 101, and the width of the upper gate structure 160B may decrease along the first direction X in a direction away from the upper surface of the substrate 101.

[0041] The lower source / drain region 150A may be disposed on the active region 105 on at least one side of the gate structure 160, and may be connected to the side surfaces of the lower channel layers 141A and 142A. The lower source / drain region 150A may be disposed as a source region or a drain region of the first (lower) transistor structure TR1. The lower source / drain region 150A may include epitaxial growth from the surface of the recessed portion of the active region 105 and the two side surfaces of the lower channel layers 141A and 142A. Similarly, the upper source / drain region 150B may be connected to the side surfaces of the upper channel layers 141B and 142B on at least one side of the gate structure 160, and may be spaced apart from the lower source / drain region 150A in the vertical direction. The upper source / drain region 150B may be disposed as a source region or a drain region of the second (upper) transistor structure TR2. The upper source / drain region 150B may include epitaxial growth using both side surfaces of the upper channel layers 141B and 142B as seed layers.

[0042] The lower source / drain region 150A and the upper source / drain region 150B may include semiconductor epitaxy such as silicon (Si). The lower source / drain region 150A and the upper source / drain region 150B may include impurities of different types and / or concentrations. For example, when the first transistor structure TR1 is a P-type MOSFET, the upper source / drain region 150A may include P-type doped silicon germanium (SiGe), and when the second transistor structure TR2 is an N-type MOSFET, the upper source / drain region 150B may include N-type doped silicon (Si). Therefore, the cross-sectional surfaces of the lower source / drain region 150A and the upper source / drain region 150B in the second direction (e.g., Y direction) may be in different shapes. For example, the cross-sectional surfaces of the lower source / drain region 150A and the upper source / drain region 150B may be in a circular shape, an elliptical shape, a pentagonal shape, a hexagonal shape, or a shape similar thereto. In an example implementation, since the lower source / drain region 150A is formed between the gate spacer layer 164 and the first barrier pattern 171 , a cross-sectional surface of the lower source / drain region 150A in the Y direction may have a trapezoidal shape whose width may increase toward the upper surface of the substrate 101 .

[0043] The lower source / drain region 150A may fill the lower recessed region RCB defined by the side surfaces of the lower channel layers 141A and 142A, the side surfaces of the gate structure 160, and the upper surface of the active region 105. The upper source / drain region 150B may fill the upper recessed region RCU defined by the side surfaces of the upper channel layers 141B and 142B, the side surfaces of the gate structure 160, and the lower surface and side surfaces of the barrier structure 170. For example, the middle portion 300P may be a portion where the side surfaces of the lower recessed region RCB and the side surfaces of the upper recessed region RCU are connected to each other. In addition, the middle portion 300P may be a portion where the side surfaces of the lower source / drain region 150A and the side surfaces of the upper source / drain region 150B may extend and be connected to each other. In an example implementation, the middle portion 300P may be a region where the sign of the slope of the side of the source / drain region 150 is reversed. For example, the side of the source / drain region 150 may change from a positive slope to a negative slope in the middle portion 300P in the vertical direction. In an example implementation, the slope of the side surface of the lower recessed region RCB and the slope of the side surface of the upper recessed region RCU may have opposite signs. The middle portion 300P may be a recess formed by contacting the side surface of the lower recessed region RCB and the side surface of the upper recessed region RCU. The height of the middle portion 300P may be substantially equal to or lower than the height 300UL of the upper surface of the intermediate insulating structure MDI, and may be substantially equal to or higher than the height 300BL of the lower surface of the intermediate insulating structure MDI. The height of the middle portion 300P may be substantially equal to or higher than the height of the uppermost surface of the lower gate structure 160A disposed below the lower surface of the intermediate insulating structure MDI, and may be substantially equal to or lower than the height of the lowermost surface of the upper gate structure 160B disposed on the upper surface of the intermediate insulating structure MDI. The height 150BL of the lowermost end of the upper source / drain region 150B may be lower than the height 300UL of the uppermost surface of the intermediate insulating structure MDI. The height 150AL of the upper end of the lower source / drain region 150A may be set at a height substantially equal to or higher than the height 300BL of the lower surface of the intermediate insulating structure MDI. The upper portion of the lower source / drain region 150A may horizontally overlap with the intermediate insulating structure MDI.

[0044] In an example implementation, the lower source / drain region 150A may include a first lower inclined surface 150A1 that may be inclined and a second lower inclined surface 150A2 having a slope different from that of the first lower inclined surface 150A1, and the widths of the first lower inclined surface 150A1 and the second lower inclined surface 150A2 in the X direction may increase downward from an upper portion of the lower source / drain region 150A. The upper source / drain region 150B may include a first upper inclined surface 150B1 that may be inclined and a second upper inclined surface 150B2 inclined in a direction different from that of the first upper inclined surface 150B1, and the widths of the first upper inclined surface 150B1 and the second upper inclined surface 150B2 in the X direction may decrease downward from an upper portion of the upper source / drain region 150B. Therefore, the cross-sectional surfaces of the lower source / drain region 150A and the upper source / drain region 150B in the X direction may be a trapezoidal shape (the lower base of the trapezoid is closer to the substrate than the upper base of the trapezoid) and an inverted trapezoidal shape (the lower base of the trapezoid is farther away from the substrate than the upper base of the trapezoid), respectively.

[0045] The blocking structure 170 may be disposed between the lower source / drain region 150A and the upper source / drain region 150B. The blocking structure 170 may vertically overlap the lower source / drain region 150A and the upper source / drain region 150B. The upper surface of the blocking structure 170 may be in a downwardly convex shape, but the exemplary implementation thereof is not limited thereto. Figure 2A As shown, the lower surface of the blocking structure 170 may be in a flat shape, but its example implementation is not limited thereto. In another example implementation, the lower surface of the blocking structure 170 may be in a shape that is convex upward or convex downward. The blocking structure 170 may include a first blocking pattern 171 formed along the lower portion and lower surface of the side surface of the upper recessed region RCU and a second blocking pattern 172 located on the first blocking pattern 171. The first blocking pattern 171 and the second blocking pattern 172 may include insulating materials such as oxides, nitrides, or oxynitrides. The first blocking pattern 171 and the second blocking pattern 172 may include different materials, but its example implementation is not limited thereto. The blocking structure 170 may isolate the lower source / drain region 150A and the upper source / drain region 150B from each other in the vertical direction Z.

[0046] The contact structure 180 may penetrate at least a portion of the interlayer insulating layer 190, may contact the source / drain region 150, and may apply an electrical signal to the source / drain region 150. The contact structure 180 may contact the upper portion of the upper source / drain region 150B. Although not shown for ease of description, a contact plug connected to the lower source / drain region 150A may be further included. The contact plug connected to the lower source / drain region 150A may include a horizontal contact portion extending in a direction horizontal to the upper surface of the substrate 101 (e.g., the Y direction), and a vertical contact portion connected to the horizontal contact portion and extending in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction). The horizontal contact portion may be disposed on the upper surface of the lower source / drain region 150A, and the vertical contact portion may penetrate the interlayer insulating layer 190. The contact plug may include a material substantially the same as that of the contact structure 180. However, the contact plug is not limited to the above structure and may be in various shapes. For example, the contact plug may have a shape similar to that of the contact structure 180. Fig.18 The back contact structure 210 of the semiconductor device 100p is the same structure.

[0047] The contact structure 180 may be disposed on the source / drain region 150, and in an example implementation, the contact structure 180 may be disposed to have a length in the Y direction that is longer than that of the source / drain region 150. The contact structure 180 may have an inclined side surface in which the width of the lower portion may be further reduced than the width of the upper portion according to the aspect ratio, but example implementations thereof are not limited thereto. The contact structure 180 may be disposed to be recessed into the source / drain region 150 to a predetermined depth.

[0048] The contact structure 180 may include a first metal semiconductor compound layer 182 disposed at the lower end, a barrier layer 184 disposed along the sidewall, and a plug conductive layer 186. The first metal semiconductor compound layer 182 may be, for example, a metal silicide layer. The barrier layer 184 may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The plug conductive layer 186 may include a metal material, such as aluminum (Al), tungsten (W), or molybdenum (Mo). In an example implementation, the contact structure 180 may be arranged to penetrate at least a portion of the source / drain region 150. In an example implementation, the number of conductive layers included in the contact structure 180 and their arrangement may be changed in various ways. In addition, a wiring structure such as a contact structure may be further provided on the gate electrode 165, and a wiring structure connected to the contact structure 180 may be further provided on the contact structure 180.

[0049] The interlayer insulating layer 190 may be provided to cover the source / drain regions 150, the gate structure 160, and the device isolation layer 110. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, oxynitride, and a low-k dielectric.

[0050] Figure 3 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0051] refer to Figure 3 In the semiconductor device 100a, the lower source / drain region 150A may be recessed into a portion of the active region 105 and may include a lower source / drain protruding region 150AP protruding toward the lower gate structure 160A, and the upper source / drain region 150B may include an upper source / drain protruding region 150BP protruding toward the upper gate structure 160B. Fig.19C In the process of forming the upper recessed region RCU, further etching the upper recessed region RCU in the horizontal direction by a wet etching process, and forming the upper source / drain region 150B in the upper recessed region RCU, the upper source / drain protruding region 150BP is formed. The lower source / drain protruding region 150AP may be formed by forming the lower recessed region RCB, further etching the lower recessed region RCB in the horizontal direction by a wet etching process, and forming the lower source / drain region 150A in the lower recessed region RCB. The formation of the lower source / drain protruding region 150AP and the formation of the upper source / drain protruding region 150BP may be independent of each other.

[0052] Figure 4 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0053] refer to Figure 4 In the semiconductor device 100b, the intermediate insulating structure MDI may include a semiconductor pattern 140S located between a plurality of intermediate insulating patterns 300 and a plurality of intermediate insulating patterns 300. The semiconductor pattern 140S may include silicon (Si) or silicon germanium (SiGe). The semiconductor pattern 140S may have an etching selectivity for the plurality of channel layers 141A, 142A, 141B, and 142B, the lower sacrificial layer 120A, the middle sacrificial layer 120B, and the upper sacrificial layer 120C. When the semiconductor device 100b is described later, the semiconductor pattern 140S may include a semiconductor pattern 140S located between the plurality of intermediate insulating patterns 300 and the plurality of intermediate insulating patterns 300. The semiconductor pattern 140S may include silicon (Si) or silicon germanium (SiGe). The semiconductor pattern 140S may have an etching selectivity for the plurality of channel layers 141A, 142A, 141B, and 142B, the lower sacrificial layer 120A, the middle sacrificial layer 120B, and the upper sacrificial layer 120C. Fig.19B When the middle sacrificial layer 120B is removed in the process of FIG. 1 , the semiconductor pattern 140S may remain. Therefore, the semiconductor pattern 140S may be disposed between the middle insulating patterns 300 .

[0054] Figure 5is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0055] refer to Figure 5 In the semiconductor device 100c, the intermediate insulating structure MDI may include a first air gap AG1. The first air gap AG1 may vertically overlap the lower gate structure 160A and the upper gate structure 160B. The first air gap AG1 may be formed at the same Fig.19A In an example implementation, the semiconductor pattern 140S may not be replaced by the intermediate insulating pattern 300, and the semiconductor pattern 140S may be selectively removed in a subsequent process, thereby forming a first air gap AG1. The first air gap AG1 may include a gas composed of air or a material used in a manufacturing process of the semiconductor device 100c, which may also be applicable to another example implementation.

[0056] Figure 6 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0057] refer to Figure 6 , the semiconductor device 100d can be Figure 5 The semiconductor device 100c includes a second air gap AG2. For example, the blocking structure 170 may not include the first and second blocking patterns 171 and 172, but may include the second air gap AG2. The second air gap AG2 may vertically overlap the lower source / drain region 150A and the upper source / drain region 150B. In addition to manufacturing Figure 5 In addition to the process of manufacturing the semiconductor device 100c in the embodiment of the present invention, the second air gap AG2 may be formed by selectively removing the first barrier pattern 171 and the second barrier pattern 172 through the first air gap AG1. Therefore, the first air gap AG1 and the second air gap AG2 may be connected to each other. The second air gap AG2 may include a gas composed of air or a material used in the process of manufacturing the semiconductor device 100, which may also be applicable to another exemplary implementation.

[0058] Figure 7 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0059] refer to Figure 7 In the semiconductor device 100e, the second barrier pattern 172 may cover the upper surface of the lower source / drain region 150A. Fig.19FDuring the process in the process, the process of covering the upper surface of the lower source / drain region 150A with the first barrier pattern 171 may not be performed, and the second barrier pattern 172 may be formed to contact the upper surface of the lower source / drain region 150A. Therefore, the first barrier pattern 171 may be disposed on the side surface of the second barrier pattern 172.

[0060] Figure 8 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0061] refer to Figure 8 , different from Figure 2A In the example implementation, the semiconductor device 100f may further include an internal spacer layer 130 disposed on the lower surface of each of the plurality of channel layers 141A, 142A, 141B, and 142B and the lower surface of the intermediate insulating structure MDI on both sides of the gate structure 160 in the first direction. In the example implementation, the internal spacer layer 130 may be in contact with at least one of the lower source / drain region 150A and the upper source / drain region 150B. The internal spacer layer 130 may be disposed between the plurality of channel layers 141A, 142A, 141B, and 142B in parallel with the gate electrode 165. The internal spacer layer 130 may be in contact with the gate dielectric layer 162. The internal spacer layer 130 may be disposed between the gate structure 160 and the source / drain region 150. The side surface of the internal spacer layer 130 may be in contact with the source / drain region 150. The gate electrode 165 may be electrically isolated from the source / drain region 150 by the inner spacer layer 130. A side surface of the inner spacer layer 130 opposite to the gate electrode 165 may have a shape that is rounded outward toward the gate electrode 165. For example, the inner spacer layer 130 may be formed of oxide, nitride, and oxynitride, and may be formed of a low dielectric constant film.

[0062] The inner spacer layer 130 may be formed of the same material as the gate spacer layer 164, but its exemplary implementation is not limited thereto. For example, the inner spacer layer 130 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN. The inner spacer layer 130 may also be applicable to other exemplary implementations.

[0063] Fig. 9 is an enlarged cross-sectional view showing a semiconductor device according to an example implementation to show Figure 2B The corresponding area.

[0064] refer to Fig. 9In the semiconductor device 100g, the shape of the lower source / drain region 150A may be symmetrical with respect to a surface CL where the blocking structure 170 and the lower source / drain region 150A meet each other and a shape formed by combining the intermediate insulating structure MDI and the upper source / drain region 150B. In an example implementation, the upper recess region RCU and the lower recess region RCB may be symmetrical with respect to a surface CL where the blocking structure 170 and the lower source / drain region 150A meet each other, which may be because the thickness of the uppermost channel layer 142B among the upper channel layers 141B and 142B is configured to be greater than the thickness of the upper channel layers 141B other than the lower channel layers 141A and 142A and the uppermost channel layer 142B, but the example implementation is not limited thereto.

[0065] Fig.10 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0066] refer to Fig.10 In the semiconductor device 100h, the barrier structure 170 may be formed in a structure in which a first barrier pattern 171 surrounds a second barrier pattern 172. The first barrier pattern 171 may surround an upper surface, a lower surface, and a side surface of the second barrier pattern 172. The first barrier pattern 171 may be disposed between an upper surface of the second barrier pattern 172 and a lower surface of the upper source / drain region 150B. The first barrier pattern 171 may be disposed between an upper surface of the second barrier pattern 172 and a lower surface of the upper source / drain region 150B. Figure 19G The first barrier pattern 171 may be formed on the second barrier pattern 172 before forming the upper source / drain region 150A, but its exemplary implementation is not limited thereto. The first barrier pattern 171 may be formed to fill the space between the second barrier pattern 172 and the upper source / drain region 150A after forming the upper source / drain region 150A. The structure of the barrier structure 170 as above may also be applicable to another exemplary implementation.

[0067] Fig.11 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0068] refer to Fig.11 , the semiconductor device 100i may further include a third air gap AG3 between the second barrier pattern 172 and the first barrier pattern 171. The third air gap AG3 may be formed when the second barrier pattern 172 is formed to be convex downward and the first barrier pattern 171 does not completely fill the space between the second barrier pattern 172 and the upper source / drain region 150B. The third air gap AG3 may include a gas composed of air or a material used in a process of manufacturing the semiconductor device 100i, which may also be applicable to another exemplary implementation.

[0069] Fig.12 is an enlarged cross-sectional view showing a semiconductor device according to an example implementation to show Figure 2B The corresponding area.

[0070] refer to Fig.12 , the semiconductor device 100j may not include the second barrier pattern 172, and may include a third air gap AG3 surrounded by the first barrier pattern 171. By removing the second barrier pattern 172 and forming the first barrier pattern 171, the third air gap AG3 surrounded by the first barrier pattern 171 may be formed. The first barrier pattern 171 and the third air gap AG3 may electrically insulate the upper source / drain region 150B from the lower source / drain region 150A.

[0071] Fig.13 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0072] refer to Fig.13 The shape of the blocking structure 170 of the semiconductor device 100k may be similar to Fig.10 The shape of the semiconductor device 100h in the embodiment is different. The upper surface of the blocking structure 170 may be convex upward toward the upper source / drain region 150B, and the lower surface of the blocking structure 170 may be convex downward toward the lower source / drain region 150A. However, the shape is not limited to the above shape. In another example implementation, the upper surface of the blocking structure 170 (i.e., the upper surface of the first blocking pattern 171) may be wavy, and the lower surface of the blocking structure 170 (i.e., the lower surface of the first blocking pattern 171) may also be wavy, which may be due to the shape of the upper surface of the lower source / drain region 150A and the shape of the lower surface of the upper source / drain region 150B.

[0073] Fig.14 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0074] refer to Fig.14 The semiconductor device 100L may further include a third air gap AG3 between the upper surface of the second barrier pattern 172 and the lower surface of the upper source / drain region 150B. The shape of the first barrier pattern 171 may be similarly applicable to Fig.13 The shape of the first barrier pattern 171 is described in FIG. Fig.14 In the example implementation of FIG. 1 , the description of the third air gap AG3 can be the same as Fig.11 The description of the third air gap AG3 in is basically the same.

[0075] Fig.15 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Figure 2B The corresponding area.

[0076] refer to Fig.15 , the semiconductor device 100m may not include the second barrier pattern 172, but may include a third air gap AG3 surrounded by the first barrier pattern 171. The shape of the first barrier pattern 171 may be similarly applicable to Fig.13 The shape of the first barrier pattern 171 is described in FIG. Fig.15 In the example implementation of FIG. 1 , the description of the third air gap AG3 can be the same as Fig.12 The description of the third air gap AG3 in is basically the same.

[0077] Fig.16A is a cross-sectional view showing a semiconductor device. Fig. 16B is an enlarged cross-sectional view showing a portion of a semiconductor device. Fig.16A Shown with Figure 2A corresponding area, and Fig. 16B Shows Fig.16A Magnified “B” area in the image.

[0078] refer to Fig.16A and Fig. 16B , the cross-sectional surface of the lower source / drain region 150A in the semiconductor device 100n in the X direction may be in an inverted trapezoidal shape (i.e., the upper base of the trapezoid is closer to the substrate than the lower base of the trapezoid). In an exemplary implementation, the width of the upper portion of the lower source / drain region 150A in the X direction may be greater than the width of the lower portion. In the process of forming the lower source / drain region 150A, a recessed region may be further formed in the horizontal direction (e.g., the X direction and the Y direction) so that the width of the upper portion of the lower source / drain region 150A in the X direction may be greater than the lower width of the blocking structure 170 in the X direction. Since the recessed region is further formed in the horizontal direction, the cross-sectional surface of the lower source / drain region 150A on the active region 105 in the Y direction may be in a hexagonal or pentagonal shape. A curved portion in a portion where the upper surface of the lower source / drain region 150A and the side surface of the blocking structure 170 may be connected to each other may be obtained.

[0079] In an example implementation, the width of the lower gate structure 160A in the X direction may gradually increase toward the upper surface of the substrate 101. The width of the lower channel layers 141A and 142A in the X direction may gradually increase toward the upper surface of the substrate 101. Among the lower channel layers 141A and 142A, the width of the second lower channel layer 142A as the uppermost channel layer in the X direction may be substantially equal to or less than the width of the first upper channel layer 141B as the lowermost channel layer among the upper channel layers 141B and 142B in the X direction. In the process of forming the lower source / drain region 150A, by forming an additional recessed region in the horizontal direction, the length of the lower channel layers 141A and 142A may be adjusted, and the process of forming the epitaxial layer may be improved.

[0080] Fig.17 is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example implementation to illustrate Fig. 16B The corresponding area.

[0081] refer to Fig.17 ,exist Fig. 16B In the semiconductor device 100n in FIG. 1 , when a recessed region is further formed in the horizontal direction (eg, the X direction and the Y direction) to form the lower source / drain region 150A, the lower source / drain region 150A may include a lower source / drain protruding region 150AP. In an example implementation, in the later described Fig.19C In the process, the lower source / drain protruding region 150AP can be formed by forming a lower recessed region RCB, further etching the lower recessed region RCB in the horizontal direction by a wet etching process, and forming a lower source / drain region 150A in the lower recessed region RCB. The upper source / drain protruding region 150BP can be formed by forming an upper recessed region RCU, further etching the upper recessed region RCU in the horizontal direction by a wet etching process, and forming an upper source / drain region 150B in the upper recessed region RCU. Fig.17 In the embodiment, the upper source / drain protruding region 150BP may also be formed, but only the lower source / drain protruding region 150AP may be formed, or only the upper source / drain protruding region 150BP may be formed. The formation of the lower source / drain protruding region 150AP and the formation of the upper source / drain protruding region 150BP may be independent of each other.

[0082] Fig.18 A cross-sectional view showing a portion of a semiconductor device is presented to show Figure 2A The corresponding area.

[0083] refer to Fig.18 ,Apart from Figure 2A In addition to the components of the semiconductor device 100, Fig.18The semiconductor device 100 p in FIG. 1 may further include a wiring structure having a via VA and a metal interconnect ML, a lower insulating structure (bottom dielectric isolation structure; BDI), a back side contact structure 210 , a back side power structure 195 , and a lower insulating layer 196 .

[0084] The via VA may penetrate the first upper insulating layer 192. The via VA may be connected to the contact structure 180. The via VA may be formed of a conductive material.

[0085] The metal interconnect ML may form a back-end BEOL process together with the via VA. The metal interconnect ML and the via VA may be provided as an interconnection portion for signal transmission. In an example implementation, a signal network may be configured by connecting from the metal interconnect ML and the via VA to a device region (e.g., source / drain region 150 and gate electrode 165) through a contact structure 180. The via VA and the metal interconnect ML may also be applicable to the semiconductor device 100, but for ease of description, they may not be provided.

[0086] The lower insulating structure BDI may be disposed between the lowermost surface of the lower gate structure 160A and the upper surface of the active region 105. The lower insulating structure BDI may include a material substantially the same as that of the middle insulating structure MDI, but example implementations thereof are not limited thereto.

[0087] The back contact structure 210 can be connected to the lower source / drain region 150A by penetrating the substrate 101 below the lower source / drain region 150A. The back contact structure 210 can penetrate the substrate 101 and can extend vertically. The side surface of the back contact structure 210 and the side surface of the substrate 101 can contact each other. The back contact structure 210 can be a self-aligned contact (SAC) aligned by the lower insulating structure BDI. Therefore, a contact margin can be ensured between the back contact structure 210 and the lower source / drain region 150A. The back contact structure 210 can be partially recessed into the lower region of the lower source / drain region 150A, and can contact the recessed lower surface of the lower source / drain region 150A.

[0088] The back contact structure 210 may include a liner layer 214, a second metal semiconductor compound layer 212, and a conductive layer 216. Although not shown, the back contact structure 210 may further include an insulating liner for insulation from the substrate 101. The liner layer 214 may form an outer side surface of the back contact structure 210 and a portion of an upper surface of the back contact structure 210. However, in an example implementation, the extension range of the liner layer 214 may vary. The liner layer 214 may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0089] The second metal semiconductor compound layer 212 may be disposed at the upper end of the back contact structure 210 and may form at least a portion of the upper surface of the back contact structure 210. The back contact structure 210 may be in contact with the source / drain region 150 through the second metal semiconductor compound layer 212 disposed on its surface. However, in example implementations, the scope of the second metal semiconductor compound layer 212 may not be limited to the example shown. The second metal semiconductor compound layer 212 may be, for example, a metal silicide layer. The conductive layer 216 may be disposed to fill the contact hole surrounded by the liner layer 214 and the second metal semiconductor compound layer 212. The conductive layer 216 may include a metal material such as aluminum (Al), tungsten (W) or molybdenum (Mo). In example implementations, the number of conductive layers included in the back contact structure 210 and their arrangement forms may be changed in various ways. In some example implementations, the liner layer 214 and / or the second metal semiconductor compound layer 212 may not be provided.

[0090] The back power structure 195 may be connected to the lower end or lower surface of the back contact structure 210. The back power structure 195 together with the back contact structure 210 may form a back power delivery network (BSPDN) to which power or ground voltage is applied, and may also be referred to as a back power rail or a buried power rail. For example, the back power structure 195 may be a buried interconnect extending in a certain direction (e.g., the Y direction) below the back contact structure 210, but the form of the back power structure 195 is not limited thereto. For example, in some example implementations, the back power structure 195 may include a via region and / or a line region. The back power structure 195 may include a conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo).

[0091] The lower insulating layer 196 may be provided to cover the substrate 101. The lower insulating layer 196 may include at least one of oxide, nitride, and oxynitride, and may include, for example, a low dielectric constant material. In example implementations, the lower insulating layer 196 may include a plurality of insulating layers.

[0092] FIG. 19A to FIG. 19H is a cross-sectional view showing a method of manufacturing a semiconductor device, Figures 1 to 2B Example embodiments of a method for a semiconductor device 100 and methods related thereto Figure 2A The corresponding cross-sectional surface.

[0093] refer to Fig.19A, sacrificial layers 120 , lower channel layers 141A and 142A, semiconductor patterns 140S, and upper channel layers 141B and 142B may be alternately stacked on the substrate 101 , an active structure may be formed, and a sacrificial gate structure 200 may be formed in the second direction Y to intersect the active structure.

[0094] The sacrificial layer 120 may include a lower sacrificial layer 120A, a middle sacrificial layer 120B, and an upper sacrificial layer 120C. The lower sacrificial layer 120A and the upper sacrificial layer 120C may be formed by Figure 2A The subsequent process shown is replaced with a gate dielectric layer 162 and a gate electrode 165. The intermediate sacrificial layer 120B and the semiconductor pattern 140S can be formed by Figure 2A The subsequent process shown is replaced by an intermediate insulation structure MDI.

[0095] The sacrificial layer 120 may be formed of a material having an etching selectivity with respect to the lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B. The lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B may include a material different from that of the sacrificial layer 120. In example implementations, the lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B may include silicon (Si), and the sacrificial layer 120 may include silicon germanium (SiGe), but example implementations thereof are not limited thereto.

[0096] The sacrificial layer 120, the lower channel layers 141A and 142A, and the upper channel layers 141B and 142B may be formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial layer 120, the lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B may have a thickness ranging from about 100 to about 1000. In example implementations, the number of lower channel layers 141A and 142A, semiconductor patterns 140S, and upper channel layers 141B and 142B alternately stacked with the sacrificial layers 120 may vary.

[0097] Thereafter, an active structure may be formed by removing the sacrificial layer 120 , the lower channel layers 141A and 142A, the semiconductor pattern 140S, the upper channel layers 141B and 142B, and a portion of the substrate 101 , and a sacrificial gate structure 200 may be formed on the active structure.

[0098] The active structure may include sacrificial layers 120, lower channel layers 141A and 142A, semiconductor patterns 140S, and upper channel layers 141B and 142B alternately stacked on one another, and may also include an active region 105 formed by removing a portion of the substrate 101 and protruding to the upper surface of the substrate 101. The active structures may be formed in the form of lines extending in one direction (e.g., the X direction) and may be spaced apart from one another in the Y direction.

[0099] The device isolation layer 110 may be formed by filling an insulating material in a region where a portion of the substrate 101 is removed, and recessed into the active region 105 to protrude. An upper surface of the device isolation layer 110 may be formed at a height lower than that of an upper surface of the active region 105.

[0100] like Figure 2A As shown, the sacrificial gate structure 200 may be configured as a sacrificial structure formed in a region where the gate dielectric layer 162 and the gate electrode 165 are disposed on the upper portion of the channel structure 140 by a subsequent process. The sacrificial gate structure 200 may include a first sacrificial gate layer 202, a second sacrificial gate layer 205, and a mask pattern layer 206 stacked in sequence. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be patterned using the mask pattern layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be configured as an insulating layer and a conductive layer, respectively. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon nitride. The sacrificial gate structure 200 may have a line shape intersecting the active structure and extending in one direction. For example, the sacrificial gate structure 200 may extend in the Y direction and may be spaced apart from each other in the X direction.

[0101] refer to Fig.19B , a middle insulating structure MDI may be formed, and a gate spacer layer 164 may be formed to cover upper surfaces and side surfaces of the sacrificial gate structure 200 and the active structure.

[0102] The intermediate sacrificial layer 120B and the semiconductor pattern 140S may have an etching selectivity with respect to the lower sacrificial layer 120A, the upper sacrificial layer 120C, the lower channel layers 141A and 142A, and the upper channel layers 141B and 142B, so that the intermediate sacrificial layer 120B and the semiconductor pattern 140S may be selectively removed. The intermediate insulating structure MDI may be formed by filling the intermediate insulating pattern 300 in the area where the intermediate sacrificial layer 120B and the semiconductor pattern 140S have been removed. The intermediate insulating pattern 300 may include, for example, oxide or nitride. In another example implementation, the semiconductor pattern 140S may not be removed. In addition, in another example implementation, the semiconductor pattern 140S may have an etching selectivity with respect to the intermediate sacrificial layer 120B. The intermediate insulating structure MDI may be formed by removing the intermediate sacrificial layer 120B, filling the area where the intermediate sacrificial layer 120B has been removed with the intermediate insulating pattern 300, and removing the semiconductor pattern 140S. Figure 5 The first air gap AG1 of the semiconductor device 100c is formed in FIG.

[0103] The gate spacer layer 164 may be formed to cover the sidewall and upper surface of the sacrificial gate structure 200. The gate spacer layer 164 may form a film having a uniform thickness along the upper and side surfaces of the sacrificial gate structure 200 and the active structure. The gate spacer layer 164 may cover the upper surface of the device isolation layer 110. The gate spacer layer 164 may be formed of a material having a low dielectric constant, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0104] refer to Fig.19C , a portion of the gate spacer layer 164 may be removed, a portion of the upper channel layers 141B and 142B, the upper sacrificial layer 120C, and the intermediate insulating structure MDI may be removed, and a first barrier pattern 171 may be formed.

[0105] A portion of the gate spacer layer 164 may be removed by anisotropic etching. Thus, the upper surface of the device isolation layer 110, the upper surface of the sacrificial gate structure 200, and the gate spacer layer 164 present on the upper surface of the active structure may be removed. A portion of the gate spacer layer 164 present on the side surface of the active structure may also be removed so that the thickness may be reduced.

[0106] The upper recess region RCU may be formed by removing a portion of the exposed upper sacrificial layer 120C, the upper channel layers 141B and 142B, and the intermediate insulating structure MDI between the sacrificial gate structures 200 .

[0107] Because the upper recessed area RCU is formed such that its width in the first direction X decreases downward, the upper recessed area RCU may have an inclined side surface. The upper recessed area RCU may penetrate at least a portion of the intermediate insulating structure MDI. The height of the lower end of the upper recessed area RCU may be substantially equal to or lower than the height of the surface where the intermediate insulating structure MDI and the upper sacrificial layer 120C contact each other, and may be substantially equal to or higher than the height of the contact surface between the intermediate insulating structure MDI and the lower sacrificial layer 120A. In another exemplary implementation, in order to manufacture Figure 3 In the semiconductor device 100a, an upper recess region RCU may be formed, and the upper recess region RCU may be further formed in a horizontal direction through a wet etching process.

[0108] The first barrier pattern 171 may be formed to cover the sacrificial gate structure 200, the gate spacer layer 164, the active structure, and the upper recessed region RCU. The first barrier pattern 171 may be formed as a film having a uniform thickness along the upper and side surfaces of the sacrificial gate structure 200, the upper and side surfaces of the gate spacer layer 164, the upper and side surfaces of the active structure, the side and lower surfaces of the upper recessed region RCU, and the upper surface of the device isolation layer 110. The first barrier pattern 171 may be formed along the surface of the intermediate insulating structure MDI exposed by the upper recessed region RCU. The first barrier pattern 171 may include oxide or nitride.

[0109] refer to Fig.19D , the lower recess region RCB may be formed by removing a portion of the first barrier pattern 171, the lower channel layers 141A and 142A, the lower sacrificial layer 120A, and a portion of the intermediate insulating structure MDI.

[0110] The first barrier pattern 171 exposed between the sacrificial gate structures 200 may be partially removed through an anisotropic etching process, and the lower channel layers 141A and 142A, the lower sacrificial layer 120A, and the intermediate insulating structure MDI may be removed, thereby forming a lower recess region RCB.

[0111] The lower recessed region RCB may have a side surface so that its width in the first direction X may gradually increase toward the upper surface of the substrate 101. The lower recessed region RCB may partially remove the upper portion of the active region 105, but its example implementation is not limited thereto. The width of the upper recessed region RCU in the first direction X may gradually decrease toward the upper surface of the substrate 101. The width of the lower recessed region RCB in the first direction X may decrease or increase toward the upper surface of the substrate 101, thereby may include a middle portion 300P, which is a portion where the side surface of the lower recessed region RCB is connected to the side surface of the upper recessed region RCU. In the middle portion 300P, the slope of the side surface of the lower recessed region RCB may be transformed into a positive slope or a negative slope, and the slope of the side surface of the upper recessed region RCU may be transformed into a negative slope or a positive slope. In another example implementation, in order to manufacture Figure 3 In the semiconductor device 100a, a recessed region RCB may be formed, and the recessed region RCB may be further etched in a horizontal direction through a wet etching process.

[0112] refer to Fig.19E , the lower source / drain region 150A may be formed by forming an epitaxial layer in the lower recess region RCB.

[0113] The lower source / drain region 150A may be formed by epitaxial growth and may extend to contact the lower channel layers 141A and 142A and the lower sacrificial layer 120A in the lower recessed region RCB. The lower surface of the lower source / drain region 150A may have a downwardly convex shape, but example implementations thereof are not limited thereto. Due to in-situ doping, the lower source / drain region 150A may include impurities. The lower source / drain region 150A (150AL, see Figure 2B ) may be higher than the height of the surface where the intermediate insulating structure MDI and the lower sacrificial layer 120A contact each other. Depending on the type of impurities, the upper surface of the lower source / drain region 150A may be flat or convex upward. Therefore, the shape of the lower surface of the intermediate insulating structure MDI formed in the subsequent process may vary.

[0114] refer to Fig.19F , the barrier structure 170 may be formed by forming a first barrier pattern 171 and a second barrier pattern 172 .

[0115] The first barrier pattern 171 may be formed to cover the upper surface of the lower source / drain region 150A. The second barrier pattern 172 may be formed to fill a portion of the upper recessed region RCU. The second barrier pattern 172 may have a shape in which its upper surface may be convex downward. The barrier structure 170 may be formed by removing the first barrier pattern 171 exposed on the sidewall of the upper recessed region RCU and filling a portion of the upper recessed region RCU with the second barrier pattern 172. The second barrier pattern 172 may protect the first barrier pattern 171. In the process of removing the first barrier pattern 171, the first barrier pattern 171 may also be removed from the device isolation layer 110.

[0116] refer to Figure 19G , an upper source / drain region 150B may be formed on the intermediate insulating structure MDI to fill the upper recess region RCU.

[0117] The upper source / drain region 150B may be formed by epitaxial growth and may extend to contact the upper channel layers 141B and 142B and the upper sacrificial layer 120C in the upper recessed region RCU. The upper surface of the upper source / drain region 150B may be in an upwardly convex shape, and the lower surface of the upper source / drain region 150B may be in a downwardly convex shape, but example implementations thereof are not limited thereto. Due to in-situ doping, the upper source / drain region 150B may include impurities.

[0118] refer to Fig.19H , the interlayer insulating layer 190 may be formed, and the sacrificial gate structure 200 , the upper sacrificial layer 120C, and the lower sacrificial layer 120A may be removed.

[0119] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 200 and the source / drain regions 150 and performing a planarization process.

[0120] The sacrificial gate structure 200, the upper sacrificial layer 120C, and the lower sacrificial layer 120A may be selectively removed relative to the gate spacer layer 164, the interlayer insulating layer 190, the lower channel layers 141A and 142A, the upper channel layers 141B and 142B, and the intermediate insulating structure MDI. First, the upper gap region UR may be formed by removing the sacrificial gate structure 200, and the lower gap region LR may be formed by removing the lower sacrificial layer 120A and the upper sacrificial layer 120C exposed by the upper gap region UR. For example, when the lower sacrificial layer 120A and the upper sacrificial layer 120C include silicon germanium (SiGe) and the lower channel layers 141A and 142A and the upper channel layers 141B and 142B include silicon (Si), the lower gap region LR may be formed by using peracetic acid and / or a solution (NH4+) used as an etchant in an SC1 (standard cleaning-1) cleaning process. 4 OH:H2 O 2 :H 2 O=1:1:5) A wet etching process is performed to selectively remove the lower sacrificial layer 120A and the upper sacrificial layer 120C.

[0121] Afterwards, refer to Figure 2A , a gate dielectric layer 162 and a gate electrode 165 may be formed in the upper gap region UR and the lower gap region LR. A gate capping layer 166 may be formed in the upper gap region UR. In addition, Figures 1 to 2B The illustrated semiconductor device 100 may be manufactured by forming a contact structure 180 .

[0122] FIG. 20A to FIG. 20J is a cross-sectional view showing a method of manufacturing a semiconductor device according to an example implementation, to show the manufacturing Fig.18 Example implementations of the method of the semiconductor device 100p in Fig.18 The corresponding cross-sectional surface.

[0123] refer to Fig. 20A , a sacrificial barrier layer 120D may be formed on the substrate 101, and similarly Fig.19A In the process, the sacrificial layer 120, the lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B may be alternately stacked, an active structure may be formed, and a sacrificial gate structure may be formed in the second direction Y to intersect the active structure.

[0124] The sacrificial barrier layer 120D may be formed of a material having an etching selectivity relative to the sacrificial layer 120, the lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B. The sacrificial barrier layer 120D may include silicon (Si) or silicon germanium (SiGe). When the sacrificial barrier layer 120D includes silicon germanium (SiGe), the sacrificial barrier layer 120D may have an etching selectivity due to the difference in germanium (Ge) concentration with the sacrificial layer 120. The sacrificial barrier layer 120D may be replaced with a lower insulating structure BDI through a subsequent process.

[0125] Afterwards, you can execute Fig.19A Basically the same process.

[0126] refer to Fig. 20B , a middle insulating structure MDI and a lower insulating structure BDI may be formed, and a gate spacer layer 164 may be formed.

[0127] The intermediate insulating structure MDI may be formed by selectively removing the intermediate sacrificial layer 120B and the semiconductor pattern 140S and filling the intermediate insulating pattern 300. The lower insulating structure BDI may be formed by selectively removing the sacrificial barrier layer 120D and filling the removed area with the lower insulating pattern 310. However, the process is not limited to the above process, and the intermediate insulating structure MDI and the lower insulating structure BDI may be simultaneously formed by simultaneously removing the sacrificial barrier layer 120D, the intermediate sacrificial layer 120B, and the semiconductor pattern 140S and filling the layers with insulating material. According to another example implementation, the intermediate insulating structure MDI and the lower insulating structure BDI may be formed in the process of forming the gate structure 160. Thereafter, the gate structure 160 may be formed by performing the same Fig.19B The gate spacer layer 164 is formed by substantially the same process as in FIG.

[0128] Afterwards, you can execute Fig.19C and Fig.19D Basically the same process.

[0129] refer to Fig. 20C , the dummy recess region DRC may be formed by partially removing the lower insulating structure BDI and the active region 105 .

[0130] The dummy recess region DRC may be formed by partially removing the lower insulating structure BDI and the upper portion of the active region 105 through an etching process. The dummy recess region DRC may have a shape whose width decreases toward the upper surface of the substrate 101, but example implementations thereof are not limited thereto.

[0131] refer to Fig.20D , a sacrificial epitaxial layer 150S may be formed to fill the dummy recess region DRC, and a lower source / drain region 150A may be formed to fill the lower recess region RCB.

[0132] The sacrificial epitaxial layer 150S may be formed on the active region 105 between the gate spacer layers 164. The sacrificial epitaxial layer 150S may be formed by filling the dummy recess region DRC with a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In an example implementation, the sacrificial epitaxial layer 150S may include silicon germanium (SiGe).

[0133] Afterwards, you can execute Fig.19E The lower source / drain region 150A is formed by substantially the same process as in FIG.

[0134] refer to Fig.20E , can be done by executing Fig.19F The intermediate insulating structure MDI is formed by basically the same process as in the above.

[0135] refer to Fig.20F , by executing Figure 19G By substantially the same process as in FIG. 1 , an upper source / drain region 150B may be formed to fill the upper recess region RCU.

[0136] refer to Figure 20G , by executing Fig.19H By substantially the same process as in FIG. 1 , the interlayer insulating layer 190 may be formed, and the sacrificial gate structure 200, the upper sacrificial layer 120C, and the lower sacrificial layer 120A may be removed. Thus, the upper gap region UR and the lower gap region LR may be formed.

[0137] refer to Fig. 20H , a gate structure 160 may be formed in the upper gap region UR and the lower gap region LR.

[0138] The gate dielectric layer 162 may be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 may be formed to fill the upper gap region UR and the lower gap region LR. The gate electrode 165 and the gate spacer layer 164 may be removed from the upper portion of the upper gap region UR to a predetermined depth. In the upper gap region UR, a gate capping layer 166 may be formed in a region where the gate electrode 165 and the gate spacer layer 164 have been removed. Thus, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166 may be formed.

[0139] refer to Fig.20I , a contact structure 180 , a via VA, and a metal interconnection ML may be formed.

[0140] A contact hole connected to the source / drain region 150 may be formed in the interlayer insulating layer 190, and a barrier layer 184 and a plug conductive layer 186 may be sequentially formed so that the contact hole is filled. Specifically, a material forming the barrier layer 184 may be filled in the contact hole, and by performing a silicidation process, a first metal semiconductor compound layer 182 such as a silicide layer may be formed at a lower end. Thereafter, by performing a planarization process such as CMP, the upper surface of the contact structure 180 and the upper surface of the interlayer insulating layer 190 may be substantially coplanar with each other.

[0141] A first upper insulating layer 192 may be formed to cover the contact structure 180 and the gate structure 160, and a via VA penetrating the first upper insulating layer 192 and connected to the contact structure 180 may be formed. A second upper insulating layer 193 may be formed to cover the first upper insulating layer 192 and the via VA, and a metal interconnection ML may be formed by patterning the second upper insulating layer 193 and filling each layer with a conductive material. The metal interconnection ML is not limited to the above process and may also be formed by a subtractive process.

[0142] refer to Fig. 20J , you can refer to FIG. 20A to FIG. 20I The entire structure formed is attached to a carrier substrate SUB, and a back contact hole BCH may be formed.

[0143] The carrier substrate SUB may be attached to the second upper insulating layer 193 or the metal interconnection ML to Fig.20I The process is performed on the lower surface of the substrate 101 in FIG. Fig. 20J In the example, the entire structure can be Fig.20I The structure shown is rotated or inverted in a mirror image.

[0144] The substrate 101 may be penetrated so that the sacrificial epitaxial layer 150S may be exposed and the sacrificial epitaxial layer 150S may be selectively removed. The sacrificial epitaxial layer 150S may be removed and a back contact hole BCH may be formed to penetrate a portion of the lower source / drain region 150A, but example implementations thereof are not limited thereto.

[0145] In another example implementation, the substrate 101 may be removed from the upper surface of the substrate 101 , an insulating layer may be formed, and a back side contact hole BCH penetrating the insulating layer may be formed.

[0146] The back contact structure 210 may be formed to fill the back contact hole BCH. The second metal semiconductor compound layer 212 may be formed by performing a metal semiconductorization process such as a silicidation process using the lower source / drain region 150A exposed by the back contact hole BCH. The back contact structure 210 may be formed by forming a liner layer 214 on the side surface of the back contact hole BCH and forming a conductive layer 216 to fill the back contact hole BCH.

[0147] Afterwards, refer to Fig.18 , a back power structure 195 can be formed.

[0148] After forming the lower insulating layer 196, the back power structure 195 may be formed by partially removing the lower insulating layer 196, and the carrier substrate SUB may be removed. Fig.18The semiconductor device 100h may be packaged in a state where the back side power structure 195 is disposed at an upper portion, but example implementations thereof are not limited thereto.

[0149] According to the aforementioned example implementation, by including a structure having a first lower inclined surface and a second lower inclined surface, wherein the first lower inclined surface is inclined so that the width of the lower source / drain region in the first direction increases from the lower source / drain region toward the upper portion and the second lower inclined surface has a slope different from the slope of the first lower inclined surface, a cross-sectional surface of the lower source / drain region in the X direction can be trapezoidal in shape, thereby providing a semiconductor device with improved electrical properties.

[0150] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope that can be claimed. Certain features described in the context of a separate implementation in the present disclosure can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. In addition, although features can be described above as functioning in a specific combination and even initially claimed as such, one or more features from a combination can be removed from the combination in some cases, and the combination can be directed to a sub-combination or a variation of a sub-combination.

[0151] While example implementations have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: An active region extending along a first direction on the substrate; a device isolation layer, the device isolation layer being disposed on the substrate and defining the active area; lower channel layers, the lower channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; an upper channel layer, the upper channel layers being disposed on the lower channel layer and spaced apart from each other in the vertical direction; an intermediate insulating structure, the intermediate insulating structure being disposed between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers; a gate structure intersecting the active region, surrounding each of the lower channel layers and each of the upper channel layers, and extending in a second direction; a lower source / drain region, the lower source / drain region being disposed on the active region on at least one side of the gate structure and connected to the lower channel layer; an upper source / drain region connected to each of the upper channel layers on at least one side of the gate structure and spaced apart from the lower source / drain region in the vertical direction; as well as a blocking structure disposed between the lower source / drain region and the upper source / drain region, The lower source / drain region fills a lower recessed region defined by a side surface of the lower channel layer, a side surface of the gate structure, and an upper surface of the active region. wherein the upper source / drain region fills an upper recessed region defined by a side surface of the upper channel layer, a side surface of the gate structure, and a lower surface and a side surface of the barrier structure, and The slope of the side surface of the lower recessed area and the slope of the side surface of the upper recessed area have opposite signs.

2. The semiconductor device according to claim 1, further comprising: a middle portion, wherein the middle portion is a portion where the side surface of the lower recessed area is connected to the side surface of the upper recessed area, The middle portion is a concave portion formed by an upper portion of the lower concave region and a lower portion of the upper concave region.

3. The semiconductor device according to claim 2, wherein: The height of the middle portion is substantially equal to or lower than the height of the upper surface of the intermediate insulating structure, and substantially equal to or higher than the height of the lower surface of the intermediate insulating structure.

4. The semiconductor device according to claim 2, wherein: A side surface of the lower source / drain region and a side surface of the upper source / drain region extend and meet each other in the middle portion.

5. The semiconductor device according to claim 2, wherein: The height of the middle portion is substantially equal to or higher than the height of the uppermost surface of the gate structure disposed below the lower surface of the intermediate insulating structure, and substantially equal to or lower than the height of the lowermost surface of the gate structure disposed on the upper surface of the intermediate insulating structure.

6. The semiconductor device according to claim 1, further comprising: An inner spacer layer contacts at least one of the lower source / drain region and the upper source / drain region and is disposed on both sides of the gate structure in the first direction.

7. The semiconductor device according to claim 1, in, The thickness of the uppermost upper channel layer among the upper channel layers is greater than the thickness of each of the lower channel layers, and is also greater than the thickness of each of the upper channel layers except the uppermost upper channel layer among the upper channel layers, and The lower recessed region is symmetrical to the upper recessed region with respect to a surface where the blocking structure and the lower source / drain region are connected to each other.

8. The semiconductor device according to claim 1, further comprising: a lower insulating structure disposed between a lowermost surface of the gate structure and an upper surface of the active region; as well as A back contact structure penetrates a portion of the lower source / drain region and the lower insulating structure and is connected to the lower source / drain region below the lower source / drain region.

9. The semiconductor device according to claim 1, wherein: The height of the lowermost end of the upper source / drain region is lower than the height of the uppermost surface of the intermediate insulating structure.

10. The semiconductor device according to claim 1, wherein An upper portion of the lower source / drain region horizontally overlaps the intermediate insulating structure.

11. A semiconductor device, comprising: An active region extending along a first direction on the substrate; a device isolation layer, the device isolation layer being disposed on the substrate and defining the active area; lower channel layers, the lower channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; an upper channel layer, the upper channel layers being disposed on the lower channel layer and spaced apart from each other in the vertical direction; an intermediate insulating structure, the intermediate insulating structure being disposed between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers; a lower gate structure intersecting the active region, surrounding each of the lower channel layers, extending in the second direction, and disposed below a lower surface of the intermediate insulating structure; an upper gate structure, the upper gate structure surrounding each of the upper channel layers, extending in the second direction, and disposed on an upper surface of the intermediate insulating structure; a lower source / drain region, the lower source / drain region being disposed on the active region on at least one side of the lower gate structure and connected to each of the lower channel layers; an upper source / drain region connected to each of the upper channel layers on at least one side of the upper gate structure and spaced apart from the lower source / drain region in the vertical direction; as well as a blocking structure disposed between the lower source / drain region and the upper source / drain region, wherein the width of the upper portion of the lower source / drain region in the first direction is greater than the width of the lower portion of the blocking structure in the first direction, wherein the width of the lower gate structure in the first direction decreases toward the upper surface of the substrate, and Wherein, the width of the upper gate structure in the first direction increases toward the upper surface of the substrate.

12. The semiconductor device according to claim 11, in, The width of the lower channel layer in the first direction decreases toward the upper surface of the substrate, and Wherein, the width of the upper channel layer in the first direction increases toward the upper surface of the substrate.

13. The semiconductor device according to claim 11, wherein The intermediate insulating structure includes a plurality of intermediate insulating patterns and a semiconductor pattern located between the plurality of intermediate insulating patterns.

14. The semiconductor device according to claim 11, in, The intermediate insulating structure includes a first air gap, and Wherein, the first air gap vertically overlaps the lower gate structure and the upper gate structure.

15. The semiconductor device according to claim 14, in, The blocking structure comprises a second air gap, wherein the second air gap vertically overlaps the lower source / drain region and the upper source / drain region, and Wherein, the first air gap and the second air gap are connected to each other.

16. The semiconductor device according to claim 11, in, The lower source / drain region is recessed into a portion of the active region and includes a lower source / drain protruding region protruding toward the lower gate structure, and Wherein, the upper source / drain region includes an upper source / drain protruding region protruding toward the upper gate structure.

17. The semiconductor device according to claim 11, in, The cross-sectional surface of the upper source / drain region in the first direction is in an inverted trapezoidal shape, and Wherein, a cross-sectional surface of the lower source / drain region in the first direction is in a trapezoidal shape.

18. The semiconductor device according to claim 11, in, The blocking structure comprises: a first barrier pattern formed along an upper surface of the lower source / drain region, a lower surface of the upper source / drain region, and a side surface of the intermediate insulating structure; and At least one of a second barrier pattern or a third air gap surrounded by the first barrier pattern.

19. A semiconductor device, comprising: An active region extending along a first direction on the substrate; a plurality of channel layers, the plurality of channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure intersecting the active region, surrounding each of the plurality of channel layers and extending in a second direction; a lower source / drain region, the lower source / drain region being disposed on the active region on at least one side of the gate structure and connected to a portion of the plurality of channel layers; an upper source / drain region, the upper source / drain region being connected to another portion of the plurality of channel layers at at least one side of the gate structure and being spaced apart from the lower source / drain region in the vertical direction; as well as a blocking structure disposed between the lower source / drain region and the upper source / drain region, The lower source / drain region includes a first lower inclined surface and a second lower inclined surface, the first lower inclined surface has a first slope, and the second lower inclined surface has a second slope different from the first slope of the first lower inclined surface.

20. The semiconductor device according to claim 19, wherein The upper source / drain region includes a first upper inclined surface and a second upper inclined surface, wherein the first upper inclined surface is inclined so that the width of the upper source / drain region in the first direction decreases downward from the upper part of the upper source / drain region, and the second upper inclined surface is inclined so that the width of the upper source / drain region in the first direction decreases downward from the upper part of the upper source / drain region at a rate different from that of the first upper inclined surface.

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