Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, the structure comprises a substrate, the substrate comprises a first device region and a second device region which are adjacent along a first direction, a plurality of raised channel structures are formed on the substrate, the channel structures extend along a second direction and are arranged in parallel along the first direction, the first device region is used for forming a first device, and the second device region is used for forming a second device; the second device region is used for forming a second device, the first device and the second device are different in type, and the first direction is perpendicular to the second direction; the partition structure extends in the first direction, crosses and penetrates through the channel structures, the partition structure comprises a first partition structure located in the first device region and a second partition structure located in the second device region in the first direction, and the first partition structure and the second partition structure are made of different materials. The performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently being widely used. Therefore, with the increase in density and integration of semiconductor devices, the gate size of transistors is getting shorter and shorter, and the control ability of traditional planar transistors over channel current becomes weaker, resulting in short channel effects, causing leakage current to increase, and ultimately affecting the electrical performance of semiconductor devices.

[0003] In order to better adapt to the reduction of feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (FinFETs). In the current semiconductor process, the gate cut technology is usually used to cut the strip gate. The cut gate corresponds to different transistors, which can improve the integration of transistors. At the same time, the single diffusion break (SDB) structure is used to cut the strip channel structure to electrically isolate the active area structure on both sides of the SDB, which can reduce the polysilicon contact distance (CPP). Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region and a second device region adjacent to each other along a first direction, a plurality of protruding channel structures formed on the substrate, the channel structures extending along the second direction and arranged in parallel along the first direction, the first device region being used to form a first device, the second device region being used to form a second device, the first device and the second device being of different types, and the first direction being perpendicular to the second direction; a partition structure extending along the first direction across and through the plurality of channel structures, the partition structure including along the first direction a first partition structure located in the first device region, and a second partition structure located in the second device region, the first partition structure and the second partition structure being made of different materials.

[0006] Optionally, the semiconductor structure also includes: multiple gate structures spanning the channel structure, the gate structures extending along the first direction and arranged in parallel along the second direction, part of the gate structures being located on one side of the partition structure, and the rest of the gate structures being located on the other side of the partition structure; along the second direction, at least the first partition structure in the partition structure is equal in width to the gate structure.

[0007] Optionally, two partition structures are formed between adjacent partial gate structures and the remaining partial gate structures.

[0008] Optionally, the first partition structures of the two partition structures are arranged in parallel along the second direction, and the second partition structures of the two partition structures are an integrated structure.

[0009] Optionally, the semiconductor structure also includes: a dielectric layer located on the substrate and covering the side walls of the channel structure and the gate structure; a mask layer covering the dielectric layer and the gate structure; a first partition structure passing through the dielectric layer and the mask layer; a second partition structure whose top is lower than the top of the dielectric layer, and the second partition structure, the mask layer above it, the dielectric layer on its upper side, and the first partition structure form a gap.

[0010] Optionally, the gap also extends to the side of the second partition structure and is surrounded by the second partition structure and the dielectric layer on the side thereof.

[0011] Optionally, along the second direction, a gap enclosed by the second partition structure, the mask layer above it, and the dielectric layer on the upper side thereof is equal to the width of the gate structure.

[0012] Optionally, two partition structures are formed between adjacent partial gate structures and the remaining partial gate structures, the first partition structures of the two partition structures are arranged in parallel along the second direction, and each first partition structure encloses a gap corresponding to the position of the second partition structure along the first direction.

[0013] Optionally, the second partition structure of the two partition structures is an integrated structure, and the gaps corresponding to the two first partition structures are all surrounded by the integrated structure.

[0014] Optionally, the material of the first partition structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride; the material of the second partition structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0015] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region and a second device region adjacent to each other along a first direction, the first device region being used to form a first device, the second device region being used to form a second device, and the types of the first device and the second device being different; forming a protruding second partition structure on the substrate in the second device region, the second partition structure extending along the first direction; forming a plurality of protruding channel structures on the substrate, the channel structures extending along the second direction and arranged in parallel along the first direction, and in the second device region, the channel structures are partitioned by the second partition structure, and the second direction is perpendicular to the first direction; the second partition structure extends along the first direction to remove part of the channel structure in the first device region, so that the channel structure in the first device region is disconnected; forming a first partition structure in contact with the second partition structure at the location where the channel structure in the first device region is disconnected, the first partition structure extending along the first direction to span across and penetrate the plurality of channel structures, and forming a partition structure with the second partition structure, and the first partition structure and the second partition structure are made of different materials.

[0016] Optionally, before the second partition structure is extended along the first direction to remove part of the channel structure of the first device area, the formation method also includes: forming multiple gate structures across the channel structure, the gate structures extend along the first direction and are arranged in parallel along the second direction, part of the gate structure is in contact with the second partition structure, another part of the gate structure is located on one side of the second partition structure, and the remaining part of the gate structure is located on the other side of the second partition structure; the step of extending the second partition structure along the first direction to remove part of the channel structure of the first device area includes: removing the gate structure in contact with the second partition structure to form an opening exposing part of the channel structure of the first device area; removing the channel structure exposed by the opening to disconnect the channel structure in the first device area; in the step of forming a first partition structure in contact with the second partition structure at the location where the channel structure of the first device area is disconnected, the first partition structure is formed in the opening.

[0017] Optionally, in the step of forming a plurality of gate structures spanning the channel structure, two gate structures are in contact with the second isolation structure.

[0018] Optionally, in the step of forming a plurality of gate structures spanning the channel structure, two gate structures are in contact with the same second isolation structure.

[0019] Optionally, in the step of forming multiple gate structures across the channel structure, the gate structure in contact with the second partition structure also covers the top of the second partition structure; before forming the opening, the formation method also includes: forming a dielectric layer covering the side walls of the channel structure and the gate structure; forming a mask layer covering the dielectric layer and the top of the gate structure; the step of forming the opening includes: patterning the mask layer to form a mask opening exposing the top of the gate structure in contact with the second partition structure; removing the gate structure in contact with the second partition structure along the mask opening to form an opening, and the opening also extends to the top of the second partition structure; in the step of forming the first partition structure in the opening, the first partition structure penetrates the dielectric layer and the mask layer, and the second partition structure, the mask layer above it, the dielectric layer on the upper side thereof, and the first partition structure form a gap.

[0020] Optionally, an isotropic etching process is used to remove the gate structure in contact with the second partition structure.

[0021] Optionally, a chemical vapor deposition process is used to form the first partition structure in the opening.

[0022] Optionally, in the step of forming multiple gate structures across the channel structure, the gate structure in contact with the second partition structure also covers the side wall of the second partition structure; in the step of forming the first partition structure in the opening, the gap also extends to the side of the second partition structure and is surrounded by the second partition structure and the dielectric layer on its side.

[0023] Optionally, in the step of forming multiple gate structures across the channel structure, two gate structures are in contact with the second partition structure; in the step of forming the first partition structure in the opening, each first partition structure encloses a gap corresponding to the position of the second partition structure along the first direction.

[0024] Optionally, in the step of forming multiple gate structures across the channel structure, two gate structure items are in contact with the same second partition structure; in the step of forming a first partition structure in the opening, the gaps corresponding to the two first partition structures are surrounded by the same second partition structure.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiment of the present invention, the partition structure includes a first partition structure located in the first device area and a second partition structure located in the second device area along the first direction, and the first partition structure and the second partition structure are made of different materials; in the embodiment of the present invention, different materials are used as the first partition structure in the first device area and the second partition structure in the second device area, which is conducive to flexible selection of different materials and adapting to the performance of different devices. For example, for NMOS devices, materials that increase tensile stress are used, and for PMOS devices, materials that increase compressive stress are used, which is conducive to improving the flexibility of material selection for semiconductor devices, and is conducive to the targeted selection of performance-related materials for the first device and the second device, thereby facilitating improving the performance of the semiconductor structure.

[0027] In the formation method provided in the embodiment of the present invention, the first partition structure extends along the first direction, spans and penetrates multiple channel structures, and forms a partition structure with the second partition structure, and the first partition structure and the second partition structure are made of different materials; in the embodiment of the present invention, different materials are used to form the first partition structure in the first device area and the second partition structure in the second device area, which is conducive to flexible selection of different materials and adapting to the performance of different devices. For example, for NMOS devices, materials that increase tensile stress are used, and for PMOS devices, materials that increase compressive stress are used, which is conducive to improving the flexibility of material selection for semiconductor devices, and is conducive to the targeted selection of performance-related materials for the first device and the second device, thereby facilitating improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 to Figure 2 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0029] Figures 3 to 6 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0030] Figures 7 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0032] Figure 1 to Figure 2 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0033] Combined with reference Figure 1 and Figure 2 , Figure 2 for Figure 1The cross-sectional view along the AA direction, the semiconductor structure comprises: a substrate 10, including a first direction (such as Figure 1 A plurality of protruding channel structures 11 are formed on the substrate 10, and the channel structures 11 are arranged along the second direction (as shown in the Y direction in FIG. 1 ). Figure 1 The first device region 10P is used to form a first device, and the second device region 10N is used to form a second device. The first device and the second device are of different types, and the first direction is perpendicular to the second direction. The partition structure 21 extends along the first direction to cross and penetrate the multiple channel structures 11. The first device region 10P and the second device region 10N share the same partition structure 21.

[0034] The first device region 10P and the second device region 10N share the same partition structure 21, that is, the partition structure 21 of the first device region 10P and the second device region 10P is formed using the same material, which is difficult to adapt to the performance of different devices. For example, using a material that is beneficial to the performance of an NMOS device may easily have an adverse effect on the performance of a PMOS device, thereby affecting the performance of the semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region and a second device region adjacent to each other along a first direction, a plurality of protruding channel structures formed on the substrate, the channel structures extending along the second direction and arranged in parallel along the first direction, the first device region being used to form a first device, the second device region being used to form a second device, the first device and the second device being of different types, and the first direction being perpendicular to the second direction; a partition structure extending along the first direction across and through the plurality of channel structures, the partition structure including along the first direction a first partition structure located in the first device region, and a second partition structure located in the second device region, the first partition structure and the second partition structure being made of materials of different energies.

[0036] In an embodiment of the present invention, different materials are used as the first partition structure of the first device area and the second partition structure of the second device area, which is conducive to the flexible selection of different materials to adapt to the performance of different devices. For example, for NMOS devices, materials that increase tensile stress are used, and for PMOS devices, materials that increase compressive stress are used. This is conducive to improving the flexibility of material selection for semiconductor devices and is conducive to the targeted selection of performance-related materials for the first device and the second device, thereby facilitating the improvement of the performance of the semiconductor structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 3 to 6It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0039] Combined with reference Figures 3 to 6 , Figure 3 is a top view, Figure 4 for Figure 3 Cross-sectional view along AA direction, Figure 5 for Figure 3 Cross-sectional view along BB direction, Figure 6 for Figure 3 The cross-sectional view along the CC direction, the semiconductor structure comprises: a substrate 100, including a first direction (such as Figure 3 A first device region 100P and a second device region 100N are adjacent to each other in the second direction (as shown in the Y direction), and a plurality of protruding channel structures 110 are formed on the substrate 100. The channel structures 110 are arranged along the second direction (as shown in the Y direction) of FIG. Figure 3 The first device region 100P is used to form a first device, and the second device region 100N is used to form a second device. The first device and the second device are of different types, and the first direction is perpendicular to the second direction. A partition structure (not shown) extends along the first direction to cross and penetrate multiple channel structures 110. The partition structure includes a first partition structure 210 located in the first device region 100P and a second partition structure 220 located in the second device region 100N along the first direction. The first partition structure 210 and the second partition structure 220 are made of different materials.

[0040] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a fin field effect transistor (FinFET).

[0041] In this embodiment, the substrate 100 includes a first device region 100P and a second device region 100N adjacent to each other. The first device region 100P is used to form a first device, and the second device region 100N is used to form a second device. The first device and the second device are of different types.

[0042] Specifically, as an example, the first device is a PMOS transistor, and the second device is a NMOS transistor.

[0043] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0044] The channel structure 110 is used to provide a channel of the fin field effect transistor. In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium or III-V semiconductor materials.

[0045] The partition structure is used to partition the channel structure 110 .

[0046] In this embodiment, the partition structure of the channel structure 110 is a mixed diffusion break (MDB) structure, which is used to electrically isolate devices on both sides of the MDB structure, and is beneficial to reducing the polysilicon contact polypitch (CPP).

[0047] In the present embodiment, different materials are used as the first partition structure 210 of the first device area 100P and the second partition structure 220 of the second device area 100N, which is conducive to the flexible selection of different materials to adapt to the performance of different devices. For example, for NMOS devices, materials that increase tensile stress are used, and for PMOS devices, materials that increase compressive stress are used. This is conducive to improving the flexibility of material selection for semiconductor devices, and is conducive to the targeted selection of performance-related materials for the first device and the second device, thereby facilitating the improvement of the performance of the semiconductor structure.

[0048] In this embodiment, the material of the first partition structure 210 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the first partition structure 210 is one or more of silicon oxide, silicon nitride and silicon oxynitride that provide compressive stress.

[0049] The first partition structure 210 is formed by using one or more materials of silicon oxide, silicon nitride and silicon oxynitride that provide compressive stress, which is beneficial to improving the compressive stress of the PMOS device.

[0050] In this embodiment, the material of the second partition structure 220 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the second partition structure 220 is one or more of silicon oxide, silicon nitride and silicon oxynitride that provide tensile stress.

[0051] The second partition structure 220 is formed by using one or more materials of silicon oxide, silicon nitride and silicon oxynitride that provide tensile stress, which is beneficial to improving the tensile stress of the NMOS device.

[0052] In this embodiment, the semiconductor structure also includes: multiple gate structures 200 spanning the channel structure 110, the gate structures 200 extend along the first direction and are arranged in parallel along the second direction, part of the gate structures 200 are located on one side of the partition structure, and the rest of the gate structures 200 are located on the other side of the partition structure.

[0053] The gate structure 200 is used to control the opening and closing of the channel of the transistor. In this embodiment, the gate structure 200 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0054] The gate dielectric layer is used to isolate the gate structure 200 from the channel structure 110. The material of the gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 、SiO 2 and La 2 O 3 In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel structure. Specifically, the material of the gate oxide layer may be silicon oxide.

[0055] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0056] In this embodiment, the gate structure 200 is a metal gate structure. Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0057] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0058] In the present embodiment, a partition structure is formed at the position of the gate structure 200 by replacing part of the gate structure 200 with an insulating material. The gate structure 200 process that is already required is used to occupy space in advance for forming the partition structure, which is beneficial to improving the process integration and reducing the difficulty of forming the partition structure. Accordingly, in the present embodiment, part of the gate structure 200 is located on one side of the partition structure, and the remaining part of the gate structure 200 is located on the other side of the partition structure.

[0059] In this embodiment, a second partition structure 210 is pre-formed at the partition position of the second device region 100N. After the gate structure 200 is formed at the partition position, the gate structure 200 at this position is removed to form an opening, and a first partition structure 210 is formed at the opening position of the first device region 100P.

[0060] In other embodiments, after forming a gate structure at the partition position, the gate structure at the position may be removed to form an opening, a first partition structure may be formed at the opening position of the first device region, and a second partition structure may be formed at the opening position of the second device region.

[0061] Therefore, in this embodiment, along the second direction, at least the first partition structure 210 and the gate structure 200 in the partition structure have the same width.

[0062] In this embodiment, two partition structures are formed between adjacent partial gate structures 200 and the remaining partial gate structures 200 .

[0063] Two partition structures are formed between the adjacent partial gate structures 200 and the remaining partial gate structures 200 , which is beneficial to enhance the partition effect of the partition structures.

[0064] In this embodiment, the partition structure is an MDB structure. Specifically, the first partition structure 210 is a double diffusion break (DDB) structure, and the second partition structure 220 is a single diffusion break (SDB) structure. Accordingly, in this embodiment, the first partition structures 210 of the two partition structures are arranged in parallel along the second direction, and the second partition structures 220 of the two partition structures are an integrated structure.

[0065] In this embodiment, the semiconductor structure further includes: a dielectric layer 300 located on the substrate 100 and covering the sidewalls of the channel structure and the gate structure 200 .

[0066] The dielectric layer 300 is used to isolate adjacent devices and is also used to provide a process basis for forming the gate structure 200 .

[0067] In this embodiment, the material of the dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0068] In this embodiment, the semiconductor structure further includes: a mask layer 400 covering the dielectric layer 300 and the gate structure 200 .

[0069] The mask layer 400 is used as an etching mask for forming a partition structure, and is also used to form a gap with the second partition structure 220 .

[0070] In this embodiment, the material of the mask layer 400 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 400 can be a single-layer structure or a stacked-layer structure. As an example, the material of the mask layer 400 is silicon oxide and silicon nitride, that is, the mask layer 400 is a multi-layer structure, including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

[0071] In this embodiment, the top of the second partition structure 220 is lower than the top of the dielectric layer 300 , and the second partition structure 220 , the mask layer 400 thereon, the dielectric layer 300 on its upper side, and the first partition structure 210 form a gap 500 .

[0072] The gap 500 and the second partition structure 220 together isolate the devices on both sides of the second partition structure 220, and the second partition structure 220, the mask layer 400 above it, the dielectric layer 300 on its upper side, and the first partition structure 210 form a gap 500, which is beneficial to reduce coupling capacitance.

[0073] In this embodiment, the first partition structure 210 penetrates the dielectric layer 300 and the mask layer 400 .

[0074] After the gate structure 200 is formed at the partition position, the gate structure 200 at the position is removed, an opening is formed using the mask layer 400 as a mask, and a first partition structure 210 is formed at the opening position of the first device area 100P. Therefore, the first partition structure 210 penetrates the dielectric layer 300 and the mask layer 400. Moreover, the first partition structure 210 penetrates the mask layer 400 to seal the gap 500 above the second partition structure 220, thereby enclosing the gap 500 with the second partition structure 220, the mask layer 400 and the dielectric layer 300.

[0075] In the present embodiment, a second partition structure 220 is pre-formed at the partition position of the second device region 100N, and a gate structure 200 is subsequently formed to cover a portion of the top and side walls of the second partition structure 220. The gate structure 200 at the partition position is removed to expose the side walls of the second partition structure 220. Therefore, in the present embodiment, the gap 500 also extends to the side of the second partition structure 220 and is surrounded by the second partition structure 220 and the dielectric layer 300 on its side.

[0076] In this embodiment, along the second direction, a gap 500 formed by the second partition structure 220 , the mask layer 400 thereon, and the dielectric layer 300 thereon and on its upper side is equal in width to the gate structure 200 .

[0077] As can be seen from the above, the gap 500 surrounded by the second partition structure 220, the mask layer 400 above it, and the dielectric layer 300 on the upper side thereof is obtained by removing the gate structure 200 at the partition position. Therefore, along the second direction, the gap 500 surrounded by the second partition structure 220, the mask layer 400 above it, and the dielectric layer 300 on the upper side thereof is equal to the width of the gate structure 200.

[0078] In the present embodiment, the first partition structure 210 is a DDB structure, and the second partition structure 220 is an SDB structure. The first partition structure 210 extends along the second direction to the corresponding position of the second partition structure 220, which is the position of the gap 500. The first partition structure 210 is a DDB structure, and two gaps 500 are formed at the corresponding position. Therefore, in the present embodiment, two partition structures are formed between adjacent partial gate structures 200 and the remaining partial gate structures 200. The first partition structures 210 of the two partition structures are arranged in parallel along the second direction, and each first partition structure 210 forms a corresponding gap 500 at the position of the second partition structure 220 along the first direction.

[0079] Correspondingly, in this embodiment, the second partition structure 220 of the two partition structures is an integrated structure, and the gaps 500 corresponding to the two first partition structures 210 are all surrounded by the integrated structure.

[0080] Figures 7 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0081] Combined with reference Figure 7 and Figure 8 , Figure 8 for Figure 7 A cross-sectional view along the AA direction is provided, wherein a substrate 100 is provided, including a first direction (eg Figure 7 The first device region 100P and the second device region 100N are adjacent to each other (as shown in the Y direction), the first device region 100P is used to form a first device, and the second device region 100N is used to form a second device, and the first device and the second device are of different types.

[0082] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a fin field effect transistor (FinFET).

[0083] In this embodiment, the substrate 100 includes a first device region 100P and a second device region 100N adjacent to each other. The first device region 100P is used to form a first device, and the second device region 100N is used to form a second device. The first device and the second device are of different types.

[0084] Specifically, as an example, the first device is a PMOS transistor, and the second device is a NMOS transistor.

[0085] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0086] Continue to combine references Figure 7 and Figure 8 A protruding second partition structure 220 is formed on the substrate 100 in the second device region 100N, and the second partition structure 220 extends along the first direction.

[0087] The second isolation structure 220 is used to subsequently isolate the channel structure of the second device region 100N.

[0088] In this embodiment, the second partition structure 220 is a single diffusion break (SDB) structure, which is beneficial to reducing the contact poly pitch (CPP) of polysilicon.

[0089] In this embodiment, the material of the second partition structure 220 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the second partition structure 220 is one or more of silicon oxide, silicon nitride and silicon oxynitride that provide tensile stress.

[0090] The second partition structure 220 is formed by using one or more materials of silicon oxide, silicon nitride and silicon oxynitride that provide tensile stress, which is beneficial to improving the tensile stress of the NMOS device.

[0091] Continue to combine references Figure 7 and Figure 8 , a plurality of protruding channel structures 110 are formed on the substrate 100, and the channel structures 110 are arranged along the second direction (eg Figure 7 In the second device region 100N, the channel structure 110 is partitioned by the second partition structure 220, and the second direction is perpendicular to the first direction.

[0092] The channel structure 110 is used to provide a channel of the FinFET.

[0093] In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium or Group III-V semiconductor materials.

[0094] It should be noted that, in this embodiment, the second partition structure 220 is first formed at the partition position of the second device area 100N, and then the channel structure 110 is formed. In the second device area 100N, the channel structure 110 formed on both sides of the second partition structure 220 is correspondingly partitioned by the second partition structure 220.

[0095] In other embodiments, it is also possible to first form a channel structure, then remove part of the channel structure at the partition position of the second device region, and after removing part of the channel structure at the partition position of the second device region, form a second partition structure at that position.

[0096] Combined with reference Fig. 9 and Fig.10 , Fig.10 for Fig. 9 In the cross-sectional view along the BB direction, before the second partition structure 220 subsequently extends along the first direction to remove part of the channel structure 110 in the first device area 100N, the formation method also includes: forming a plurality of gate structures 200 across the channel structure 110, the gate structures 200 extend along the first direction and are arranged in parallel along the second direction, part of the gate structure 200 is in contact with the second partition structure 220, another part of the gate structure 200 is located on one side of the second partition structure 220, and the remaining part of the gate structure 200 is located on the other side of the second partition structure 220.

[0097] It should be noted that for the sake of clarity, Fig. 9 The dielectric layer is not shown.

[0098] The gate structure 200 is used to control the opening and closing of the channel of the transistor. In this embodiment, the gate structure 200 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0099] The gate dielectric layer is used to isolate the gate structure 200 from the channel structure 110. The material of the gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 、SiO 2 and La 2 O 3 In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O3 It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel structure. Specifically, the material of the gate oxide layer may be silicon oxide.

[0100] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0101] In this embodiment, the gate structure 200 is a metal gate structure. Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0102] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0103] In the present embodiment, part of the gate structure 200 is in contact with the second partition structure 220, another part of the gate structure 200 is located on one side of the second partition structure 220, and the remaining part of the gate structure 200 is located on the other side of the second partition structure 220, so that the gate structure 200 in contact with the second partition structure 220 is subsequently replaced with an insulating material, and a first partition structure is formed at the position of the gate structure 200 in contact with the second partition structure 220. The gate structure 200 process that is already required is used to occupy space in advance for forming the first partition structure, which is beneficial to improving process integration and reducing the difficulty of forming a partition structure.

[0104] In this embodiment, in the step of forming a plurality of gate structures 200 crossing the channel structure 110 , two gate structures 200 are in contact with the second isolation structure 220 .

[0105] In the step of forming multiple gate structures 200 across the channel structure 110, two gate structures 200 are in contact with the second partition structure 220. Accordingly, two first partition structures are subsequently formed in the first device area 100P at the positions of the two gate structures 200 in contact with the second partition structure 220, which is beneficial to enhance the isolation effect of the partition structure.

[0106] In this embodiment, in the step of forming a plurality of gate structures 200 crossing the channel structure 110 , two gate structures 200 are in contact with the same second isolation structure 200 .

[0107] In this embodiment, the first partition structure subsequently formed is a double diffusion break (DDB) structure, and the second partition structure 220 is a single diffusion break (SDB) structure. The first partition structure is obtained by replacing the gate structure 200 that is in contact with the second partition structure 220. Therefore, in the step of forming multiple gate structures 200 across the channel structure 110, two gate structures 200 are in contact with the same second partition structure 200.

[0108] In this embodiment, in the step of forming the plurality of gate structures 200 crossing the channel structure 110 , the gate structure 200 in contact with the second partition structure 220 also covers the top of the second partition structure 220 .

[0109] The gate structure 200 in contact with the second partition structure 220 occupies a spatial position for subsequently forming a gap in the second device area 100N. That is, the gate structure 200 in contact with the second partition structure 220 also covers the top of the second partition structure 220. After the gate structure 200 in contact with the second partition structure 220 is subsequently removed, a gap can be formed on the top of the second partition structure 220.

[0110] In this embodiment, in the step of forming a plurality of gate structures 200 crossing the channel structure 110 , the gate structure 200 in contact with the second partition structure 220 also covers the sidewall of the second partition structure 220 .

[0111] The gate structure 200 in contact with the second partition structure 220 also covers the top of the second partition structure 220 , and after the gate structure 200 in contact with the second partition structure 220 is subsequently removed, a gap can also be formed on the side of the second partition structure 220 .

[0112] In this embodiment, before subsequently forming the opening, the forming method further includes: forming a dielectric layer 300 covering the sidewalls of the channel structure 110 and the gate structure 200 .

[0113] The dielectric layer 300 is used to isolate adjacent devices and is also used to provide a process basis for forming the gate structure 200 .

[0114] In this embodiment, the material of the dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0115] Combined with reference Fig.11 and Fig.12 , Fig.12 for Fig.11In the cross-sectional view along the AA direction, a mask layer 400 is formed to cover the dielectric layer 300 and the top of the gate structure 200 .

[0116] The mask layer 400 is used as an etching mask for forming a partition structure, and is also used to form a gap with the second partition structure 220 later.

[0117] In this embodiment, the material of the mask layer 400 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 400 can be a single-layer structure or a stacked-layer structure. As an example, the material of the mask layer 400 is silicon oxide and silicon nitride, that is, the mask layer 400 is a multi-layer structure, including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

[0118] Combined with reference Figures 11 to 21 A first partition structure 210 in contact with the second partition structure 220 is formed at the disconnection point of the channel structure 110 in the first device region 100N. The first partition structure 210 extends along the first direction to span and penetrate multiple channel structures 110, and forms a partition structure (not marked) with the second partition structure 220. The first partition structure 210 and the second partition structure 220 are made of different materials.

[0119] The partition structure is used to partition the channel structure 110 .

[0120] In this embodiment, the partition structure of the channel structure 110 is a mixed diffusion break (MDB) structure, which is used to electrically isolate devices on both sides of the MDB structure, and is beneficial to reducing the polysilicon contact polypitch (CPP).

[0121] In the present embodiment, different materials are used as the first partition structure 210 of the first device area 100P and the second partition structure 220 of the second device area 100N, which is conducive to the flexible selection of different materials to adapt to the performance of different devices. For example, for NMOS devices, materials that increase tensile stress are used, and for PMOS devices, materials that increase compressive stress are used. This is conducive to improving the flexibility of material selection for semiconductor devices, and is conducive to the targeted selection of performance-related materials for the first device and the second device, thereby facilitating the improvement of the performance of the semiconductor structure.

[0122] In this embodiment, the material of the first partition structure 210 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the first partition structure 210 is one or more of silicon oxide, silicon nitride and silicon oxynitride that provide compressive stress.

[0123] The first partition structure 210 is formed by using one or more materials of silicon oxide, silicon nitride and silicon oxynitride that provide compressive stress, which is beneficial to improving the compressive stress of the PMOS device.

[0124] Combined with reference Figures 11 to 15 The step of extending the second partition structure 220 along the first direction to remove a portion of the channel structure 110 in the first device region 100P includes: removing the gate structure 200 in contact with the second partition structure 220 to form an opening 420 exposing a portion of the channel structure 110 in the first device region 100P.

[0125] The opening 420 is used to provide a process platform for removing the channel structure 110 at the isolation position of the first device region 100P.

[0126] Specifically, in conjunction with reference Fig.11 and Fig.12 The step of forming the opening 420 includes: patterning the mask layer 400 to form a mask opening 410 exposing the top of the gate structure 200 in contact with the second partition structure 220 .

[0127] The mask opening 410 is used to remove the exposed gate structure 200 to form an opening 420 .

[0128] Combined with reference Figures 13 to 15 , Fig.14 for Fig.13 Cross-sectional view along AA direction, Fig.15 for Fig.13 In the cross-sectional view along the BB direction, the gate structure 200 in contact with the second partition structure 220 is removed along the mask opening 410 to form an opening 420 , which also extends to the top of the second partition structure 220 .

[0129] The gate structure 200 in contact with the second partition structure 220 is removed along the mask opening 410 to expose the channel structure 110 , in preparation for removing the channel structure 110 at the partition position of the first device region 100P.

[0130] In this embodiment, the gate structure 200 in contact with the second partition structure 220 extends from the first device area 100P to the second device area 100N, covering the side walls and top of the second partition structure 220. Therefore, the opening 420 formed by removing the gate structure 200 in contact with the second partition structure 220 also extends to the top of the second partition structure 220.

[0131] In this embodiment, an isotropic etching process is used to remove the gate structure 200 in contact with the second partition structure 220 .

[0132] The use of an isotropic etching process to remove the gate structure 200 in contact with the second partition structure 220 is beneficial for completely removing the gate structure 220, especially the portion of the gate structure 200 in contact with the second partition structure 220 located in the second device area 100N. The isotropic etching process is also easy to obtain a larger etching selectivity, which is beneficial for reducing damage to the channel structure 110 in the step of removing the gate structure 200 in contact with the second partition structure 220.

[0133] Specifically, in this embodiment, an isotropic wet etching process is used to remove the gate structure 200 in contact with the second partition structure 220 .

[0134] Combined with reference Fig.16 and Fig.17 , Fig.17 for Fig.16 In the cross-sectional view along the AA direction, the channel structure 110 exposed by the opening 420 is removed, so that the channel structure 110 in the first device region 100P is disconnected.

[0135] The channel structure 110 exposed by the opening 420 is removed, so that the channel structure 110 in the first device region 100P is disconnected, in preparation for forming the first partition structure 210 .

[0136] Combined with reference Figures 18 to 21 , Fig.19 for Fig.18 Cross-sectional view along AA direction, Fig. 20 for Fig.18 Cross-sectional view along BB direction, Fig.21 for Fig.18 In the cross-sectional view along the CC direction, in the step of forming the first partition structure 210 contacting the second partition structure 220 at the disconnected portion of the channel structure 110 of the first device region 100N, the first partition structure 210 is formed in the opening 420 .

[0137] In this embodiment, the partition structure is an MDB structure. Specifically, the first partition structure 210 is a DDB structure, and the second partition structure 220 is an SDB structure. Accordingly, in this embodiment, the first partition structures 210 of the two partition structures are arranged in parallel along the second direction, and the second partition structures 220 of the two partition structures are an integrated structure.

[0138] In this embodiment, in the step of forming the first partition structure 210 in the opening 420, the first partition structure 210 penetrates the dielectric layer 300 and the mask layer 400, and the second partition structure 220, the mask layer 400 above it, the dielectric layer 300 on its upper side, and the first partition structure 210 form a gap 500.

[0139] The gap 500 and the second partition structure 220 together isolate the devices on both sides of the second partition structure 220, and the second partition structure 220, the mask layer 400 above it, the dielectric layer 300 on its upper side, and the first partition structure 210 form a gap 500, which is beneficial to reduce coupling capacitance.

[0140] In this embodiment, the first partition structure 210 penetrates the dielectric layer 300 and the mask layer 400. After the gate structure 200 is formed at the partition position, the gate structure 200 at the position is removed, and an opening 420 is formed using the mask layer 400 as a mask. The first partition structure 210 is formed at the position of the opening 420 in the first device area 100P. Therefore, the first partition structure 210 penetrates the dielectric layer 300 and the mask layer 400. Moreover, the first partition structure 210 penetrates the mask layer 400 to seal the gap 500 above the second partition structure 220, thereby enclosing the gap 500 with the second partition structure 220, the mask layer 400 and the dielectric layer 300.

[0141] In this embodiment, the gate structure 200 in contact with the second partition structure 220 also covers the side wall of the second partition structure 220. Therefore, in the step of forming the first partition structure 210 in the opening 420, the gap 500 also extends to the side of the second partition structure 220 and is surrounded by the second partition structure 220 and the dielectric layer 300 on its side.

[0142] In this embodiment, there are multiple gate structures 200 in contact with the second partition structure 220. In the step of forming the first partition structure 210 in the opening 420, each first partition structure 210 encloses a gap 500 corresponding to the position of the second partition structure 220 along the first direction.

[0143] In this embodiment, the first partition structure 210 is a DDB structure, and the second partition structure 220 is an SDB structure. The first partition structure 210 extends along the second direction to the corresponding position of the second partition structure 220, which is the position of the gap 500. The first partition structure 210 is a DDB structure, and two gaps 500 are formed at the corresponding position. Therefore, in this embodiment, in the step of forming the first partition structure 210 in the opening 420, the gaps 500 corresponding to the two first partition structures 210 are all surrounded by the same second partition structure 220.

[0144] In this embodiment, the first partition structure 210 is formed in the opening 420 by using a chemical vapor deposition process.

[0145] The performance of the chemical vapor deposition process in filling the gap is not too strong, so that in the process of forming the first partition structure 210 in the opening 420, the first partition structure 210 will not be filled into the gap 500 as much as possible, so that the gap 500 has enough space.

[0146] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a first device region and a second device region adjacent to each other along a first direction, a plurality of protruding channel structures formed on the substrate, the channel structures extending along the second direction and arranged in parallel along the first direction, the first device region being used to form a first device, the second device region being used to form a second device, the first device and the second device being of different types, and the first direction being perpendicular to the second direction; A partition structure extends along the first direction to cross and penetrate the plurality of channel structures. The partition structure includes a first partition structure located in the first device region and a second partition structure located in the second device region. The first partition structure and the second partition structure are made of different materials.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a plurality of gate structures spanning the channel structure, the gate structures extending along the first direction and arranged in parallel along the second direction, a portion of the gate structures being located on one side of the partition structure, and a remaining portion of the gate structures being located on the other side of the partition structure; Along the second direction, at least the first partition structure among the partition structures has the same width as the gate structure.

3. The semiconductor structure according to claim 2, wherein: Two partition structures are formed between adjacent portions of the gate structure and the remaining portions of the gate structure.

4. The semiconductor structure according to claim 3, characterized in that The first partition structures of the two partition structures are arranged in parallel along the second direction, and the second partition structures of the two partition structures are an integrated structure.

5. The semiconductor structure according to claim 2 or 3, characterized in that: The semiconductor structure further includes: a dielectric layer located on the substrate and covering the sidewalls of the channel structure and the gate structure; A mask layer covering the dielectric layer and the gate structure; The first partition structure penetrates the dielectric layer and the mask layer; The top of the second partition structure is lower than the top of the dielectric layer, and the second partition structure, the mask layer above it, the dielectric layer on the upper side thereof, and the first partition structure form a gap.

6. The semiconductor structure according to claim 5, characterized in that The gap also extends to the side of the second partition structure and is surrounded by the second partition structure and the dielectric layer on the side thereof.

7. The semiconductor structure according to claim 5, characterized in that Along the second direction, the gap formed by the second partition structure, the mask layer above it, and the dielectric layer on the upper side thereof is equal to the width of the gate structure.

8. The semiconductor structure according to claim 5, characterized in that Two partition structures are formed between adjacent portions of the gate structure and the remaining portions of the gate structure, the first partition structures of the two partition structures are arranged in parallel along the second direction, and each of the first partition structures encloses a corresponding gap at the position of the second partition structure along the first direction.

9. The semiconductor structure according to claim 8, characterized in that The second partition structure of the two partition structures is an integrated structure, and the gaps corresponding to the two first partition structures are both surrounded by the integrated structure.

10. The semiconductor structure according to claim 1, wherein: The material of the first partition structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride; the material of the second partition structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a first device region and a second device region adjacent to each other along a first direction, wherein the first device region is used to form a first device, and the second device region is used to form a second device, and the first device and the second device are of different types; forming a protruding second partition structure on the substrate in the second device region, wherein the second partition structure extends along the first direction; forming a plurality of protruding channel structures on the substrate, wherein the channel structures extend along a second direction and are arranged in parallel along the first direction, and in the second device region, the channel structures are partitioned by the second partition structures, and the second direction is perpendicular to the first direction; The second partition structure extends along the first direction to remove a portion of the channel structure in the first device region, so that the channel structure in the first device region is disconnected; A first partition structure in contact with the second partition structure is formed at the disconnection point of the channel structure in the first device region. The first partition structure extends along the first direction, spans and penetrates multiple channel structures, and forms a partition structure with the second partition structure. The first partition structure and the second partition structure are made of different materials.

12. The method for forming a semiconductor structure according to claim 11, wherein: Before the second partition structure extends along the first direction to remove part of the channel structure in the first device region, the forming method further includes: forming a plurality of gate structures across the channel structure, the gate structures extending along the first direction and arranged in parallel along the second direction, part of the gate structures contacting the second partition structure, another part of the gate structures being located on one side of the second partition structure, and the remaining part of the gate structures being located on the other side of the second partition structure; The step of extending the second partition structure along the first direction to remove a portion of the channel structure in the first device region includes: removing the gate structure in contact with the second partition structure to form an opening exposing a portion of the channel structure in the first device region; removing the channel structure exposed by the opening, so that the channel structure in the first device region is disconnected; In the step of forming a first partition structure in contact with the second partition structure at a location where the channel structure of the first device region is disconnected, the first partition structure is formed in the opening.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming a plurality of gate structures spanning the channel structure, two of the gate structures are in contact with the second isolation structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a plurality of gate structures spanning the channel structure, two of the gate structures are in contact with the same second isolation structure.

15. The method for forming a semiconductor structure according to claim 12 or 13, characterized in that: In the step of forming a plurality of gate structures spanning the channel structure, the gate structure in contact with the second partition structure also covers the top of the second partition structure; Before forming the opening, the forming method further comprises: forming a dielectric layer covering the sidewalls of the channel structure and the gate structure; forming a mask layer covering the dielectric layer and the top of the gate structure; The step of forming the opening includes: patterning the mask layer to form a mask opening exposing the top of the gate structure in contact with the second partition structure; Removing the gate structure in contact with the second partition structure along the mask opening to form the opening, wherein the opening also extends to the top of the second partition structure; In the step of forming the first partition structure in the opening, the first partition structure penetrates the dielectric layer and the mask layer, and the second partition structure, the mask layer above it, the dielectric layer above and on its side, and the first partition structure form a gap.

16. The method for forming a semiconductor structure according to claim 15, wherein: An isotropic etching process is used to remove the gate structure in contact with the second partition structure.

17. The method for forming a semiconductor structure according to claim 15, wherein: The first partition structure is formed in the opening by using a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 15, wherein: In the step of forming a plurality of gate structures spanning the channel structure, the gate structure in contact with the second partition structure also covers the sidewall of the second partition structure; In the step of forming the first partition structure in the opening, the gap also extends to the side of the second partition structure and is surrounded by the second partition structure and the dielectric layer on the side thereof.

19. The method for forming a semiconductor structure according to claim 15, wherein: In the step of forming a plurality of gate structures across the channel structure, two of the gate structures are in contact with the second isolation structure; In the step of forming the first partition structures in the opening, each of the first partition structures correspondingly encloses a gap at the position of the second partition structure along the first direction.

20. The method for forming a semiconductor structure according to claim 19, wherein: In the step of forming a plurality of gate structures across the channel structure, two of the gate structure items are in contact with the same second partition structure; In the step of forming the first partition structure in the opening, the gaps corresponding to the two first partition structures are both surrounded by the same second partition structure.

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