Passivated contact solar cell and method of making same

Abstract

The invention relates to the technical field of solar cells, in particular to a passivation contact solar cell and a preparation method thereof. The passivation contact solar cell comprises a tunneling oxide layer and multiple polycrystalline silicon layers which are sequentially located on one side of a silicon substrate, the multiple polycrystalline silicon layers sequentially comprise the first polycrystalline silicon layer,..., the Mth polycrystalline silicon layer in the direction away from the tunneling oxide layer, and M is an integer larger than or equal to 2; and the thickness of the first polycrystalline silicon layer is greater than the thickness of each of the other polycrystalline silicon layers. According to the passivation contact solar cell, the polycrystalline silicon layers of a multi-layer structure are arranged, the difference between the polycrystalline silicon layers is beneficial for reducing the situation that doping elements penetrate through silicon oxide to enter the silicon substrate, meanwhile, the phenomenon of film explosion is reduced, and the conversion efficiency of the passivation cell is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a passivated contact solar cell and a preparation method thereof. Background Art

[0002] The photovoltaic industry's demand for high-efficiency cells has driven the continuous development of different technologies, such as a solar cell based on passivation contact technology. The tunneling oxide layer and polysilicon layer that make up this type of cell structure will affect the passivation contact effect, and only when the two structures are better matched together can the ideal passivation effect be achieved. Studies have shown that there is a pinhole structure in silicon oxide, which plays an auxiliary role in carrier transport, and even plays a leading role when the pinhole density is high. In addition to the pinhole structure, there is a sub-nanometer pit on the surface of silicon oxide. These sub-nanometer pits provide excellent surface passivation and efficient tunneling effect for most carriers. The polysilicon layer plays a role in selective carrier transport, effectively transporting carriers of one polarity (electrons or holes), while protecting the substrate silicon wafer from direct contact with the metal electrode, reducing the chance of carrier recombination, and improving the open circuit voltage and fill factor of the battery. Therefore, the combined action of silicon oxide and polysilicon forms a passivation contact structure as the back passivation layer of the battery, effectively reducing surface recombination and metal contact recombination.

[0003] However, the high-performance passivation contact solar cell structure requires that the doping concentration and annealing temperature can be reasonably controlled during the polysilicon formation process. Otherwise, excessive doping concentration and annealing temperature will cause the doping elements to pass through the polysilicon layer, or even tunnel through the oxide layer, thereby destroying the passivation effect. In addition, the penetration of the doping elements into the tunneling oxide layer destroys the distribution of the pinhole density, thereby affecting the tunneling of the majority carriers and the electrical performance of the cell. Therefore, the current mass production line of tunneling oxidation cells increases the thickness of polysilicon to about 100nm to avoid the penetration of doping elements in silicon oxide during the annealing process. However, an overly thick polysilicon layer not only increases the defect density and the composite density, but also increases the parasitic absorption.

[0004] At present, there are two main ways to prepare polysilicon film layers, namely: low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition. Compared with the above two methods, plasma-enhanced chemical vapor deposition is more easily accepted due to its production capacity advantage. In plasma-enhanced chemical vapor deposition, silane SiH4 decomposes to produce Si under ionization and produces hydrogen atoms that can achieve passivation. Due to the effect of temperature, hydrogen easily overflows and accumulates at the interface between the polysilicon layer and SiO2, which is the phenomenon of film explosion; film explosion may cause uneven film layer, increase in lateral transmission channels, and even film layer shedding, seriously affecting battery efficiency.

[0005] Therefore, it is a technical problem in the art to provide a passivated contact solar cell that can reduce the influence of doping elements on the tunneling oxide layer and reduce the occurrence of film explosion phenomenon. Summary of the invention

[0006] In order to solve the above technical problems, the present invention introduces different film layer structures to reduce the influence of doping elements on the tunneling oxide layer, reduce the occurrence of film explosion phenomenon, and further improve the electrical performance of the passivated contact solar cell.

[0007] The present invention adopts the following technical solutions:

[0008] A passivated contact solar cell comprises a tunneling oxide layer and a plurality of polysilicon layers sequentially located on one side of a silicon substrate, wherein the plurality of polysilicon layers sequentially comprise a first polysilicon layer, ..., an Mth polysilicon layer in a direction away from the tunneling oxide layer, wherein M is an integer greater than or equal to 2; and the thickness of the first polysilicon layer is greater than the thickness of the polysilicon layers of the other layers.

[0009] Furthermore, at least one layer of intrinsic microcrystalline silicon layer is included between the first polycrystalline silicon layer and the Mth polycrystalline silicon layer.

[0010] Furthermore, at least one intrinsic microcrystalline silicon layer is included between the tunnel oxide layer and the first polysilicon layer.

[0011] Furthermore, at least one intrinsic microcrystalline silicon layer is included between the tunneling oxide layer and the first polycrystalline silicon layer; and at least one intrinsic microcrystalline silicon layer is included between the first polycrystalline silicon layer and the Mth polycrystalline silicon layer.

[0012] The present invention also provides a method for preparing a passivated contact solar cell, which comprises the following steps in sequence:

[0013] (1) Preparing a silicon substrate;

[0014] (2) preparing a tunneling oxide layer on one side of the silicon substrate;

[0015] (3) depositing a first polysilicon layer, ..., an Mth polysilicon layer in sequence on the tunnel oxide layer, wherein M is an integer greater than or equal to 2; and the deposition thickness of the first polysilicon layer is greater than the deposition thickness of the other polysilicon layers.

[0016] Furthermore, after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

[0017] Furthermore, before depositing the first polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

[0018] Furthermore, before depositing the first polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer; after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

[0019] Furthermore, during the deposition of the first polysilicon layer, the temperature is 425-460° C., the silane flow rate range is 2000-2500 sccm, the hydrogen flow rate range is 5000-7000 sccm, the deposition time is 350-450 s, and the deposition thickness of the first polysilicon layer is 60-80 nm.

[0020] Furthermore, during the deposition of the intrinsic microcrystalline silicon layer, the temperature is 325-400° C., the silane flow rate range is 2000-2500 sccm, the hydrogen flow rate range is 15000-20000 sccm, and the deposition time is 30-50 s.

[0021] The present invention has the following beneficial effects:

[0022] (1) The passivated contact solar cell of the present invention is provided with a polysilicon layer having a multi-layer structure. The differentiation between the polysilicon layers helps to reduce the penetration of doping elements into the silicon substrate through the oxide layer, while reducing the occurrence of film explosion, thereby further improving the conversion efficiency of the passivated cell.

[0023] (2) The present invention further adds an intrinsic microcrystalline silicon layer between the polycrystalline silicon layers and / or between the polycrystalline silicon layer and the oxide layer. Microcrystalline silicon has high electron mobility and good light transmittance, which can help to further increase the current density and improve the electrical performance of the battery. DETAILED DESCRIPTION

[0024] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0025] Academic research shows that within a certain thickness range, the thickness of the polysilicon layer has little effect on the recombination. However, as the thickness of the polysilicon layer increases, the inflection point of the doping concentration gradually becomes deeper, the depth of doping into the silicon substrate increases, and the Auger recombination increases. In addition, as the thickness of the polysilicon film increases, the hydrogen concentration increases, and the possibility of film explosion during annealing increases.

[0026] In order to change the physical and chemical disadvantages brought by the existing film layer structure and comprehensively consider the influence of polysilicon thickness, doping concentration, etc., the present invention provides a passivated contact solar cell, including a tunneling oxide layer and a multi-layer polysilicon layer sequentially located on one side of a silicon substrate, the multi-layer polysilicon layer sequentially including a first polysilicon layer, ..., an Nth polysilicon layer, wherein N is an integer greater than or equal to 2; the thickness of the first polysilicon layer is greater than the thickness of the polysilicon layers of other layers.

[0027] The passivated contact solar cell of the present invention is provided with a polysilicon layer having a multi-layer structure. The thickness, refractive index and annealing temperature of each layer are different to ensure the passivation and carrier transmission, so as to reduce the penetration of doping elements into the silicon substrate through the oxide layer, and reduce the occurrence of film explosion, thereby further improving the conversion efficiency of the passivated cell. The thickness of the first polysilicon layer is greater than the thickness of the polysilicon layers of the other layers, and the first polysilicon layer acts as a barrier layer to prevent doping elements from entering the interior of the silicon wafer.

[0028] Specifically, as an embodiment of the present invention, at least one intrinsic microcrystalline silicon layer is further included between the first polycrystalline silicon layer and the Nth polycrystalline silicon layer.

[0029] Specifically, as an implementation mode of the present invention, at least one intrinsic microcrystalline silicon layer is further included between the tunneling oxide layer and the first polysilicon layer.

[0030] Specifically, as an embodiment of the present invention, at least one intrinsic microcrystalline silicon layer is included between the tunneling oxide layer and the first polysilicon layer, and at least one intrinsic microcrystalline silicon layer is included between the first polysilicon layer and the Nth polysilicon layer.

[0031] The present invention also adds an intrinsic microcrystalline silicon layer between the multi-layer polysilicon layers and between the polysilicon layer and the oxide layer. The microcrystalline silicon has high electron mobility and good light transmittance, which can help to further increase the current density and improve the battery electrical performance. At the same time, considering the parasitic absorption caused by microcrystalline silicon and the light loss caused by light transmittance, the microcrystalline silicon layer is set between the multi-layer polysilicon layers or between the polysilicon layer and the oxide layer, rather than the outermost structure.

[0032] Specifically, as an embodiment of the present invention, the overall thickness of the multi-layer polysilicon layer is not specifically limited; however, if it is too thick, the cost will be too high, and the process time will be relatively long, and the film layer itself has many defects and absorbs light strongly. Therefore, based on the actual two-field requirements of the production line and cost and other factors, the total thickness of the polysilicon layer is less than 100nm. At the same time, for the thickness of each layer of polysilicon layer, under the premise that the thickness of the first polysilicon layer is the largest, the thickness of other layers is not specifically limited, and the thickness of other layers may be the same or different. More specifically, as an embodiment of the present invention, the thickness of the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, ..., the Mth polysilicon layer gradually decreases; or, the thickness of the second polysilicon layer, the third polysilicon layer, ..., the Mth polysilicon layer gradually increases.

[0033] Specifically, as an embodiment of the present invention, the solar cell includes a tunneling oxide layer, a first polysilicon layer, and a second polysilicon layer, which are sequentially located on one side of a silicon substrate; the thickness of the first polysilicon layer is 60-80nm, and the thickness of the second polysilicon layer is 10-30nm.

[0034] Specifically, as an embodiment of the present invention, a passivated contact solar cell includes a silicon substrate, wherein the front side of the silicon substrate is provided with a p+ emitter, an aluminum oxide dielectric layer, a front anti-reflection layer, and a front conductive metal electrode in sequence from the inside to the outside, and the back side is provided with a tunneling oxide layer, a doped polysilicon layer, a back anti-reflection layer, and a back conductive metal electrode in sequence from the inside to the outside. The back conductive metal electrode penetrates the back anti-reflection layer and contacts the doped polysilicon layer, and the front conductive metal electrode penetrates the front anti-reflection layer and contacts the aluminum oxide dielectric layer.

[0035] The doped polysilicon layer is obtained by doping the polysilicon layer with elements; if the silicon substrate is an N-type silicon substrate, the doped polysilicon layer is phosphorus-doped polysilicon; if the silicon substrate is a P-type silicon substrate, the doped polysilicon layer is boron-doped polysilicon. The front anti-reflection layer and the back anti-reflection layer are one or more combinations of SiNx, SiOxNy, and SiOx.

[0036] The polysilicon layer includes a first polysilicon layer, ..., an Mth polysilicon layer in sequence, wherein M is an integer greater than or equal to 2; the thickness of the first polysilicon layer is greater than the thickness of the polysilicon layers of other layers. As an embodiment of the present invention, after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, it also includes depositing at least one layer of intrinsic microcrystalline silicon layer; or, before depositing the first polysilicon layer, it also includes depositing at least one layer of intrinsic microcrystalline silicon layer; or, before depositing the first polysilicon layer, it also includes depositing at least one layer of intrinsic microcrystalline silicon layer, and after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, it also includes depositing at least one layer of intrinsic microcrystalline silicon layer.

[0037] Specifically, as the first embodiment of the present invention, the passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, and a second polysilicon layer sequentially located on one side of a silicon substrate;

[0038] As a second embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer sequentially located on one side of a silicon substrate;

[0039] As a third embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, and a fourth polysilicon layer sequentially located on one side of a silicon substrate;

[0040] As a fourth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, a fourth polysilicon layer, and a fifth polysilicon layer sequentially located on one side of a silicon substrate;

[0041] As a fifth embodiment of the present invention, a passivated contact solar cell comprises a tunneling oxide layer, a first polysilicon layer, an intrinsic microcrystalline silicon layer, and a second polysilicon layer sequentially located on one side of a silicon substrate;

[0042] As a sixth embodiment of the present invention, a passivated contact solar cell comprises a tunneling oxide layer, a first polysilicon layer, an intrinsic microcrystalline silicon layer, a second polysilicon layer, and a third polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0043] As a seventh embodiment of the present invention, a passivated contact solar cell comprises a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, an intrinsic microcrystalline silicon layer, and a third polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0044] As an eighth embodiment of the present invention, a passivated contact solar cell comprises a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, a first intrinsic microcrystalline silicon layer, a second intrinsic microcrystalline silicon layer, and a third polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0045] As a ninth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, an intrinsic microcrystalline silicon layer, a second polysilicon layer, a third polysilicon layer, and a fourth polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0046] As a tenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, a first intrinsic microcrystalline silicon layer, a second polysilicon layer, a second intrinsic microcrystalline silicon layer, a third polysilicon layer, and a fourth polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0047] As an eleventh embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, an intrinsic microcrystalline silicon layer, a third polysilicon layer, and a fourth polysilicon layer sequentially located on one side of a silicon substrate;

[0048] As a twelfth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, an intrinsic microcrystalline silicon layer, and a fourth polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0049] As a thirteenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, an intrinsic microcrystalline silicon layer, a first polycrystalline silicon layer, and a second polycrystalline silicon layer sequentially located on one side of a silicon substrate;

[0050] As a fourteenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first intrinsic microcrystalline silicon layer, a second intrinsic microcrystalline silicon layer, a first polycrystalline silicon layer, and a second polycrystalline silicon layer, which are sequentially located on one side of a silicon substrate;

[0051] As a fifteenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, an intrinsic microcrystalline silicon layer, a first polycrystalline silicon layer, a second polycrystalline silicon layer, and a third polycrystalline silicon layer, which are sequentially located on one side of a silicon substrate;

[0052] As a sixteenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, an intrinsic microcrystalline silicon layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, and a fourth polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0053] As a seventeenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, an intrinsic microcrystalline silicon layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, a fourth polysilicon layer, and a fifth polysilicon layer, which are sequentially located on one side of a silicon substrate;

[0054] As an eighteenth embodiment of the present invention, a passivated contact solar cell includes a tunneling oxide layer, a first intrinsic microcrystalline silicon layer, a first polycrystalline silicon layer, a second intrinsic microcrystalline silicon layer, a second polycrystalline silicon layer, and a third polycrystalline silicon layer, which are sequentially located on one side of a silicon substrate.

[0055] It should be noted that the above implementation modes are merely listed rather than exhaustive, and it does not mean that the present invention only includes the above implementation modes. Any other modifications made according to the limitations of the present invention belong to the protection scope of the present invention.

[0056] The present invention also provides a method for preparing a passivated contact solar cell, comprising the following steps:

[0057] (1) Preparing a silicon substrate;

[0058] (2) preparing a tunneling oxide layer on one side of the silicon substrate;

[0059] (3) depositing a first polysilicon layer, ..., an Mth polysilicon layer in sequence on the tunnel oxide layer, wherein M is an integer greater than or equal to 2; and the deposition thickness of the first polysilicon layer is greater than the deposition thickness of the other polysilicon layers.

[0060] Specifically, as an embodiment of the present invention, after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, it also includes depositing at least one intrinsic microcrystalline silicon layer.

[0061] Specifically, as an embodiment of the present invention, before depositing the first polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

[0062] Specifically, as an embodiment of the present invention, before depositing the first polysilicon layer, it also includes depositing at least one layer of intrinsic microcrystalline silicon layer; and after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, it also includes depositing at least one layer of intrinsic microcrystalline silicon layer.

[0063] Specifically, as an embodiment of the present invention, during the deposition process of the first polysilicon layer, the temperature is 425-460°C, the silane flow rate range is 2000-2500sccm, the hydrogen flow rate range is 5000-7000sccm, the deposition time is 350-450s, and the deposition thickness of the first polysilicon layer is 60-80nm, forming a polysilicon layer with a relatively low hydrogen content, which can also meet the doping concentration requirements and contact requirements.

[0064] Specifically, as an embodiment of the present invention, during the deposition process of the second polysilicon layer, the temperature is 425-460°C, the silane flow rate range is 2500-3300sccm, the hydrogen flow rate range is 8000-10000sccm, the deposition time is 50-100s, and the thickness of the second polysilicon layer is 10-30nm, forming a polysilicon layer with good density and high hydrogen content.

[0065] Specifically, as an embodiment of the present invention, during the deposition of the intrinsic microcrystalline silicon layer, the temperature is 325-400°C, the silane flow rate is in the range of 2000-2500sccm, the hydrogen flow rate is in the range of 15000-20000sccm, the deposition time is 30-50s, and the thickness of the intrinsic microcrystalline silicon layer is 5-10nm. The hydrogen-rich microcrystalline silicon layer can meet the requirements of hydrogen passivation and light transmission, will not hinder the lateral transmission of majority carriers, and can reduce the diffusion of doping elements toward the silicon substrate to a certain extent.

[0066] Specifically, as an embodiment of the present invention, the method for preparing the passivated contact solar cell comprises the following steps:

[0067] (1) Texturing, boron diffusion, and laser doping to form a selective emitter;

[0068] (2) preparing a tunnel oxide layer on the back side of a silicon substrate, and sequentially depositing a first polysilicon layer, ..., an Mth polysilicon layer on the tunnel oxide layer, wherein M is an integer greater than or equal to 2; the deposition thickness of the first polysilicon layer is greater than the deposition thickness of the other polysilicon layers; and preparing a doped polysilicon layer by phosphorus diffusion or boron diffusion;

[0069] (3) Prepare anti-reflection layer and conductive metal electrode.

[0070] More specifically, as an embodiment of the present invention, the method for preparing the passivated contact solar cell comprises the following steps:

[0071] 1) Texturing: using acid and alkali chemicals to remove organic contamination and metal impurities on the surface of N-type single crystal silicon wafers, forming a surface pyramid structure on the front of the silicon substrate;

[0072] 2) Boron diffusion and laser doping form a selective emitter. BCl3 or BBr3 is used as a boron source to form a borosilicate glass film on the front of the silicon substrate. A continuous laser is used to dope the metal contact area on the surface of the silicon substrate. The laser-doped silicon substrate is subjected to high-temperature annealing to form a p+ emitter after oxidation annealing.

[0073] 3) Single-sided HF etching to remove the back BSG; using the front BSG as a barrier layer, an alkaline solution is used to etch and remove the back-side doping layer;

[0074] 4) first depositing a tunnel oxide layer by an LPCVD process, and then sequentially depositing a first polysilicon layer, ..., an Mth polysilicon layer on the tunnel oxide layer, wherein M is an integer greater than or equal to 2; and the deposition thickness of the first polysilicon layer is greater than the deposition thickness of the other polysilicon layers;

[0075] 5) Phosphorus diffusion, using POCl3 as the diffusion source, to dope the polysilicon layer with n-type phosphorus to form a back-doped polysilicon layer;

[0076] 6) Single-sided HF etching to remove the PSG on the surface of the front polysilicon layer after diffusion; alkaline solution etching to remove the polysilicon layer on the front PSG surface, and hydrofluoric acid cleaning to remove the BSG on the front and the PSG on the back;

[0077] 7) Using ALD atomic layer deposition method, an aluminum oxide dielectric layer is deposited on the front side; using tubular or plate PECVD to deposit an anti-reflection layer on the front and back sides of the silicon wafer;

[0078] 8) Printing Ag paste for the front electrode and Ag paste for the back electrode, co-sintering to form a good ohmic contact, and obtaining a front conductive metal electrode and a back conductive metal electrode; light injection to repair defects inside and on the surface of the battery.

[0079] Specifically, as an embodiment of the present invention, after depositing the first polysilicon layer and before depositing the Nth polysilicon layer, at least one layer of intrinsic microcrystalline silicon layer is also deposited; or, before depositing the first polysilicon layer, at least one layer of intrinsic microcrystalline silicon layer is also deposited; or, before depositing the first polysilicon layer, at least one layer of intrinsic microcrystalline silicon layer is deposited, and after depositing the first polysilicon layer and before depositing the Mth polysilicon layer, at least one layer of intrinsic microcrystalline silicon layer is also deposited.

[0080] The present invention will be further described below with reference to specific embodiments.

[0081] Example 1

[0082] A passivated contact solar cell comprises an N-type silicon substrate, wherein the front side of the silicon substrate is provided with a p+ emitter, an aluminum oxide dielectric layer, a front anti-reflection layer and a front conductive metal electrode in sequence from the inside to the outside, and the back side is provided with a tunneling oxide layer, a doped polysilicon layer, a back anti-reflection layer and a back conductive metal electrode in sequence from the inside to the outside. The back conductive metal electrode penetrates the back anti-reflection layer and contacts the doped polysilicon layer, and the front conductive metal electrode penetrates the front anti-reflection layer and contacts the aluminum oxide dielectric layer.

[0083] The doped polysilicon layer is obtained by doping the polysilicon layer with phosphorus; the polysilicon layer includes a first polysilicon layer and a second polysilicon layer in sequence.

[0084] The method for preparing a passivated contact solar cell in this embodiment includes the following steps:

[0085] 1) Texturing: using acid and alkali chemicals to remove organic contamination and metal impurities on the surface of N-type single crystal silicon wafers, forming a surface pyramid texture on the front side of the silicon substrate;

[0086] 2) Boron diffusion and laser doping form a selective emitter, using BCl3 as a boron source, a diffusion temperature of 1000°C, a diffusion square resistance of 200Ω / sq, forming a borosilicate glass film on the front of the silicon substrate, and using a continuous laser to dope the metal contact area on the surface of the silicon substrate. The laser-doped silicon substrate is subjected to high-temperature annealing, and a p+ emitter is formed after oxidation annealing;

[0087] 3) Single-sided HF etching to remove the back BSG; using the front BSG as a barrier layer, an alkaline solution is used to etch and remove the back-side diffusion doping layer;

[0088] 4) using the LPCVD process to first deposit a tunnel oxide layer, in an LPCVD furnace tube, using O2 as an oxidant, the oxidation temperature is 600° C., and an in-situ oxidation growth tunnel oxide layer is performed on the back of the silicon wafer; then a first polysilicon layer and a second polysilicon layer are sequentially deposited on the tunnel oxide layer;

[0089] 5) Phosphorus diffusion, using POCl3 as the diffusion source, to dope the intrinsic polysilicon layer with n-type phosphorus to form a back-doped polysilicon layer;

[0090] 6) Single-sided HF etching to remove the PSG on the surface of the front polysilicon layer after diffusion; alkaline solution etching to remove the polysilicon layer on the front PSG surface, and hydrofluoric acid cleaning to remove the BSG on the front and the PSG on the back;

[0091] 7) Using ALD atomic layer deposition method, TMA as precursor, H2O as oxidant, and reaction temperature controlled at 300°C, an aluminum oxide dielectric layer is deposited on the front side; using tubular or plate PECVD to deposit an anti-reflection layer on the front and back sides of the silicon wafer;

[0092] 8) Printing Ag paste for the front electrode and Ag paste for the back electrode, co-sintering to form a good ohmic contact, and obtaining a front conductive metal electrode and a back conductive metal electrode; light injection to repair defects inside and on the surface of the battery.

[0093] The deposition method of the polysilicon layer is as follows:

[0094] During the deposition of the first polysilicon layer, the temperature was 450° C., the silane flow rate range was 2200 sccm, the hydrogen flow rate range was 6000 sccm, the deposition time was 400 s, and the deposition thickness of the first polysilicon layer was 70 nm.

[0095] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0096] Example 2

[0097] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0098] The polysilicon layer includes a first polysilicon layer and a second polysilicon layer in sequence.

[0099] The deposition method of the polysilicon layer is as follows:

[0100] During the deposition of the first polysilicon layer, the temperature was 460° C., the silane flow rate range was 2500 sccm, the hydrogen flow rate range was 7000 sccm, the deposition time was 450 s, and the deposition thickness of the first polysilicon layer was 80 nm.

[0101] During the deposition of the second polysilicon layer, the temperature was 460° C., the silane flow rate range was 2500 sccm, the hydrogen flow rate range was 8000 sccm, the deposition time was 50 s, and the thickness of the second polysilicon layer was 10 nm.

[0102] Example 3

[0103] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0104] The polysilicon layer includes a first polysilicon layer and a second polysilicon layer in sequence.

[0105] The deposition method of the polysilicon layer is as follows:

[0106] During the deposition of the first polysilicon layer, the temperature was 425° C., the silane flow rate range was 2000 sccm, the hydrogen flow rate range was 5000 sccm, the deposition time was 350 s, and the deposition thickness of the first polysilicon layer was 60 nm.

[0107] During the deposition of the second polysilicon layer, the temperature was 425° C., the silane flow rate range was 3300 sccm, the hydrogen flow rate range was 10000 sccm, the deposition time was 100 s, and the thickness of the second polysilicon layer was 30 nm.

[0108] Example 4

[0109] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0110] The polysilicon layer includes a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer in sequence.

[0111] The deposition method of the polysilicon layer is as follows:

[0112] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2000 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 60 nm.

[0113] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0114] During the deposition of the third polysilicon layer, the temperature was 450° C., the silane flow rate range was 2500 sccm, the hydrogen flow rate range was 8000 sccm, the deposition time was 50 s, and the thickness of the second polysilicon layer was 10 nm.

[0115] Example 5

[0116] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0117] The polysilicon layer includes a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer in sequence.

[0118] The deposition method of the polysilicon layer is as follows:

[0119] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2000 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 60 nm.

[0120] During the deposition of the second polysilicon layer, the temperature was 450° C., the silane flow rate range was 2500 sccm, the hydrogen flow rate range was 8000 sccm, the deposition time was 50 s, and the thickness of the second polysilicon layer was 10 nm.

[0121] During the deposition of the third polysilicon layer, the temperature was 450° C., the silane flow rate range was 3000 sccm, the hydrogen flow rate range was 9000 sccm, the deposition time was 75 s, and the thickness of the second polysilicon layer was 20 nm.

[0122] Example 6

[0123] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0124] The polysilicon layer includes a first polysilicon layer, an intrinsic microcrystalline silicon layer, and a second polysilicon layer in sequence.

[0125] The deposition method of the polysilicon layer is as follows:

[0126] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0127] During the deposition of the intrinsic microcrystalline silicon layer, the temperature was 325° C., the silane flow rate range was 2000 sccm, the hydrogen flow rate range was 15000 sccm, the deposition time was 30 s, and the deposition thickness of the intrinsic microcrystalline silicon layer was 5 nm.

[0128] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0129] Example 7

[0130] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0131] The polysilicon layer includes a first polysilicon layer, an intrinsic microcrystalline silicon layer, and a second polysilicon layer in sequence.

[0132] The deposition method of the polysilicon layer is as follows:

[0133] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0134] During the deposition of the intrinsic microcrystalline silicon layer, the temperature is 400° C., the silane flow rate range is 2500 sccm, the hydrogen flow rate range is 20000 sccm, the deposition time is 50 s, and the deposition thickness of the intrinsic microcrystalline silicon layer is 10 nm.

[0135] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0136] Example 8

[0137] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0138] The polysilicon layer includes a first polysilicon layer, an intrinsic microcrystalline silicon layer, and a second polysilicon layer in sequence.

[0139] The deposition method of the polysilicon layer is as follows:

[0140] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0141] During the deposition of the intrinsic microcrystalline silicon layer, the temperature is 350° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 18000 sccm, the deposition time is 40 s, and the deposition thickness of the intrinsic microcrystalline silicon layer is 8 nm.

[0142] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0143] Example 9

[0144] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0145] The polysilicon layer includes a first polysilicon layer, a second polysilicon layer, an intrinsic microcrystalline silicon layer, and a third polysilicon layer in sequence.

[0146] The deposition method of the polysilicon layer is as follows:

[0147] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0148] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0149] During the deposition of the intrinsic microcrystalline silicon layer, the temperature is 350° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 18000 sccm, the deposition time is 40 s, and the deposition thickness of the intrinsic microcrystalline silicon layer is 8 nm.

[0150] During the deposition of the third polysilicon layer, the temperature was 450° C., the silane flow rate range was 2500 sccm, the hydrogen flow rate range was 8000 sccm, the deposition time was 50 s, and the thickness of the second polysilicon layer was 10 nm.

[0151] Example 10

[0152] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0153] The polysilicon layer includes an intrinsic microcrystalline silicon layer, a first polysilicon layer, and a second polysilicon layer in sequence.

[0154] The deposition method of the polysilicon layer is as follows:

[0155] During the deposition of the intrinsic microcrystalline silicon layer, the temperature is 350° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 18000 sccm, the deposition time is 40 s, and the deposition thickness of the intrinsic microcrystalline silicon layer is 8 nm.

[0156] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0157] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0158] Embodiment 11

[0159] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0160] The polysilicon layer includes a first polysilicon layer, a second polysilicon layer, and an intrinsic microcrystalline silicon layer in sequence.

[0161] The deposition method of the polysilicon layer is as follows:

[0162] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0163] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0164] During the deposition of the intrinsic microcrystalline silicon layer, the temperature is 350° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 18000 sccm, the deposition time is 40 s, and the deposition thickness of the intrinsic microcrystalline silicon layer is 8 nm.

[0165] Example 12

[0166] This embodiment is basically the same as the first embodiment, and the only difference is the structure of the polysilicon layer and the deposition method. Specifically:

[0167] The polysilicon layer includes a first intrinsic microcrystalline silicon layer, a first polycrystalline silicon layer, a second intrinsic microcrystalline silicon layer, and a second polycrystalline silicon layer in sequence.

[0168] The deposition method of the polysilicon layer is as follows:

[0169] During the deposition of the first intrinsic microcrystalline silicon layer, the temperature was 350° C., the silane flow rate range was 2200 sccm, the hydrogen flow rate range was 18000 sccm, the deposition time was 40 s, and the deposition thickness of the intrinsic microcrystalline silicon layer was 8 nm.

[0170] During the deposition of the first polysilicon layer, the temperature is 450° C., the silane flow rate range is 2200 sccm, the hydrogen flow rate range is 6000 sccm, the deposition time is 350 s, and the deposition thickness of the first polysilicon layer is 65 nm.

[0171] During the deposition of the second intrinsic microcrystalline silicon layer, the temperature was 320° C., the silane flow rate range was 2000 sccm, the hydrogen flow rate range was 16000 sccm, the deposition time was 35 s, and the deposition thickness of the intrinsic microcrystalline silicon layer was 6 nm.

[0172] During the deposition of the second polysilicon layer, the temperature is 450° C., the silane flow rate range is 3000 sccm, the hydrogen flow rate range is 9000 sccm, the deposition time is 75 s, and the thickness of the second polysilicon layer is 20 nm.

[0173] Comparative Example 1

[0174] This comparative example is basically the same as Example 1, except that the polysilicon layer is a single layer with a thickness of 90 nm.

[0175] The passivated contact solar cells prepared in the embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0176] Table 1 Performance test results

[0177] Group Eta / % Voc / V Isc / A FF / % Example 1 26.56 0.726 14.13 85.93 Example 2 26.55 0.728 14.16 85.75 Example 3 26.58 0.729 14.13 85.95 Example 4 26.57 0.728 14.16 85.80 Example 5 26.63 0.729 14.14 86.06 Example 6 26.64 0.730 14.17 85.86 Example 7 26.58 0.728 14.17 85.83 Example 8 25.54 0.729 14.13 85.83 Example 9 26.55 0.728 14.16 85.84 Example 10 26.56 0.729 14.16 85.75 Embodiment 11 26.52 0.729 14.11 85.90 Example 12 26.56 0.729 14.18 85.58 Comparative Example 1 26.50 0.725 14.11 85.76

[0178] It can be seen from the performance test results of Examples 1-12 and Comparative Example 1 in Table 1 that, compared with the conventional single-layer polycrystalline silicon layer structure, the passivated contact solar cell of the present invention, by setting a multi-layer structure of polycrystalline silicon layers, the differentiation between the polycrystalline silicon layers helps to reduce the penetration of doping elements into the silicon substrate through the oxide layer, while reducing the occurrence of film explosion, and improving the conversion efficiency of the passivated cell. Furthermore, by adding an intrinsic microcrystalline silicon layer between the polycrystalline silicon layers and / or between the polycrystalline silicon layer and the oxide layer, compared with the microcrystalline silicon layer being set in the outermost layer, the influence of parasitic absorption can be reduced, and the battery electrical performance is better.

[0179] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A passivated contact solar cell, characterized in that It includes a tunneling oxide layer and a plurality of polysilicon layers sequentially located on one side of a silicon substrate, wherein the plurality of polysilicon layers sequentially include a first polysilicon layer, ..., an Mth polysilicon layer in a direction away from the tunneling oxide layer, wherein M is an integer greater than or equal to 2; and the thickness of the first polysilicon layer is greater than the thickness of the polysilicon layers of the other layers.

2. The passivated contact solar cell according to claim 1, characterized in that: At least one layer of intrinsic microcrystalline silicon layer is included between the first polycrystalline silicon layer and the Mth polycrystalline silicon layer.

3. The passivated contact solar cell according to claim 1, characterized in that: At least one intrinsic microcrystalline silicon layer is provided between the tunnel oxide layer and the first polysilicon layer.

4. The passivated contact solar cell according to claim 3, characterized in that: At least one layer of intrinsic microcrystalline silicon layer is included between the first polycrystalline silicon layer and the Mth polycrystalline silicon layer.

5. A method for preparing a passivated contact solar cell, characterized in that: The following steps are included in sequence: (1) Preparing a silicon substrate; (2) preparing a tunneling oxide layer on one side of the silicon substrate; (3) depositing a first polysilicon layer, ..., an Mth polysilicon layer in sequence on the tunnel oxide layer, wherein M is an integer greater than or equal to 2; and the deposition thickness of the first polysilicon layer is greater than the deposition thickness of the other polysilicon layers.

6. The method for preparing a passivated contact solar cell according to claim 5, characterized in that: After depositing the first polysilicon layer and before depositing the Mth polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

7. The method for preparing a passivated contact solar cell according to claim 5, characterized in that: After preparing the tunnel oxide layer and before depositing the first polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

8. The method for preparing a passivated contact solar cell according to claim 7, characterized in that: After depositing the first polysilicon layer and before depositing the Mth polysilicon layer, the method further includes depositing at least one intrinsic microcrystalline silicon layer.

9. The method for preparing a passivated contact solar cell according to claim 5, characterized in that: During the deposition of the first polysilicon layer, the temperature is 425-460° C., the silane flow rate range is 2000-2500 sccm, the hydrogen flow rate range is 5000-7000 sccm, the deposition time is 350-450 s, and the deposition thickness of the first polysilicon layer is 60-80 nm.

10. The method for preparing a passivated contact solar cell according to any one of claims 6 to 8, characterized in that: During the deposition of the intrinsic microcrystalline silicon layer, the temperature is 325-400° C., the silane flow rate range is 2000-2500 sccm, the hydrogen flow rate range is 15000-20000 sccm, and the deposition time is 30-50 s.