Mother substrate and display panel using same

Abstract

The invention discloses a mother substrate and a display panel using the mother substrate. The mother substrate is used for the display panel. A mother substrate for a display panel includes: a conductive ring disposed in a non-display area outside a display area and surrounding each of the display areas; and one or more dummy pixel driving circuits, the one or more dummy pixel driving circuits being disposed in a non-display area outside the display area. An electrostatic discharge (ESD) prevention structure inside the dummy pixel driving circuit may prevent defects of the display panel due to ESD occurring in a manufacturing process of the display panel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0096834, filed on Jul. 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present specification relates to a mother substrate and a display panel using the mother substrate. Background Art

[0004] Electroluminescent display devices may be roughly classified into organic light emitting display devices in which organic light emitting diodes (OLEDs) are provided in pixels and inorganic light emitting display devices in which inorganic light emitting diodes (hereinafter referred to as “LEDs”) are provided in pixels.

[0005] Since electroluminescent display devices use self-luminous elements to display images, they do not require a separate light source such as a backlight unit, and can be implemented in a thin and diverse form. Electroluminescent display devices not only have excellent power consumption, response speed, brightness, and viewing angle, but also have excellent contrast and color reproduction rate because black gradations can be expressed as completely black.

[0006] The organic light emitting display device needs to be designed to prevent the penetration of oxygen and moisture, because the penetration of moisture and oxygen may cause oxidation between the organic light emitting layer and the electrode.

[0007] As an example of an inorganic light-emitting display device, a micro LED display device in which a micro LED is provided in a pixel is attracting attention as a next-generation display device. The micro LED may be an inorganic LED having a size of 100 μm or less. The micro LED is manufactured by a separate semiconductor process and is transferred to a pixel position on a substrate of a display panel for a display device so that they can be provided in each sub-pixel for each color. Summary of the invention

[0008] In a process for manufacturing a display panel, electrostatic discharge (ESD) may occur. Such ESD may cause problems such as insulation breakdown or short circuit between thin film layers of the display panel.

[0009] The present specification is to address the above mentioned needs and / or problems.

[0010] The present specification provides a mother substrate capable of blocking electrostatic discharge affecting a display panel and a display panel including the mother substrate.

[0011] Problems or limitations to be solved or addressed by the present disclosure are not limited to the above-mentioned problems or limitations, and other problems or limitations not mentioned will be clearly understood by those skilled in the art from the following description.

[0012] According to one aspect of the present specification, a mother substrate is provided, the mother substrate comprising: a plurality of display areas, the plurality of display areas comprising a plurality of light-emitting areas provided with light-emitting elements, a plurality of wirings, and a plurality of pads connected to the plurality of wirings; a pixel driving circuit, the pixel driving circuit being arranged in the display area and comprising an electrostatic prevention structure; a conductive ring, the conductive ring being arranged in a non-display area outside the display area and surrounding each of the plurality of display areas; and one or more dummy pixel driving circuits, the one or more dummy pixel driving circuits being arranged in a non-display area outside the display area. The dummy pixel driving circuit may have the same electrostatic prevention structure as the pixel driving circuit.

[0013] According to another aspect of the present specification, a mother substrate is provided, the mother substrate comprising: a driving driver, the driving driver comprising one or more pixel driving circuits arranged in a display area; a conductive ring, the conductive ring being arranged in a non-display area outside the display area and surrounding the display area; and a dummy driver, the dummy driver being arranged in the non-display area outside the display area, wherein the driving driver of the display area and the dummy driver of the non-display area include electrostatic protection circuits identical to each other. The conductive ring can be electrically connected to the electrostatic protection circuit of the dummy driver through wiring.

[0014] The display panel may include a display area, and may be separated from the mother substrate.

[0015] According to the present specification, a dummy pixel driving circuit having substantially the same function and the same structure as a pixel driving circuit in the display panel arranged on a mother substrate is provided outside the display panel, and an electrostatic discharge (ESD) protection structure is used inside the dummy pixel driving circuit, thereby preventing defects of the display panel due to ESD generated in the manufacturing process of the display panel.

[0016] According to the present specification, the yield of display panels can be increased, the manufacturing process of display panels can be optimized, and production energy consumption can be reduced.

[0017] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1 is a diagram showing a display device according to one embodiment of the present specification;

[0020] Figure 2 yes Figure 1 An enlarged view of region A;

[0021] Figure 3 is a diagram showing a partial area of ​​a pixel;

[0022] Figure 4 It is along Figure 3 A cross-sectional view taken along line II' in FIG.

[0023] Figure 5 It is along Figure 3 A cross-sectional view taken along line II-II';

[0024] Figure 6 It is along Figure 3 A cross-sectional view taken along line III-III';

[0025] Figure 7 is a cross-sectional view showing an example in which a main light emitting element and a sub-light emitting element are electrically connected to a pixel driving circuit;

[0026] Figure 8 is a diagram showing a display device according to another embodiment of the present specification;

[0027] Fig. 9 It is along Figure 8 A cross-sectional view taken along line IV-IV';

[0028] Fig.10 is a cross-sectional view of a display panel schematically showing an example of a multilayer wiring pattern;

[0029] Fig.11A and Fig. 11B is a diagram showing two display panels provided on a mother substrate;

[0030] Fig.12 It is shown along Fig.11A A cross-sectional view of the longitudinal cross-sectional structure of the electrostatic blocking region taken along the line V-V';

[0031] Fig.13is a view schematically showing the structure of a driving actuator according to one embodiment of the present specification; and

[0032] Fig.14 and Fig.15 is a circuit diagram showing an electrostatic discharge (ESD) protection circuit. DETAILED DESCRIPTION

[0033] The advantages and features of the present disclosure and the methods for realizing the same will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, this embodiment will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0034] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings used to describe the embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0035] Terms such as "include," "comprising," "having," and "including" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to the singular may include the plural unless explicitly stated otherwise.

[0036] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0037] When describing the position or interconnection relationship between two components, such as "on", "above", "below", "beside", "connected or coupled to", "crossing", "intersecting", etc., unless "immediately" or "directly" is used, one or more other components may be inserted between them.

[0038] When describing a temporal precedence relationship, for example, "after", "after", "immediately", "before", etc., it may not be continuous on a temporal basis unless "immediately" or "directly" is used.

[0039] The terms “first”, “second”, etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by the sequence number preceding the component or the component name.

[0040] The following embodiments may be partially or entirely joined or combined with each other and may be linked and operated in various ways in technology. The embodiments may be performed independently or in association with each other.

[0041] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0042] A display device according to an embodiment of the present specification includes: a display panel having a display area or screen on which an image is displayed; and a pixel driving circuit for driving pixels on the display panel. The display area includes a pixel area where pixels are arranged. The pixel area includes a plurality of light-emitting areas. A light-emitting element is provided in each of the light-emitting areas. The pixel driving circuit can be built into the display panel.

[0043] Figure 1 is a diagram showing a display device according to one embodiment of the present specification; Figure 2 yes Figure 1 An enlarged view of region A; Figure 3 is a diagram showing a partial area of ​​a pixel.

[0044] Reference Figure 1 and Figure 2 A display device according to an embodiment of the present specification includes a display panel 100 that visually reproduces an input image. The display panel 100 may include a display area AA that displays an image and a non-display area NA that does not display an image. In the non-display area NA, various wirings and driving circuits may be installed, and a pad part PAD connected to an integrated circuit, a printed circuit, etc. may be provided.

[0045] The plurality of light emitting elements 10 disposed in the display area AA to form the pixel PXL may be micro-sized inorganic light emitting elements. The inorganic light emitting elements may be grown on a silicon wafer and then attached to a display panel through a transfer process.

[0046] The transfer process of the light emitting element 10 may be performed for each pre-divided area. Figure 1 , the display area AA is divided into nine transfer areas ST, but the size or number of the division of the transfer area is not limited thereto. The transfer process can be performed sequentially or simultaneously on the first to ninth transfer areas ST. In the transfer areas ST, the blue light emitting element 10, the green light emitting element 10, and the red light emitting element 10 can be sequentially transferred, respectively.

[0047] In the non-display area NA, a data driving circuit or a gate driving circuit may be provided, and wiring for supplying control signals to control these driving circuits may be provided. Here, the control signals may include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, and these control signals may be received through the pad portion PAD.

[0048] The pixel PXL can be driven by a pixel driving circuit. The pixel driving circuit can receive a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and outputs an anode voltage and a cathode voltage of the light-emitting element 10 to drive a plurality of pixels. The driving voltage can be a high potential voltage (EVDD). The cathode voltage can be a low potential voltage (EVSS) usually applied to the pixel. The anode voltage can be a voltage corresponding to the pixel data value of the image signal. The pixel driving circuit can be arranged in the non-display area NA or in the lower part of the display area AA.

[0049] Each of the pixels PXL may include a plurality of sub-pixels, each of which has a different color. For example, the plurality of pixels may include a red sub-pixel provided with a light emitting element 10 emitting light of a red wavelength, a green sub-pixel provided with a light emitting element 10 emitting light of a green wavelength, and a blue sub-pixel provided with a light emitting element 10 emitting light of a blue wavelength. The plurality of pixels may also include a white pixel.

[0050] Reference Figure 2 and Figure 3 , a plurality of pixels PXL may be sequentially arranged in a first direction (X-axis direction) and a second direction (Y-axis direction). In the pixel of the display area AA, a plurality of sub-pixels of the same color may be arranged. For example, each of the plurality of pixels may include a first red sub-pixel provided with a first-first light-emitting element 11a emitting light of a red wavelength, a second red sub-pixel provided with a first-second light-emitting element 11b emitting light of a red wavelength, a first green sub-pixel provided with a second-first light-emitting element 12a emitting light of a green wavelength, a second green sub-pixel provided with a second-second light-emitting element 12b emitting light of a green wavelength, a first blue sub-pixel provided with a third-first light-emitting element 13a emitting light of a blue wavelength, and a second blue sub-pixel provided with a third-second light-emitting element 13b emitting light of a blue wavelength. The first-first light-emitting element 11a, the second-first light-emitting element 12a, and the third-first light-emitting element 13a may be interpreted as a main light-emitting element. The first-second light-emitting element 11b, the second-second light-emitting element 12b, and the third-second light-emitting element 13b may be interpreted as a secondary light-emitting element.

[0051] One sub-pixel includes one or more light emitting elements, and if one light emitting element becomes defective, the brightness of another light emitting element can be increased to adjust the brightness of the sub-pixel. However, it is not necessarily limited thereto, and one sub-pixel may include only one light emitting element.

[0052] Each of the plurality of first electrodes 161 may be disposed in the lower portion of the light emitting element 10, and may be selectively connected to the plurality of signal wirings TL1 to TL6 through the extension 161a. A high potential voltage may be applied to the pixel driving circuit through the signal wirings TL1 to TL6. The signal wirings TL1 to TL6 and the first electrodes 161 may be formed as an electrode pattern integrated in an electrode patterning process.

[0053] Illustratively, the first signal wiring TL1 may be connected to the anode electrode of the first red sub-pixel, and the second signal wiring TL2 may be connected to the anode electrode of the second red sub-pixel. The third signal wiring TL3 may be connected to the anode electrode of the first green sub-pixel, and the fourth signal wiring TL4 may be connected to the anode electrode of the second green sub-pixel. The fifth signal wiring TL5 may be connected to the anode electrode of the first blue sub-pixel, and the sixth signal wiring TL6 may be connected to the anode electrode of the second blue sub-pixel. If one sub-pixel includes only one light-emitting element, the number of signal wirings TL may be reduced by half.

[0054] The second electrode 170 may be a cathode electrode arranged in each row to apply a cathode voltage to the light emitting elements 10 arranged continuously in the first direction (X-axis direction). A plurality of second electrodes 170 may be arranged to be spaced apart from each other in the second direction (Y-axis direction). A plurality of second electrodes 170 may be connected to the cathode voltage through the contact electrode 163. Each of the plurality of second electrodes 170 may be electrically connected to the contact electrode 163. However, it is not necessarily limited thereto, and the second electrode 170 may include one electrode layer instead of being divided into a plurality of electrodes to serve as a common electrode.

[0055] Figure 4 It is along Figure 3 A cross-sectional view taken along line II' in FIG. Figure 5 It is along Figure 3 A cross-sectional view taken along line II-II'. Figure 6 It is along Figure 3 A cross-sectional view taken along line III-III'. Figure 7 is a cross-sectional view showing an example in which two light emitting elements are connected to a pixel driving circuit.

[0056] Reference Figures 3 to 5According to an embodiment, the display device includes a plurality of first electrodes 161 and a contact electrode 163 provided on a substrate 110, a plurality of light emitting elements 10 provided on the plurality of first electrodes 161, a first optical layer 141 provided between the plurality of light emitting elements 10, and a second electrode 170 provided on the plurality of light emitting elements 10.

[0057] The substrate 110 may be made of a flexible plastic. For example, the substrate 110 may be made of a single-layer or multi-layer substrate, the material of which is selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, polyacrylate, polysulfone and cycloolefin copolymer, but is not limited thereto. For example, the substrate 110 may be a ceramic substrate or a glass substrate.

[0058] The pixel driving circuit 20 may be disposed in the display area AA on the substrate 110. The pixel driving circuit 20 may include a plurality of thin film transistors using an amorphous silicon semiconductor, a polysilicon semiconductor, or an oxide semiconductor.

[0059] The pixel driving circuit 20 may include at least one driving thin film transistor, at least one switching thin film transistor, and at least one storage capacitor. When the pixel driving circuit 20 includes a plurality of thin film transistors, the thin film transistors may be formed on the substrate 110 by a thin film transistor (TFT) manufacturing process. In an embodiment, the pixel driving circuit 20 may be a collection item of a plurality of thin film transistors electrically connected to the light emitting element 10.

[0060] The pixel driving circuit 20 may be a driving driver manufactured using a metal oxide-silicon field effect transistor (MOSFET) manufacturing process on a single crystal semiconductor substrate 110. The driving driver may include a plurality of pixel driving circuits for driving a plurality of sub-pixels. When the pixel driving circuit 20 is implemented as a driving driver, after an adhesive layer is provided on the substrate 110, the driving driver may be mounted on the adhesive layer by a transfer process.

[0061] A buffer layer 121 covering the pixel driving circuit 20 may be disposed on the substrate 110. The buffer layer 121 may be made of an organic insulating material such as photosensitive photoacrylic or photosensitive polyimide, but is not limited thereto.

[0062] The buffer layer 121 may be used by stacking an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2) in multiple layers, and may be used by stacking an organic insulating material and an inorganic insulating material in multiple layers.

[0063] An insulating layer 122 may be provided on the buffer layer 121. The insulating layer 122 may be made of an organic insulating material such as photosensitive photoacrylic or photosensitive polyimide, but is not limited thereto. Connection wirings RT1 and RT2 may be provided on the buffer layer 121. The connection wirings RT1 and RT2 may be connected through corresponding signal wirings TL1 to TL6, or may be connected to the signal wirings TL1 to TL6. The connection wirings RT1 and RT2 may include a plurality of wiring patterns provided on different layers, with one or more insulating layers interposed between the different layers. The wiring patterns provided on different layers may be electrically connected via contact holes, wherein the contact holes pass through the insulating layers.

[0064] A plurality of bank patterns 130 may be disposed on the insulating layer 122. At least one light emitting element 10 may be disposed on each bank pattern 130. For example, a first light emitting element 11 may be disposed on the first bank pattern 130, a second light emitting element 12 may be disposed on the second bank pattern 130, and a third light emitting element 13 may be disposed on the third bank pattern 130.

[0065] The bank pattern 130 may be made of an organic insulating material such as photosensitive acrylic or photosensitive polyimide, but is not limited thereto. The bank pattern 130 may guide a position to which the light emitting element 10 is to be attached in a transfer process of the light emitting element 10. The bank pattern 130 may be omitted.

[0066] A solder pattern 162 may be disposed on the first electrode 161. The solder pattern 162 may be made of indium (In), tin (Sn), or an alloy thereof, but is not limited thereto.

[0067] A plurality of light emitting elements 10 may be mounted on the solder pattern 162, respectively. One pixel may include three colors of light emitting elements 10. The first light emitting element 11 may be a red light emitting element, the second light emitting element 12 may be a green light emitting element, and the third light emitting element 13 may be a blue light emitting element. Two light emitting elements may be mounted in each sub-pixel.

[0068] The first optical layer 141 may cover the plurality of light emitting elements 10 and the dam patterns 130. Thus, the first optical layer 141 may cover between the plurality of light emitting elements 10 and between the plurality of dam patterns 130. The first optical layer 141 may extend in the first direction (X) and be spaced apart in the second direction (Y) to separate between pixel rows.

[0069] The first optical layer 141 may include an organic insulating material in which fine metal particles such as titanium dioxide particles are dispersed. Light emitted from the plurality of light emitting elements 10 may be scattered by the fine metal particles dispersed in the first optical layer 141 to be emitted outward.

[0070] A second electrode 170 may be disposed on the plurality of light emitting elements 10. The second electrode 170 may be commonly connected to the plurality of pixels PXL. The second electrode 170 may be a thin electrode through which light is transmitted. The second electrode 170 may be a transparent electrode material such as indium tin oxide (ITO), but is not necessarily limited thereto.

[0071] The second electrode 170 may extend in the first direction (X-axis direction) and be spaced apart in the second direction (Y-axis direction). The second electrode 170 may include a first region 171 disposed on the top surface of the light emitting element 10 and the top surface of the first optical layer 141, a second region 172 contacting and electrically connected to the contact electrode 163, and a third region 173 disposed on the side of the first optical layer 141 and connecting the first region 171 and the second region 172.

[0072] On a plane, each of the plurality of second electrodes 170 may overlap the first optical layer 141 , and the second region 172 may cover a plane outside the first optical layer 141 .

[0073] The second optical layer 142 may be an organic insulating material surrounding the first optical layer 141. The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (e.g., siloxane). For example, the first optical layer 141 may be siloxane containing titanium oxide (TiOx), and the second optical layer 142 may be siloxane not containing titanium oxide (TiOx). However, it is not necessarily limited thereto, and the first optical layer 141 and the second optical layer 142 may be formed of the same material, or may also be formed of different materials.

[0074] According to an embodiment, since the second region 172 of the second electrode 170 is connected to the contact electrode 163 in an overall flat state, excessive stress is not concentrated at the connection point with the contact electrode 163. Therefore, cracks in the second electrode 170 can be effectively prevented.

[0075] The second optical layer 142 may cover the second region 172 and the third region 173 of the second electrode 170. The top surface of the second optical layer 142 and the top surface of the first region 171 of the second electrode 170 may be coplanar. In other words, the first optical layer 141 and the second optical layer 142 may serve as a planarization layer. Therefore, since there is no step on the surface on which the black matrix 190 is formed, the pattern of the black matrix 190 may be easily formed on the first optical layer 141 and the second optical layer 142. However, it is not necessarily limited thereto, and the top surface of the second optical layer 142 and the top surface of the second electrode 170 may have different heights.

[0076] The black matrix 190 may be an organic insulating material to which a black pigment is added. Under the black matrix 190, the second electrode 170 may be in contact with the contact electrode 163. Transmission holes 191 may be formed between patterns of the black matrix 190, and light emitted from the light emitting element 10 is emitted outward through the transmission holes 191. Through the black matrix 190, the problem that the first optical layer 141 mixes light emitted from adjacent light emitting elements 10 may be improved.

[0077] The cover layer 180 may be an organic insulating material for covering the black matrix 190 and the second electrode 170. Figure 3 In the figure, the configuration of the black matrix 190 and the cover layer 180 is omitted.

[0078] The contact electrode 163 is electrically connected to the first connection wiring RT1 disposed on the lower portion thereof, and the first connection wiring RT1 may be connected to the pixel driving circuit 20. Therefore, a cathode voltage may be applied to the second electrode 170 through the contact electrode 163. The first electrode 161 may be electrically connected to the second connection wiring RT2. This will be described later.

[0079] Reference Figure 5 The contact electrode 163 and the signal wirings TL1 to TL6 may be arranged on the same plane. The pixel driving circuit 20 may be arranged below the contact electrode 163 and the signal wirings TL1 to TL6. When the pixel driving circuit 20 is a driving driver, a plurality of driving drivers may be arranged in the display panel.

[0080] The passivation layer 133 may expose the contact electrode 163 so that the contact electrode 163 and the second electrode 170 are electrically connected. In addition, the passivation layer 133 may insulate the signal wirings TL2 to TL5 from the second electrode 170 .

[0081] Reference Figure 6 The connection portion 161 a of the first electrode 161 extends to one side surface 131 of the bank pattern 130 and is electrically connected to the connection wiring RT2 provided on the insulating layer 122 .

[0082] The first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wiring RT1 and RT2 may include a single layer or multiple layers of a metal layer selected from titanium (Ti), molybdenum (Mo) and aluminum (Al). The first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wiring RT1 and RT2 may be formed into a multilayer structure including a first layer ML1, a second layer ML2, a third layer ML3 and a fourth layer ML4.

[0083] The first layer ML1 and the third layer ML3 may include titanium (Ti) or molybdenum (Mo). The second layer ML2 may include aluminum (Al). The fourth layer ML4 may include a transparent conductive oxide layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has good adhesion to the solder pattern 162, corrosion resistance, and acid resistance.

[0084] The first layer ML1 , the second layer ML2 , the third layer ML3 , and the fourth layer ML4 may be sequentially deposited and then patterned by performing a photolithography process and an etching process.

[0085] The passivation layer 133 may be disposed on the first electrode 161 and the signal wiring TL, and may include an opening hole 133 a exposing the solder pattern 162 .

[0086] The light emitting element 10 may include a first conductive type semiconductor layer 10-1, an active layer 10-2 disposed on the first conductive type semiconductor layer 10-1, and a second conductive type semiconductor layer 10-3 disposed on the active layer 10-2. A first driving electrode 15 may be disposed on a lower portion of the first conductive type semiconductor layer 10-1, and a second driving electrode 14 may be disposed on an upper portion of the second conductive type semiconductor layer 10-3.

[0087] The light emitting element 10 can be formed on a silicon wafer using methods such as metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, etc.

[0088] The first conductive type semiconductor layer 10-1 may be implemented as a compound semiconductor such as a group III-V, group II-VI, etc., and may be doped with a first dopant. The first conductive type semiconductor layer 10-1 may be made of a composition formula of Al x1 In y1 Ga (1-x1-y1) The first conductive semiconductor layer 10-1 may be formed of any one or more of semiconductor materials of N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), InAlGaN, AlGaAs, GaP, GaAs, and AlGaInP, but is not limited thereto. When the first dopant is an n-type dopant such as Si, Ge, Sn, Se, Te, etc., the first conductive semiconductor layer 10-1 may be an n-type nitride semiconductor layer. However, when the first dopant is a p-type dopant, the first conductive semiconductor layer 10-1 may be a p-type nitride semiconductor layer.

[0089] The active layer 10-2 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 10-1 meet holes (or electrons) injected through the second conductive semiconductor layer 10-3. The active layer 10-2 can generate light that transitions to a lower energy level and has a corresponding wavelength as electrons and holes recombine.

[0090] The active layer 10-2 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the structure of the active layer 10-2 is not limited thereto. The active layer 10-2 may generate light in a visible light band. Illustratively, the active layer 10-2 may output light in any one of blue, green, and red bands.

[0091] The second conductive type semiconductor layer 10-3 may be disposed on the active layer 10-2. The second conductive type semiconductor layer 10-3 may be implemented as a compound semiconductor such as a III-V group, a II-VI group, etc., and the second conductive type semiconductor layer 10-3 may be doped with a second dopant. The second conductive type semiconductor layer 10-3 may be composed of a composition formula of In x2 Al y2 Ga 1-x2+y2 The second conductive semiconductor layer 10-3 may be formed of a semiconductor material selected from the group consisting of AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc., the second conductive semiconductor layer 10-3 doped with the second dopant may be a p-type semiconductor layer. When the second dopant is an n-type dopant, the second conductive semiconductor layer 10-3 may be an n-type nitride semiconductor layer.

[0092] A reflective layer 16 may be provided on the side surface and the lower portion of the light emitting element 10. The reflective layer 16 may have a structure in which a reflective material is dispersed in a resin layer, but is not necessarily limited thereto. Illustratively, the reflective layer 16 may be manufactured as a reflector of various structures. The light emitted from the active layer 10-2 may be reflected upward by the reflective layer 16 to improve light extraction efficiency.

[0093] Although the embodiment is described as a vertical structure in which the driving electrodes 14 and 15 are disposed on the upper and lower portions of the light emitting structure, the light emitting device may have a lateral structure or a flip chip structure in addition to the vertical structure.

[0094] Reference Figure 7, a main light emitting element 12a and a sub-light emitting element 12b of a sub-pixel may be disposed on the bank pattern 130. The second light emitting element 12 will be illustratively described. The first-first electrode 161-1 connected to the main light emitting element 12a may extend to one side surface of the bank pattern 130 to be electrically connected to the second-first connection wiring RT21 disposed on the lower portion of the first-first electrode 161-1. The first-second electrode 161-2 connected to the sub-light emitting element 12b may extend to the other side surface of the bank pattern 130 to be electrically connected to the second-second connection wiring RT22 disposed on the lower portion of the first-second electrode 161-2.

[0095] The pixel driving circuit 20 can apply an anode voltage to the main light emitting element 12a through the second-first connection wiring RT21, and can apply an anode voltage to the sub-light emitting element 12b through the second-second connection wiring RT22. The pixel driving circuit 20 can apply a cathode voltage to the main light emitting element 12a and the sub-light emitting element 12b through the first connection wiring RT1 and the second electrode 170.

[0096] The pixel driving circuit 20 can adjust the brightness by driving only the main light emitting element 12a, or can adjust the brightness by driving both the main light emitting element 12a and the auxiliary light emitting element 12b. If the main light emitting element 12a becomes dark, the brightness can be adjusted by driving only the auxiliary light emitting element 12b.

[0097] Figure 8 is a diagram illustrating a display device according to another embodiment of the present specification. Fig. 9 is along Figure 8 A cross-sectional view taken along line IV-IV′ in FIG.

[0098] Reference Figure 8 and Fig. 9 , the second electrode 170 may be electrically connected to the contact electrode 163 via a contact hole TH1 formed in the second optical layer 142. The second optical layer 142 may include a contact hole TH1 exposing the contact electrode 163. The second electrode 170 may be inserted into the contact hole TH1 of the second optical layer 142 and may contact an upper surface of the contact electrode 163. The contact hole TH1 may be formed in an outer region of the pixel.

[0099] In a manufacturing process of a display panel, thin film layers of a plurality of display panels are simultaneously formed on a mother substrate, and then a display area may be separated into individual display panel units in a scribing process.

[0100] Fig.10 is a cross-sectional view of a display panel schematically showing an example of a multilayer wiring pattern that can be applied to one embodiment of the present invention.

[0101] Reference Fig.10 , first to fifth insulating layers INS1 to INS5 may be stacked on the substrate 110. Wirings of the display panel included in the mother substrate 1100 may include a plurality of wiring patterns arranged in different layers.

[0102] At least one driving driver 20 may be provided on the substrate 110. The driving driver 20 may be at least partially embedded in the first insulating layer INS1. A first wiring pattern M1 may be provided on the first insulating layer INS1. The first insulating layer INS1 may include a single layer or a plurality of insulating layers. The second insulating layer INS2 includes a contact hole exposing an output terminal of the driving driver 20 and / or the first wiring pattern M1. A second wiring pattern M2 may be provided on the second insulating layer INS2. A portion of the second wiring pattern M2 may contact the output terminal of the driving driver 20 and / or the first wiring pattern M1 via the contact hole passing through the second insulating layer INS2. The third insulating layer INS3 may include a contact hole exposing a portion of the second wiring pattern M2. A third wiring pattern M3 may be provided on the third insulating layer INS3. A portion of the third wiring pattern M3 may contact the second wiring pattern M2 via the contact hole passing through the third insulating layer INS3.

[0103] The fourth insulating layer INS4 may include a contact hole exposing a portion of the third wiring pattern M3. The fourth wiring pattern M4 may be provided on the fourth insulating layer INS4. A portion of the fourth wiring pattern M4 may contact the third wiring pattern M3 via the contact hole passing through the fourth insulating layer INS4. The fifth insulating layer INS5 may include a contact hole exposing a portion of the fourth wiring pattern M4. The fifth wiring pattern M5 may be provided on the fifth insulating layer INS5. A portion of the fifth wiring pattern M5 may contact the fourth wiring pattern M4 via the contact hole passing through the fifth insulating layer INS5. The fifth wiring pattern M5 may include a metal pattern electrically connected to the first electrode of the light emitting element and a metal pattern connected to the second electrode of the light emitting element.

[0104] The wiring structure of the display panel included in the mother substrate 1100 is not limited to Fig.10 For example, the third wiring pattern M3 may be connected to the first wiring pattern M1 via a contact hole passing through two insulating layers INS2 and INS3 stacked below the third wiring pattern M3. The first electrode and the second electrode of the light emitting element may be electrically connected to a preset metal pattern among the first to fourth wiring patterns via contact holes passing through the respective insulating layers.

[0105] In a manufacturing process of a display panel, thin film layers of a plurality of display panels are simultaneously formed on a mother substrate, and then a display area may be separated into individual display panel units in a scribing process.

[0106] Fig.11A is a plan view showing an example of a display panel provided on a mother substrate.

[0107] Reference Fig.11A The mother substrate 1100 includes a plurality of display panels 100. After a pixel driving circuit, a thin film layer, and a light emitting element are disposed on the mother substrate 1100 and an inspection process is completed, each of the display panels 100 is separated from the mother substrate 1100 along a scribing line 190 in a scribing process.

[0108] A conductive ring 300 is provided in a non-display region of the mother substrate 1100 so that electrostatic discharge (ESD) generated in a manufacturing process of the display panel included in the mother substrate 1100 does not affect the display panel included in the mother substrate 1100. The conductive ring 300 is electrically connected to each of the display panels 100 to be at the same potential as the display panel 100. The conductive ring 300 includes a ring-shaped wiring pattern surrounding each of the display panels 100. A scribing line 190 may be provided between the display region of the display panel 100 included in the mother substrate 1100 and the conductive ring 300.

[0109] The display panel included in the mother substrate 1100 includes a plurality of pads 200, which are arranged and exposed to the outside of the display area on which the pixels are arranged. The pads 200 are electrically connected to the wiring pattern in the display area. The host system can send the signal required to drive the pixel to the pixel driving circuit through the pads 200. A flexible circuit film such as a flexible printed circuit (FPC) can be bonded to the pads 200 through an anisotropic conductive film (ACF). The mainboard of the host system can be connected to one end of the flexible circuit film, and the pads 200 of the display panel included in the mother substrate 1100 can be connected to the other end.

[0110] The pad 200 may be connected to a shorting bar 210 disposed in a non-display area on the mother substrate 1100. The shorting bar 210 may be connected to the conductive ring 300 through a connection portion 220. The conductive ring 300, the connection portion 220, the shorting bar 210, and the pad 200 may be connected to the conductive ring 300 by a connection portion 220. Fig.10 The connection structure of the conductive ring 300 , the connection portion 220 , the shorting bar 210 , and the pad 200 allows each wiring of the display panel included in the mother substrate 1100 to be at the same potential as the conductive ring 310 .

[0111] In the manufacturing process of the display panel included in the mother substrate 1100, a large amount of electric charges may be generated in a thin film deposition process, such as a process of depositing a metal layer to be patterned as the solder pattern 316. The solder pattern 316 may be Figure 6 1. The conductive ring 300 is substantially the same as the solder pattern 162 shown in FIG. 1. Since the conductive ring 300 is connected to the pad 200 and the shorting bar 210 on the mother substrate 1100, when ESD is generated in the process of forming the solder pattern 316 on the mother substrate 1100, a large amount of charge may be attracted to one or more of the display panels on the mother substrate 1100. Since the wiring of the display panel included in the mother substrate 1100 has the same potential as the conductive ring 310, a large amount of charge may flow into the display panel included in the mother substrate 1100 through the pad 200 or the solder pattern 316 within the display panel included in the mother substrate 1100, thereby causing damage to the display panel due to ESD.

[0112] Fig. 11B is a plan view showing two display panels provided on a mother substrate. Fig.12 is shown along Fig.11A A cross-sectional view of a partial longitudinal cross-sectional structure of the display panel taken along line VV′ in FIG.

[0113] Fig.12 It is assumed that the insulating layer stacking structure of the mother substrate 1100 is Fig.10 , a diagram of the first insulating layer INS1, the second insulating layer INS2 and the fifth insulating layer INS5 shown in the figure, wherein even when the insulating layer is added, the planar wiring connection structure between the Z1 area including the conductive ring 300, the Z2 area including the dummy pixel driving circuit 20a, the Z3 area including the pad 200 and the Z4 area including the pixel driving circuit 20 is basically the same.

[0114] Reference Fig. 11B and Fig.12 The mother substrate 1100 may include a plurality of display panels according to an embodiment of the present invention. After the pixel driving circuit, the thin film layer, and the light emitting element are arranged on the mother substrate 1100 and the inspection process is completed, each of the display panels 100 is separated from the mother substrate 1100 along the scribing line 190 in the scribing process.

[0115] On the mother substrate 1100, the conductive ring 300 is disposed in a non-display area outside the display area AA of the display panel 100. The conductive ring 300 includes a ring-shaped wiring pattern surrounding each of the display panels 100. The scribing line 190 may be disposed between the display area AA of the display panel 100 included in the mother substrate 1100 and the conductive ring 300. Adjacent conductive rings 300 are not connected to each other. The conductive rings 300 adjacent to each other are not electrically connected because they are separated from each other and not connected by a conductor. When the connection between adjacent conductive rings 300 is disconnected, in the manufacturing process of the display panel 100 included in the mother substrate 1100, a large amount of electric charge generated in the process of depositing a metal layer to be patterned as a solder pattern 316 may be prevented from flowing to the adjacent display panel 100 on the mother substrate 1100.

[0116] The pad 200 may be connected to the shorting bar 210 disposed in the non-display area on the mother substrate 1100. Since the structure and wiring for directly connecting the shorting bar 210 and the conductive ring 300 are eliminated, a current path through which charges may move into the display panel through the pad 200 may be blocked, thereby preventing damage caused by ESD from spreading to other display panels 100.

[0117] On the mother substrate 1100, one or more dummy pixel driving circuits 20a may be disposed in a non-display area outside the display area AA of the display panel 100. The dummy pixel driving circuit 20a may be disposed between the conductive ring 300 on the mother substrate 1100 and the display panel 100, but is not limited thereto. The dummy pixel driving circuit 20a may also be disposed in a non-display area outside the conductive ring 300.

[0118] One or more dummy pixel driving circuits 20a may be integrated into Fig.13 The dummy driver DDR may be substantially the same as the driving driver PDR in the display area AA of the display panel 100 disposed on the mother substrate 1100, and may be disposed in the same layer together with the driving driver PDR on the mother substrate 1100. The dummy driver DDR may be embedded on the mother substrate 1100 together with the driving driver PDR in the same process.

[0119] In accordance with Fig. 11B and Fig.12In one embodiment of the present invention, the conductive ring 300 may be disposed in a non-display region of a display panel included in the mother substrate 1100 of the mother substrate 1100. The conductive ring 300 may include a ring-shaped wiring pattern surrounding each of the display panels 100. The conductive ring 300 may include a first wiring pattern M1 disposed on the first insulating layer INS1 and a second wiring pattern M2 directly connected to the first wiring pattern M1 via a plurality of contact holes formed in the second insulating layer INS2.

[0120] At least one dummy driver DDR having the same structure as the driving driver PDR may be provided between the conductive ring 300 and the display panel 100 included in the mother substrate 1100. The dummy driver DDR may be at least partially embedded in the display panel 100. Fig.10 The first wiring pattern M1 may be disposed on the first insulating layer INS1. The first insulating layer INS1 may include a plurality of insulating layers. The second insulating layer INS2 includes a contact hole exposing an output terminal of the dummy driver DDR and / or the first wiring pattern M1. In the display area AA of the display panel 100, the second wiring pattern M2 may be disposed on the second insulating layer INS2. A portion of the second wiring pattern M2 may contact the first wiring pattern M1 and / or the output terminal of the driving driver 20 via a contact hole passing through the second insulating layer INS2. The fifth insulating layer INS5 may be disposed on the second insulating layer INS2 and the second wiring pattern M2. The fifth insulating layer INS5 may include a contact hole exposing a portion of the second wiring pattern M2. A dam pattern 130 may be formed on the fifth insulating layer INS5. A portion of the fifth wiring pattern M5 may contact the second wiring pattern M2 via a contact hole passing through the fifth insulating layer INS5.

[0121] After forming the fifth wiring pattern M5, a photoresist may be coated on the entire surface of the mother substrate 1100. The coated photoresist is developed to form a photoresist opening PO in a region where the solder pattern 316 is to be formed.

[0122] The upper metal layer is deposited on the entire surface of the mother substrate 1100 on which the photoresist opening PO is formed. The upper metal layer includes a first metal layer 314 covering an upper portion of the photoresist PR and solder patterns 316 disposed in the display area AA and the non-display area NA of the display panel 100.

[0123] In the display area AA and the non-display area NA, the photoresist opening PO may have an inverse tapered shape, that is, an upper surface may be wider than a lower surface, but is not limited thereto.

[0124] When the photoresist PR is removed in the strip process, the first metal layer 314 covering the photoresist PR is also removed.

[0125] Reference Fig.10 and Fig.12 , the mother substrate 1100 includes a Z1 region, a Z2 region, a Z3 region, and a Z4 region. The Z1 region indicates a partial region of the conductive ring 300. The Z2 region indicates a region in which a dummy pixel driving circuit 20a is disposed. The Z3 region includes a shorting bar 210 and a pad 200. The Z4 region indicates a region in which the pixel driving circuit 20 is disposed within the display region AA of the display panel 100.

[0126] The Z2 region may also include a light-emitting element of a dummy pixel connected to a dummy pixel driving circuit 20a. The dummy pixel circuit 20a has substantially the same function and structure as the pixel circuit of the pixel driving circuit 20 in the display panel 100. The difference is that the dummy pixel circuit 20a drives the dummy pixel, while the pixel driving circuit drives the pixel in the display region of the display panel 100. The light-emitting element of the dummy pixel may be formed to have substantially the same structure as the light-emitting element of the pixel provided in the display panel 100. Therefore, as Fig.12 As shown, like the pixel in the display panel 100, the light emitting element of the dummy pixel includes a bank pattern and a solder pattern 316 disposed on the bank pattern and in contact with the light emitting element. Fig.12 It is the cross-sectional structure of the mother substrate before the light-emitting element transfer process. Fig.12 The solder pattern 316 is omitted.

[0127] The solder pattern 316 and the light emitting element of the dummy pixel may overlap the dummy pixel driving circuit 20a in the thickness direction (Z axis direction) of the mother substrate 1100. The solder pattern and the light emitting element of the pixel disposed in the display area AA of the display panel 100 may overlap the pixel driving circuit 20.

[0128] The conductive ring 300 disposed in the non-display area of ​​the mother substrate 1100 may include a first wiring pattern M1 disposed on the first insulating layer INS1 and a second wiring pattern M2 directly connected to the first wiring pattern M1 via one or more contact holes formed in the second insulating layer INS2. The conductive ring 300 may also include one or more other wiring patterns electrically connected to the second wiring pattern M2.

[0129] The dummy pixel driving circuit 20a may be connected to the second wiring pattern M2 through one or more contact holes formed in the second insulating layer INS2, and may be connected to the fifth wiring pattern M5 in contact with the second wiring pattern M2. The fifth wiring pattern M5 electrically connected to the dummy pixel driving circuit 20a may extend to the upper portion of the region where the conductive ring 300 is located to overlap with the dummy pixel driving circuit 20a, but is not electrically connected to the conductive ring 300.

[0130] The second wiring pattern M2 may include a first connection portion M21 connected to a first terminal of the dummy driver DDR and a second connection portion M22 connected to a second terminal of the dummy driver DDR and the conductive ring 300. The conductive ring 300 may be electrically connected to an electrostatic discharge structure (or an electrostatic prevention structure or an electrostatic protection circuit) of the dummy pixel driving circuit 20a through the second connection portion M22. The first connection portion M21 and the second connection portion M22 are not directly connected to each other. The wiring pattern arranged in the Z2 region may not be electrically connected to the wiring pattern arranged in the Z3 region.

[0131] Fig.11A and Fig. 11B The pad 200 shown in FIG. 1 may be connected to the pixel driving circuit 20 provided in the display area by connecting at least one of the remaining wiring patterns except the fifth wiring pattern M5 among the wiring patterns in the display area AA. Fig.12 In the example of FIG. 1 , the pad 200 is connected to the pixel driving circuit 20 through the second wiring pattern M2 , but is not limited thereto.

[0132] In accordance with FIG. 11A to FIG. 12 In one embodiment of the present invention, when many charges are generated during the process of depositing the solder pattern 316 and the first metal layer 314 in the process of manufacturing the display panel included in the mother substrate 1100, the conductive ring 300 and the fifth wiring pattern M5 are electrically cut off from each other so that the charges are not concentrated on the conductive ring 300.

[0133] In the process of depositing the solder pattern 316 and the first metal layer 314, a large amount of charge can flow into the dummy pixel driving circuit 20a through the wiring pattern connected to the dummy pixel driving circuit 20a. The dummy driver DDR includes an ESD prevention structure identical to the driving driver PDR arranged in the display area AA of the display panel 100. The ESD prevention structure may include an ESD protection circuit connected to the output terminal of the pixel driving circuit 20 and 20a. When ESD is generated, the ESD protection circuit protects the pixel driving circuit 20 and 20a from the influence of ESD by discharging the ESD to the wiring or ground GND connected to the conductive ring 300 using a conductive switching element such as a transistor or a diode. If ESD is generated in the process of depositing the solder pattern 316 and the first metal layer 314, the ESD is discharged to the ground by the ESD protection circuit built into the dummy driver DDR, thereby protecting the dummy pixel driving circuit 20a and the display panel 100 arranged on the mother substrate 1100 from the influence of ESD. Furthermore, when ESD is generated, after the charge amount is first reduced in a process in which the charge flows into the dummy driver DDR through the solder pattern 316 and the wiring patterns M2 and M5 , the charge amount is secondarily reduced in the dummy driver DDR.

[0134] Fig.13 FIG. 1 is a view schematically showing the structure of a driving actuator according to one embodiment of the present specification.

[0135] Reference Fig.13 The display area AA of the display panel 100 includes one or more driving drivers PDR in which a plurality of pixel driving circuits 20a are integrated. The non-display area of ​​the mother substrate 110 includes one or more dummy drivers DDR in which a plurality of pixel driving circuits 20a are integrated.

[0136] The driving driver PDR and the dummy driver DDR have substantially the same structure. Each of the driving driver PDR and the dummy driver DDR includes an ESD protection circuit EDC connected to the input / output terminal of the pixel driving circuit 20 and 20a. When ESD is generated, if charges flow to the input / output terminals of the driving driver PDR and the dummy driver DDR, the charges are discharged to the ground wiring GR through the ESD protection circuit EDC, thereby protecting the pixel driving circuit 20 and 20a from the influence of ESD.

[0137] The first terminal 201 of the dummy driver DDR may be connected to the first connection portion M21 , and the second terminal 202 of the dummy driver DDR may be connected to the second connection portion M22 .

[0138] The ESD protection circuit EDC can be implemented in various structures. As an example, the ESD protection circuit EDC can be implemented as follows: Fig.14 The circuit shown in, but not limited to.

[0139] Fig.14 and Fig.15 is a circuit diagram showing an ESD protection circuit.

[0140] Reference Fig.14 , the ESD protection circuit includes a transistor T1 connected between a first node 203 and a second node 204, a first capacitor C1 connected between the first node 203 and a third node 205, and a second capacitor C2 connected between the second node 204 and the third node 205. An input / output terminal of the dummy driver DDR may be connected to the first node 203, and the second node 204 may be connected to the ground wiring GR.

[0141] The transistor T1 includes a drain electrode connected to a first node 203 , a source electrode connected to a second node 204 , and a gate electrode connected to a third node 205 .

[0142] When ESD is generated and charges flow into the dummy driver DDR through its input / output terminal, the voltage of the first node 203 increases and the gate voltage of the transistor T1 increases through the capacitor C1, turning on the transistor T1. Therefore, a large amount of charges generated by ESD can be discharged through the ground wiring GR.

[0143] Reference Fig.15 The ESD protection circuit includes a first transistor T01 connected between a first node 207 and a second node 208, a second transistor T02 connected between the second node 208 and a third node 209, and a third transistor T03 connected between the first node 207 and the third node 209. An input / output terminal of the dummy driver DDR may be connected to the first node 207, and the third node 209 may be connected to the ground wiring GR.

[0144] The first transistor T01 includes a drain electrode and a gate electrode connected to the first node 207 and a source electrode connected to the second node 208. The second transistor T02 includes a drain electrode connected to the second node 208 and a source electrode and a gate electrode connected to the third node 209. The third transistor T03 includes a drain electrode connected to the first node 207, a gate electrode connected to the second node 208, and a source electrode connected to the third node 209.

[0145] When ESD is generated and charges flow into the dummy driver DDR through its input / output terminal, the voltage of the first node 207 increases, turning on the transistors T01, T02, and T03. Therefore, a large amount of charges generated by ESD can be discharged through the ground wiring GR.

[0146] According to one or more embodiments of the present disclosure, the display device may be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMP), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, vehicle navigation, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, camera devices, video cameras, and home appliances, etc. In addition, the display device according to one or more embodiments of the present disclosure may be applied to organic light emitting lighting devices or inorganic light emitting lighting devices.

[0147] According to one or more embodiments of the present disclosure, a mother substrate and a display panel may be described as follows.

[0148] According to one or more embodiments of the present disclosure, a mother substrate for a display panel may include: a plurality of display areas, the plurality of display areas including a plurality of light-emitting areas provided with light-emitting elements, a plurality of wirings, and a plurality of pads connected to the plurality of wirings; a pixel driving circuit, the pixel driving circuit being provided in the display area and including a static electricity prevention structure; a conductive ring, the conductive ring being provided in a non-display area outside the display area and surrounding each of the plurality of display areas; and one or more dummy pixel driving circuits, the one or more dummy pixel driving circuits being provided in the non-display area outside the display area. The dummy pixel driving circuit may have the same static electricity prevention structure as the pixel driving circuit.

[0149] The dummy pixel driving circuit may be disposed in a non-display area between the conductive ring and the display area.

[0150] The conductive rings surrounding each of the plurality of display areas may be separated from each other.

[0151] The mother substrate may also include: a first insulating layer, which covers at least a portion of the pixel driving circuit and the dummy pixel driving circuit; a first wiring pattern, which is arranged on the first insulating layer; a second insulating layer, which is formed on the first wiring pattern; and a second wiring pattern, which is arranged on the second insulating layer and is electrically connected to the dummy pixel driving circuit and the conductive ring via a plurality of contact holes formed on the second insulating layer.

[0152] The second wiring pattern may include: a first connection portion connected to the dummy pixel driving circuit; and a second connection portion connected to the conductive ring. The first connection portion and the second connection portion of the second wiring pattern may be separated from each other without being directly connected.

[0153] The mother substrate may further include: a third insulating layer formed on the second wiring pattern; and a third wiring pattern disposed on the third insulating layer and electrically connected to the first connection portion via at least one contact hole formed on the third insulating layer.

[0154] The mother substrate may further include a bank pattern disposed on the third insulating layer. The third wiring pattern may be formed to cover the bank pattern. The mother substrate may further include a solder pattern formed on the bank pattern.

[0155] At least a portion of the third wiring pattern may overlap the conductive ring.

[0156] The mother substrate may further include a dummy pixel in which a dummy light emitting element is disposed. The dummy light emitting element is disposed in the non-display area and is connected to the dummy pixel driving circuit.

[0157] The dummy pixel may include a bank pattern of the dummy pixel, and a solder pattern disposed on the bank pattern of the dummy pixel and in contact with the dummy light emitting element.

[0158] At least a portion of the dummy pixel may overlap the dummy pixel driving circuit in a thickness direction of the mother substrate.

[0159] The mother substrate may also include: a dummy driver, in which one or more of the one or more dummy pixel driving circuits are integrated; a first connecting portion, which connects the solder pattern of the dummy pixel to the first terminal of the dummy driver; and a second connecting portion, which connects the conductive ring to the second terminal of the dummy driver.

[0160] The solder pattern of the dummy pixel may overlap the dummy pixel driving circuit in a thickness direction of the mother substrate.

[0161] At least a portion of the second connection portion may overlap the dummy pixel driving circuit in a thickness direction of the mother substrate.

[0162] According to one or more embodiments of the present disclosure, a mother substrate for a display panel may include: a driving driver, the driving driver including one or more pixel driving circuits arranged in a display area; a conductive ring, the conductive ring is arranged in a non-display area outside the display area and surrounds the display area; and a dummy driver, the dummy driver is arranged in the non-display area outside the display area. The driving driver of the display area and the dummy driver of the non-display area may include electrostatic protection circuits identical to each other. The conductive ring may be electrically connected to the electrostatic protection circuit of the dummy driver via wiring.

[0163] According to one or more embodiments of the present disclosure, a display panel may be separated from a mother substrate for the display panel at its final manufacturing stage and include a display area and a pixel driving circuit but not a conductive ring and a dummy pixel driving circuit.

[0164] According to one or more embodiments of the present disclosure, the display panel is separated from the mother substrate for the display panel at its final manufacturing stage, and includes the display area and the driving driver but does not include the conductive ring and the dummy driver.

[0165] The object achieved by the present disclosure, means for achieving the object, and the effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0166] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A mother substrate, comprising: a plurality of display areas, the plurality of display areas including a plurality of light emitting areas provided with light emitting elements, a plurality of wirings, and a plurality of pads connected to the plurality of wirings; a pixel driving circuit, the pixel driving circuit being arranged in the display area and comprising a static electricity prevention structure; a conductive ring disposed in a non-display area outside the display area and surrounding each of the plurality of display areas; as well as one or more dummy pixel driving circuits, wherein the one or more dummy pixel driving circuits are arranged in the non-display area outside the display area, The dummy pixel driving circuit has the same static electricity prevention structure as the pixel driving circuit.

2. The mother substrate according to claim 1, wherein: The dummy pixel driving circuit is disposed in a non-display area between the conductive ring and the display area.

3. The mother substrate according to claim 1, wherein: The dummy pixel driving circuit is disposed in a non-display area outside the conductive ring.

4. The mother substrate according to claim 1, wherein: The conductive rings surrounding each of the plurality of display areas are separated from each other.

5. The mother substrate according to claim 2, further comprising: a first insulating layer, wherein the first insulating layer covers at least a portion of the pixel driving circuit and the dummy pixel driving circuit; a first wiring pattern, the first wiring pattern being disposed on the first insulating layer; a second insulating layer formed on the first wiring pattern; as well as a second wiring pattern, the second wiring pattern being disposed on the second insulating layer and being electrically connected to the dummy pixel driving circuit and the conductive ring via a plurality of contact holes formed on the second insulating layer, Wherein, the second wiring pattern comprises: a first connection portion connected to the dummy pixel driving circuit; and a second connection portion connected to the conductive ring, and The first connection portion and the second connection portion of the second wiring pattern are separated from each other without being directly connected.

6. The mother substrate according to claim 5, further comprising: a third insulating layer formed on the second wiring pattern; as well as A third wiring pattern is provided on the third insulating layer and is electrically connected to the first connection portion via at least one contact hole formed on the third insulating layer.

7. The mother substrate according to claim 6, further comprising: a bank pattern, the bank pattern being disposed on the third insulating layer, wherein the third wiring pattern is formed to cover the bank pattern, and The mother substrate further includes a solder pattern formed on the bank pattern.

8. The mother substrate according to claim 6, wherein: At least a portion of the third wiring pattern overlaps the conductive ring.

9. The mother substrate according to claim 1, further comprising: A dummy pixel is provided with a dummy light emitting element in the dummy pixel, wherein the dummy light emitting element is provided in the non-display area and connected to the dummy pixel driving circuit.

10. The mother substrate according to claim 9, wherein: The dummy pixel includes a bank pattern of the dummy pixel, and a solder pattern disposed on the bank pattern of the dummy pixel and in contact with the dummy light emitting element.

11. The mother substrate according to claim 9, wherein: At least a portion of the dummy pixel overlaps the dummy pixel driving circuit in a thickness direction of the mother substrate.

12. The mother substrate according to claim 10, further comprising: a dummy driver in which one or more of the one or more dummy pixel driving circuits are integrated; a first connection portion connecting the solder pattern of the dummy pixel to a first terminal of the dummy driver; as well as A second connection portion connects the conductive ring to a second terminal of the dummy driver.

13. The mother substrate according to claim 12, wherein: The solder pattern of the dummy pixel overlaps the dummy pixel driving circuit in a thickness direction of the mother substrate.

14. The mother substrate according to claim 12, wherein: At least a portion of the second connection portion overlaps the dummy pixel driving circuit in a thickness direction of the mother substrate.

15. A display panel, wherein: The display panel is separated from the mother substrate according to any one of claims 1 to 14 for the display panel at its final manufacturing stage, and includes the display area and the pixel driving circuit, but does not include the conductive ring and the dummy pixel driving circuit.

16. A mother substrate, comprising: A driving driver, the driving driver comprising one or more pixel driving circuits arranged in the display area; a conductive ring, the conductive ring being disposed in a non-display area outside the display area and surrounding the display area; as well as a dummy driver, the dummy driver being arranged in a non-display area outside the display area, The driving driver of the display area and the dummy driver of the non-display area include the same electrostatic protection circuits, and The conductive ring is electrically connected to the electrostatic protection circuit of the dummy driver via wiring.

17. A display panel, wherein: The display panel is separated from the mother substrate for the display panel according to claim 16 at its final manufacturing stage, and includes the display area and the driving driver but does not include the conductive ring and the dummy driver.

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