Multi-die panel level high performance computing component

Abstract

Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores include dielectric layers with interconnect structures (vias, conductive traces) to convert die-level leads arranged at fine pitches to panel-level leads arranged at thicker pitches. Local interconnects and local interconnect components provide electrical communication between integrated circuit dies in the panel. The coreless panel architecture may include a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer may have interconnect structures and local interconnect features. Panel embodiments having a glass core or glass reinforcement layer may include waveguides and channels through which liquid coolant passes, and may further include photonic integrated circuits. The panel-level manufacturing technique may cause the panel to have a size greater than (e.g., greater than 300 mm) a component manufactured using the wafer-level manufacturing technique.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and priority from, U.S. utility patent application No. 17 / 871,443, filed on July 22, 2022, and entitled “MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS.” The disclosure of the prior application is considered part of the disclosure of the present application and is hereby incorporated by reference in its entirety into the disclosure of the present application. Background Art

[0003] As the technical challenges of high-performance computing (HPC) continue to increase, heterogeneous integration extensions have become an important performance enabler. Heterogeneous integration extensions can include components with increased die volume, increased interconnect density, increased bandwidth, and improved power efficiency. As a result, many different advanced packaging architecture solutions have been deployed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An example HPC package in which a panel architecture is implemented is illustrated in accordance with various embodiments.

[0005] Figure 2 is a simplified cross-sectional illustration of an example multi-die architecture providing reference for the presented embodiments.

[0006] Figure 3 is a simplified cross-sectional illustration of an example panel architecture with a glass reinforcement layer in accordance with various embodiments.

[0007] Figure 4A is a simplified cross-sectional illustration of a first example local interconnect feature.

[0008] Figure 4B is a simplified cross-sectional illustration of a second example local interconnect feature.

[0009] Figure 4C is a simplified cross-sectional illustration of a third example local interconnect feature.

[0010] Figure 4D is a simplified top view of a third example local interconnect component.

[0011] Figure 5 is a simplified cross-sectional illustration of a panel architecture with a photonic integrated circuit implemented in a glass reinforcement layer according to various embodiments.

[0012] Figure 6 is a simplified cross-sectional illustration of a panel architecture with microchannels implemented in a glass reinforcement layer according to various embodiments.

[0013] Figure 7 is a simplified cross-sectional illustration of an example conductive contact as may be implemented in various embodiments.

[0015] Figure 8-9 is a simplified cross-sectional diagram illustrating a process flow for fabricating a panel-level HPC system using a panel architecture in accordance with various embodiments.

[0016] Fig.10 is a first example method of forming a panel.

[0017] Fig.11 is a second example method of forming a panel.

[0018] Fig.12 is a third example method of forming a panel.

[0019] Fig.13 is a simplified cross-sectional illustration of a portion of an example panel substrate including a glass core.

[0020] Fig.14 is a simplified cross-sectional illustration of an example panel assembly including a panel including a glass core and local interconnect components positioned within a set of dielectric layers of the panel.

[0021] Fig.15 is a simplified cross-sectional illustration of an example panel including a glass core with local interconnect components located within the glass core.

[0022] Fig.16 is a simplified cross-sectional illustration of an example panel including a glass core and a photonic integrated circuit.

[0023] Fig.17 is a simplified cross-sectional illustration of an example panel including a glass core, a photonic integrated circuit, and local interconnect features located in a dielectric layer.

[0024] Fig.18 is a simplified cross-sectional illustration of an example panel including a glass core, a photonic integrated circuit, and local interconnect components located in the glass core.

[0025] Fig.19 is a simplified cross-sectional illustration of an example panel including a glass core with microchannels and a photonic integrated circuit.

[0026] Fig. 20 is a simplified cross-sectional illustration of an example panel including a glass core with microchannels, a photonic integrated circuit, and local interconnect features located in a dielectric layer.

[0027] Fig.21 is a simplified cross-sectional illustration of an example panel including a glass core having microchannels, a photonic integrated circuit, and local interconnect components located in the glass core.

[0028] Fig. 22 is a simplified cross-sectional illustration of an exemplary coreless panel.

[0029] Fig.23 is a simplified cross-sectional illustration of an example coreless panel including local interconnect components.

[0030] Fig.24 is a simplified cross-sectional illustration of an example coreless panel including a photonic integrated circuit.

[0031] Fig.25 is a simplified cross-sectional illustration of an example coreless panel including a photonic integrated circuit and local interconnect components.

[0032] Fig.26 is a fourth example method of forming a panel.

[0033] Fig. 27 is a top view of a wafer and die that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0034] Fig.28 is a simplified cross-sectional side view illustrating an implementation of an integrated circuit on a die that may be included in various embodiments according to any of the embodiments disclosed herein.

[0035] Fig.29 is a cross-sectional side view of a microelectronic assembly that can include any of the embodiments disclosed herein.

[0036] Fig.30 is a block diagram of an example electrical device that may include any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0037] As the technical challenges of high-performance computing (HPC) continue to increase, heterogeneous integration expansion has become an important performance enabler. Heterogeneous integration expansion can include increased interconnect density, increased number of integrated circuit dies per package, increased bandwidth, and improved power efficiency. Therefore, in response to higher data bandwidth requirements, many different advanced packaging architecture solutions have been deployed to increase planar and three-dimensional (3D) input / output (I / O) line density and area density, and enable more efficient die decomposition and heterogeneous integration to shorten time to market. Other technical solutions to HPC challenges include 2.5D / 3D advanced packaging technologies, such as die embedding and / or the use of local interconnect components to provide interconnections between dies (e.g., silicon (Si) interposers or bridges), so as to enable significantly higher packaged integrated circuit die and I / O counts and densities, thereby meeting HPC market segment needs and product performance requirements.

[0038] Applications that rely on extremely high performance computing include those expected to perform at 10 petaflops (10 21 Floating point operations). These applications may be referred to as zettascale performance applications. Non-limiting examples of zettascale performance applications include supercomputing, autonomous driving, and machine learning. Implementing a platform with zettascale performance capabilities presents technical challenges, and it is expected that packaging and system-level architecture innovations will be developed to achieve this performance level. The proposed technical solutions include system-level heterogeneous integration of computing, I / O, memory, power management, and thermal management components. Some available high-performance computing solutions include implementing system-level architectures on a chip (also referred to as wafer-level system integration, or wafer-level solutions). However, wafer-level system integration introduces several technical challenges. As can be appreciated, wafer-level system integration has a package that is limited in size by the diameter of the wafer. Additionally, wafer-level system integration puts a complete system on one wafer; therefore, solving the yield problem of wafer-level solutions may become very challenging.

[0039] The embodiments disclosed herein propose technical solutions to the above-mentioned technical problems in the form of panel-level components (referred to herein individually as "panels") and systems including panels or panel-level components. Embodiments of the panel may include multiple components (e.g., integrated circuit components) assembled using panel-level manufacturing techniques. As used herein, the term "panel-level" manufacturing technology refers to a manufacturing technology as described below: wherein integrated circuit dies are assembled and interconnections between them are formed on a single substrate and / or carrier, thereby creating an overall structure. If the overall structure includes multiple panels, the overall structure is singulated into individual panels. The overall structure can be packaged before singulation (e.g., by overmolding), or the individual panels can be packaged after singulation. In application, one or more of the panels can be assembled to create a multi-panel architecture or panel assembly, as described in more detail below. The area of ​​an individual panel (and a multi-panel architecture or component) can be less than, equal to, or greater than the area of ​​a wafer on which any one of the individual integrated circuit dies of the panel may have been formed.

[0040] Embodiments include various panel architectures. The panel architecture includes interconnect structures (e.g., conductive traces, vias) for routing die-level signals to package-level signals and local interconnects for routing signals between integrated circuit dies. Some panel architectures include a glass layer (or glass core), wherein a dielectric layer is located on one side or both sides of the glass layer. Other panel architectures do not include a glass layer. The dielectric layer (in some embodiments together with the glass layer) includes an interconnect structure. Panel architectures including and not including a glass layer may be referred to as "core" and "coreless" architectures, respectively, herein. Some panel architectures including coreless architectures are assembled on a glass carrier, which provides mechanical rigidity and a flat surface on which a panel can be manufactured. One benefit of the mechanical rigidity that a glass carrier (or glass reinforcement layer) can provide is to limit the amount of warping that a panel may experience during manufacturing or in the field. Some panel architectures assembled on a glass carrier may include a glass layer (also referred to as a glass reinforcement layer herein) to provide additional mechanical rigidity to the panel. The thickness of the glass reinforcement layer may be thinner than the glass layer used in the core panel architecture. Thus, a panel manufactured on a glass carrier and having a glass reinforcement layer can be thinner than other panels having a glass layer and manufactured without a glass carrier.

[0041] The provided panel architecture provides several technical and economic advantages, first of all, design support for panel-level solutions that have larger areas than available wafer-level (300 mm diameter wafer size) solutions; although wafer-level integration may limit packaged HPC solutions to an area of ​​approximately 215 millimeters (mm) × 215 mm, in some embodiments, the individual panels disclosed herein can reach an area in the range of approximately 250 mm × 250 mm to approximately 600 mm × 600 mm, and in other embodiments, the individual panels can exceed 600 mm × 600 mm in area. Additionally, a single panel can provide a panel-level HPC solution; however, in other embodiments, the individual panels can be further assembled into larger HPC solutions, such as Figure 1 As shown in the figure.

[0042] Other non-limiting examples of the advantages of the provided panel architecture include support for design redundancy (creating multi-die structures by assembling smaller known good dies (KGDs)), additional mechanical rigidity and capacity for fine pitch geometries supported by glass reinforcement layers, interconnect structures for intra-panel die-to-die or chiplet-to-chiplet communications, cavities in the glass reinforcement layers to accommodate discrete device integration (e.g., discrete devices such as deep trench capacitors, capacitors, transistors, magnetic inductor arrays (MIA), inductors, etc.), flexible thermal management, and the flexibility to vertically integrate integrated circuit dies and other components into the panel. Additionally, embodiments may use a glass carrier to provide improved flatness and mechanical rigidity to the panel during manufacturing and assembly. These concepts are expanded upon in more detail below.

[0043] Hereinafter, example embodiments will be described in conjunction with the following drawings, wherein the same reference numerals designate the same elements. The drawings are not necessarily to scale, but may rely on the spatial orientation and relative positioning of features. As can be appreciated, specific terms, such as "ceiling" and "floor", as well as "upper", "uppermost", "lower", "above", "below", "bottom" and "top" refer to the direction of the drawings to which reference is made based on observation. Further, terms such as "front", "rear", "tail", "side", "vertical" and "horizontal" may describe the orientation and / or position of parts of components in a consistent but arbitrary reference system, which becomes clear by reference to the text and associated drawings describing the components in question. Such terms may include the words specifically mentioned above, their derivatives and words of similar meaning.

[0044] As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other, with no layers or components between them. For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase "located on..." (alternatively, "located below...", "located above / above...", or "located next to..." in the context of a first layer or component located on a second layer or component) includes (i) configurations in which a first layer or component is directly physically attached to a second layer (i.e., adjacent), and (ii) components and configurations in which a first layer or component is attached (e.g., coupled) to a second layer or component via one or more intermediate layers or components.

[0045] Terms modified by the word "substantially" include arrangements, orientations, spacings, or positionings that vary slightly from the meaning of the unmodified term. For example, a portion of a first layer or feature that is substantially perpendicular to a second layer or feature may include a first layer or feature that is + / -20 degrees from the second layer or feature, and a first surface that is substantially parallel to a second surface may include a first surface that is within a certain degree of parallelism to the second surface. The amount of variation covered by the terms modified by the term "substantially" is used throughout the text to indicate a specific arrangement, orientation, spacing, positioning, etc. Values ​​modified by the word "approximately" include values ​​within a range of + / -10% of the described value, and values ​​listed as being within a range include values ​​within a range of 10% less than the lower limit of the described range and 10% greater than the upper limit of the described range.

[0046] As used herein, the term "electronic component" may refer to an active electronic circuit (eg, a processing unit, a memory, a storage device, a FET) or a passive electronic circuit (eg, a resistor, an inductor, a capacitor).

[0047] As used herein, the term "integrated circuit component" may refer to an electronic component that is configured on a semiconductor material to perform a function. An integrated circuit (IC) component may include any computing system component described or referenced herein or one or more of any other computing system components, such as a processor unit (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0048] A non-limiting example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die (referred to herein simply as a "die"); the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts may enable the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0049] Non-limiting examples of packaged integrated circuit components include one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit dies and the packaging substrate are sealed in a housing material such as metal, plastic, glass, or ceramic. The housing often includes an integrated heat sink (IHS); the packaged integrated circuit component often has bumps, leads, or pins attached to the packaging substrate (directly or by wires that attach the bumps, leads, or pins to the packaging substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or substrate) or another component.

[0050] The following detailed description is not intended to limit the application and use of the disclosed technology. It can be obvious that new embodiments can be practiced without every detail described herein. For the sake of brevity, well-known structures and devices can be shown in block diagram form to facilitate description thereof.

[0051] Embodiments of the provided panel architecture are directed to solving technical problems faced in providing HPC or zettascale performance to applications by using panels. In some embodiments, an HPC solution may include a single panel of the provided architecture. In other examples, such as Figure 1 As illustrated in FIG. 1 , the HPC solution is implemented using a panel assembly 100 that includes a plurality of panels of a provided panel architecture that are assembled.

[0052] exist Figure 1 In the non-limiting example of , the panel assembly 100 includes four assembled panels (panel 102, panel 104, panel 106, and panel 108), where the four panels are assembled to form the panel assembly 100, the individual panels may be referred to as "sub-panels" or "panel quads" or "quad panels". However, the panel assembly 100 may include more or less than four panels and panels arranged in any manner (e.g., square (e.g., 2×2, 4×4, 6×6), rectangular (e.g., 2×4, 3×5, 4×7)). The panels of the panel assembly 100 may be attached to a panel-level substrate 112. The panel-level substrate 112 may include a printed circuit board, a film substrate, or another suitable substrate. In various embodiments and HPC solutions, individual panels or the entire panel assembly 100 may be overmolded using a sealant 110. The sealant 110 may include a molding compound, a dielectric material, a metal, a ceramic, a plastic, or a combination thereof.

[0053] In various embodiments, individual panels of panel assembly 100 may have an area in the range of approximately 250-300 mm x 250-300 mm (eg, see Figure 1 ). In other embodiments, the individual panels of the panel assembly 100 may have an area in the range of approximately 450-600 mm x 450-600 mm or larger. That is, the lateral dimension of the panel (the dimension of the panel orthogonal to the panel thickness) may be 250-300 mm in some embodiments, and 450-600 mm in other embodiments. In other embodiments, the individual panels may be smaller or larger. For example, in some embodiments, the lateral dimension of the panel is greater than 250 mm.

[0054] The boxes drawn inside each of the panels indicate separate unpackaged integrated circuit dies (e.g., die 114, die 116, die 118, and die 120). Unpackaged integrated circuit dies (die 114, die 116, die 118, and die 120) may also be referred to as chips, chiplets, chip complexes, or chiplet complexes. Although the terms die, chip, and chiplet may be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a functional subset of a larger integrated circuit component, which is formed using one or more chiplets connected by inter-die interconnects (e.g., interposers, bridges, local interconnect components, local silicon interconnects). As feature sizes have decreased and the demand for higher performance larger integrated circuit components has increased, the use of chiplets in integrated circuit components has become attractive. The method of assembling multiple known good dies (chiplets) to form larger integrated circuit components results in improved manufacturing efficiency because the overall yield of integrated circuit components assembled from multiple chiplets is better than the yield of integrated circuit components in which chiplet functionality is implemented on a single large integrated circuit die. Any integrated circuit die, chip, or chiplet may implement any portion of the functionality of any processor unit described or referenced herein.

[0055] Although the illustrations depict the chiplets within and among panels as having uniform sizes, in practice, the chiplet sizes (lateral dimensions and thickness) and shapes within and across panels may vary among chiplets; further, the chiplets on a given panel may vary by type / functionality (e.g., compute, memory, I / O, power management (controlling power delivery and / or powering components)). In a non-limiting example, each of the panels includes 12 dies arranged in a 4×3 array, although other numbers of dies per panel, as well as other die arrangements within panels, are also supported. Additionally, the integrated circuit component die area and die height within a given panel may vary. Further, the panels may have any shape, such as a substantially non-circular shape (e.g., a substantially square shape, a substantially rectangular shape (such as panels 102, 104, 106, 108)), or a substantially circular shape.

[0056] As described in more detail below, in some embodiments, panel assembly 100 may be co-packaged with other electronic components or optical interconnects or waveguides, and may support a photonic integrated circuit (PIC) of a panel attached or connected thereto. In some embodiments, the other electronic components or PICs may be located external to the panel, such as indicated by position 122. In other embodiments, a panel of the panel assembly may have its substrate etched with a waveguide, and may further include one or more other electronic components or PICs in a keep-out zone of the panel, such as indicated by position 124 of panel 108, for example.

[0057] The panel may take the form of a populated or unpopulated panel substrate. Both the populated and unpopulated panel substrates are configured (e.g., configured with appropriate pinouts) to communicatively couple associated integrated circuit dies to one another (e.g., via fine pitch redistribution layers, conductive traces, or local interconnect features such as Figure 4A bridge shown in the figure).

[0058] The shear line A-A' is the combination Figure 2 , 3 , 5, 6, and 13-25 for intra-panel (i.e., inside a panel) architectural discussions. Cut line BB' provides a reference for inter-panel (i.e., between panels) architectural discussions such as creating a panel component, in Fig. 9 Referenced again in .

[0059] Figure 2 A simplified cross-sectional illustration of a portion 200 of a panel is provided as a reference for discussion of general panel architecture, and Figure 3-9 The embodiments illustrated in 13-25 provide for Figure 2 Technical improvements to the general panel architecture of the Figure 2 Many of the components in Figure 3-9 and 13-25, as observable using comparisons of shape, position, and context.

[0060] For example, the interconnect structures (vias, conductive traces) 228, 328, 428, 528, 628, 728, 828, 1328, 2228, etc. are similar; the build-up layers (or alternatively, redistribution layers (RDL) or dielectric layers) 222, 322, 422, 522, 622, 722, 822, 1322, 2222, etc. are similar; the build-up layers, dielectric or redistribution layers 224, 324, 424, 524, 624, 724, 824, 1324, 2224, etc. are similar; conductive pads (or contacts) 232, 332, 532, 632, 1332, 2232, etc. are similar; conductive contacts 226, 326, 526, 626, 1326, 2226, etc. are similar; upper surface contact layers 256, 356, 1356, 2256 are similar; lower surface contact layers 260, 360, 1360, 2260 are similar; thermal management solutions 209, 96 0, 962, 1409, 1509, 2309 are similar; glass reinforcement layers 350, 550, 650, etc. are similar; glass cores 1351, 1451, 1551, etc. are similar; interconnect structures in the form of through-glass vias 352, 552, 652, 1352, etc. are similar; solder resist or dielectric materials 212, 312, 512, 612, 1312, 2212, etc. are similar; solder resist or dielectric materials 218, 318, 5 18, 618, 1318, 2218, etc. are similar; microchannels 668, 1968, 2068, etc. are similar; local interconnect components 234, 334, 434, 534, 634, 1434, 2334, 2434, etc. are similar; waveguides 564, 1664, 2464, etc. are similar, photonic integrated circuits 562, 1662a, 1662b, 1762a, 1762b, 2462, 2562, etc. are similar, FAUs 1621a, 1621b, 1721a, 172b, 2421 and 2521, etc. are similar, etc. Further, those skilled in the art will appreciate that although some object numbers are omitted in some figures to simplify clutter, objects that share the same shape, location and / or context with labeled objects in other figures are similar (e.g., include the same material, have the same size, possess the same properties). Figure 3-7 and 13-25 focus on the (in-panel) panel architecture of unpopulated panels, and Figure 8-9 Filling and encapsulating the panels is described.

[0061] As used herein, "pitch" means the physical distance at which a feature is repeated (e.g., the space from the center of one instance of a feature to the center of an adjacent instance of the feature). For example, on surface 203, conductive contacts 226 have a pitch 240, and on surface 205, conductive pads 232 have a pitch 242.

[0062] As used herein, "fine pitch" generally means the pitch of the die scale, as indicated on surface 203, and "coarse pitch" generally means the package level pitch, as indicated on surface 205. The fine pitch size may include a range of approximately 0.001 mm to approximately 0.3 mm. In some embodiments, features with fine pitch have a size of approximately 1 μm (micrometer) or less. In other embodiments, features with fine pitch may have a size of approximately 0.5 μm or less. In addition to conductive contacts used to attach an integrated circuit die to a panel, other features in the panel that may have fine pitch include vias in one or more RDLs adjacent to the leads of the integrated circuit die. The fine pitch geometry is smaller than the "coarse pitch" geometry.

[0063] As indicated on surface 205, "coarse pitch" 242 generally refers to the geometry associated with package-level conductive pads 332 (or contacts 332); the coarse pitch may be a ball grid array (BGA) pitch or a land grid array (LGA) pitch. In various embodiments, the BGA pitch is in the range of about 0.1 mm to about 1 mm, and the LGA pitch is in the range of about 0.1 mm to about 1 mm. Additionally, as generally represented in the figures, the thickness of the conductive traces of the RDL adjacent to the package-level conductive contacts or conductive pads 332 at surface 205 may be thicker than the conductive traces in the RDL adjacent to the leads of the integrated circuit die at surface 203.

[0064] In some embodiments, the pitch at surface 203 is less than the pitch at surface 205, and in some embodiments, the pitch at surface 203 is the same as the pitch at surface 205. Conductive contacts 226 and conductive pads 232 may include solder, copper, or another suitable metal or other material.

[0065] Reference is made herein to buildup layers or redistribution layers (RDLs) (e.g., 222, 322, 422, 522, 622, 722, and 822). Although the accompanying drawings illustrate two RDL 222 sublayers and two RDL 224 sublayers, in practice, any number of RDL sublayers may be present. For example, in server applications, the RDL may include up to 10 sublayers. In various embodiments, the RDL includes a dielectric material and may include a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, which is a material including silicon, oxygen and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material including fluorine, silicon and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, which is a material including silicon, oxygen and hydrogen). In some embodiments, the RDL includes a photoimageable dielectric (PID). In some embodiments, the RDL includes an Ajinomoto build-up film (often referred to as an ABF), which is a material including an organic resin matrix having different types of fillers (e.g., silica fillers of different sizes or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk) and / or dissipation factor (insertion loss) (Df)) of the RDL.

[0066] In some embodiments, it is advantageous for the RDL to have a CTE that matches the CTE of the integrated circuit die attached to the panel substrate (e.g., matches the CTE of silicon). In some embodiments, the dielectric material of the RDL can have a CTE that is close to (e.g., within 10%) the CTE of silicon. In other embodiments, the dielectric material of the RDL can be any type of epoxy molding compound. The RDL or buildup layer can include a metal layer having conductive traces (or metal lines), and the metal used for the interconnect metal in the RDL includes copper or other suitable metals.

[0067] Local interconnect components and interconnect structures are related herein. As used herein, local interconnect components refer to components of separate manufacturing that route signals between dies within a panel. In contrast, external interconnect components can be used to route signals between panels. As used herein, "interconnect structures" may include one or more conductive traces, one or more through-holes, or a combination thereof. The term conductive trace may refer to a through-hole contact, which may be a metal line to which a through-hole is connected, and does not include a lateral signal routing portion. The interconnect structure may be present in various RDLs, dielectric layers, build-up layers, or glass layers, and may span multiple such layers. The interconnect structure may collectively provide a conductive path from a feature on the first surface 203 of the panel substrate 201 to a feature on the second surface 205 of the panel substrate. In various embodiments, the interconnect structure in the first dielectric layer is attached to the interconnect structure in the second dielectric layer, thereby providing a conductive path through the substrate.

[0068] Portion 200 relates to cut line A-A' and includes substrate 201. Substrate 201 may have a thickness 210 in the range of substantially 0.05 mm to substantially 3 mm, where substantially equals + / - 10%), and may include one or more buildup or redistribution layers 214, 216, 218, and 220. Region 202 (column on the left side of the page) provides signal communications and conversion routing (e.g., converting fine pitch die-level signals to coarser pitch panel-level signals) for die or chiplets 204 attached at upper surface 203, and on the right side, region 206 provides signal communications and conversion routing for die or chiplets 208 attached at upper surface 203. For individual ones of the one or more chiplets that are part of portion 200, solder resist or other dielectric material 212 on the upper substrate surface may be patterned with corresponding pinouts (physical arrangement of conductive contacts 226 at corresponding pitches). The corresponding pinouts may include individual conductive contacts 226 arranged as conductive contacts of individual chiplets or dies (e.g., die 204 and die 208). In some embodiments, the conductive contacts 226 are arranged in the upper surface contact layer 256 as two distinguishable sets having the same pitch (e.g., die pitch or fine pitch), however, in other embodiments, the conductive contacts 226 are arranged as two sets that do not have the same die pitch or fine pitch. Further, the conductive contacts associated with one die may be arranged at more than one pitch. Some signal routing may occur from at least one conductive contact in the first conductive contact 226 set (e.g., die 204) to at least one conductive contact in the second conductive contact 226 set (e.g., die 208) via the local interconnect component 234. Some of the through-holes 228b may be arranged at a fine pitch to match the pitch of the conductive contacts 226.

[0069] In various embodiments, RDL 222 includes features (e.g., interconnect structures including metal lines and vias) having a finer pitch than the pitch of features in RDL 224. Thus, RDLs 222 and 224 can be considered to translate the tighter pitch of the die pads (matching the pitch of conductive pads 226) to the larger pitch of the panel pads (matching the pitch of conductive pads 232). Although RDL 222 is depicted as including two layers, RDL 214 and RDL 216, and RDL 224 is depicted as including two layers, RDL 218 and RDL 220, in practice, the number of layers in RDL 222 and RDL 224 may vary. Those skilled in the art will appreciate that in this discussion, distinctions in the various dielectric or buildup layers attributed to RDL 222 and RDL 224 have been introduced for illustrative purposes; in a cross-sectional image of substrate 201, such as by transmission electron microscopy (TEM), layers 212, 214, 216, 218, and 220 may be indistinguishable.

[0070] For illustrative purposes, RDL 222 includes interconnect structure 228, and RDL 224 includes interconnect structure 230. Interconnect structure 228 may be arranged within RDLs 214 and 216 to route electrical signals according to a wide variety of applications; in particular, the arrangement is not limited to Figure 2 . In some embodiments, the interconnect structure 228 may include conductive traces or metal wires (wires) and / or via contacts 228a and vias 228b. The conductive traces, via contacts, and vias may include conductive materials such as metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof). The wires of the interconnect structure 228a may be arranged to route electrical signals along a surface that is substantially parallel to the surface 203 of the substrate 201. For example, the wires of the interconnect structure 228a may route electrical signals in directions into and out of the page and / or in directions across the page. The vias 228b may be arranged to route electrical signals in a planar direction that is substantially perpendicular to the surface of the substrate 201. Likewise, the interconnect structure 230 may include conductive traces or lines and / or via contacts 230a and / or vias 230b, which include conductive materials such as metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof). The lines of the interconnect structure 230a may be arranged to route electrical signals in a direction substantially parallel to the surface 203 of the substrate 201. For example, the lines 230a may route electrical signals in directions into and out of the page and / or in a direction across the page. The vias 230b may be arranged to route electrical signals in a planar direction substantially perpendicular to the surface of the substrate 201.

[0071] The local interconnect component 234 is used to communicatively couple the chiplets 204 and 208. The substrate 201 can be part of a filled or unfilled product. In various filled embodiments, there can be components indicated in the area 290 attached at the upper surface 203 of the substrate 201. For example, the filled panel substrate can be filled with corresponding tube cores or chiplets (e.g., 204, 208), which can be attached via conductive tube core bumps 238 or any solder or hybrid bonding (bonding components through the bonding of interconnections and dielectric layers of components (direct attachment)). In some embodiments, polymers can be used to bond copper conductive contacts (e.g., pads) on the tube core to copper conductive contacts (e.g., 226) of the panel substrate. In some embodiments, polymers can also be used to bond solder conductive contacts on the tube core to solder conductive contacts on the panel substrate. In some embodiments, inorganic materials (e.g., silicon dioxide, silicon nitride) can be used to bond the copper conductive contacts of the components together. In some embodiments, the die is attached to the substrate 201 by direct attachment of bumps (e.g., microbumps) attached to both surfaces (e.g., die surface, panel surface). In some embodiments, the chiplet also has an underfill (not shown) applied below the chiplet and above the surface of the substrate 201. A large form factor thermal management solution 236 can be implemented, which includes cooling components such as a vapor chamber, a heat pipe, a heat sink, or a liquid-cooled cold plate. The thermal management solution is a large form factor solution because it can be a panel-level thermal management solution (providing cooling to the integrated circuit die of a panel) or a multi-panel thermal management solution (providing cooling to the integrated circuit die of multiple panels). As part of the thermal management solution, a thermally conductive layer interface material (TIM) can be located above the die 204, 208. The TIM can be any suitable material, such as a thermal compound filled with silver particles, thermal grease, phase change material, indium foil, or graphite sheet. The thermal management solution can be a conformal solution that accommodates differences in the height of the integrated circuit die for which the thermal management solution provides cooling. For example, the thermal management solution may include a substantially planar cooling component and a TIM of varying thickness between the cooling component and the integrated circuit die. In another example, the cooling component is non-planar and the profile of the cooling component may vary with the thickness of the integrated circuit die for which the cooling component provides cooling. In such an embodiment, the TIM may have a substantially uniform thickness between the cooling component and the integrated circuit die of varying thickness. The thermal management solution may also include an integrated heat sink. Fig. 9 An example of a panel with a thermal management solution is provided.

[0072] Now go to Figure 3, embodiments of the provided panel architecture include a glass reinforcement layer between dielectric layers or RDLs of a substrate. The simplified cross-sectional illustration of portion 300 relates to cut line AA' and includes substrate 301. Substrate 301 includes a glass reinforcement layer 350 sandwiched between dielectric layer or RDL 322 and dielectric layer or RDL 324. In various embodiments, the overall height of the substrate does not change (e.g., substantially 210, Figure 2 ), and RDLs 322 and 324 are thinned or omitted to accommodate glass reinforcement layer 350, the height / thickness 380 of which is in the range of about 30 microns to 1.5 mm ± 10%. Figure 2 By analogy with the objects in , RDL 322 may include multiple buildup layers, dielectric layers, or redistribution layers, and RDL 324 may include multiple buildup layers, dielectric layers, or redistribution layers. Also, by analogy, solder resist or other dielectric material 312 may be patterned to have lead-outs for corresponding one or more chiplets that may be attached to a substrate of a panel. The lead-outs may include individual conductive contacts 326 arranged at a fine pitch, and the upper surface contact layer 356 may also take the form of other embodiments (e.g., 726a, 726b), such as in combination with Figure 7 The lower surface contact layer 360 may also take the form of other embodiments (e.g., 760), such as in combination with Figure 7 Also as mentioned above, vias / contacts / traces / pads 328, 330, 360, and 332 are similar to counterparts 228, 230, 260, and 232. Local interconnect component 334 is similar to local interconnect component 234. Region 302 is dedicated to the first die, and region 306 is dedicated to the second die.

[0073] The glass reinforcement layer 350 may include glass (as used herein, the glass may be an alkali-free alkaline earth borosilicate alumino glass, such as a glass including aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium, such as a glass including SiO2, Al2O3, B2O3, and MgO), or a photosensitive glass (a photoprocessable or photostructurable glass). In some embodiments, the photosensitive glass may be a glass belonging to the lithium-silicate glass family (e.g., a glass including lithium, silicon, and oxygen), which includes metal particles, such as gold, silver, or other suitable metal particles. The glass reinforcement layer 350 may include a plurality of glass sheets (in a non-limiting example, three glass sheets 350-1, 350-2, and 350-3 are illustrated).

[0074] The glass reinforcement layer 350 may include some or all of the interconnect structures to support signal routing from the contacts 326 at the die surface (303) of the substrate 301 to the conductive pads 332. The interconnect structures may include through holes 352 in the glass layer 350, which may be referred to as through-glass vias (TGVs). The interconnect structures collectively provide a conductive path from features on the first surface 303 of the panel substrate 301 to other features on the first surface 303 and / or the conductive pads 332. The individual glass sheets 350-1, 350-2, and 350-3 may have respective dielectric layers (351-1, 351-2, 351-3) located on their lower surfaces to act as an adhesive layer to laminate the glass sheets over / on the solder resist or dielectric layer 354 having conductive contacts 358 and traces therein. Although those skilled in the art will appreciate that in practice, "layers" and "sheets" may be used interchangeably, these concepts are used here to help understand the embodiments.

[0075] In various embodiments, the thickness 362 of the glass sheets 350-1, 350-2, 350-3 can be substantially in the range of 20-150 microns, where substantially means + / - 5%. In some embodiments, the thickness of any of the glass sheets can be different from the thickness of any other glass sheet in the glass layer. In various embodiments, the dielectric layer 351 can include Ajinomoto built-up film (ABF), epoxy molding compound, any other dielectric layer mentioned or described herein, or any other suitable dielectric material. In various embodiments, the dielectric layer 351 can be substantially 10 microns thick.

[0076] The local interconnect component 334 in the glass reinforcement layer 350 facilitates communication between two or more chiplets in a portion of a substrate, panel, and / or panel assembly 100. The local interconnect component 334 may include an interposer (or bridge), or one or more redistribution layers (RDL). The local interconnect component 334 may be selectively located in the substrate. That is, in a panel including two dies connected by a local interconnect component (e.g., 334), the panel may further include adjacent dies that are not connected by a local interconnect component.

[0077] Figure 4A A simplified cross-sectional illustration of a first example local interconnect feature is illustrated. Figure 4A 4 is a simplified cross-sectional illustration of a portion 400 of a panel substrate including an RDL 422 and a first glass sheet 450 as part of a glass layer of the panel. The glass layer 450 may be a glass reinforcement layer (eg, 350, 550, 650) or may be a glass reinforcement layer (eg, 350, 550, 650). Figure 13-21The glass layer of a portion of the glass core in the embodiment of FIG. RDL 422 includes two constituent layers (sub-layers) 422a and 422b. Local interconnect component 434 (or bridge) is located in glass sheet 450 and provides interconnection between a first die attached to conductive contact 406 and a second die connected to conductive contact 408 (the first and second dies are not shown).

[0078] The bridge conductive contact 476 is located on the surface 474 of the local interconnect component 434. In various embodiments, the bridge conductive contact 476 includes copper. The local interconnect component 434 includes conductive traces 480a, 480b, 480c, and 480d located in the first, second, third, and fourth dielectric layers 492, 494, 496, and 498, respectively. The dielectric layers 492, 494, 496, and 498 further include through-holes 478 that provide connections between conductive traces in different dielectric layers or between conductive traces and the bridge conductive contact 476.

[0079] Bridge vias 478 and bridge conductive traces 480 may include copper or another suitable conductive material and provide a conductive path between bridge conductive contacts 476. Dielectric layers 492, 494, 496, 498, and 422 may be a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide, fluorine-doped silicon dioxide, hydrogen-doped silicon dioxide, or silicon nitride.

[0080] The interconnect structures (conductive traces 428a and vias 428b) in RDL 422 are similar to interconnect structures 328a and 328b and provide conductive paths from bridge conductive contacts 476 to conductive contacts 406 of the first die or chiplet and to conductive contacts 408 of the second die or chiplet. Vias 452 provide connections from the RDL interconnect structures to bridge conductive pads 476. In embodiments where the top surface 474 of local interconnect component 434 is flush with the top surface of the top glass sheet within the glass layer (e.g., surface 483), vias 452 may not be present.

[0081] In some embodiments, the area in one or more dielectric layers located above the local interconnect component may include an interconnect structure that provides a conductive path between the tube cores attached to the panel substrate. For example, area 487 in dielectric layer 422 includes conductive traces 428c and vias 428d that provide a conductive path between one of conductive contacts 406 and one of conductive contacts 408. In other embodiments, the area above the local interconnect component does not include routing that provides a conductive path between adjacent tube cores. Conductive contacts and traces / vias 406, 428a, 428b, 428c, 428d, 452, 476, 478, 480a, and 480b together provide a conductive path between the first and second tube cores, and thus allow the tube cores to be communicatively coupled.

[0082] In an example, two of the vias 478 connect conductive trace 480b to 480c, and 480c to bridge pad 480d, which in turn is connected to via 428e and conductive trace 428f located within glass layer 450. Thus, local interconnect component 434 may also provide a conductive path between the first and second dies to a conductive trace located in the glass layer below local interconnect component 434.

[0083] Figure 4B 4 is a simplified cross-sectional illustration of a second example local interconnect component. The local interconnect component 435 includes a through-silicon via (TSV) 452. The TSV 452 provides a conductive path from an interconnect structure (via 452) located adjacent to a top surface 474 of the local interconnect component 435 to an interconnect structure (via 454) located adjacent to a bottom surface 484 of the local interconnect component 435. In various embodiments, the TSV may include copper, tungsten, or another metal.

[0084] Figure 4B Further illustrated is a trench capacitor 456 located in the local interconnect component 435. The trench capacitor 456 includes a first terminal (one or more first capacitor conductive traces) 458, a second terminal (one or more second capacitor conductive traces) 458, and a capacitor dielectric 459 positioned between the first terminal 457 and the second terminal 458. The first and second terminals 457 and 458 include one or more conductive traces oriented substantially perpendicular to the top surface (e.g., upper surface 203) of the panel substrate in which the local interconnect component 435 is located. The capacitor dielectric 459 may include any of the dielectrics disclosed herein (e.g., doped or undoped silicon dioxide, silicon nitride) or any other suitable dielectric. The first and second terminals 457 and 458 are further connected to a conductive trace 486 of the local interconnect component, which allows connection to the capacitor 456 through an interconnect structure (e.g., via 452) external to the local interconnect component 435. In addition to trench capacitors, the local interconnect component may also include other types of capacitors, such as planar capacitors.

[0085] Figure 4C and 4D4 is a cross-sectional and top view illustration of a third example local interconnect component. Local interconnect component 437 includes a magnetic inductor array (MIA) 475. MIA 475 includes pads 477, vias 479, and conductive traces 481. Conductive traces 481 act as inductors and are surrounded by ferromagnetic material 491. Conductive traces 481 may include copper or another suitable metal, pads 477 may include nickel, palladium, and gold or another suitable metal or alloy, and ferromagnetic material 491 may include iron or an iron alloy. In some embodiments, ferromagnetic material 491 includes iron or iron alloy particles in an epoxy matrix.

[0086] In addition to TSVs, capacitors, and inductors (eg, MIAs), in other embodiments, local interconnect components 434 may include other passive components, such as resistors and / or active components, such as transistors.

[0087] As mentioned above, the local interconnect components located in the panel substrate (such as the local interconnect components 434 embedded in the portion 400 of the panel substrate) can be implemented as a silicon interposer (interposer) or a local silicon interconnect (local interconnect). In some embodiments, the local interconnect components can be Embedded Multi-die Interconnect Bridge (EMIB).In some embodiments, the local interconnect component may conform to the Universal Chiplet Interconnect Express (UCIe) standard.

[0088] The local interconnect components may be fabricated separately from the panel substrate and then located, integrated into, or embedded within the panel substrate. Separate fabrication of the local interconnect components allows the local interconnect components to be created using semiconductor fabrication techniques, thereby creating local interconnect components having internal features (e.g., vias, pads, conductive traces) having geometries (e.g., via width / space, conductive trace width / space / thickness) that may be smaller than the geometries of similar features external to the local interconnect components in the panel substrate.

[0089] The local interconnect component can be located in the panel substrate by forming a cavity in the panel substrate at a point during panel manufacturing (e.g., forming a cavity in a glass layer and / or one or more dielectric layers), inserting the local interconnect component into the panel substrate, and forming the remainder of the panel substrate. The local interconnect component can be located in a glass layer or one or more RDLs. The local interconnect component can span more than one RDL. The upper surface of the RDL can be flush with the upper surface on the RDL, including the upper surface of the RDL being part of the upper surface of the panel surface. As such, in the context of a local interconnect component located in a glass layer or one or more RDLs, the phrase "located" can refer to a local interconnect component that is fully embedded (the glass layer or one or more RDLs are positioned adjacent to all sides of the local interconnect component) or partially embedded (the glass layer or one or more RDLs are positioned adjacent to less than all sides of the local interconnect component).

[0090] In some embodiments, local interconnects that provide conductive paths between adjacent die in a panel may be provided by an interconnect structure that is part of one or more RDL layers that provide routing of die-level signals to package-level signals. That is, adjacent die in a panel may be interconnected without using separately manufactured local interconnect components that are placed in the panel substrate during panel manufacturing. Figure 4A Area 487, Fig.13 Area 1387, Fig.16 Area 1687, Fig.19 Area in 1987, Fig. 22 Area 2287 and Fig.24 Area 2487 in illustrates such a local interconnect.

[0091] refer to Figure 5 In various embodiments, panel assembly 100 may implement waveguide routing and / or silicon photonic components, such as photonic integrated circuits (PICs). The simplified cross-sectional illustration of portion 500 relates to cut line AA′ and includes substrate 501 . Figure 5 A photonic integrated circuit (PIC) 562 implemented in the panel architecture of portion 500 of the panel substrate 501 is illustrated, the photonic integrated circuit (PIC) 562 being implemented directly in the glass reinforcement layer 550. The PIC 562 and associated waveguide routing 564 outside the substrate 501 may also be implemented directly in the substrate 501, or directly in the glass reinforcement layer 550.

[0092] In these embodiments, the waveguide route 564 can be manufactured by laser direct writing in the glass sheet of the glass reinforcement layer 550. In an embodiment, the waveguide route 564 is a closed path formed or etched in the glass reinforcement layer 550, having a first end 565 and a second end 567. The waveguide route 564 is configured to passively allow light of a specific wavelength or wavelength range to travel therethrough. That is, in operation, the waveguide route 564 provides operable communication by receiving light from a first source (such as the PIC 562) at a first end 565, and passively transmitting the light to a second end 567, where the light can leave the waveguide route 564 (alternatively, the light can travel through the waveguide route in the opposite direction). In some embodiments, as illustrated, the waveguide route 564 has a first end 565 in operable communication with the PIC 562 and a second end 567 at the surface of the glass reinforcement layer. In various embodiments, as illustrated, with respect to Figure 5 , the second end 567 can be at a vertically oriented surface, and in other embodiments, about Figure 5 , the second end 567 may be at a laterally oriented surface. In various embodiments, there may be an optional optical coupling component 569 added to the surface at the second end 567 for attaching external components to the waveguide routing 564. Although in Figure 5 564 may be implemented as a two-dimensional or three-dimensional pattern having a uniform diameter and a total path length that may include curves and / or loops, where the total path length (generally from the first end 565 to the second end 567) reflects the particular application.

[0093] In some embodiments, the waveguide routing 564 may include a dielectric material having a higher dielectric constant, and therefore a higher refractive index, than the material surrounding the waveguide routing (glass reinforcement layer 550). In some embodiments, the waveguide includes silicon and oxygen. In some embodiments, the waveguide may include a photonic crystal fiber, a hollow tube with a reflective inner surface (e.g., a polished metal or multilayer film that guides light by Bragg reflection), or a small prism surrounding a hollow tube that reflects light via internal reflection.

[0094] Photonic integrated circuits implement one or more photonic functions and include one or more optical components, such as waveguides, lasers, electro-optic modulators, polarizers, photodetectors, and the like. PICs are often used in data communications (such as fiber optic communications) and sensing applications. Examples of the use of PICs include wavelength division multiplexing (WDM), interferometers, wave modulators, optical transceivers, light detection and ranging (LiDAR) antennas, and the like.

[0095] A non-limiting example of an optical component that may be included in a PIC is a silicon microring resonator (MRR), generally referred to herein as a ring resonator structure. A ring resonator structure is a passive structure that generally includes (i) a compact circular microring structure including an optical silicon waveguide that loops back on itself with a small bending radius to resonate at one or more frequencies referred to as the spectral response or free spectral range (FSR), and (ii) a linear silicon waveguide located near and in communication with the microring structure.

[0096] In various embodiments, the microring structure is substantially circular and the silicon waveguide is substantially linear (i.e., + / - 10%) relative to the circular shape and substantially + / - 10% relative to the linear shape. In some embodiments, the microring structure may have an elliptical or racetrack shape. In some embodiments, the silicon waveguide may include a curve in a region along the microring structure to enhance the coupling effect between the silicon waveguide and the microring structure. In some embodiments of the ring resonator structure, the ring resonator structure further includes an optional second silicon waveguide that is also linear.

[0097] In some embodiments, the micro-ring structure may include silicon. In some embodiments, the micro-ring structure may include a lightly doped P region, a lightly doped N region, a highly doped P+ region, a highly doped N+ region, intrinsic silicon, and silicon dioxide (as a separator between different Si doping regimes when needed). Optical components such as PICs may be embedded within the panel substrate by forming a cavity in the panel substrate at one point during panel fabrication, inserting the optical component into the panel substrate, and forming the remainder of the panel substrate.

[0098] When implementing PIC 562, the number of glass sheets (e.g., individual glass sheets 550-1, 550-2, and 550-3) may be informed by the thickness of PIC 562. For example, for PICs with thicknesses in the range of 300 microns to 1 millimeter, glass reinforcement layer 550 should be equal to the thickness of the PIC, and thus, the associated number of glass layers may be in the range of three to ten.

[0099] A non-limiting way to identify the PIC may include visually inspecting both the material present in the cross-sectional view and the structure and shape of the material to determine that a ring resonator structure has been implemented. Although in various embodiments, the ring resonator structure may include the same material as an electronic integrated circuit (e.g., a CMOS (complementary metal oxide semiconductor) component), the structure of the ring resonator structure and its shape employ a different doping profile than the CMOS component. Various embodiments of the ring resonator structure may have a thickness (on a cross-sectional view) of approximately 220 nanometers.

[0100] like Figure 5As shown in , in various embodiments, an optional local interconnect component 534 may also be present in the glass reinforcement layer 550. The integration of the local interconnect component (e.g., 534) and the PIC (e.g., 562) into the glass reinforcement layer of the panel is independent of each other. That is, the panel may include one or more local interconnect components and / or one or more PICs.

[0101] The waveguide routing 564 can enable the embedded PIC 562 to communicate with a fiber array unit (FAU) connector located outside the panel. The FAU connector can be a top-side connector, such as a grating coupler, or an edge connector, such as a microlens or a V-groove. Return to Reference Figure 1 In various panel assembly 100 embodiments, the FAU may be implemented in the panel architecture, for example, within the panel 108 at location 124 (see, for example, Fig. 9 , FAU 910), or outside the panel but within the panel assembly, for example, at position 122. Any of the panels or panel assemblies herein may have multiple PICs and multiple FAUs.

[0102] like Figure 6 As illustrated in , embodiments of the panel architecture may employ cavities and / or microchannels in the glass reinforcement layer. The simplified cross-sectional illustration of portion 600 relates to the shear line A-A' and includes a substrate 601. Microchannels 668 may be added to the glass reinforcement layer 650 to help remove heat from the components of the panel. Microchannel 668 is another example of a closed path formed in the glass reinforcement layer 650. Microchannel 668 may include lateral portions 668-1 and 668-2 and a vertical portion 668-3. In some embodiments, the microchannel lateral portion is formed on the surface of the glass layer (or glass sheet) by, for example, etching or laser cutting, and the microchannel vertical portion is formed by, for example, drilling through the glass layer (or glass sheet). In some embodiments, the microchannel vertical portion may include a through-glass through hole of appropriate diameter to facilitate the flow of liquid coolant. In other embodiments, the lateral portion of the microchannel 668 may be located inside the glass layer. Microchannel vertical portion 668-3 extends through more than one glass sheet (through 650-1 and 650-2 and into 650-3). In an embodiment, the microchannel lateral portion (e.g., 668-2) can be located near the set of conductive contacts, where "near" means at the surface of the glass reinforcement layer located below the conductive contacts. It can be appreciated that although Figure 6 The illustration is two-dimensional, but the three-dimensional nature of the design / configuration of microchannel 668 is indicated; for example, transverse portion 668 - 2 passes in front of two TGVs 652 and behind one TGV 652 .

[0103] Some embodiments have cavities added to the glass reinforcement layer 650 to act as a pool or reservoir for liquid coolant. When there is a cavity 671, the cavity 671 can reside in the glass reinforcement layer, and similar to the microchannel 668, the cavity 671 can be etched or laser cut into the surface of the glass sheet. In other embodiments, the cavity can be formed inside the glass layer. In embodiments that implement the cavity 671 and the microchannel 668, the microchannel 668 can be configured to use the flow of the liquid coolant in the cavity to extract heat from the glass reinforcement layer 650. Therefore, the microchannel 668 can have a diameter that is a function of the selected liquid coolant (e.g., water, alcohol, ethylene glycol) because the diameter is selected to accommodate the movement of the selected liquid coolant at the expected operating temperature of the tube core near the microchannel 668. The glass in the glass reinforcement layer 650 can provide an airtight seal around the microchannel 668 for the liquid coolant flowing closest to the corresponding tube core, thereby enhancing the cooling functionality of the tube core.

[0104] Substrate 601 illustrates optional local interconnect features 634 implemented in glass reinforcement layer 650, as described in connection with other embodiments. However, other embodiments of substrate 601 and / or the resulting panel do not necessarily include optional local interconnect features 634. In other words, a panel may include cavities 671 and / or microchannels 668 without local interconnect features 634.

[0105] The panel may include one or more ports (e.g., at 673) to allow connection to an external liquid-cooled thermal management solution to cool the panel, for example, by controlling the flow of fluid into / out of the microchannel 668. In various embodiments, the liquid-cooled thermal management solution may include: a heat exchanger to remove heat from heated liquid coolant leaving the panel that has absorbed heat generated by the die on the panel; a pump to provide circulation of the coolant through the microchannels; and conduits to connect the panel, the heat exchanger, and the pump. The liquid-cooled thermal management solution can cool multiple panels. Further, the liquid-cooled thermal management solution can be co-located in the same system as the panel cooled by the liquid-cooled thermal management solution, or located external to the system in which the panel is located. For example, in a rack-level solution, the liquid-cooled thermal management solution can cool panel components located in multiple systems within a rack. Panels employing microchannels and cavities may or may not have a large form factor thermal management solution attached to the top of the panel. That is, the panel can provide removal of heat generated by the die within the panel through thermal management solutions located both below the die (cavities and / or microchannels) and above the die (e.g., thermal management solutions such as liquid cooling, vapor chambers, heat sinks, etc.).

[0106] In manufacturing, various techniques may be used to fill and package embodiments of the panel architecture. Figure 7 , embodiment 700 illustrates a solder resist or dielectric layer 712 having conductive pads 726 therein, to which solder balls 702 may be attached at a first pitch or fine pitch to allow a die or chiplet to be attached thereto. In embodiment 720, the solder resist or dielectric layer 712 is shown as having recesses 706 etched therein, to which solder balls 708 are placed prior to attaching the die or chiplet. Notably, the recesses 706 have tapered walls that are wider at the upper opening and narrower where the recesses meet the conductive contacts. Similarly, the bottom surface of the panel architecture may have exposed second level interconnects (SLIs) or conductive contacts 732 arranged in the solder resist or dielectric layer 718 at a pitch greater than the pitch of the conductive contacts or the pitch of a BGA or land grid array (LGA). Solder balls 710 may be attached to the SLIs or conductive contacts 732. Figure 7 The examples in are non-limiting.

[0107] Move to Figure 8-9 , provides an example processing flow for the panel architecture. Figure 8-9 The illustration in FIG. 1 relates to the cut line BB', because the chips (chiplets) 1-3 are the first panel ( Fig. 9 106), and chips (chiplets) 4-5 are part of a second panel ( Fig. 9 "Panel 2" in the figure is generally similar to a portion of panel 108). Figure 8-9 The processing flow shown in the figure can be used to combine the above Figure 3 , 5 -6 and 21-25, some intra-panel architectural features, such as local interconnect components, are indicated for chips 1-3 and for chips 4-5, respectively, although microchannels and cavities are not depicted to simplify the drawings. The order of operations described in the process flow is non-limiting, the operations may be performed in a different order, and operations may be added or subtracted without changing the final product. At one point in manufacturing and packaging, Panel 1 and Panel 2 will be singulated or cut apart (at 859).

[0108] At 800, a glass carrier 806 is employed to build a plurality of panels thereon. The glass carrier 806 is used to provide a mechanically rigid surface for depositing corresponding buildup layers or RDLs and solder resists, performing etching, depositing copper or other conductive trace and pad materials, and building a glass reinforcement layer 850 to achieve a panel substrate structure as described herein. The glass carrier 806 may also provide a level of flatness that may not be achievable using other types of substrates, such as printed circuit boards including organic substrate materials. The flatness provided by the glass carrier may enable the formation of smaller feature sizes (e.g., via width / space, conductive contact width / space), thereby enabling the formation of conductive contacts, vias, and other features with fine pitches. The area of ​​the glass carrier 806 is at least the same size as the area of ​​a single panel described herein, and may be, for example, 510 mm×515 mm, or larger or smaller as required. The glass carrier 806 may be an alkali-free alkaline earth borosilicate aluminate glass, such as a glass including aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium), such as a glass including SiO2, Al2O3, B2O3, and MgO, or a photosensitive glass. The thickness of the glass carrier 806 may be in the range of 0.5 to 2 mm + / - 110%.

[0109] On the upper surface 803 of the panel architecture (similar to the upper surfaces 203, 303, 503, and 603), conductive contacts 808 are arranged to attach corresponding chips or dies at positions 802-1, 802-2, 802-3, 802-4, and 802-5. The conductive contacts 808 are arranged at a suitable pitch for the corresponding dies to attach (e.g., "die pitch"), so the pitch of the conductive contacts at position 802-1 can be different from the pitch of the conductive contacts 808 at position 802-2, and so on. In various embodiments, the conductive contacts 808 are attached at a fine pitch for first level interconnection (FLI) with the corresponding dies.

[0110] Optional embedded structures, such as local interconnect components 804-1, 804-2, and 804-3 may be formed at this stage of packaging. Optional cavities 671 and microchannels 668 may be etched at this stage. Additionally, optional waveguides may be etched, and photonic integrated circuits may be embedded at this stage (e.g., Fig. 9 , PIC 906, waveguide 908). Although not depicted for clarity of illustration, the RDL interconnect structure can be implemented directly on the local interconnect component.

[0111] At 835, as illustrated, the corresponding integrated circuit dies or chips can be attached to (i.e., assembled to) the panel substrate. As described above, the chips (chip 1, chip 2, chip 3, chip 4, and chip 5) can implement different functionalities, have different heights, have different pin arrangements (leads), have different lateral dimensions, and / or can occupy different amounts of cross-sectional area within the panel. Different panels can have the same or different numbers of chips. The assembly at 835 can be referred to as fine pitch assembly being performed. At 835, any welding technology or hybrid bonding technology can be used. The various chips can be assembled to the panel substrate using bottom filler 812; and although the bottom filler 812 is depicted as being uniform, in practice, the bottom fillers of individual chips can be different (e.g., the bottom filler under chip 1 can be different from the bottom filler of chip 2, etc.). The embodiment at 835 can be referred to as filling the panel substrate.

[0112] At 855, the glass carrier 806 can be peeled or removed from the populated panel substrate, and the panel substrate can be cut into respective panels (e.g., the four panel quads initially described), as indicated by dashed lines 859. At 855, solder balls 857 can be attached via second level interconnects or conductive contacts 832 at the lower surface, and mechanical contact enabling can be performed, such as for LGA attachment. Alternatively, solder balls 857 can be added prior to cutting the populated panel substrate into respective panels.

[0113] Depicted at 900, respective large form factor thermal solutions 960 and 962 may be added to the individual populated panel substrates (Panel 1 and Panel 2), and in various embodiments, underfills 964 and 966 may be added respectively beneath the large form factor thermal solutions 960 and 962. Co-packaged integrated circuit components, such as FAU 910, may be added at 930.

[0114] Depending on the embodiment, encapsulant 972 may be applied / overmolded over the panel, as illustrated at 930 for Panel 1. At 930, in a non-limiting example, FAU 910 may be attached to PIC 906 via waveguide 908 as part of Panel 2. In other embodiments, the co-packaged integrated circuit components may be located outside of the panel, above the panel, or stacked vertically with the panel.

[0115] In some embodiments, at 930, a single packaged multi-die panel (e.g., Panel 1) having the panel architecture provided herein is a complete HPC solution for an application. In other embodiments, multiple panels are assembled into a panel assembly, such as Figure 1Panel assembly 100. Embodiment 950 generally reflects cut line B-B', illustrating panel 1 and panel 2 assembled onto panel-level substrate 970. Panel-level substrate 970 may include one or more layers, wherein each layer includes an inorganic or organic dielectric material (such as any of the dielectric materials disclosed or referenced herein), one or more conductive traces, and one or more through-holes. Substrate 970 may provide a conductive path between panels. For example, substrate 970 includes conductive traces 973 and through-holes 974 of two substrate layers that provide a conductive path connection between conductive contacts 976 of panel 1 and conductive contacts 978 of panel 2. The resulting panel assembly at 950 may provide a complete HPC solution for an application, or the panel assembly from 950 may be further assembled with other components to provide a complete HPC solution.

[0116] Fig.10 is an example first method of forming a panel. At 1004 in method 1000, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm×250 mm, the first dielectric layer including conductive pads arranged at a first pitch. At 1008, a glass layer is formed on the first dielectric layer, the glass layer including local interconnect components. At 1012, a second dielectric layer is positioned on the glass layer, the second dielectric layer including conductive contacts arranged at a second pitch, the conductive contacts further arranged into a first set and a second set, the local interconnect components being used to provide electrical communication between a first conductive contact in the first set and a first conductive contact in the second set. At 106, an interconnect structure is positioned in the glass layer, the interconnect structure providing electrical communication between a second conductive contact in the first set and one of the conductive pads.

[0117] Fig.11 is an example second method of forming a panel. At 1104, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm×250 mm, the first dielectric layer including conductive pads arranged at a first pitch. At 1108, a glass layer is formed on the first dielectric layer, the glass layer including a photonic integrated circuit (PIC). At 1112, a second dielectric layer is positioned on the glass layer, the second dielectric layer including conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first set and a second set. The PIC is configured to electrically communicate with a first conductive contact in the first set or the second set. At 1116, an interconnect structure is positioned in the glass layer, the interconnect structure being used to provide electrical communication between a second conductive contact in the first set and one of the conductive pads.

[0118] Fig.12is an example third method of forming a panel. At 1204, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm×250 mm, the first dielectric layer including conductive pads arranged at a first pitch. At 1208, a glass layer is formed on the first dielectric layer, the glass layer including microchannels. At 1212, a second dielectric layer is positioned on the glass layer, the second dielectric layer including conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first set and a second set. The microchannel is configured to have a portion proximate to the first set. At 1216, an interconnect structure is positioned in the glass layer, the interconnect structure being used to provide electrical communication between a conductive contact in the first set and one of the conductive pads.

[0119] The sequence of elements in methods 1000, 1100, and 1200 is non-limiting. The operations of the methods may be performed in a different order, and operations may be added or subtracted without changing the final product. For example, any of methods 1000, 1100, and 1200 may further include attaching a first die to a first set; and attaching a second die to a second set, thereby creating a populated substrate. In a second example, any of methods 1000, 1100, and 1200 may further include peeling the glass carrier from the populated substrate; and forming solder bumps on the conductive pads.

[0120] Figure 13-21 Simplified cross-sectional views of various "core" panel embodiments are shown, wherein the panel substrate includes a glass core. Figure 1 The dielectric layer is located on the upper surface of the glass core (between the integrated circuit die and the glass core) or on the upper and lower surfaces of the glass core. The glass core provides Figure 3 , 5 -6 glass reinforcement layer has similar functions (signal routing, mechanical stability during manufacturing, flat surface on which dielectric layers can be formed) and possesses similar properties (can be composed of the same material, with a coefficient of expansion close to that of the integrated circuit die attached to the panel), but due to Figure 13-21 The panel embodiment shown in FIG. 1 is not assembled on a glass carrier, so Figure 13-21 The glass core can be compared Figure 3 , 5 The -6 has a thicker glass reinforcement layer.

[0121] Fig.1313 is a simplified cross-sectional illustration of an example panel substrate portion including a glass core. Panel portion 1300 includes a glass core 1351 positioned between a first set of dielectric layers (RDL, build-up layers) 1322 (1322a, 1322b, 1322c, 1322d) and a second set of dielectric layers 1324 (1324a, 1324b). The first set of dielectric layers 1322 are stacked vertically, and the second set of dielectric layers 1324 are stacked vertically. That is, an individual first dielectric layer 1322 (e.g., 1322a) is positioned adjacent to another first dielectric layer 1322 (e.g., 1322b), and an individual second dielectric layer 1324 (e.g., 1324a) is positioned adjacent to another second dielectric layer 1324 (e.g., 1324b). Glass core 1351 includes glass layer 1354, sealing layers 1370 and 1372, and through glass vias (TGVs) 1352 in layer 1354. Glass core 1351 has a thickness 1380. Sealing layers 1370 and 1372 include dielectric layer 1374 in which TGV contacts 1376 are located.

[0122] The upper surface contact layer 1356 includes solder resist or other suitable dielectric material 1312 and conductive contacts 1326, and the conductive contacts 1326 are arranged to correspond to the pinouts of the chiplets to be attached to the panel portion 1300. The upper surface contact layer 1356 (and therefore, the conductive contacts 1326) is located on the top dielectric layer (e.g., 1322a) of the first dielectric layer 1322. The conductive contact sets 1326 are arranged at a fine pitch. The lower surface contact layer 1360 includes solder resist or other suitable dielectric material 1318, and the conductive contacts 1332 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 1360 (and therefore, the conductive contacts 1332) is located on the bottom dielectric layer (e.g., 1324b) of the second dielectric layer 1324. The conductive contact sets 1332 are arranged at a pitch greater than the fine pitch at which the conductive contact sets 1326 are arranged.

[0123] The dielectric layer 1322 includes conductive traces 1328a and vias 1328b, and the dielectric layer 1324 includes conductive traces 1330a and vias 1330b. The local interconnect including vias 1328b and conductive traces 1328a included in the region 1387 provides a conductive path between conductive contacts 1326 belonging to a first conductive contact set 1364 to be attached to a first integrated circuit die and conductive contacts 1326 belonging to a second conductive contact set 1366 to be attached to a second integrated circuit die.

[0124] Vias 1328b and 1330b are shown as being tapered, with the narrower end of the via being closer to the glass core 1351 than the wider end of the via. These tapers reflect that dielectric layers 1322 and 1324 are built up from glass core 1351, and when individual dielectric layers 1322 and 1324 are etched to form via apertures, they are etched toward glass core 1351. Vias in dielectric layers of other panel embodiments that include glass cores (e.g., vias 1428b, 1430b, 1528b, 1530b, 1628b, 1630b) are similarly tapered.

[0125] Fig.14 14 is a simplified cross-sectional illustration of an example panel assembly including a panel including a glass core and local interconnect components located in a dielectric layer set of the panel. Panel assembly 1400 includes panel 1403, integrated circuit components 1405 and 1407 attached to panel 1403, and thermal management solution 1409. Panel 1403 includes a glass core 1451 positioned between a first dielectric layer set 1422 (1422a, 1422b, 1422c, 1422d) and a second dielectric layer set 1424 (1424a, 1424b). The first dielectric layer set 1422 and the second dielectric layer set 1424 are vertically stacked. Glass core 1451 includes a glass layer 1454, sealing layers 1470 and 1472, and a through glass via (TGV) 1452 located in the glass layer 1454. Glass core 1451 has a thickness 1480. The sealing layers 1470 and 1472 include a dielectric layer 1474 in which the TGV contacts 1476 are located.

[0126] The upper surface contact layer 1456 includes solder resist or other suitable dielectric material 1412 and conductive contacts 1426, and the conductive contacts 1426 are arranged to correspond to the pinouts of the tube cores 1404 and 1408 directly attached to the panel 1403. The upper surface contact layer 1456 (and therefore, the conductive contacts 1426) are located on the top dielectric layer (e.g., 1422a) of the first dielectric layer 1422. The conductive contact set 1426 is arranged at a fine pitch. The lower surface contact layer 1460 includes solder resist or other suitable dielectric material 1418, and the conductive contacts 1432 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 1460 (and therefore, the conductive contacts 1432) are located on the bottom dielectric layer (e.g., 1424b) of the second dielectric layer 1424. The conductive contact sets 1432 are arranged at a pitch that is greater than the fine pitch at which the conductive contact sets 1426 are arranged.

[0127] The dielectric layer 1422 includes conductive traces 1428a and vias 1428b, and the dielectric layer 1424 includes conductive traces 1430a and vias 1430b. The local interconnect component 1434 provides a conductive path between the conductive contacts 1426 connected to the die 1404 and the first packaged integrated circuit component 1492 and the conductive contacts 1426 connected to the die 1408 and the second packaged integrated circuit component 1407.

[0128] Integrated circuit dies 1404 and 1408 are attached to panel substrate 1401 at conductive contacts 1426 via solder balls 1438. In other embodiments, dies 1404 and 1408 may be attached to the panel substrate via other methods, such as hybrid bonding. Panel 1403 further includes solder balls 1410 attached to panel substrate 1401 at conductive contacts 1432. In other embodiments, panel 1403 does not include solder balls 1410, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1432 as pads. Packaged panel 1403 further includes an encapsulant 1498 that encapsulates dies 1404 and 1408 and panel substrate 1401.

[0129] Integrated circuit components 1405 and 1407 are attached to panel 1403 via a package-on-package assembly technique, wherein solder balls 1411 of integrated circuit components 1405 and 1407 are attached to through-package vias 1415 that extend through encapsulant 1498 and are attached to conductive contacts 1426. Panel assembly 1400 illustrates only one example of how a package may be attached to a packaged panel. In other embodiments, integrated circuit components may be attached to a package panel via different methods.

[0130] Fig.15 1 is a simplified cross-sectional illustration of an example panel including a glass core in which local interconnect components are located. Panel 1500 includes integrated circuit dies 1504a, 1504b, 1504c, 1504d, and 1508 attached directly or indirectly to the panel, and a thermal management solution 1509. Panel 1500 includes a glass core 1551 positioned between a first vertically stacked set of dielectric layers 1522 (1522a, 1522b, 1522c, 1522d) and a second vertically stacked set of dielectric layers 1524 (1524a, 1524b). Glass core 1551 includes a glass layer 1554, sealing layers 1570 and 1572, and a through glass via (TGV) 1552 located in glass layer 1554. Glass core 1551 has a thickness 1580. The sealing layers 1570 and 1572 include a dielectric layer 1574 in which the TGV contacts 1576 are located.

[0131] The upper surface contact layer 1556 includes solder resist or other suitable dielectric material 1512 and conductive contacts 1526, which are arranged to correspond to the pinouts of the tube cores 1504a and 1508 directly attached to the panel substrate 1501. The upper surface contact layer 1556 (and therefore, the conductive contacts 1526) are located on the top dielectric layer (e.g., 1522a) of the first dielectric layer 1522. The conductive contact set 1526 is arranged at a fine pitch. The lower surface contact layer 1560 includes solder resist or other suitable dielectric material 1518, and the conductive contacts 1532 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 1560 (and therefore, the conductive contacts 1532) are located on the bottom dielectric layer (e.g., 1524b) of the second dielectric layer 1524. The conductive contact sets 1532 are arranged at a pitch that is greater than the fine pitch at which the conductive contact sets 1526 are arranged.

[0132] Dielectric layer 1522 includes conductive traces 1528a and vias 1528b, and dielectric layer 1524 includes conductive traces 1530a and vias 1530b. Local interconnect features 1534 located in glass layer 1554 of glass core 1551 provide a conductive path between one of conductive contacts 1526 connected to die 1504a and one of conductive contacts connected to die 1508.

[0133] Integrated circuit dies 1504a and 1508 are attached to panel substrate 1501 at conductive contacts 1526 via solder balls 1538. In other embodiments, dies 1504a and 1508 may be attached to panel substrate 1501 via other methods, such as hybrid bonding. Panel 1500 further includes solder balls 1510 attached to panel substrate 1501 at conductive contacts 1532. In other embodiments, panel 1500 does not include solder balls 1510, and the panel may be attached to other components, such as a printed circuit board, via conductive contacts 1532 as pads.

[0134] Integrated circuit die 1504a, 1504b, 1504c and 1504d are stacked vertically and connected by solder bumps (or microbumps) 1519, which are connected to through-silicon vias (TSVs) 1517 extending through die 1504c and 1504d. TSVs may include copper, carbon nanotubes, graphene nanotubes, or another suitable material. Stacked die 1504a-d may implement various functionalities, and in one embodiment, die 1504a may be a high bandwidth memory (HBM) controller die that controls HBM die 1504b-d. In other embodiments, die 1504a may include TSVs 1517 connected to conductive contacts 1526. Panel 1500 illustrates an example of how a panel may accommodate vertically stacked integrated circuit die. In other embodiments, integrated circuit components may be attached to the panel via different methods.

[0135] Fig.16 1 is a simplified cross-sectional illustration of an example panel including a glass core and a photonic integrated circuit. Panel 1600 includes integrated circuit dies 1604 and 1608, a glass core 1651 positioned between a first vertically stacked set of dielectric layers 1622 (1622a, 1622b, 1622c, 1622d), a second vertically stacked set of dielectric layers 1624 (1624a, 1624b), photonic integrated chips 1622a and 1622b, and a thermal management solution 1609. Glass core 1651 includes a glass layer 1654, sealing layers 1670 and 1673, and through-glass vias (TGVs) 1652 located in glass layer 1654. Glass core 1651 has a thickness 1680. Sealing layers 1670 and 1672 include a dielectric layer 1674 in which TGV contacts 1676 are located.

[0136] The upper surface contact layer 1656 includes solder resist or other suitable dielectric material 1612 and conductive contacts 1626, which are arranged to correspond to the pinouts of the tube cores 1604 and 1608 directly attached to the panel 1600. The upper surface contact layer 1656 (and therefore, the conductive contacts 1626) are located on the top dielectric layer (e.g., 1622a) of the first dielectric layer 1622. The conductive contact set 1626 is arranged at a fine pitch. The lower surface contact layer 1660 includes solder resist or other suitable dielectric material 1618, and the conductive contacts 1632 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 1660 (and therefore, the conductive contacts 1632) are located on the bottom dielectric layer (e.g., 1624b) of the second dielectric layer 1624. The conductive contact sets 1632 are arranged at a pitch that is greater than the pitch at which the conductive contact sets 1626 are arranged.

[0137] Dielectric layer 1622 includes conductive traces 1628a and vias 1628b, and dielectric layer 1624 includes conductive traces 1630a and vias 1630b. Local interconnects including vias 1628b and conductive traces 1628a included in region 1687 provide a conductive path between conductive contacts 1626 attached to die 1604 and conductive contacts 1626 attached to die 1608.

[0138] Integrated circuit dies 1604 and 1608 are attached to conductive contacts 1626 via solder balls 1638. In other embodiments, dies 1604 and 1608 may be attached to conductive contacts 1626 via other methods, such as hybrid bonding. Panel 1600 further includes solder balls 1610 attached to conductive contacts 1632. In other embodiments, panel 1600 does not include solder balls 1610, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1632 as pads.

[0139] Panel 1600 includes photonic integrated circuits (PICs) 1662a and 1662b. PICs 1662a and 1662b are located on glass layer 1654. PICs 1662a and 1662b are attached to conductive contacts 1626 associated with dies 1604 and 1608, respectively. The PICs are integrated into panel 1600 during panel manufacturing and are therefore considered part of panel 1600. Waveguides 1664a and 1664b are located in glass layer 1654 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1600. Fiber array units 1621a and 1621b are attached to panel 1600, with waveguide 1664a providing a path for optical communication of optical signals generated or received by PIC 1662a or FAU 1621a, and waveguide 1664b providing a path for optical communication of optical signals generated or received by PIC 1662b or FAU 1621b.

[0140] Fig.17 17 is a simplified cross-sectional illustration of an example panel including a glass core, a photonic integrated circuit, and local interconnect components. Panel 1700 includes integrated circuit dies 1704 and 1708, a glass core 1751 positioned between a first vertically stacked set of dielectric layers 1722 (1722a, 1722b, 1722c, 1722d), a second vertically stacked set of dielectric layers 1724 (1724a, 1724b), and a thermal management solution 1709. Glass core 1751 includes a glass layer 1754, sealing layers 1770 and 1772, and a through-glass via (TGV) 1752 located in glass layer 1754. Glass core 1751 has a thickness 1780.

[0141] The upper surface contact layer 1756 includes solder resist or other suitable dielectric material 1712 and conductive contacts 1726, which are arranged to correspond to the pinouts of the tube cores 1704 and 1708 directly attached to the panel 1700. The upper surface contact layer 1756 (and therefore, the conductive contacts 1726) are located on the top dielectric layer (e.g., 1722a) of the first dielectric layer 1722. The conductive contact set 1726 is arranged at a fine pitch. The lower surface contact layer 1760 includes solder resist or other suitable dielectric material 1718, and the conductive contacts 1732 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 1760 (and therefore, the conductive contacts 1732) are located on the bottom dielectric layer (e.g., 1724b) of the second dielectric layer 1724. The conductive contact sets 1732 are arranged at a pitch that is greater than the finer pitch at which the conductive contact sets 1726 are arranged.

[0142] The dielectric layer 1722 includes conductive traces 1728a and vias 1728b, and the dielectric layer 1724 includes conductive traces 1730a and vias 1730b. The local interconnect features 1734 provide conductive paths between the conductive contacts 1726 attached to the die 1704 and the conductive contacts attached to the die 1708.

[0143] Integrated circuit dies 1704 and 1708 are attached to conductive contacts 1726 via solder balls 1738. In other embodiments, dies 1704 and 1708 may be attached to conductive contacts 1726 via other methods, such as hybrid bonding. Panel 1700 further includes solder balls 1710 attached to conductive contacts 1732. In other embodiments, panel 1700 does not include solder balls 1710, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1732 as pads.

[0144] Panel 1700 includes photonic integrated circuits (PICs) 1762a and 1762b. PICs 1762a and 1762b are located on glass layer 1754. PICs 1762a and 1762b are attached to conductive contacts 1726 associated with dies 1704 and 1708, respectively. PICs 1762a and 1762b are integrated into panel 1700 during panel manufacturing and are therefore considered part of panel 1700. Waveguides 1764a and 1764b are located in glass layer 1754 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1700. Fiber array units 1721a and 1721b are attached to panel 1700, with waveguide 1764a providing a path for optical communication of optical signals generated or received by PIC 1762a or FAU 1721a, and waveguide 1764b providing a path for optical communication of optical signals generated or received by PIC 1762b or FAU 1721b.

[0145] Fig.18 18 is a simplified cross-sectional illustration of an example panel including a glass core, a photonic integrated circuit, and local interconnect components located in the glass core. Panel 1800 includes integrated circuit dies 1804 and 1808, a glass core 1851 positioned between a first vertically stacked set of dielectric layers 1822 (1822a, 1822b, 1822c, 1822d), a second vertically stacked set of dielectric layers 1824 (1824a, 1824b), and a thermal management solution 1809. Glass core 1851 includes a glass layer 1854, sealing layers 1870 and 1872, and a through-glass via (TGV) 1852 located in glass layer 1854. Glass core 1851 has a thickness 1880.

[0146] The upper surface contact layer 1856 includes solder resist or other suitable dielectric material 1812 and conductive contacts 1826, which are arranged to correspond to the pinouts of the tube cores 1804 and 1808 directly attached to the panel 1800. The upper surface contact layer 1856 (and therefore, the conductive contacts 1826) are located on the top dielectric layer (e.g., 1822a) of the first dielectric layer 1822. The conductive contact set 1826 is arranged at a fine pitch. The lower surface contact layer 1860 includes solder resist or other suitable dielectric material 1818, and the conductive contacts 1832 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 1860 (and therefore, the conductive contacts 1832) are located on the bottom dielectric layer (e.g., 1824b) of the second dielectric layer 1824. The conductive contact sets 1832 are arranged at a pitch that is greater than the pitch at which the conductive contact sets 1826 are arranged.

[0147] Dielectric layer 1822 includes conductive traces 1828a and vias 1828b, and dielectric layer 1824 includes conductive traces 1830a and vias 1830b. Local interconnect features 1834 located in glass core 1851 provide conductive paths between conductive contacts 1826 connected to die 1804 and conductive contacts connected to die 1808.

[0148] Integrated circuit dies 1804 and 1808 are attached to conductive contacts 1826 via solder balls 1838. In other embodiments, dies 1804 and 1808 may be attached to conductive contacts 1826 via other methods, such as hybrid bonding. Panel 1800 further includes solder balls 1810 attached to conductive contacts 1832. In other embodiments, panel 1800 does not include solder balls 1810, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1832 as pads.

[0149] Panel 1800 includes photonic integrated circuits (PICs) 1862a and 1862b. PICs 1862a and 1862b are located on glass layer 1854. PICs 1862a and 1862b are attached to conductive contacts 1826 associated with dies 1804 and 1808, respectively. The PICs are integrated into panel 1800 during panel manufacturing and are therefore considered part of panel 1800. Waveguides 1864a and 1864b are located in glass layer 1854 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1800. Fiber array units 1821a and 1821b are attached to panel 1800, with waveguide 1864a providing a path for optical communication of optical signals generated or received by PIC 1862a or FAU 1821a, and waveguide 1864b providing a path for optical communication of optical signals generated or received by PIC 1862b or FAU 1821b.

[0150] Fig.19 1 is a simplified cross-sectional illustration of an example panel including a glass core with microchannels and photonic integrated circuits. Panel portion 1900 includes a glass core 1951 positioned between a first set of dielectric layers (RDL, build-up layers) 1922 (1922a, 1922b, 1922c, 1922d) and a second set of dielectric layers 1924 (1924a, 1924b). The first set of dielectric layers 1922 are stacked vertically, and the second set of dielectric layers 1924 are stacked vertically. Glass core 1951 includes glass layer 1954, sealing layers 1970 and 1972, and through-glass vias (TGVs) 1952 located in layer 1954. Glass core 1951 has a thickness 1980. Sealing layers 1970 and 1972 include dielectric layer 1974 in which TGV contacts 1976 are located.

[0151] The upper surface contact layer 1956 includes solder resist or other suitable dielectric material 1912 and conductive contacts 1926, which are arranged to correspond to the pinouts of the tube cores 1904 and 1908 directly attached to the conductive contacts 1926. The upper surface contact layer 1956 (and therefore, the conductive contacts 1926) are located on the top dielectric layer (e.g., 1922a) of the first dielectric layer 1922. The conductive contact set 1926 is arranged at a fine pitch. The lower surface contact layer 1960 includes solder resist or other suitable dielectric material 1918, and the conductive contacts 1932 are arranged to correspond to the desired panel-level pinouts. The lower surface contact layer 1960 (and therefore, the conductive contacts 1932) are located on the bottom dielectric layer (e.g., 1924b) of the second dielectric layer 1924. The conductive contact sets 1932 are arranged at a pitch that is greater than the fine pitch at which the conductive contact sets 1926 are arranged.

[0152] Dielectric layer 1922 includes conductive traces 1928a and vias 1928b, and dielectric layer 1924 includes conductive traces 1930a and vias 1930b. Local interconnects including vias 1928b and conductive traces 1928a included in region 1987 provide a conductive path between conductive contacts 1926 attached to die 1904 and conductive contacts 1926 attached to die 1908.

[0153] Integrated circuit dies 1904 and 1908 are attached to conductive contacts 1926 via solder balls 1938. In other embodiments, dies 1904 and 1908 may be attached to conductive contacts 1926 via other methods, such as hybrid bonding. Panel 1900 further includes solder balls 1910 attached to conductive contacts 1932. In other embodiments, panel 1900 does not include solder balls 1910, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1932 as pads.

[0154] Panel 1900 includes photonic integrated circuits (PICs) 1962a and 1962b. PICs 1962a and 1962b are located on glass layer 1954. PICs 1962a and 1962b are attached to conductive contacts 1926 associated with dies 1904 and 1908, respectively. The PICs are integrated into panel 1900 during panel manufacturing and are therefore considered part of panel 1900. Waveguides 1964a and 1964b are located in glass layer 1954 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1900. Fiber array units 1921a and 1921b are attached to panel 1900, with waveguide 1964a providing a path for optical communication of optical signals generated or received by PIC 1962a or FAU 1921a, and waveguide 1964b providing a path for optical communication of optical signals generated or received by PIC 1962b or FAU 1921b.

[0155] like Fig.19 , in some embodiments, the panel can include cavities and / or microchannels in the glass core. In general, including microchannels in the glass core of the panel helps remove heat generated by integrated circuit dies attached to the panel or any heat generating components located in the panel (such as active components located in local interconnect components). Microchannels 1968 are located in the glass layer 1954 and can be formed on the surface of the glass layer 1954 by, for example, etching or laser cutting. In other embodiments, microchannels 1968 can be located in the interior of the glass layer 1954. It can be appreciated that although Fig.19 The illustration of is two-dimensional, but the three-dimensional nature of the design / configuration of micro-tunnels 1968 is indicated by micro-tunnels 1968 being illustrated as passing in front of several of the TGVs 1952 and behind other TGVs 1952.

[0156] Some panel embodiments with microchannels may further include a cavity in the glass core to act as a pool or reservoir for a liquid coolant. The microchannels may be configured to extract heat from the glass core using the flow of liquid coolant in the cavity. In panel 1900, the glass core 1951 includes a cavity 1971. The cavity 1971 may be etched or laser cut into the surface of the glass layer 1954. In other embodiments, the cavity may be formed within the interior of the glass layer. Port 1973 provides a connection to an external liquid cooling thermal management solution, such as by controlling the flow of fluid into / out of the microchannel 1968, to cool the panel 1900.

[0157] Fig. 202000 includes integrated circuit dies 2004 and 2008, a glass core 2051 positioned between a first vertically stacked set of dielectric layers 2022 (2022a, 2022b, 2022c, 2022d), a second vertically stacked set of dielectric layers 2024 (2024a, 2024b), and a thermal management solution 2009. The glass core 2051 includes a glass layer 2054, sealing layers 2070 and 2072, and a through-glass via (TGV) 2052 located in the glass layer 2054. The glass core 2051 has a thickness 2080.

[0158] The upper surface contact layer 2056 includes solder resist or other suitable dielectric material 2012 and conductive contacts 2026, which are arranged to correspond to the pinouts of the tube cores 2004 and 2008 directly attached to the panel 2000. The upper surface contact layer 2056 (and therefore, the conductive contacts 2026) are located on the top dielectric layer (e.g., 2022a) of the first dielectric layer 2022. The conductive contact set 2026 is arranged at a fine pitch. The lower surface contact layer 2060 includes solder resist or other suitable dielectric material 2018, and the conductive contacts 2032 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 2060 (and therefore, the conductive contacts 2032) are located on the bottom dielectric layer (e.g., 2024b) of the second dielectric layer 2024. The conductive contact sets 2032 are arranged at a pitch that is greater than the pitch at which the conductive contact sets 2026 are arranged.

[0159] The dielectric layer 2022 includes conductive traces 2028a and vias 2028b, and the dielectric layer 2024 includes conductive traces 2030a and vias 2030b. The local interconnect features 2034 provide conductive paths between the conductive contacts 2026 attached to the die 2004 and the conductive contacts attached to the die 2008.

[0160] Integrated circuit dies 2004 and 2008 are attached to conductive contacts 2026 via solder balls 2038. In other embodiments, dies 2004 and 2008 may be attached to conductive contacts 2026 via other methods, such as hybrid bonding. Panel 2000 further includes solder balls 2010 attached to conductive contacts 2032. In other embodiments, panel 2000 does not include solder balls 2010, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2032 as pads.

[0161] Panel 2000 includes photonic integrated circuits (PICs) 2022a and 2022b. PICs 2022a and 2022b are located on glass layer 2054. PICs 2062a and 2062b are attached to conductive contacts 2026 associated with dies 2004 and 2008, respectively. PICs 2062a and 2062b are integrated into panel 2000 during panel manufacturing and are therefore considered part of panel 2000. Waveguides 2064a and 2064b are located in glass layer 2054 and are also manufactured during panel manufacturing and are therefore also considered part of panel 2000. Fiber array units 2021a and 2021b are attached to panel 2000, with waveguide 2064a providing a path for optical communication of optical signals generated or received by PIC 2062a or FAU 2021a, and waveguide 2064b providing a path for optical communication of optical signals generated or received by PIC 2062b or FAU 2021b.

[0162] Glass core 2051 includes microchannels 2068 located in glass layer 2054. Microchannels 2068 can be formed on the surface of glass layer 2054 by, for example, etching or laser cutting. In other embodiments, microchannels 2068 can be located in the interior of glass layer 2054. It can be appreciated that although Fig. 20 The illustration of is two-dimensional, but the three-dimensional nature of the design / configuration of micro-channels 2068 is indicated by micro-channels 2068 being illustrated as passing in front of several of the TGVs 2052 and behind other TGVs 2052.

[0163] The glass core 2051 further includes a cavity 2071 connected to the microchannel 2068. The cavity 2071 can be etched or laser cut into the surface of the glass layer 2054. In other embodiments, the cavity can be formed in the interior of the glass layer. Port 2073 provides a connection to an external liquid cooling thermal management solution to cool the panel 2000, for example by controlling the flow of fluid into / out of the microchannel 2068.

[0164] Fig.2121 is a simplified cross-sectional illustration of an example panel including a glass core with microchannels, a photonic integrated circuit, and local interconnect components located in the glass core. Panel 2100 includes integrated circuit dies 2104 and 2108, a glass core 2151 positioned between a first vertically stacked set of dielectric layers 2122 (2122a, 2122b, 2122c, 2122d), a second vertically stacked set of dielectric layers 2124 (2124a, 2124b), and a thermal management solution 2109. Glass core 2151 includes glass layer 2154, sealing layers 2170 and 2172, and through-glass vias (TGVs) 2152 located in glass layer 2154. Glass core 2151 has a thickness 2180.

[0165] The upper surface contact layer 2156 includes solder resist or other suitable dielectric material 2112 and conductive contacts 2126, which are arranged to correspond to the pinouts of the tube cores 2104 and 2108 directly attached to the panel 2100. The upper surface contact layer 2156 (and therefore, the conductive contacts 2126) are located on the top dielectric layer (e.g., 2122a) of the first dielectric layer 2122. The conductive contact set 2126 is arranged at a fine pitch. The lower surface contact layer 2160 includes solder resist or other suitable dielectric material 2118, and the conductive contacts 2132 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 2160 (and therefore, the conductive contacts 2132) are located on the bottom dielectric layer (e.g., 2124b) of the second dielectric layer 2124. The conductive contact sets 2132 are arranged at a pitch that is greater than the pitch at which the conductive contact sets 2126 are arranged.

[0166] Dielectric layer 2122 includes conductive traces 2128a and vias 2128b, and dielectric layer 2124 includes conductive traces 2130a and vias 2130b. Local interconnect features 2134 located in glass core 2151 provide conductive paths between conductive contacts 2126 connected to die 2104 and conductive contacts connected to die 2108.

[0167] Integrated circuit dies 2104 and 2108 are attached to conductive contacts 2126 via solder balls 2138. In other embodiments, dies 2104 and 2108 may be attached to conductive contacts 2126 via other methods, such as hybrid bonding. Panel 2100 further includes solder balls 2110 attached to conductive contacts 2132. In other embodiments, panel 2100 does not include solder balls 2110, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2132 as pads.

[0168] Panel 2100 includes photonic integrated circuits (PICs) 2162a and 2162b. PICs 2162a and 2162b are located on glass layer 2154. PICs 2162a and 2162b are attached to conductive contacts 2126 associated with dies 2104 and 2108, respectively. The PICs are integrated into panel 2100 during panel manufacturing and are therefore considered part of panel 2100. Waveguides 2164a and 2164b are located in glass layer 2154 and are also manufactured during panel manufacturing and are therefore also considered part of panel 2100. Fiber array units 2121a and 2121b are attached to panel 2100, wherein waveguide 2164a provides a path for optical communication between PIC 2162a and FAU 2121a, and waveguide 2164b provides a path for optical communication between PIC 2162b and FAU 2121b.

[0169] Panel 2100 includes photonic integrated circuits (PICs) 2122a and 2122b. PICs 2122a and 2122b are located on glass core 2151. PICs 2162a and 2162b are attached to conductive contacts 2126 associated with dies 2104 and 2108, respectively. The PICs are integrated into panel 2100 during panel manufacturing and are therefore considered part of panel 2100. Waveguides 2164a and 2164b are located in glass layer 2154 and are also manufactured during panel manufacturing and are therefore considered part of panel 2100. Fiber array units 2121a and 2121b are attached to panel 2100, with waveguide 2164a providing a path for optical communication of optical signals generated or received by PIC 2162a or FAU 2121a, and waveguide 2164b providing a path for optical communication of optical signals generated or received by PIC 2162b or FAU 2121b.

[0170] Glass core 2151 includes microchannels 2168 located in glass layer 2154. Microchannels 2168 can be formed on the surface of glass layer 2154 by, for example, etching or laser cutting. In other embodiments, microchannels 2168 can be located in the interior of glass layer 2154. It can be appreciated that although Fig.21 The illustration of is two-dimensional, but the three-dimensional nature of the design / configuration of microchannels 2168 is indicated by the microchannels 2168 being illustrated as passing in front of several TGVs 2152 and behind other TGVs 2152.

[0171] The glass core 2151 further includes a cavity 2171 connected to the microchannel 2168. The cavity 2171 can be etched or laser cut into the surface of the glass layer 2154. In other embodiments, the cavity can be formed in the interior of the glass layer. The port 2173 provides a connection to an external liquid cooling thermal management solution to cool the panel 2100, for example by controlling the flow of fluid into / out of the microchannel 2168.

[0172] Figure 13-21 The "core" panels and panel assemblies illustrated in the drawings are merely illustrative, wherein an integrated circuit die is attached to a panel substrate or panel. As discussed above, the Figure 13-21 More integrated circuit dies as shown are attached to or incorporated into a panel or panel assembly, and a die attached to the panel may have different lateral dimensions, area, height, shape and / or implement different functionality than another die attached to or incorporated into the panel.

[0173] Figure 13-21 The glass cores of the embodiments illustrated in FIG. 1 (eg, glass cores 1351, 1451, 1551) may include any glass described or referenced herein, or include any one of the glasses described or referenced herein (eg, Figure 3 , 5 -6 glass reinforcement layer) may include materials. Figure 13-21 In the embodiment illustrated in , the dielectric layers of the sealing layer in the glass core (eg, dielectric layers 1374 , 1474 , 1574 ) may include any dielectric material described or referenced herein. Figure 13-21 The TGVs (e.g., TGVs 1352, 1452, 1552) in the glass core in the illustrated embodiment may include copper or any other suitable metal. In alternative embodiments, the glass core may not include TGV contacts (e.g., 1376, 1476, 1576), and vias (e.g., vias 1328b, 1330b, 1428b, 1430b, 1528b, 1530b) in the dielectric layers on either side of the glass core may be directly attached to the TGVs.

[0174] Figure 13-21 The upper surface contact layer (e.g., 1326, 1426, 1526) illustrated in FIG. 1 may take the form of other upper surface contact layer embodiments, such as in combination with Figure 7 those described (e.g., 726a, 726b). Figure 13-21 The lower surface contact layer (e.g., 1360, 1460, 1560) illustrated in FIG. 1 may take the form of other lower surface contact layer embodiments, such as in combination with Figure 7Those described (e.g., lower surface contact layer embodiment 760).

[0175] Figure 14-21 The thermal management solutions illustrated in (eg, 1409, 1509, 1609) may include any cooling component described or referenced herein and attached to an integrated circuit component or integrated circuit die via a thermal interface material.

[0176] Figure 16-21 The fiber array units (e.g., 1621a, 1621b, 1721a, 1721b, 1821a, 1821b) illustrated in the drawings may be attached to a panel during panel manufacturing and may be part of a terminal panel product or attached to a panel after panel manufacturing. Any FAU described or referenced herein may include an optical fiber (e.g., 1625, 1725, 1825) that is part of an optical connection between panels in a system or between panels across different systems.

[0177] Figure 19-21 The microchannels (e.g., microchannels 1968, 2068, 2168) illustrated in the figure are in a glass core layer, and the microchannels can have a diameter as a function of a selected liquid coolant (e.g., water, alcohol, ethylene glycol) because the diameter is selected to accommodate the movement of the selected liquid coolant at the expected operating temperature of the tube core located near the microchannel. The glass core can provide a seal around the microchannel for the liquid coolant flowing closest to the corresponding tube core, thereby enhancing the cooling functionality of the tube core. Microchannel ports (e.g., 1973, 2073, 2173) allow the microchannels to be connected to an external liquid-cooled thermal management solution to cool the panel, for example, by controlling the flow of fluid into / out of the microchannel. In various embodiments, the liquid-cooled thermal management solution may include: a heat exchanger to remove heat from the heated liquid coolant leaving the panel, which has absorbed heat generated by the tube core on the panel; a pump to provide circulation of the coolant through the microchannel; and a conduit to connect the panel, the heat exchanger, and the pump. Liquid-cooled thermal management solutions can cool multiple panels.

[0178] Further, a liquid-cooled thermal management solution (which includes microchannels in a glass core and / or cooling components attached to one or more integrated circuit components and / or a die attached to a panel or panel assembly) can be co-located in the same system as the panel or panel assembly cooled by the liquid-cooled thermal management solution. In some embodiments, the thermal management solution is located outside the system. For example, in a rack-level solution, a liquid-cooled thermal management solution can cool panels located in multiple systems within a rack. Panels that employ microchannels and cavities may or may not have a large form factor thermal management solution attached to the top of the panel. That is, the panel can remove heat generated by the die within the panel through thermal management solutions located both below the die (cavities and / or microchannels) and above the die (e.g., thermal management solutions such as liquid cooling, vapor chambers, heat sinks, etc.).

[0179] Figure 13-21 The "core" panel embodiment illustrated in FIG. 1 includes various panel features that can be independently integrated into the panel. That is, these panel features are independent of each other and can be mixed and matched to produce a panel other than Figure 13-21 These panel features include local interconnects that are integrally formed with the dielectric layers of the panel and provide electrical communication between the die in the panel, local interconnect components that are separately manufactured during panel fabrication and placed within the panel (in one or more dielectric layers or the glass core) and provide electrical communication between the die in the panel, PICs, waveguides, vertically stacked packaged or unpackaged die, and microchannels (and reservoirs) in the glass core.

[0180] Figure 22-25 Simplified cross-sectional views of various "coreless" panel embodiments are illustrated, where the panel includes a set of dielectric layers to which integrated circuit dies are attached but does not include a core (such as a glass core for a "core" panel embodiment). Figure 1 The dielectric layers in a coreless panel are not formed on a core that becomes part of the panel, but are formed on a glass carrier that provides mechanical stability and a flat surface during panel manufacturing, enabling the formation of panel features with fine pitches. Figure 22-25 The glass carrier used during manufacturing is not shown in FIG. Since coreless panel embodiments do not have a glass core or glass reinforcement layer, they can be thinner than either of those types of panel embodiments.

[0181] Fig. 2222 is a simplified cross-sectional illustration of an example coreless panel. Panel 2200 includes integrated circuit dies 2204 and 2208 attached to a vertically stacked set of dielectric layers 2222, and a thermal management solution 2209. Upper surface contact layer 2256 includes solder resist or other suitable dielectric material 2212 and conductive contacts 2226, which are arranged to correspond to the pinouts of dies 2204 and 2208 directly attached to panel 2200. Upper surface contact layer 2256 (and therefore, conductive contacts 2226) is located on the top dielectric layer (e.g., 2222a) of dielectric layer 2222. The conductive contact set 2226 is arranged at a fine pitch. Lower surface contact layer 2260 includes solder resist or other suitable dielectric material 2218, and conductive contacts 2232 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 2260 (and therefore, the conductive contacts 2232) are located on the bottom dielectric layer (eg, 2222d) of the dielectric layer 2222. The conductive contact sets 2232 are arranged at a pitch that is greater than the fine pitch at which the conductive contact sets 2226 are arranged.

[0182] The dielectric layer 2222 includes conductive traces 2228a and vias 2228b. The local interconnects including vias 2228b and conductive traces 2228a included in the region 2287 provide a conductive path between conductive contacts 2226 attached to the integrated circuit die 2204 and conductive contacts 2226 attached to the second integrated circuit die 2208.

[0183] Integrated circuit dies 2204 and 2208 are attached to conductive contacts 2226 via solder balls 2238. In other embodiments, dies 2204 and 2208 may be attached to conductive contacts 2226 via other methods, such as hybrid bonding. Panel 2200 further includes solder balls 2210 attached to conductive contacts 2232. In other embodiments, panel 2200 does not include solder balls 2210, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2232 as pads.

[0184] Fig.2323 is a simplified cross-sectional illustration of an example coreless panel including local interconnect components. Panel 2300 includes integrated circuit dies 2304 and 2308 attached to a vertically stacked set of dielectric layers 2322, and a thermal management solution 2309. Upper surface contact layer 2356 includes solder resist or other suitable dielectric material 2312 and conductive contacts 2326, which are arranged to correspond to the pinouts of dies 2304 and 2308 directly attached to conductive contacts 2326. Upper surface contact layer 2356 (and therefore, conductive contacts 2326) is located on the top dielectric layer (e.g., 2322a) of first dielectric layer 2322. Conductive contact set 2326 is arranged at a fine pitch. Lower surface contact layer 2360 includes solder resist or other suitable dielectric material 2318 and conductive contacts 2332, which are arranged to correspond to the desired panel-level pinouts. The lower surface contact layer 2360 (and therefore, the conductive contacts 2332) are located on the bottom dielectric layer (eg, 2322b) of the dielectric layer 2322. The conductive contact sets 2332 are arranged at a pitch that is greater than the fine pitch at which the conductive contact sets 2326 are arranged.

[0185] The dielectric layer 2322 includes conductive traces 2328a and vias 2328b. The local interconnect features 2334 provide a conductive path between the conductive contacts 2326 attached to the die 2304 and the conductive contacts attached to the die 2308.

[0186] Integrated circuit dies 2304 and 2308 are attached to conductive contacts 2326 via solder balls 2338. In other embodiments, dies 2304 and 2308 may be attached to conductive contacts 2326 via other methods, such as hybrid bonding. Panel 2300 further includes solder balls 2310 attached to conductive contacts 2332. In other embodiments, panel 2300 does not include solder balls 2310, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2332 as pads.

[0187] Fig.24 is a simplified cross-sectional illustration of an example coreless panel including a photonic integrated circuit. Panel 2400 includes integrated circuit dies 2404 and 2408 attached to a vertically stacked set of dielectric layers 2422 (1622a, 2422b, 2422c, 2422d), a photonic integrated circuit 2462, a waveguide interposer 2427, and a thermal management solution 2409.

[0188] The upper surface contact layer 2456 includes solder resist or other suitable dielectric material 2412 and conductive contacts 2426, which are arranged to correspond to the pinouts of the tube core 2404 and 2408 directly attached to the conductive contacts 2526. The upper surface contact layer 2456 (and therefore, the conductive contacts 2426) is located on the top dielectric layer (e.g., 2422a) of the dielectric layer 2422. The conductive contact set 2426 is arranged at a fine pitch. The lower surface contact layer 2460 includes solder resist or other suitable dielectric material 2418, and the conductive contacts 2432 are arranged to correspond to the desired panel level pinouts. The lower surface contact layer 2460 (and therefore, the conductive contacts 2432) is located on the bottom dielectric layer (e.g., 2422d) of the dielectric layer 2422. The conductive contact sets 2432 are arranged at a pitch that is greater than the finer pitch at which the conductive contact sets 2426 are arranged.

[0189] The dielectric layer 2422 includes conductive traces 2428a and vias 2428b. The local interconnect including vias 2428b and conductive traces 2428a included in the region 2487 provides a conductive path between conductive contacts 2426 attached to the die 2404 and conductive contacts 2426 attached to the die 2408.

[0190] Dies 2404 and 2408 are attached to conductive contacts 2426 via solder balls 2438. In other embodiments, dies 2404 and 2408 may be attached to conductive contacts 2426 via other methods, such as hybrid bonding. Panel 2400 further includes solder balls 2410 attached to conductive contacts 2432. In other embodiments, panel 2400 does not include solder balls 2410, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2432 as pads.

[0191] The die 2404 is attached to the PIC 2462 via solder balls 2419, which are attached to pads 2431 and 2433 belonging to the die 2404 and the PIC 2462, respectively. The die 2404 can implement one or more functions, including analog functions implemented using electronic components (such as transistors). In some embodiments, the die 2404 can control the behavior of the PIC and / or act as an interface between the PIC 2462 and other panel components (e.g., the die 2408). In the context of communicating with the PIC, the die 2404 can be referred to as an electronic integrated chip (EIC), and the PIC 2462 and the die 2404 can be collectively referred to as a PIC-EIC pair.

[0192] The waveguide interposer 2427 includes a waveguide 2464 that provides a path for optical communication of optical signals generated or received by the PIC 2462 or the FAU 2421. The waveguide interposer 2427 may be formed as part of the panel 2400 during assembly of the panel.

[0193] Fig.25 25 is a simplified cross-sectional illustration of an example coreless panel including photonic integrated circuits and local interconnect components. Panel 2500 includes integrated circuit dies 2504 and 2508 attached to a vertically stacked set of dielectric layers 2522 (2522a, 2522b, 2522c, 2522d), a photonic integrated circuit 2562, a waveguide interposer 2527, and a thermal management solution 2509.

[0194] The upper surface contact layer 2556 includes solder resist or other suitable dielectric material 2512 and conductive contacts 2526, which are arranged to correspond to the pinouts of the tube cores 2504 and 2508 directly attached to the conductive contacts 2526. The upper surface contact layer 2556 (and therefore, the conductive contacts 2526) are located on the top dielectric layer (e.g., 2522a) of the dielectric layer 2522. The conductive contact set 2526 is arranged at a fine pitch. The lower surface contact layer 2560 includes solder resist or other suitable dielectric material 2518, and the conductive contacts 2532 are arranged to correspond to the desired panel-level pinouts. The lower surface contact layer 2560 (and therefore, the conductive contacts 2532) are located on the bottom dielectric layer (e.g., 2522d) of the dielectric layer 2522. The conductive contact sets 2532 are arranged at a pitch that is greater than the pitch at which the conductive contact sets 2526 are arranged.

[0195] The dielectric layer 2522 includes conductive traces 2528a and vias 2528b. The local interconnect features including vias 2528b and conductive traces 2528a included in the region 2562 provide a conductive path between conductive contacts 2526 attached to the die 2504 and conductive contacts 2526 attached to the die 2508.

[0196] Dies 2504 and 2508 are attached to conductive contacts 2526 via solder balls 2538. In other embodiments, dies 2504 and 2508 may be attached to conductive contacts 2526 via other methods, such as hybrid bonding. Panel 2500 further includes solder balls 2510 attached to conductive contacts 2532. In other embodiments, panel 2500 does not include solder balls 2510, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2532 as pads.

[0197] The die 2504 is attached to the PIC 2562 via solder balls 2519, which are attached to pads 2531 and 2533 belonging to the die 2504 and the PIC 2562, respectively. The die 2504 can implement one or more functions, including analog functions implemented using electronic components (such as transistors). In some embodiments, the die 2504 can control the behavior of the PIC and / or act as an interface between the PIC 2562 and other panel components (e.g., die 2508). In the context of communicating with the PIC, 2504 can be referred to as an electronic integrated chip (EIC), and the PIC 2562 and the die 2504 can be collectively referred to as a PIC-EIC pair.

[0198] The waveguide interposer 2527 includes a waveguide 2564 that provides a path for optical communication of optical signals generated or received by the PIC 2462 or the FAU 2421. The waveguide interposer 2527 may be formed as part of the panel 2500 during assembly of the panel.

[0199] Figure 22-25 The "coreless" panels and panel sections shown in FIG. are illustrative only. Also, as previously discussed, the coreless panels and panel sections may be Figure 22-25 More integrated circuit dies as shown are attached to the panel, and a die attached to or incorporated into the panel may have a different lateral size, area, shape, height and / or implement different functionality than another die attached to or incorporated into the panel.

[0200] Figure 22-25 The upper surface contact layer (e.g., 2226, 2326, 2426, 2526) illustrated in FIG. 2 may take the form of other upper surface contact layer embodiments, such as in combination with Figure 7 those described (e.g., 726a, 726b). Figure 22-25 The lower surface contact layer (e.g., 2260, 2360, 2460) illustrated in FIG. 2 may take the form of other lower surface contact layer embodiments, such as in combination with Figure 7 Those described (e.g., lower surface contact layer embodiment 760).

[0201] Figure 22-25 The thermal management solutions illustrated in (eg, 2209, 2309, 2409, 2509) may include any cooling component described or referenced herein and attached to an integrated circuit component or integrated circuit die via a thermal interface material.

[0202] Figure 24-25The fiber array units (e.g., 2421, 2521) illustrated in the figure can be attached to the panel during panel manufacturing and can be part of the end panel product or attached to the panel after panel manufacturing. Any of the FAUs described or referenced herein may include an optical fiber (e.g., 2425, 2525) that is part of the optical connection between panels in a system or between panels across different systems.

[0203] Figure 24-25 The waveguide interposer illustrated in FIG. 24 (e.g., 2427, 2527) may include any glass described or referenced herein, or include any of the glass layers described or referenced herein (e.g., Figure 3 , 5 -6 glass reinforcement layer) may include materials.

[0204] Figure 22-25 The coreless panel embodiment illustrated in includes various panel features that can be independently integrated into the panel. Figure 22-25 The panel features illustrated in the drawings, along with various other panel features described herein, are independent of each other and can be mixed and matched to produce a Figure 22-25 These panel features include local interconnects that are integrally formed with the dielectric layers of the panel and provide electrical communication between the die in the panel, local interconnect components that are separately manufactured during panel manufacturing and placed within the panel and provide electrical communication between the die, PIC and waveguide interposers, and vertically stacked packaged or unpackaged die in the panel.

[0205] Fig.26 is a fourth example method of forming a panel. At 2604 in method 2600, the following are formed on a glass carrier: a plurality of dielectric layers, individual dielectric layers of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts on a top dielectric layer of the dielectric layers; and a plurality of second conductive contacts on a bottom dielectric layer of the dielectric layers, the first conductive contacts being arranged at a first pitch less than 100 nm, the second conductive contacts being arranged at a second pitch greater than the first pitch. At 2608, one or more integrated circuit dies are attached to the first conductive contacts. At 2612, the glass carrier is removed from the dielectric layers.

[0206] The sequence of elements in method 2600 is non-limiting. The operations of method 2600 may be performed in a different order, and operations may be added or subtracted without changing the final product. For example, method 2600 may further include etching one or more of the dielectric layers to create a cavity; and positioning a bridge in the cavity, the bridge comprising one or more conductive traces and one or more vias.

[0207] Various non-limiting embodiments of panel architectures and methods for manufacturing the panel architectures have been described. The disclosed panel embodiments can enable high performance computing (e.g., zettascale computing) applications using panels with sizes exceeding those possible through wafer-level integration. The provided embodiments enable system-level heterogeneous integration of computing, I / O, memory, power management integrated circuit components and dies (which can include vertical stacking of integrated circuit components and dies), and thermal cooling solutions.

[0208] Fig. 27 2702 is a top view of a wafer 2700 and die 2702 that may be included in any of the embodiments disclosed herein. The wafer 2700 may be composed of semiconductor materials and may include one or more die 2702 formed on a surface of the wafer 2700. After the fabrication of integrated circuit components on the wafer 2700 is completed, the wafer 2700 may undergo a singulation process in which the die 2702 are separated from one another to provide discrete "chips" or integrated circuit components designated for packaging. The individual die 2702 that include the integrated circuit components may include one or more transistors (e.g., Fig.28 Some of the transistors 2840, as discussed below) are used to route electrical signals to transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or supporting circuits of any other integrated circuit components. In some embodiments, wafer 2700 or die 2702 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Additionally, multiple devices may be combined on a single die 2702. For example, a memory array formed by multiple memory devices may be formed on the same die 2702 as a processor unit (e.g., Fig.30 The processor unit 3002 of the embodiment of the present invention may be a processor unit 3002 or other logic configured to store information in a memory device or execute instructions stored in a memory array. In some embodiments, the die 2702 may be attached to a wafer 2700 that includes other dies and the wafer 2700 is then singulated, a manufacturing process known as die-to-wafer assembly technology.

[0209] Fig.282800, which may be included in any of the embodiments disclosed herein. One or more of the integrated circuits 2800 may be included in one or more dies 2702 ( Fig. 27 ). The integrated circuit 2800 may be formed on a die substrate 2802 (eg, Fig. 27 2700) and may be included in a die (e.g., Fig. 27 In the tube core 2702).

[0210] The die substrate 2802 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 2802 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 2802 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 2802. Although some examples of materials from which the die substrate 2802 may be formed may be formed here, materials that may be used as the basis for the integrated circuit 2800 may be used. The die substrate 2802 may be a portion of a singulated die (e.g., Fig. 27 2702 in the tube) or wafer (e.g., Fig. 27 chip 2700).

[0211] The integrated circuit 2800 may include one or more device layers 2804 disposed on a die substrate 2802. The device layer 2804 may include features of one or more transistors 2840 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 2802. The transistor 2840 may include, for example, one or more source and / or drain (S / D) regions 2820, a gate 2822 to control current flow between the S / D regions 2820, and one or more S / D contacts 2824 to route electrical signals to or from the S / D regions 2820.

[0212] The gate 2822 may be formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include a layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0213] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2840 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a fill metal layer. Further metal layers, such as barrier layers, may be included for other purposes.

[0214] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0215] In some embodiments, when viewed as a cross section of transistor 2840 along the source-channel-drain direction, the gate electrode may include a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 2802 and two sidewall portions substantially perpendicular to the top surface of die substrate 2802. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 2802 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 2802. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0216] In some embodiments, sidewall spacer pairs may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two, three, or four sidewall spacer pairs may be formed on opposite sides of the gate stack.

[0217] The S / D region 2820 may be formed within the die substrate 2802 adjacent to the gate 2822 of the individual transistor 2840. The S / D region 2820 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 2802 to form the S / D region 2820. An annealing process to activate the dopants and diffuse them further into the die substrate 2802 may follow the ion implantation process. In the latter process, the die substrate 2802 may first be etched to form a recess at the location of the S / D region 2820. An epitaxial deposition process may then be implemented to fill the recess with the material used to manufacture the S / D region 2820. In some implementations, the S / D region 2820 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, S / D region 2820 may be formed using one or more alternative semiconductor materials such as germanium or III-V materials or alloys. In further embodiments, S / D region 2820 may be formed using one or more metal and / or metal alloy layers.

[0218] Electrical signals, such as power and / or input / output (I / O) signals, may be transmitted through one or more interconnect layers (in the Fig.28 2806-2810) to and / or from devices (e.g., transistors 2840) of device layer 2804. For example, conductive features (e.g., gates 2822 and S / D contacts 2824) of device layer 2804 can be electrically coupled to interconnect structures 2828 of interconnect layers 2806-2810. The one or more interconnect layers 2806-2810 can form a metallization stack (also referred to as an "ILD stack") 2819 of integrated circuit 2800.

[0219] Interconnect structures 2828 may be arranged within interconnect layers 2806-2810 to route electrical signals according to a wide variety of designs; in particular, the arrangements are not limited to Fig.28 Although the specific configuration of the interconnect structure 2828 is depicted in FIG. Fig.28 A particular number of interconnect layers 2806 - 2810 are depicted in FIG. 2 , but embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than depicted.

[0220] In some embodiments, the interconnect structure 2828 may include lines 2828a and / or vias 2828b filled with a conductive material such as a metal. The lines 2828a may be arranged to route electrical signals in a planar direction substantially parallel to the surface of the die substrate 2802 on which the device layer 2804 is formed. For example, the lines 2828a may route electrical signals in a direction in and out of the page and / or in a direction across the page. The vias 2828b may be arranged to route electrical signals in a planar direction substantially perpendicular to the surface of the die substrate 2802 on which the device layer 2804 is formed. In some embodiments, the vias 2828b may electrically couple the lines 2828a of different interconnect layers 2806-2810 together.

[0221] Interconnect layers 2806-2810 may include dielectric material 2826 disposed between interconnect structures 2828, such as Fig.28 . In some embodiments, the dielectric material 2826 disposed between the interconnect structures 2828 in different ones of the interconnect layers 2806-2810 can have different compositions; in other embodiments, the composition of the dielectric material 2826 between different interconnect layers 2806-2810 can be the same. The device layer 2804 can include a dielectric material 2826 disposed between the transistor 2840 and the bottom layer of the metallization stack. The dielectric material 2826 included in the device layer 2804 can have a different composition than the dielectric material 2826 included in the interconnect layers 2806-2810; in other embodiments, the composition of the dielectric material 2826 in the device layer 2804 can be the same as the dielectric material 2826 included in any one of the interconnect layers 2806-2810.

[0222] A first interconnect layer 2806 (referred to as metal 1 or "M1") can be formed directly on the device layer 2804. In some embodiments, as shown, the first interconnect layer 2806 can include lines 2828a and / or vias 2828b. The lines 2828a of the first interconnect layer 2806 can be coupled to contacts (e.g., S / D contacts 2824) of the device layer 2804. The vias 2828b of the first interconnect layer 2806 can be coupled to the lines 2828a of the second interconnect layer 2808.

[0223] A second interconnect layer 2808 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 2806. In some embodiments, the second interconnect layer 2808 may include vias 2828b to couple lines 2828 of the second interconnect layer 2808 with lines 2828a of the third interconnect layer 2810. Although the lines 2828a and vias 2828b are structurally depicted with the lines within individual interconnect layers for clarity, in some embodiments, the lines 2828a and vias 2828b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0224] A third interconnect layer 2810 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) may be formed successively on the second interconnect layer 2808 according to similar techniques and configurations as described in connection with the second interconnect layer 2808 or the first interconnect layer 2806. In some embodiments, "higher" interconnect layers (i.e., farther from the device layer 2804) in the metallization stack 2819 in the integrated circuit 2800 may be thicker than lower interconnect layers in the metallization stack 2819, and the lines 2828a and vias 2828b in the higher interconnect layers may be thicker than the lines and vias in the lower interconnect layers.

[0225] Integrated circuit 2800 may include solder resist material 2834 (eg, polyimide or similar material) and one or more conductive contacts 2836 formed on interconnect layers 2806-2810. Fig.28 , the conductive contact 2836 is illustrated as being in the form of a bonding pad. The conductive contact 2836 can be electrically coupled to the interconnect structure 2828 and configured to route the electrical signal of the (one or more) transistors 2840 to an external device. For example, a solder bond can be formed on one or more conductive contacts 2836 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit 2800 to another component (e.g., a printed circuit board). The integrated circuit 2800 may include additional or alternative structures to route electrical signals from the interconnect layers 2806-2810; for example, the conductive contacts 2836 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0226] In some embodiments where the integrated circuit 2800 is a double-sided die, the integrated circuit 2800 may include another metallization stack (not shown) on the opposite side of the device layer(s) 2804. The metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 2806-2810 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 2804 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 2800 from the conductive contacts 2836.

[0227] In other embodiments where the integrated circuit 2800 is a double-sided die, the integrated circuit 2800 may include one or more through-silicon vias (TSVs) through the die substrate 2802; these TSVs may contact the device layer(s) 2804 and may provide a conductive path between the device layer(s) 2804 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 2800 from the conductive contacts 2836. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of the integrated circuit 2800 from the conductive contacts 2836 to the transistors 2840 and any other components integrated into the die 2800, and the metallization stack 2819 may be used to route I / O signals from the conductive contacts 2836 to the transistors 2840 and any other components integrated into the die 2800.

[0228] Multiple integrated circuits 2800 can be stacked with one or more TSVs in individual stacked devices to provide a connection between one of the devices and any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between the individual HBM and base integrated circuit dies. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0229] Fig.29 2900. The microelectronic assembly 2900 is a cross-sectional side view of a microelectronic assembly 2900 that may include any of the embodiments disclosed herein. The microelectronic assembly 2900 includes a plurality of integrated circuit components disposed on a circuit board 2902 (which may be a motherboard, a system board, a mainboard, etc.). The microelectronic assembly 2900 may include components disposed on a first side 2940 of the circuit board 2902 and an opposing second side 2942 of the circuit board 2902; in general, the components may be disposed on one or both sides 2940 and 2942.

[0230] In some embodiments, circuit board 2902 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2902 (optionally in conjunction with other metal layers). In other embodiments, circuit board 2902 may be a non-PCB substrate. Fig.29The microelectronic assembly 2900 illustrated in FIG. 1 includes a package-on-interposer structure 2936 coupled to a first side 2940 of a circuit board 2902 via a coupling component 2916. The coupling component 2916 can electrically and mechanically couple the package-on-interposer structure 2936 to the circuit board 2902 and can include solder balls (e.g., Fig.29 ), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0231] Package-on-interposer structure 2936 may include integrated circuit component 2920 coupled to interposer 2904 via coupling component 2918. Coupling component 2918 may take any suitable form for the application, such as those discussed above with reference to coupling component 2916. Fig.29 A single integrated circuit component 2920 is shown in FIG. 2 , but multiple integrated circuit components may be coupled to interposer 2904 ; indeed, additional interposers may be coupled to interposer 2904 . Interposer 2904 may provide an intermediate substrate for bridging circuit board 2902 and integrated circuit components 2920 .

[0232] Integrated circuit component 2920 may be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (eg, Fig. 27 The tube core 2702, Fig.28 integrated circuit 2800) and / or one or more other suitable components.

[0233] The unpackaged integrated circuit component 2920 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 2904. In embodiments where the integrated circuit component 2920 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or two or more different types (a heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component 2920 may include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, an input / output (I / O) controller, or a memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (such as The packaged multi-die integrated circuit components may be referred to as multi-chip packages (MCPs) or multi-chip modules (MCMs).

[0234] Interposer 2904 can extend the connection to a wider pitch, or reroute the connection to a different connection. For example, interposer 2904 can couple integrated circuit component 2920 to a ball grid array (BGA) conductive contact set of coupling component 2916 for coupling to circuit board 2902. Fig.29 In the embodiment illustrated in , integrated circuit component 2920 and circuit board 2902 are attached to opposite sides of interposer 2904; in other embodiments, integrated circuit component 2920 and circuit board 2902 may be attached to the same side of interposer 2904. In some embodiments, three or more components may be interconnected by way of interposer 2904.

[0235] In some embodiments, the interposer 2904 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 2904 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 2904 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2904 may include metal interconnects 2908 and vias 2910, including but not limited to through-vias 2910-1 (which extend from the first side 2950 of the interposer 2904 to the second side 2954 of the interposer 2904), blind vias 2910-2 (which extend from the first or second side 2950 or 2954 of the interposer 2904 to the internal metal layers) and buried vias 2910-3 (which connect the internal metal layers).

[0236] In some embodiments, interposer 2904 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 2904 including a silicon interposer may further include one or more routing layers to route connections on a first side of interposer 2904 to an opposite second side of interposer 2904.

[0237] Interposer 2904 may further include embedded devices 2914, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on interposer 2904. Package-on-interposer structure 2936 may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board, the interposer may be formed on a plurality of interposers.

[0238] The integrated circuit component 2900 may include an integrated circuit component 2924 coupled to the first side 2940 of the circuit board 2902 via a coupling component 2922. The coupling component 2922 may take the form of any of the embodiments discussed above with reference to the coupling component 2916, and the integrated circuit component 2924 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 2920.

[0239] Fig.29 The integrated circuit assembly 2900 illustrated in the figure includes a package-on-package structure 2934 coupled to the second side 2942 of the circuit board 2902 by a coupling component 2928. The package-on-package structure 2934 may include an integrated circuit component 2926 and an integrated circuit component 2932 coupled together by a coupling component 2930, such that the integrated circuit component 2926 is disposed between the circuit board 2902 and the integrated circuit component 2932. The coupling components 2928 and 2930 may take the form of any of the embodiments of the coupling component 2916 discussed above, and the integrated circuit components 2926 and 2932 may take the form of any of the embodiments of the integrated circuit component 2920 discussed above. The package-on-package structure 2934 may be configured according to any of the package-on-package structures known in the art.

[0240] Fig.30 2900, or one or more of the structures disclosed herein. Fig.30 3000, but any one or more of these components may be omitted or duplicated as applicable to the application. In some embodiments, some or all of the components included in the electrical device 3000 may be attached to one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-chip (SoC) die. In various embodiments, the electrical device 3000 is enclosed by or integrated with a housing.

[0241] Additionally, in various embodiments, the electrical device 3000 may not include Fig.30 , but the electrical device 3000 may include interface circuitry for coupling to one or more of the components illustrated in . For example, the electrical device 3000 may not include the display device 3006, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 3006 may be coupled. In another example set, the electrical device 3000 may not include the audio input device 3024 or the audio output device 3008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 3024 or the audio output device 3008 may be coupled.

[0242] The electrical device 3000 may include one or more processor units 3002 (e.g., one or more processor units). As used herein, the term "processor unit", "processing unit" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 3002 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, a processor unit may be referred to as an XPU (or xPU).

[0243] The electrical device 3000 may include a memory 3004, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 3004 may include memory located on the same integrated circuit die as the processor unit 3002. The memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (lL4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0244] In some embodiments, electrical device 3000 may include one or more processor units 3002 that are heterogeneous or asymmetric with respect to another processor unit in electrical device 3000. A wide variety of differences may exist between processor units 3002 in the system in terms of a spectrum of metrics including architecture, microarchitecture, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity among processor units 3002 in electrical device 3000.

[0245] In some embodiments, the electrical device 3000 may include a communication component 3012 (e.g., one or more communication components). For example, the communication component 3012 may manage wireless communications for transmitting data to and from the electrical device 3000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may use modulated electromagnetic radiation to transmit data through a non-solid medium. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0246] The communication component 3012 can implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project together with any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. The communication component 3012 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 3012 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 3012 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivative protocols, as well as any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication component 3012 can operate according to other wireless protocols. The electrical device 3000 may include an antenna 3022 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0247] In some embodiments, the communication component 3012 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As noted above, the communication component 3012 can include multiple communication components. For example, the first communication component 3012 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 3012 can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 3012 can be dedicated to wireless communications, and the second communication component 3012 can be dedicated to wired communications.

[0248] The electrical device 3000 may include a battery / power circuit 3014. The battery / power circuit 3014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 3000 to an energy source separate from the electrical device 3000 (e.g., AC line power).

[0249] The electrical device 3000 may include a display device 3006 (or corresponding interface circuitry, as discussed above). The display device 3006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0250] The electrical device 3000 may include an audio output device 3008 (or corresponding interface circuitry, as discussed above). The audio output device 3008 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0251] The electrical device 3000 may include an audio input device 3024 (or corresponding interface circuitry, as discussed above). The audio input device 3024 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 3000 may include a global navigation satellite system (GNSS) device 3018 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. The GNSS device 3018 may communicate with a satellite-based system and, as is known in the art, may determine the geographic location of the electrical device 3000 based on information received from one or more GNSS satellites.

[0252] The electrical device 3000 may include another output device 3010 (or corresponding interface circuitry, as discussed above). Examples of another output device 3010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0253] The electrical device 3000 may include another input device 3020 (or corresponding interface circuitry, as discussed above). Examples of another input device 3020 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereo camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0254] The electrical device 3000 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or equipment, a manufacturing equipment). In some embodiments, the electrical device 3000 may be any other electronic device that processes data. In some embodiments, the electrical device 3000 may include multiple discrete physical components. Given the range of devices that the electrical device 3000 may represent, as in various embodiments, in some embodiments, the electrical device 3000 may be referred to as a computing device or a computing system.

[0255] Thus, embodiments of improved via structures for use with embedded components have been provided. The provided embodiments advantageously enable the use of finer pitch architectures and high density input / output (I / O) designs in multi-chip packages.

[0256] Although at least one embodiment has been presented in the foregoing detailed description, it will be appreciated that there are a large number of variations. It will also be appreciated that the disclosed embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. On the contrary, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the disclosed embodiments. Various changes may be made to the function and arrangement of elements without departing from the scope of the present disclosure as set forth in the appended claims and their legal equivalents.

[0257] As used herein, phrases such as "an embodiment," "various embodiments," "some embodiments," and the like indicate that some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe common objects and indicate different instances of similar objects referred to; unless specifically stated, they do not imply a given sequence in time or space in a ranking or any other manner. According to the patent application, "connected" indicates elements that are in direct physical or electrical contact with each other, and "coupled" indicates elements that cooperate or interact with each other, and the coupled elements may or may not be in direct physical or electrical contact. Furthermore, the terms "include," "comprise," "have," and the like are used synonymously to indicate non-exclusive inclusion.

[0258] As used in the present application and claims, a list of items joined by the term "at least one of" or the term "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0259] As used in this application and the claims, the phrase "an individual of" or "a corresponding one of" followed by a list of items that are enumerated or claimed to have a property, characteristic, etc. means that all items in the list possess the claimed or enumerated property, characteristic, etc. For example, the phrase "an individual of A, B, or C includes a sidewall" or "a corresponding one of A, B, or C includes a sidewall" means that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0260] For the purpose of better understanding, the operating theories, scientific principles or other theoretical descriptions presented herein with reference to the devices or methods of the present disclosure have been provided and are not intended to be limiting in scope. The devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such operating theories.

[0261] The following examples pertain to additional embodiments of the techniques disclosed herein.

[0262] Example A1 includes: a first dielectric layer, comprising conductive pads arranged at a first pitch; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged into a first set and a second set, the first set of conductive contacts being further arranged at a second pitch; a glass layer located between the first dielectric layer and the second dielectric layer; a local interconnect component located in the glass layer, the local interconnect component being used to provide electrical communication between a first conductive contact in the first set and a first conductive contact in the second set; and a conductive path between a second conductive contact in the first set and one of the conductive pads, the conductive path comprising an interconnect structure.

[0263] Example A2 includes the subject matter of Example A1, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or the second dielectric layer, and wherein the conductive path further includes a second interconnect structure located in the glass layer and coupled to the first interconnect structure.

[0264] Example A3 includes the subject matter of Example A1, wherein the interconnect structure is a first interconnect structure located in a first dielectric layer, wherein the conductive path further includes a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is configured to couple the first interconnect structure to the third interconnect structure.

[0265] Example A4 includes the subject matter of any of Examples A1-A3, wherein the interconnect structure includes conductive traces and vias.

[0266] Example A5 includes the subject matter of Example A1, wherein the first dielectric layer includes more than one sub-layer, the individual sub-layers including respective conductive traces and vias.

[0267] Example A6 includes the subject matter of Example A1, wherein the second dielectric layer includes more than one sub-layer, the individual sub-layers including respective conductive traces and vias.

[0268] Example A7 includes the subject matter of Example A1, wherein the glass layer includes a glass sheet.

[0269] Example A8 includes the subject matter of Example A1, wherein the glass layer includes more than one glass sheet.

[0270] Example A9 includes the subject matter of Example A1, wherein the glass layer includes more than one glass sheet, and respective glass sheets have a thickness in a range of 100-150 microns.

[0271] Example A10 includes the subject matter of Example A1, wherein the glass layer has a thickness substantially in the range of 300 micrometers to 1 millimeter.

[0272] Example A11 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer adjacent thereto.

[0273] Example A12 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer comprises an Ajinomoto built-up film (ABF).

[0274] Example A13 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer is substantially 10 microns thick.

[0275] Example A14 includes the subject matter of Example A1, wherein the glass layer includes silicon and oxygen.

[0276] Example A15 includes the subject matter of Example A14, wherein the glass layer further includes aluminum, boron, or an alkaline earth metal.

[0277] Example A16 includes the subject matter of Example A1, wherein the local interconnect component comprises silicon.

[0278] Example A17 includes the subject matter of Example A1, wherein the local interconnect component is a redistribution layer.

[0279] Example A18 includes the subject matter of any of Examples A1-A17, further comprising: a first die attached to the first set of conductive contacts; and a second die attached to the second set of conductive contacts.

[0280] Example A19 includes the subject matter of any of Examples A1-A17, further including: a first die attached to a first set of conductive contacts; a second die attached to a second set of conductive contacts; and wherein the first die has a first functionality and the second die has a second functionality that is different from the first functionality.

[0281] Example A20 includes the subject matter of any of Examples A1-A17, further comprising a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

[0282] Example A21 includes the subject matter of any of Examples A18-A20, further including an encapsulant over the first die and the second die.

[0283] Example A22 includes the subject matter of Example A21, wherein the device is a panel and further includes a cooling component located on the panel.

[0284] Example A23 includes the subject matter of Example A22, wherein the cooling component includes a heat exchanger.

[0285] Example A24 includes the subject matter of Example A21 or Example A22, wherein the apparatus is a first panel and further includes a second panel in electrical communication with the first panel.

[0286] Example A25 includes the subject matter of Example A24, further comprising: a substrate; the first panel and the second panel are attached to the substrate.

[0287] Example A26 includes the subject matter of Example A25, further comprising an electronic component attached to the substrate, the electronic component being located outside of the first panel and the second panel.

[0288] Example A27 includes the subject matter of Example A26, and further comprises: a housing enclosing the panel; and a heat pump connected to a heat exchanger on the panel via a conduit.

[0289] Example A28 includes the subject matter of any of Examples A25-A29, further comprising a power management system electrically coupled to the panel.

[0290] Example A29 is a method comprising: forming a first dielectric layer on a glass carrier, the glass carrier having an area of ​​at least 250 mm × 250 mm, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising local interconnect components; positioning a second dielectric layer on the glass layer, the second dielectric layer comprising: conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first set and a second set; the local interconnect components being used to provide electrical communication between a first conductive contact in the first set and a first conductive contact in the second set; and positioning an interconnect structure in the glass layer, the interconnect structure being used to provide electrical communication between a second conductive contact of the first set and one of the conductive pads.

[0291] Example A30 includes the subject matter of Example A29, further comprising: attaching a first die to the first set; and attaching a second die to the second set, thereby creating a populated substrate.

[0292] Example A31 includes the subject matter of Example A30, further comprising: peeling the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0293] Example A32 includes the subject matter of Example A31, further comprising singulating the populated substrate to thereby create the first panel and the second panel.

[0294] Example A33 includes the subject matter of Example A32, further comprising attaching the thermal solution to the first panel or the second panel.

[0295] Example A34 is a device comprising: a first dielectric layer comprising conductive pads arranged at a first pitch; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged into a first set and a second set, the first set of conductive contacts being arranged at a second pitch smaller than the first pitch; a glass layer located between the first dielectric layer and the second dielectric layer, the glass layer comprising through-glass vias; a photonic integrated circuit (PIC) located in the glass layer and electrically communicating with a first conductive contact from the first set; and a conductive path from a second conductive contact of the first set to one of the conductive pads, the conductive path comprising an interconnect structure positioned in the first dielectric layer or the second dielectric layer.

[0296] Example A35 includes the subject matter of Example A34, wherein the PIC comprises a silicon microring resonator.

[0297] Example A36 includes the subject matter of Example A34, further comprising a waveguide associated with the PIC located in the glass layer.

[0298] Example A37 includes the subject matter of any of Examples A34-A36, wherein the interconnect structure includes conductive traces and vias.

[0299] Example A38 includes the subject matter of Example A34, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or the second dielectric layer, and wherein the conductive path further includes a second interconnect structure located in the glass layer and coupled to the first interconnect structure.

[0300] Example A39 includes the subject matter of Example A34, wherein the interconnect structure is a first interconnect structure located in a first dielectric layer, wherein the conductive path further includes a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is configured to couple the first interconnect structure to the third interconnect structure.

[0301] Example A40 includes the subject matter of any of Examples A38-A39, wherein the first dielectric layer includes more than one sublayer, the individual sublayers including respective conductive traces and vias.

[0302] Example A41 includes the subject matter of any of Examples A38-A40, wherein the second dielectric layer includes more than one sublayer, the individual sublayers including respective conductive traces and vias.

[0303] Example A42 includes the subject matter of any of Examples A34-A41, wherein the glass layer includes a glass sheet.

[0304] Example A43 includes the subject matter of any of Examples A34-A41, wherein the glass layer includes more than one glass sheet.

[0305] Example A44 includes the subject matter of any of Examples A34-A41, wherein the glass layer includes more than one glass sheet, and the respective glass sheets have a thickness in a range of 100-150 microns.

[0306] Example A45 includes the subject matter of any of Examples A34-A41, wherein the thickness of the glass layer is substantially in the range of 300 micrometers to 1 millimeter.

[0307] Example A46 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer positioned adjacent thereto.

[0308] Example A47 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer comprises an Ajinomoto built-up film (ABF).

[0309] Example A48 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer is substantially 10 microns thick.

[0310] Example A49 includes the subject matter of Example A34, wherein the glass layer includes silicon and oxygen.

[0311] Example A50 includes the subject matter of Example A34, wherein the glass layer further includes aluminum, boron, or an alkaline earth metal.

[0312] Example A51 includes the subject matter of any of Examples A34-A50, further comprising a local interconnect component located in the glass layer, the local interconnect component providing electrical communication between a third conductive contact located in the first set and a fourth conductive contact located in the second set.

[0313] Example A52 includes the subject matter of any of Examples A34-A51, further comprising a first die attached to the first set of conductive contacts and a second die attached to the second set of conductive contacts.

[0314] Example A53 includes the subject matter of any of Examples A34-A51, further comprising: a first die attached to a first set of conductive contacts; a second die attached to a second set of conductive contacts; and wherein the first die has a first functionality and the second die has a second functionality that is different from the first functionality.

[0315] Example A54 includes the subject matter of any of Examples A34-A51, further comprising a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

[0316] Example A55 includes the subject matter of any of Examples A52-A54, further including an encapsulant over the first die and the second die.

[0317] Example A56 includes the subject matter of Example A55, wherein the device is a panel and further includes a cooling component located on the panel.

[0318] Example A57 includes the subject matter of Example A56, wherein the cooling component includes a heat exchanger.

[0319] Example A58 includes the subject matter of any of Examples A56-A57, wherein the device is a first panel and further includes a second panel in electrical communication with the first panel.

[0320] Example A59 includes the subject matter of Example A58, further comprising: a substrate; and a first panel and a second panel attached to the substrate.

[0321] Example A60 includes the subject matter of Example A59, further comprising an electronic component attached to the substrate, the electronic component being located outside of the first panel and the second panel.

[0322] Example A61 includes the subject matter of Example A58, and further comprises: a housing enclosing the first panel; and a heat pump connected to the heat exchanger on the panel via a conduit.

[0323] Example A62 includes the subject matter of Example A58, further comprising a power management system electrically coupled to the panel.

[0324] Example A63 is a method comprising: forming a first dielectric layer on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm × 250 mm, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising a photonic integrated circuit (PIC); positioning a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first set and a second set; the PIC being configured to electrically communicate with a first conductive contact in the first set or the second set; and positioning an interconnect structure in the glass layer, the interconnect structure being used to provide electrical communication between a second conductive contact of the first set and one of the conductive pads.

[0325] Example A64 includes the subject matter of Example A63, further comprising: attaching a first die to the first set; and attaching a second die to the second set, thereby creating a populated substrate.

[0326] Example A65 includes the subject matter of Example A64, further comprising: peeling the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0327] Example A66 includes the subject matter of Example A65, further comprising singulating the populated substrate to thereby create the first panel and the second panel.

[0328] Example A67 includes the subject matter of Example A66, further comprising attaching the thermal solution to the first panel or the second panel.

[0329] Example A68 is a device comprising: a first dielectric layer comprising conductive pads arranged at a first pitch; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first set and a second set; a glass layer located between the first dielectric layer and the second dielectric layer; a microchannel located in the glass layer, the microchannel being configured to accommodate the flow of a liquid coolant; and a conductive path from a second conductive contact of the first set or the second set to one of the conductive pads, the conductive path comprising an interconnect structure positioned in the first dielectric layer, the second dielectric layer, or the glass layer.

[0330] Example A69 includes the subject matter of Example A68, wherein the microchannel has a lateral portion proximate to the first set of conductive contacts.

[0331] Example A70 includes the subject matter of Example A68, further comprising a cavity located in the glass layer.

[0332] Example A71 includes the subject matter of Example A68, wherein the interconnect structure includes conductive traces and vias.

[0333] Example A72 includes the subject matter of Example A71, wherein the interconnect structure is located in the first dielectric layer.

[0334] Example A73 includes the subject matter of Example A72, wherein the interconnect structure is a first interconnect structure and further includes a second interconnect structure located in the second dielectric layer, the second interconnect structure coupled to the first interconnect structure via a through-glass via in the glass layer.

[0335] Example A74 includes the subject matter of Example A68, wherein the first dielectric layer includes more than one sublayer, the individual sublayers including corresponding conductive traces and vias.

[0336] Example A75 includes the subject matter of Example A68, wherein the second dielectric layer includes more than one sublayer, the individual sublayers including corresponding conductive traces and vias.

[0337] Example A76 includes the subject matter of Example A68, wherein the glass layer includes a glass sheet.

[0338] Example A77 includes the subject matter of Example A68, wherein the glass layer includes more than one glass sheet.

[0339] Example A78 includes the subject matter of Example A68, wherein the glass layer includes more than one glass sheet, and the respective glass sheets have a thickness in the range of 100-150 microns.

[0340] Example A79 includes the subject matter of Example A68, wherein the glass layer has a thickness substantially in the range of 300 micrometers to 1 millimeter.

[0341] Example A80 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer positioned adjacent thereto.

[0342] Example A81 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer comprises an Ajinomoto built-up film (ABF).

[0343] Example A82 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer is substantially 10 microns thick.

[0344] Example A83 includes the subject matter of Example A68, wherein the glass layer includes silicon and oxygen.

[0345] Example A84 includes the subject matter of Example A83, wherein the glass layer further includes aluminum, boron, or an alkaline earth metal.

[0346] Example A85 includes the subject matter of any of Examples A68-A84, further comprising a first die attached to the first set of conductive contacts and a second die attached to the second set of conductive contacts.

[0347] Example A86 includes the subject matter of any of Examples A68-A84, further comprising: a first die attached to a first set of conductive contacts; a second die attached to a second set of conductive contacts; and wherein the first die has a first functionality and the second die has a second functionality that is different from the first functionality.

[0348] Example A87 includes the subject matter of any of Examples A68-A84, further comprising a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

[0349] Example A88 includes the subject matter of any of Examples A65-A87, further including an encapsulant over the first die and the second die.

[0350] Example A89 includes the subject matter of Example A88, wherein the device is a panel and further includes a cooling component located on the panel.

[0351] Example A90 includes the subject matter of Example A89, wherein the cooling component includes a heat exchanger.

[0352] Example A91 includes the subject matter of any of Examples A89-A90, wherein the device is a first panel and further includes a second panel in electrical communication with the first panel.

[0353] Example A92 includes the subject matter of Example A91, further comprising: a substrate; and a first panel and a second panel attached to the substrate.

[0354] Example A93 includes the subject matter of Example A92, further comprising an electronic component attached to the substrate, the electronic component being located outside of the first panel and the second panel.

[0355] Example A94 includes the subject matter of Example A93, and further comprises: a housing enclosing the panel; and a heat pump connected to a heat exchanger on the panel via a conduit.

[0356] Example A95 includes the subject matter of Example A94, further comprising a power management system electrically coupled to the panel.

[0357] Example A96 is a method comprising: forming a first dielectric layer on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm × 250 mm, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising microchannels; positioning a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first set and a second set; the microchannel being configured to have a portion proximate to the first set; and positioning an interconnect structure in the glass layer, the interconnect structure being used to provide electrical communication between the first set of conductive contacts and one of the conductive pads.

[0358] Example A97 includes the subject matter of Example A96, further comprising: attaching the first die to the first set; and attaching the second die to the second set of dies, thereby creating a populated substrate.

[0359] Example A98 includes the subject matter of Example A97, further comprising: peeling the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0360] Example A99 includes the subject matter of Example A98, further comprising singulating the populated substrate to thereby create the first panel and the second panel.

[0361] Example A100 includes the subject matter of Example A99, further comprising attaching the thermal solution to the first panel or the second panel.

[0362] Example B1 is a device comprising: one or more first dielectric layers, individual first dielectric layers in the first dielectric layer positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on the top dielectric layer of the first dielectric layer, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; one or more second dielectric layers, individual second dielectric layers positioned adjacent to another second dielectric layer, individual first dielectric layers in the first dielectric layer and individual second dielectric layers in the second dielectric layer comprising one or more conductive traces and one or more through holes; a plurality of second conductive contacts located on the bottom dielectric layer of the second dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; and a glass core comprising a glass layer, the glass core being positioned between the one or more first dielectric layers and the one or more second dielectric layers, the glass core comprising through-glass through holes.

[0363] Example B2 includes the subject matter of Example B1, further comprising a conductive path from a conductive contact in the first set of first conductive contacts to a conductive contact in the second set of first conductive contacts, the conductive path comprising a conductive trace of one of the first dielectric layers and a through hole of one of the first dielectric layers.

[0364] Example B3 includes the subject matter of Example B1, further including a conductive path from one of the first conductive contacts to one of the second conductive contacts, the conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one through hole of one of the first dielectric layers, a through-glass through hole of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one through hole of one of the second dielectric layers.

[0365] Example B4 is a device comprising: one or more first dielectric layers, an individual first dielectric layer positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layer, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; one or more second dielectric layers, an individual second dielectric layer positioned adjacent to another second dielectric layer, the individual first dielectric layer and the individual second dielectric layer comprising one or more conductive traces and one or more through holes; a plurality of second conductive contacts located on a bottom dielectric layer of the second dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a glass core comprising a glass layer, the glass core being positioned between the first dielectric layer and the second dielectric layer, the glass core comprising through-glass through holes; and a bridge located in the first dielectric layer or the glass core, the bridge comprising one or more conductive traces and one or more through holes, the bridge comprising silicon.

[0366] Example B5 includes the subject matter of Example B4, further comprising a conductive path from a conductive contact in the first set of first conductive contacts to a conductive contact in the second set of first conductive contacts, the conductive path comprising a conductive trace of the bridge and a via of the bridge.

[0367] Example B6 includes the subject matter of Example B4, further including a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one through hole of one of the first dielectric layers, a through-glass through hole of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one through hole of one of the second dielectric layers.

[0368] Example B7 includes the subject matter of Examples B4-B6, wherein the bridge spans two or more first dielectric layers.

[0369] Example B8 includes the subject matter of Examples B4-B7, wherein the bridge further includes one or more through-silicon vias.

[0370] Example B9 includes the device of any of Examples B4-B6, wherein the bridge is located in the glass core.

[0371] Example B10 includes the subject matter of Examples B4-B9, wherein the bridge includes a trench capacitor, the trench capacitor comprising a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric positioned between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second capacitor conductive trace being oriented substantially perpendicular to a surface of a top dielectric layer of the first dielectric layer.

[0372] Example B11 includes the subject matter of Examples B4-B10, wherein the bridge further comprises a plurality of conductive traces, individual ones of the conductive traces of the bridge being surrounded by a ferromagnetic material comprising iron.

[0373] Example B12 includes the subject matter of Examples B4-B11, wherein the bridge further includes a transistor.

[0374] Example B13 includes the subject matter of the example apparatus of any of Examples B1-B12, wherein the first pitch is less than approximately 1 micron.

[0375] Example B14 includes the subject matter of the example apparatus of any of Examples B1-B12, wherein the first pitch is less than approximately 0.5 microns.

[0376] Example B15 includes the subject matter of the example apparatus of any of Examples B1-B14, wherein the glass core further includes a waveguide.

[0377] Example B16 includes the subject matter of Example B15, wherein the waveguide is located in the glass layer, the waveguide comprising a dielectric material having a dielectric constant greater than the dielectric constant of the glass.

[0378] Example B17 includes the subject matter of Example B15, wherein the waveguide comprises silicon and oxygen.

[0379] Example B18 includes the subject matter of Example B15, wherein the apparatus further comprises a photonic integrated circuit, the waveguide to provide a path for optical communication of an optical signal to be generated or received by the photonic integrated circuit.

[0380] Example B19 includes the subject matter of Example B15, wherein the apparatus further comprises an optical fiber array unit, and the waveguide is used to provide a path for optical communication of an optical signal to be generated or received by the optical fiber array unit.

[0381] Example B20 includes the subject matter of any of Examples B1-B19, wherein individual ones of the through-holes are tapered, the individual ones of the through-holes comprising a narrower end and a wider end, the narrower end being positioned closer to the glass core than the wider end.

[0382] Example B21 includes the subject matter of Examples B1-B20, wherein the glass includes aluminum, oxygen, boron, silicon, and an alkaline earth metal.

[0383] Example B22 includes the subject matter of Examples B1-B20, wherein the glass includes silicon, lithium, oxygen, and a metal.

[0384] Example B23 includes the subject matter of the example apparatus of any of Example B22, wherein the metal is gold or silver.

[0385] Example B24 includes the subject matter of Examples B1-B23, wherein the glass core includes one or more microchannels.

[0386] Example B25 includes the subject matter of Example B24, wherein the one or more microchannels include one or more lateral portions and one or more vertical portions.

[0387] Example B26 includes the subject matter of Example B25, wherein the through-glass via is a first through-glass via and the one or more vertical portions of the microchannel include a second through-glass via.

[0388] Example B27 includes the subject matter of Example B25, wherein the glass core further includes a reservoir connected to at least one of the microchannels.

[0389] Example B28 includes the subject matter of Examples B24-B27, wherein the apparatus further comprises a heat exchanger, a pump, and one or more conduits for connecting one of the microchannels to the heat exchanger and / or the pump.

[0390] Example B29 includes the subject matter of Examples B1-B28, further comprising a plurality of integrated circuit dies, individual ones of the integrated circuit dies being attached to one or more of the first conductive contacts.

[0391] Example B30 includes the subject matter of Example B29, wherein a lateral dimension of a first integrated circuit die in the integrated circuit dies is different than a lateral dimension of a second integrated circuit die in the integrated circuit dies.

[0392] Example B31 includes the subject matter of Example B29, wherein a thickness of a first integrated circuit die in the integrated circuit dies is different than a thickness of a second integrated circuit die in the integrated circuit dies.

[0393] Example B32 includes the subject matter of Example B29, wherein functionality implemented by a first one of the integrated circuit dies is different from functionality implemented by a second one of the integrated circuit dies.

[0394] Example B33 includes the subject matter of Example B29, wherein one of the integrated circuit dies includes a plurality of third conductive contacts attached to the first set of first conductive contacts via solder balls.

[0395] Example B34 includes the subject matter of Example B29, wherein one of the integrated circuit dies includes a plurality of third conductive contacts directly attached to the first set of first conductive contacts.

[0396] Example B35 includes the subject matter of Example B34, wherein the third conductive contact and the first set of first conductive contacts comprise copper.

[0397] Example B36 includes the subject matter of Example B29, wherein one of the integrated circuit dies includes a bottom dielectric layer directly attached to the top dielectric layer of the first dielectric layer.

[0398] Example B37 includes the subject matter of Example B29, wherein a first integrated circuit die in the integrated circuit die includes a first surface and a second surface opposite to the first surface, the first integrated circuit die is attached to a first conductive contact at the first surface of the first integrated circuit die, and the device further includes an additional integrated circuit die, which is attached to the second surface of the first integrated circuit die.

[0399] Example B38 includes the subject matter of Example B29, further comprising: an encapsulant for encapsulating an integrated circuit die, the encapsulant comprising a through-package via; and a packaged integrated circuit component, comprising an integrated circuit component attached to the through-package via, the through-package via being attached to one of the first conductive contacts.

[0400] Example B39 includes the subject matter of Examples B1-B38, wherein the glass core has a lateral dimension of at least 250 mm.

[0401] Example B40 includes the subject matter of Examples B1-B38, wherein the glass core has a lateral dimension of at least 400 mm.

[0402] Example B41 includes the subject matter of Examples B1-B40, wherein the glass core has a rectangular shape.

[0403] Example B42 includes the subject matter of Examples B1-B40, wherein the glass core has a non-circular shape.

[0404] Example B43 includes the subject matter of Examples B29-B42, further comprising a cooling component located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

[0405] Example B44 includes the subject matter of Examples B1-B43, further including a housing comprising a first dielectric layer and a second dielectric layer.

[0406] Example B45 includes the subject matter of Examples B1-B44, further including a power management component.

[0407] Example B46 is a device comprising: a plurality of first dielectric layers, individual first dielectric layers being positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts and a second set of first conductive contacts arranged at a first pitch; a plurality of second dielectric layers, individual second dielectric layers being positioned adjacent to another second dielectric layer, individual first dielectric layers in the first dielectric layers and individual second dielectric layers in the second dielectric layers comprising one or more first conductive traces and one or more first through holes; a plurality of second conductive contacts located on a bottom dielectric layer of the second dielectric layers, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a first glass core comprising a glass layer, the first glass core being positioned between one or more first dielectric layers and one or more second dielectric layers, the first glass core comprising a first through-glass through hole; a plurality of first integrated circuit dies, individual first integrated circuit dies in the first integrated circuit dies being attached to one or more of the first conductive contacts; a plurality of a third dielectric layer; a plurality of third conductive contacts located on a top dielectric layer of the third dielectric layer; the plurality of third conductive contacts include a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth dielectric layers, individual third dielectric layers in the third dielectric layer and individual fourth dielectric layers in the fourth dielectric layer include one or more second conductive traces and one or more second through holes; a plurality of fourth conductive contacts located on a surface of a bottom dielectric layer of the fourth dielectric layer; a second glass core including a glass layer, the second glass core being located between the third dielectric layer and the fourth dielectric layer, the second glass core including second through-glass through holes; a plurality of second integrated circuit dies, individual second integrated circuit dies in the second integrated circuit dies being attached to one or more of the third conductive contacts; and a substrate including one or more fifth dielectric layers, individual fifth dielectric layers in the fifth dielectric layers including one or more conductive traces and one or more through holes, a conductive path from one of the second conductive contacts to one or the fourth conductive contact including a conductive trace of one of the fifth dielectric layers and a through hole of one of the fifth dielectric layers.

[0408] Example B47 includes the subject matter of Example B46, wherein the conductive path is a first conductive path, further comprising a second conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the second conductive path comprising a conductive trace of one of the first dielectric layers and a through hole of one of the first dielectric layers.

[0409] Example B48 includes the subject matter of Example B46, wherein the conductive path is a first conductive path, the device further includes a second conductive path from the first conductive contact to the second conductive contact, the second conductive path including at least one conductive trace of the first dielectric layer, at least one through-hole of the first dielectric layer, a first through-glass through-hole of the first glass core, a conductive trace of one of the second dielectric layers, and at least one through-hole of one of the second dielectric layers.

[0410] Example B49 is a device comprising: a plurality of first dielectric layers, individual first dielectric layers being positioned adjacent to another first dielectric layer; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second dielectric layers, individual second dielectric layers being positioned adjacent to another second dielectric layer, individual first dielectric layers and individual second dielectric layers comprising one or more first conductive traces and one or more first through holes; a plurality of first conductive contacts located on a bottom dielectric layer of the second dielectric layers a plurality of second conductive contacts arranged at a second pitch, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a first glass core comprising a glass layer, the first glass core being positioned between a first dielectric layer and a second dielectric layer, the first glass core comprising a first through-glass via; a first bridge located in the first dielectric layer or the first glass core, the first bridge comprising one or more conductive traces and one or more vias, the first bridge comprising silicon; a plurality of first integrated circuit dies, individual first integrated circuit dies of the first integrated circuit dies being attached to one or more of the first conductive contacts; a plurality of third dielectric layers; a first glass core comprising a glass layer, the first glass core being positioned between a first dielectric layer and a second dielectric layer, the first glass core comprising a first through-glass via; a first bridge located in the first dielectric layer or the first glass core, the first bridge comprising one or more conductive traces and one or more vias, the first bridge comprising silicon; a plurality of third conductive contacts on a top dielectric layer of the third dielectric layer; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth dielectric layers, individual third dielectric layers in the third dielectric layer and individual fourth dielectric layers in the fourth dielectric layer comprising one or more second conductive traces and one or more second through-holes; a plurality of fourth conductive contacts on a bottom dielectric layer of the fourth dielectric layer; a second glass core comprising a glass layer, the second glass core being between the third dielectric layer and the fourth dielectric layer, the second glass core comprising second through-glass through-holes; and a second bridge in the third dielectric layer or the second glass core, the second bridge comprising one or more conductive traces and one or more through-holes, the second bridge comprising silicon; a plurality of second integrated circuit dies, individual second integrated circuit dies in the second integrated circuit dies being attached to one or more of the third conductive contacts; and a substrate comprising one or more fifth dielectric layers, individual fifth dielectric layers in the fifth dielectric layers comprising one or more conductive traces and one or more through-holes, a conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising one of the conductive traces of the substrate and one of the through-holes of the substrate.

[0411] Example B50 includes the subject matter of Example B49, wherein the conductive path is a first conductive path, and the device further includes a second conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the second conductive path including a conductive trace of the first bridge and a through hole of the first bridge.

[0412] Example B51 includes the subject matter of Example B49, wherein the conductive path is a first conductive path, the device further includes a second conductive path from the first conductive contact to the second conductive contact, the second conductive path including at least one conductive trace of the first dielectric layer, at least one through-hole of the first dielectric layer, a first through-glass through-hole of the first glass core, a conductive trace of one of the second dielectric layers, and at least one through-hole of one of the second dielectric layers.

[0413] Example B52 includes the subject matter of Examples B46-B51, wherein the number of first integrated circuit dies is different than the number of second integrated circuit dies.

[0414] Example B53 includes the subject matter of Examples B46-B51, wherein functionality implemented by the first plurality of integrated circuit dies is different from functionality implemented by the second plurality of integrated circuit dies.

[0415] Example B54 includes the subject matter of Examples B46-B51, further comprising a cooling component located on one or more of the first integrated circuit dies and one or more of the second integrated circuit dies, wherein the cooling component comprises a liquid-cooled cold plate, a vapor chamber, or a heat sink.

[0416] Example B55 includes the subject matter of Example B54, wherein the cooling component comprises a liquid-cooled cold plate, the apparatus further comprising a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and / or the pump.

[0417] Example B56 includes the subject matter of Examples B46-B55, further comprising a housing comprising a first dielectric layer, a second dielectric layer, and a first integrated circuit die.

[0418] Example B57 includes the subject matter of Examples B46-B56, further including a power management component.

[0419] Example C1 is a device comprising: a plurality of dielectric layers stacked vertically, individual dielectric layers in the dielectric layers comprising one or more conductive traces and one or more through holes; a plurality of first conductive contacts located on a top dielectric layer of the dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; and a plurality of second conductive contacts located on a bottom dielectric layer of the dielectric layers; the second conductive contacts are arranged at a second pitch, the second pitch being greater than the first pitch, wherein the first pitch is less than approximately 1 micron, and individual dielectric layers in the dielectric layers have a lateral dimension greater than approximately 250 mm.

[0420] Example C2 includes the subject matter of Example C1, further comprising a conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the conductive path comprising a conductive trace of the dielectric layer and a through-hole of the dielectric layer.

[0421] Example C3 includes the subject matter of Example C1, further comprising a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising a conductive trace of the dielectric layer and a through-hole of the dielectric layer.

[0422] Example C4 is a device comprising: a plurality of dielectric layers stacked vertically, individual dielectric layers in the dielectric layers comprising one or more conductive traces and one or more through-holes; a plurality of first conductive contacts located on a top dielectric layer of the dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second conductive contacts arranged on a bottom dielectric layer of the dielectric layers; the second conductive contacts are arranged at a second pitch, the second pitch being greater than the first pitch; and a bridge located in one or more dielectric layers, the bridge comprising one or more conductive traces and one or more through-holes, the bridge comprising silicon.

[0423] Example C5 includes the subject matter of Example C4, further comprising a conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the conductive path comprising a conductive trace of the bridge and a via of the bridge.

[0424] Example C6 includes the subject matter of Example C4, further comprising a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising a conductive trace of the dielectric layer and a through-hole of one of the dielectric layers.

[0425] Example C7 includes the subject matter of any of Examples C4-C6, wherein the bridge spans two or more dielectric layers.

[0426] Example C8 includes the subject matter of any of Examples C4-C7, wherein the bridge includes one or more through-silicon vias.

[0427] Example C9 includes the subject matter of any of Examples C4-C8, wherein the bridge includes a trench capacitor, the trench capacitor including a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric positioned between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second capacitor conductive trace being oriented substantially perpendicular to a surface of a top dielectric layer of the dielectric layer.

[0428] Example C10 includes the subject matter of any of Examples C4-C9, wherein the bridge further comprises a plurality of conductive traces, individual ones of the conductive traces being surrounded by a ferromagnetic layer comprising iron.

[0429] Example C11 includes the subject matter of any of Examples C4-C10, wherein the bridge includes a field effect transistor.

[0430] Example C12 includes the subject matter of any of Examples C1-C10, wherein the thickness of the dielectric layer is in a range of 0.5-200 microns.

[0431] Example C13 includes the subject matter of any of Examples C1-C12, wherein the first pitch is less than approximately 1 micron.

[0432] Example C14 includes the subject matter of any of Examples C1-C12, wherein the first pitch is less than approximately 0.5 microns.

[0433] Example C15 includes the subject matter of any of Examples C1-C14, further comprising: a photonic integrated circuit; and an interposer including glass and a waveguide to provide a communication path for optical signals to be generated or received by the photonic integrated circuit.

[0434] Example C16 includes the subject matter of Example C15, wherein the waveguide is located in the glass, the waveguide comprising a dielectric material having a dielectric constant greater than the dielectric constant of the glass.

[0435] Example C17 includes the subject matter of Example C15, wherein the waveguide includes silicon and oxygen.

[0436] Example C18 includes the subject matter of Example C15, further including an electronic integrated circuit, the electronic integrated circuit comprising a first set of electronic integrated circuit conductive contacts located on a first surface of the electronic integrated circuit and a second set of electronic integrated circuit conductive contacts located on a second surface of the electronic integrated circuit opposite to the first surface, the first set of electronic integrated circuit conductive contacts being attached to one or more of the first conductive contacts, and the photonic integrated circuit comprising one or more photonic integrated circuit conductive contacts, the photonic integrated circuit conductive contacts being attached to the second set of electronic integrated circuit conductive contacts.

[0437] Example C19 includes the subject matter of Example C15, wherein the photonic integrated circuit includes one or more photonic integrated circuit conductive contacts attached to one or more of the first conductive contacts.

[0438] Example C20 includes the subject matter of any of Examples C15-C19, wherein the apparatus further comprises an optical fiber array unit, and the waveguide is further used to provide a communication path for optical signals to be generated or received by the optical fiber array unit.

[0439] Example C21 includes the subject matter of any of Examples C15-C20, wherein the glass includes aluminum, oxygen, boron, silicon, and an alkaline earth metal.

[0440] Example C22 includes the subject matter of any of Examples C1-C21, wherein the glass includes silicon, lithium, oxygen, and a metal.

[0441] Example C23 includes the subject matter of any of Examples C22, wherein the metal is gold or silver.

[0442] Example C24 includes the subject matter of any of Examples C1-C23, further comprising a plurality of integrated circuit dies, individual ones of the dies being attached to one or more of the first conductive contacts.

[0443] Example C25 includes the subject matter of Example C24, wherein a lateral dimension of a first one of the integrated circuit dies is different than a lateral dimension of a second one of the integrated circuit dies.

[0444] Example C26 includes the subject matter of Example C24, wherein a thickness of a first integrated circuit die in the integrated circuit dies is different than a thickness of a second integrated circuit die in the integrated circuit dies.

[0445] Example C27 includes the subject matter of Example C24, wherein functionality implemented by a first one of the integrated circuit dies is different than functionality implemented by a second one of the integrated circuit dies.

[0446] Example C28 includes the subject matter of Example C24, wherein one of the integrated circuit dies includes a plurality of third integrated circuit die conductive contacts attached to the first set of conductive contacts via solder balls.

[0447] Example C29 includes the subject matter of Example C23, wherein one of the integrated circuit dies includes a plurality of third conductive contacts directly attached to the first set of first conductive contacts.

[0448] Example C30 includes the subject matter of Example C29, wherein the third plurality of integrated circuit die conductive contacts and the first set of conductive contacts comprise copper.

[0449] Example C31 includes the subject matter of Example C24, wherein one of the integrated circuit dies includes a bottom dielectric layer directly attached to a top surface of the dielectric layer.

[0450] Example C32 includes the subject matter of Example C24, wherein one of the integrated circuit dies includes a first surface and a second surface opposite to the first surface, one of the integrated circuit dies is attached to a first conductive contact at the first surface of the one of the integrated circuit dies, and the device further includes an additional integrated circuit die, which is attached to the second surface of the integrated circuit die.

[0451] Example C33 includes the subject matter of Example C24, further comprising: an encapsulant for sealing an integrated circuit die, the encapsulant comprising a through-package via; and a packaged integrated circuit component, comprising an integrated circuit component conductive contact attached to the through-package via, the through-package via being attached to one of the first conductive contacts.

[0452] Example C34 includes the subject matter of any of Examples C1-C33, wherein individual ones of the dielectric layers have a lateral dimension of at least 250 mm.

[0453] Example C35 includes the subject matter of any of Examples C1-C33, wherein individual ones of the dielectric layers have a lateral dimension of at least 400 mm.

[0454] Example C36 includes the subject matter of any of Examples C1-C35, wherein individual ones of the dielectric layers have a rectangular shape.

[0455] Example C37 includes the subject matter of any of Examples C1-C35, wherein individual ones of the dielectric layers have a non-circular shape.

[0456] Example C38 includes the subject matter of any of Examples C24-C37, further comprising a cooling component located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

[0457] Example C39 includes the subject matter of Example C38, wherein the cooling component comprises a liquid-cooled cold plate, the apparatus further comprising a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and / or the pump.

[0458] Example C40 includes the subject matter of any of Examples C1-C39, further including a housing comprising a dielectric layer.

[0459] Example C41 includes the subject matter of any of Examples C1-C40, further including a power distribution component.

[0460] Example C42 is a device comprising: a plurality of first dielectric layers arranged in a stack, individual first dielectric layers in the first dielectric layers comprising one or more first conductive traces and one or more first through holes; a plurality of first conductive contacts located on a surface of a top dielectric layer of the first dielectric layers; the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second conductive contacts arranged on a surface of a bottom dielectric layer of the first dielectric layers; the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a plurality of first integrated circuit dies, individual first integrated circuit dies in the first integrated circuit dies being attached to one or more of the first conductive contacts; a plurality of second dielectric layers arranged in a stack, individual first integrated circuit dies in the second dielectric layers An individual second dielectric layer includes one or more second conductive traces and one or more second through-holes; a plurality of third conductive contacts located on the surface of the top dielectric layer of the second dielectric layer; the plurality of third conductive contacts include a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth conductive contacts located on the surface of the bottom dielectric layer of the second dielectric layer; a plurality of second integrated circuit dies, individual second integrated circuit dies in the second integrated circuit dies being attached to one or more of the third conductive contacts; and a substrate including one or more third dielectric layers, individual third dielectric layers in the third dielectric layers including one or more conductive traces and one or more through-holes, and a conductive path from one of the second conductive contacts to one of the fourth conductive contacts includes a conductive trace of the substrate and a through-hole of the substrate.

[0461] Example C43 includes the subject matter of Example C42, wherein the conductive path is a first conductive path, further comprising a second conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the second conductive path comprising a conductive trace of the first dielectric layer and a through hole of the first dielectric layer.

[0462] Example C44 includes the subject matter of Example C42, wherein the conductive path is a first conductive path, the device further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising a conductive trace of the first dielectric layer and a through hole of the first dielectric layer.

[0463] Example C45 includes the subject matter of a device, the device comprising: one or more first dielectric layers stacked vertically, individual first dielectric layers in the first dielectric layers comprising one or more first conductive traces and one or more first through holes; a plurality of first conductive contacts located on a top dielectric layer of the first dielectric layers, the plurality of first conductive contacts comprising a first set of first conductive contacts arranged at a first pitch and a second set of first conductive contacts; a plurality of second conductive contacts arranged on a bottom dielectric layer of the first dielectric layer; the second conductive contacts are arranged at a second pitch, the second pitch being greater than the first pitch; a first bridge located in the one or more first dielectric layers, the first bridge comprising one or more conductive traces and one or more through holes, the bridge comprising silicon; a plurality of first integrated circuit dies, individual first integrated circuit dies in the first integrated circuit dies being attached to one or more of the first conductive contacts; one or more second dielectric layers stacked vertically, the second An individual second dielectric layer in the dielectric layer includes one or more second conductive traces and one or more second through-holes; a plurality of third conductive contacts located on the top dielectric layer of the second dielectric layer; the plurality of third conductive contacts include a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth conductive contacts arranged on the bottom dielectric layer of the second dielectric layer; a second bridge located in the second dielectric layer, the second bridge includes one or more conductive traces and one or more through-holes, the bridge includes silicon; and a plurality of second integrated circuit dies, individual second integrated circuit dies in the second integrated circuit dies are attached to one or more of the third conductive contacts; and a substrate including one or more third dielectric layers, individual third dielectric layers in the third dielectric layer include one or more conductive traces and one or more through-holes, and a substrate conductive path from one of the second conductive contacts to one of the fourth conductive contacts includes one of the conductive traces of the substrate and one of the through-holes of the substrate.

[0464] Example C46 includes the subject matter of Example C45, wherein the conductive path is a first conductive path, and the device further includes a second conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the second conductive path including a conductive trace of the bridge and a through hole of the bridge.

[0465] Example C47 includes the subject matter of Example C45, wherein the conductive path is a first conductive path, the device further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising a conductive trace of the first dielectric layer and a through hole of the first dielectric layer.

[0466] Example C48 includes the subject matter of any of Examples C42-C47, wherein the number of first integrated circuit dies is different than the number of second integrated circuit dies.

[0467] Example C49 includes the subject matter of any of Examples C42-C47, wherein functionality implemented by the first plurality of integrated circuit dies is different from functionality implemented by the second plurality of integrated circuit dies.

[0468] Example C50 includes the subject matter of any of Examples C42-C49, further comprising a cooling component located on one or more of the first integrated circuit dies and one or more of the second integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

[0469] Example C51 includes the subject matter of Example C50, wherein the cooling component comprises a liquid-cooled cold plate, the apparatus further comprising a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and / or the pump.

[0470] Example C52 includes the subject matter of any of Examples C42-C51, further comprising a housing comprising the first dielectric layer, the second dielectric layer, and the first integrated circuit die.

[0471] Example C53 includes the subject matter of any of Examples C42-C52, further including a power distribution component.

[0472] Example C54 includes the subject matter of a method comprising: forming on a glass carrier: a plurality of dielectric layers, individual dielectric layers of the dielectric layers comprising one or more conductive traces and one or more through-holes; a plurality of first conductive contacts on a top dielectric layer of the dielectric layers; and a plurality of second conductive contacts on a bottom dielectric layer of the dielectric layers, the first conductive contacts being arranged at a first pitch less than 1 micron and the second conductive contacts being arranged at a second pitch greater than the first pitch; attaching one or more integrated circuit dies to the first conductive contacts; and removing the glass carrier from the dielectric layers.

[0473] Example C55 includes the subject matter of Example C54, further comprising: etching one or more of the dielectric layers to create a cavity; and positioning a bridge in the cavity, the bridge comprising one or more conductive traces and one or more vias.

[0474] Example C56 includes the subject matter of Example C55, wherein the first conductive contact includes a first set of first conductive contacts and a second set of first conductive contacts, and the conductive path from a conductive contact in the first set of first conductive contacts to a conductive contact in the second set of first conductive contacts includes a conductive trace of a bridge and a through hole of the bridge.

[0475] Example C57 includes the subject matter of Example C54, wherein the glass carrier and individual ones of the dielectric layers have lateral dimensions of at least 250 mm.

[0476] Example C58 includes the subject matter of Example C54, wherein the glass carrier and individual ones of the dielectric layers have a lateral dimension of at least 400 mm.

Claims

1. A device comprising: one or more first dielectric layers, individual ones of the first dielectric layers being positioned adjacent to another first dielectric layer; a plurality of first conductive contacts on a top dielectric layer of the first dielectric layer, the plurality of first conductive contacts comprising a first set of first conductive contacts and a second set of first conductive contacts arranged at a first pitch; one or more second dielectric layers, individual second dielectric layers being positioned adjacent to another second dielectric layer, individual first ones of the first dielectric layers and individual second ones of the second dielectric layers comprising one or more conductive traces and one or more vias; a plurality of second conductive contacts on the bottom dielectric layer of the second dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; and A glass core including a glass layer is positioned between the one or more first dielectric layers and the one or more second dielectric layers, the glass core including through-glass vias.

2. The device of claim 1 , further comprising a conductive path from a conductive contact in the first set of first conductive contacts to a conductive contact in the second set of first conductive contacts, the conductive path comprising a conductive trace of one of the first dielectric layers and a through hole of one of the first dielectric layers.

3. The device of claim 1 , further comprising a conductive path from one of the first conductive contacts to one of the second conductive contacts, the conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one via of one of the first dielectric layers, a through-glass via of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers.

4. A device comprising: one or more first dielectric layers, an individual first dielectric layer being positioned adjacent to another first dielectric layer; a plurality of first conductive contacts on a top dielectric layer of the first dielectric layer, the plurality of first conductive contacts comprising a first set of first conductive contacts and a second set of first conductive contacts arranged at a first pitch; one or more second dielectric layers, an individual second dielectric layer being positioned adjacent to another second dielectric layer, an individual first dielectric layer and an individual second dielectric layer comprising one or more conductive traces and one or more vias; a plurality of second conductive contacts on the bottom dielectric layer of the second dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a glass core including a glass layer, the glass core positioned between the first dielectric layer and the second dielectric layer, the glass core including a through-glass via; and A bridge is located in the first dielectric layer, the bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon.

5. The apparatus of claim 4, further comprising a conductive path from a conductive contact in the first set of first conductive contacts to a conductive contact in the second set of first conductive contacts, the conductive path comprising a conductive trace of the bridge and a via of the bridge.

6. The device of claim 4, further comprising a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one through hole of one of the first dielectric layers, a through-glass via of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one through hole of one of the second dielectric layers.

7. The device of any one of claims 4-6, wherein the bridge spans two or more first dielectric layers.

8. The device of any one of claims 4-7, wherein the bridge further comprises one or more through silicon vias.

9. The device of any one of claims 4-6, wherein the bridge is located in a glass core.

10. A device according to any one of claims 4-9, wherein the bridge comprises a trench capacitor, the trench capacitor comprising a first capacitor conductive trace, a second capacitor conductive trace and a capacitor dielectric positioned between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second capacitor conductive trace being oriented substantially perpendicular to a surface of a top dielectric layer of the first dielectric layer.

11. The apparatus of any one of claims 4-10, wherein the bridge further comprises a plurality of conductive traces, individual ones of the conductive traces of the bridge being surrounded by a ferromagnetic material comprising iron.

12. The apparatus of any one of claims 4-11, wherein the bridge further comprises a transistor.

13. The device of any one of claims 1-12, wherein the glass core further comprises a waveguide located in the glass layer, the waveguide comprising a dielectric material having a dielectric constant greater than the dielectric constant of the glass.

14. The apparatus of claim 13, wherein the apparatus further comprises a photonic integrated circuit, the waveguide being used to provide a path for optical communication of an optical signal to be generated or received by the photonic integrated circuit.

15. The device according to claim 13, wherein the device further comprises an optical fiber array unit, the waveguide being used to provide a path for optical communication of an optical signal to be generated or received by the optical fiber array unit.

16. The device of any one of claims 1-15, wherein individual ones of the through holes are tapered, the individual ones of the through holes comprising a narrower end and a wider end, the narrower end being positioned closer to the glass core than the wider end.

17. The device of any one of claims 1-16, wherein the glass core comprises one or more microchannels.

18. The device of claim 17, wherein the glass core further comprises a reservoir connected to at least one of the microchannels.

19. The apparatus of any of claims 1-18, further comprising a plurality of integrated circuit dies, individual ones of the integrated circuit dies being attached to one or more of the first conductive contacts.

20. An apparatus comprising: a plurality of first dielectric layers, an individual first dielectric layer being positioned adjacent to another first dielectric layer; a plurality of first conductive contacts on a top dielectric layer of the first dielectric layer, the plurality of first conductive contacts comprising a first set of first conductive contacts and a second set of first conductive contacts arranged at a first pitch; a plurality of second dielectric layers, individual second dielectric layers being positioned adjacent to another second dielectric layer, individual first ones of the first dielectric layers and individual second ones of the second dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of second conductive contacts on the bottom dielectric layer of the second dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a first glass core comprising a glass layer, the first glass core being positioned between one or more first dielectric layers and one or more second dielectric layers, the first glass core comprising a first through-glass via; a plurality of first integrated circuit dies, individual ones of the first integrated circuit dies being attached to one or more of the first conductive contacts; a plurality of third dielectric layers; a plurality of third conductive contacts on a top dielectric layer of the third dielectric layer; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth dielectric layers, individual third ones of the third dielectric layers and individual fourth ones of the fourth dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of fourth conductive contacts located on a surface of the bottom dielectric layer of the fourth dielectric layer; a second glass core including a glass layer, the second glass core being between the third dielectric layer and the fourth dielectric layer, the second glass core including a second through-glass via; a plurality of second integrated circuit dies, individual ones of the second integrated circuit dies being attached to one or more of the third conductive contacts; as well as A substrate comprising one or more fifth dielectric layers, individual ones of the fifth dielectric layers comprising one or more conductive traces and one or more through-holes, and a conductive path from one of the second conductive contacts to one or the fourth conductive contact comprising a conductive trace of one of the fifth dielectric layers and a through-hole of one of the fifth dielectric layers.

21. The device of claim 20, wherein the conductive path is a first conductive path, further comprising a second conductive path from one of the first conductive contacts in the first set of first conductive contacts to one of the first conductive contacts in the second set of first conductive contacts, the second conductive path comprising a conductive trace of one of the first dielectric layers and a through hole of one of the first dielectric layers.

22. The device of claim 20, wherein the conductive path is a first conductive path, the device further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising at least one conductive trace of the first dielectric layer, at least one through-hole of the first dielectric layer, a first through-glass via of the first glass core, a conductive trace of one of the second dielectric layers, and at least one through-hole of one of the second dielectric layers.

23. An apparatus comprising: a plurality of first dielectric layers, an individual first dielectric layer being positioned adjacent to another first dielectric layer; a plurality of first conductive contacts on a top dielectric layer of the first dielectric layer, the plurality of first conductive contacts comprising a first set of first conductive contacts and a second set of first conductive contacts arranged at a first pitch; a plurality of second dielectric layers, an individual second dielectric layer being positioned adjacent to another second dielectric layer, an individual first dielectric layer and an individual second dielectric layer comprising one or more first conductive traces and one or more first vias; a plurality of second conductive contacts on the bottom dielectric layer of the second dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a first glass core including a glass layer, the first glass core being positioned between the first dielectric layer and the second dielectric layer, the first glass core including a first through-glass via; a first bridge in the first dielectric layer, the first bridge comprising one or more first bridge conductive traces and one or more first bridge vias, the first bridge comprising silicon; a plurality of first integrated circuit dies, individual ones of the first integrated circuit dies being attached to one or more of the first conductive contacts; a plurality of third dielectric layers; a plurality of third conductive contacts on a top dielectric layer of the third dielectric layer; the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth dielectric layers, individual third ones of the third dielectric layers and individual fourth ones of the fourth dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of fourth conductive contacts on the bottom dielectric layer of the fourth dielectric layer; a second glass core including a glass layer, the second glass core being between the third dielectric layer and the fourth dielectric layer, the second glass core including a second through-glass via; and a second bridge comprising one or more second bridge conductive traces and one or more second bridge vias, the second bridge comprising silicon; a plurality of second integrated circuit dies, individual ones of the second integrated circuit dies being attached to one or more of the third conductive contacts; as well as A substrate comprising one or more fifth dielectric layers, individual fifth dielectric layers in the fifth dielectric layer comprising one or more conductive traces and one or more through-holes, and a conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising one of the conductive traces of the substrate and one of the through-holes of the substrate.

24. A device according to claim 23, wherein the conductive path is a first conductive path, and the device further includes a second conductive path from one of the first conductive contacts in the first set of first conductive contacts to one of the first conductive contacts in the second set of first conductive contacts, the second conductive path including a conductive trace of the first bridge and a through hole of the first bridge.

25. The device of claim 23, wherein the conductive path is a first conductive path, the device further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising at least one conductive trace of the first dielectric layer, at least one through-hole of the first dielectric layer, a first through-glass via of the first glass core, a conductive trace of one of the second dielectric layers, and at least one through-hole of one of the second dielectric layers.

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