Integrated strain SiGe channel PMOS for GAA CMOS technology

Abstract

Horizontal gate-all-around devices and methods of making the same are described. These hGAA devices include a semiconductor material between a source region and a drain region of the device. The method includes forming a cladding material on a first material followed by a dry oxidation treatment resulting in a rearrangement of the cladding material and the first material.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly, to horizontal gate all around device structures and methods and apparatus for forming the horizontal gate all around device structures. Background Art

[0002] Transistors are key components of most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Therefore, there is a tradeoff between transistor size and speed, and "fin" field effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that significantly increases the size of the transistor without significantly increasing the area occupied by the transistor, and FinFETs are currently used in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structures to improve electrostatic coupling and reduce side effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The inventors believe that the hGAA structure provides good electrostatic control and can find widespread adoption in complementary metal oxide semiconductor (CMOS) wafer manufacturing.

[0004] Logic gate performance involves the properties of the materials used as well as the thickness and area of ​​the structural layers. However, challenges arise as some gate characteristics are adjusted to accommodate device scaling. In addition, spatial limitations between wiring on horizontal all-around gate (hGAA) devices limit the thickness of the gate dielectric material of the I / O transistors.

[0005] Severe misalignment of p-type source / drain silicon germanium (SiGE) epitaxy (EPI) for gate-all-around (GAA) p-type field effect transistor (PFET) processing is one of the biggest bottlenecks in maintaining compressive stress in the channel to improve device performance. Integrating a SiGe channel for PMOS while maintaining the Si channel is also challenging.

[0006] Thus, there is a need for improved methods for forming PMOS electronic devices. Summary of the invention

[0007] One or more embodiments of the present invention relate to a method for forming a semiconductor device. A superlattice structure on a substrate is selectively etched. The superlattice structure includes a plurality of first layers of a first material and a corresponding plurality of second layers of a second material alternately arranged as a plurality of stacked pairs, for removing each of the second layers to form a plurality of voids in the superlattice structure and a plurality of nanosheets, the nanosheets including a first layer extending between a source region and a drain region. A cladding material is formed around each of the plurality of first layers of the nanosheets to form a nanosheet having a first material, wherein the cladding material surrounds the first material. The nanosheets are dry oxidized to convert the nanosheets into a cladding material surrounded by an oxide of the first material. The first material is removed to leave a nanosheet of the cladding material.

[0008] An electronic device includes: a PMOS including a SiGe channel between a source region and a drain region; and an NMOS including a Si channel between a source region and a drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to be able to understand in detail the manner in which the above-mentioned features of the present case are used, a more particular description of the present disclosure briefly summarized above may be obtained by reference to the embodiments, some of which are shown in the accompanying drawings. It will be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and are not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0010] Figure 1 A flowchart illustrating a method for forming a semiconductor device according to some embodiments of the present disclosure; and

[0011] Figures 2 to 15 illustrates a stage of manufacturing a substrate during a method of forming a semiconductor device according to some embodiments of the present disclosure;

[0012] Fig.16 illustrates a schematic representation of an electronic device according to one or more embodiments of the present disclosure; and

[0013] Fig.17 A schematic representation of a cluster tool according to one or more embodiments of the present disclosure is illustrated.

[0014] For ease of understanding, the same reference numerals have been used to identify the same elements shared by the figures where possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. DETAILED DESCRIPTION

[0015] Before describing several exemplary embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of construction or processing steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0016] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. As will also be understood by those skilled in the art, references to a substrate may also refer to only a portion of a substrate unless the context clearly indicates otherwise. In addition, references to deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0017] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metal, metal nitride, metal alloy, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pre-processing treatments to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to the film processing directly on the substrate surface itself, in the present disclosure, as disclosed in more detail below, any film processing step disclosed may also be performed on a lower layer formed on the substrate, and the term "substrate surface" is intended to include such lower layers as indicated in the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species that can react with a substrate surface.

[0019] A transistor is a circuit component or element often formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Typically, a transistor includes a gate formed between a source and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and may exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric inserted between a gate electrode in the substrate and the channel region.

[0020] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are: the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which is a terminal that regulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is designated as I S and the current entering the channel at the drain (D) is designated as I D The drain-to-source voltage is specified as V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0021] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET). It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change the conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFET is based on the regulation of charge concentration by a metal oxide semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to an independent highly doped region separated by the body region. These regions can be p-type or n-type, but they are all of the same type and of the opposite type to the body region. After the type of doping, the source and drain (unlike the body) are highly doped, as marked by the "+" symbol.

[0022] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is the p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is the n region. The source is so named because it is the source of charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0023] As used herein, the term "Fin Field Effect Transistor (FinFET)" refers to a MOSFET transistor built on a substrate where the gates are placed on two or three sides of the channel, forming a dual-gate or tri-gate structure. Because the channel region forms a "fin" on the substrate, the generic name FinFET has been given to FinFET devices. FinFET devices have fast switching times and high current density.

[0024] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which a gate material surrounds all sides of a channel region. The channel region of a GAA transistor may include nanowires or nanoplates, strip-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or horizontal strips spaced vertically apart, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0025] In one or more embodiments, a horizontal gate-all-around (hGAA) transistor includes: a substrate having a top surface; a source region having a source and a source contact, the source region being on the top surface of the substrate; a drain region having a drain and a drain contact, the drain region being on the top surface of the substrate; a channel between the source and the drain and having an axis substantially parallel to the top surface of the substrate; a gate surrounding the channel between the source region and the drain region; a thermal oxide layer covering and contacting one or more of the gate, the source contact, or the drain contact, and a low-k dielectric layer covering the thermal oxide layer. In one or more embodiments, the low-k dielectric layer has a thickness of less than about 5 nm.

[0026] One or more embodiments of the present disclosure relate to methods of forming horizontal gate-all-around devices. Some embodiments advantageously provide integrated methods for forming complementary metal oxide semiconductor (CMPS) devices, wherein strained SiGe is used as the channel material for PMOS while maintaining the silicon channel material for NMOS. In some embodiments, the strained SiGe channel is formed using encapsulation or SiGi oxidation / condensation techniques, which provide improved compressive stress in the channel.

[0027] In some embodiments, a method for forming an hGAA device is enhanced to insert one or more processes between wiring release (etching SiGe release layer to free nano wiring) and replacement metal gate (deposition of gate dielectric, work function metal and associated material films).

[0028] Figure 1 1 is a flow chart illustrating a method 100 for forming a semiconductor device according to some embodiments of the present disclosure. Figures 2 to 15B depicts a process for manufacturing a semiconductor structure according to some embodiments of the present disclosure. The method 100 of the present invention may be part of a multi-step manufacturing process for a semiconductor device. Thus, the method may be performed in any suitable processing chamber coupled to a cluster tool. A cluster tool may include a processing chamber for manufacturing semiconductor devices, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber for manufacturing semiconductor devices.

[0029] The method 100 begins at operation 102 by providing a device having a top surface 202 (eg, Figure 2 As used in this manner, the term "providing" means that the substrate 200 becomes available for processing. For example, the substrate 200 can be provided by being placed in a suitable processing chamber. In some embodiments, the substrate 200 can be a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is composed of semiconductor material. The bulk semiconductor substrate can include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer can include one or more materials, such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In some embodiments, the semiconductor material can be a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process (such as an ion implantation process). In some embodiments, the substrate can be doped to provide a high dose of dopants at a first location on the surface of the substrate 200 to prevent the parasitic bottom device from turning on. The superlattice structure is formed on top of the first location. For example, in some embodiments, the surface of the substrate can have a thickness of about 10 18 Atom / cm 3 to about 10 19 Atom / cm 3 of dopant density.

[0030] In operation 104, at least one superlattice structure 204 is formed on top of the top surface 202 of the substrate 200 (eg, Figure 2). The superlattice structure 204 includes a plurality of first layers 224 and a corresponding plurality of second layers 226 arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked groups of layers include a group of silicon (Si) and silicon germanium (SiGe) and a group of indium phosphide (InP) and indium gallium phosphide (InGaP). In some embodiments, the plurality of first layers and the corresponding plurality of second layers may include any number of lattice matching material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of first layers 224 and the corresponding plurality of second layers 226 include 2 to 50 pairs of lattice matching materials.

[0031] Typically, parasitic devices will be present at the bottom of the superlattice structure 204. In some embodiments, as discussed above, dopants are implanted in the substrate for suppressing conduction of the parasitic devices. In some embodiments, the substrate 200 is etched so that the bottom of the superlattice structure 204 includes a portion of the substrate that is not removed, thereby allowing the substrate portion to serve as a bottom release layer for the superlattice structure 204.

[0032] In some embodiments, the thickness of the first layer 224 and the second layer 226 is in the range of about 2 nm to about 50 nm, or in the range of about 3 nm to about 20 nm. In some embodiments, the average thickness of the first layer 224 is within 0.5 to 2 times the average thickness of the second layer 226.

[0033] In some embodiments, the dielectric material 246 is deposited on the substrate 200 using conventional chemical vapor deposition methods. In some embodiments, the dielectric material 246 is recessed below the top surface 202 of the substrate 200 so that the bottom of the superlattice structure 204 is formed by the substrate 200.

[0034] In some embodiments, a replacement gate structure (eg, dummy gate structure 208) is formed over superlattice structure 204. Dummy gate structure 208 defines a channel region of the transistor device. Dummy gate structure 208 may be formed using any suitable deposition and patterning processes known in the art.

[0035] In some embodiments, sidewall spacers 210 are formed along outer sidewalls of the dummy gate structure 208. The sidewall spacers 210 of some embodiments include a suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or the like. In some embodiments, the sidewall spacers 210 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition.

[0036] In some embodiments, the embedded source region 232 and the drain region 234 are formed in the source trench and the drain trench, respectively. In some embodiments, the source region 232 is formed adjacent to a first end of the superlattice structure 204, and the drain region 234 is formed adjacent to a second opposite end of the superlattice structure. Figure 2 In the embodiment shown in FIG. 2 , a view of one of the source region 232 or the drain region 234 is not shown in front of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source region 232 or the drain region 234. In some embodiments, the source region 232 and / or the drain region 234 are formed of any suitable semiconductor material, such as but not limited to silicon, germanium, silicon germanium, or the like. In some embodiments, the source region 232 and the drain region 234 can be formed using any suitable deposition process, such as an epitaxial deposition process.

[0037] In some embodiments, an inter-layer dielectric (ILD) layer 220 is blanket deposited over the substrate 200 including the source / drain regions 232, 234, the dummy gate structure 208, and the sidewall spacers 210. The ILD layer 220 can be deposited using conventional chemical vapor deposition methods (e.g., plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition). In one embodiment, the ILD layer 220 is formed of any well-known dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. The ILD layer 220 is then polished back using conventional chemical mechanical planarization methods to expose the top of the dummy gate structure 208. In some embodiments, the ILD layer 220 is polished to expose the top of the dummy gate structure 208 and the top of the sidewall spacers 210.

[0038] In some embodiments, Figure 3 As shown, the dummy gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204. The ILD layer 220 protects the source / drain regions 232, 234 during the removal of the dummy gate structure 208. The dummy gate structure 208 can be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 208 includes polysilicon and the dummy gate structure is removed by a selective etching process. In some embodiments, the dummy gate structure 208 includes polysilicon and the superlattice structure 204 includes alternating layers of silicon (Si) and silicon germanium (SiGe).

[0039] Figure 4 Graphics Figure 32, showing an end view of a superlattice structure 204 having alternating layers of a first material 224 and a second material 226. In operation 106, as Figure 5 As shown, the wiring release process selectively etches between the first material 224 layers in the superlattice structure 204. The wiring release process forms a plurality of voids 225 between the first material 224 layers, resulting in a plurality of nanosheets 244 comprising the first layer 224 extending between the source region and the drain region.

[0040] For example, in the case where the superlattice structure 204 is composed of a silicon layer and a silicon germanium layer, the silicon germanium is selectively etched to form a channel nanowire (also known as a nanosheet). The release layer (second material 226), such as silicon germanium, can be removed using any well-known etchant that is selective to the layers of the semiconductor material layer 224, wherein the etchant etches the layers of the release layer (second material 226) at a significantly higher rate than the layers of the semiconductor material layer (first material 224). In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, in the case where the semiconductor material layer (first material 224) is silicon and the release layer (second material 226) is silicon germanium, the layer of silicon germanium can be selectively removed using a wet etchant, such as, but not limited to, an aqueous carboxylic acid / nitric acid / HF solution and an aqueous citric acid / nitric acid / HF solution. The removal of the release layer (second material 226) leaves gaps 225 between the semiconductor material layers (first material 224). The gaps 225 between the semiconductor material layers (first material 224) have a thickness of about 3 nm to about 20 nm. The remaining semiconductor material layers form a vertical array of channel nanowires coupled to source / drain regions 232, 234. The channel nanowires run parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single column of channel nanowires. The formation of the source region 232 and the drain region 234 and the formation of an optional lateral etch stop layer (not shown) advantageously provide self-alignment and structural integrity when forming the channel structure.

[0041] At optional operation 108, patterning is performed to form a PMOS device formed by method 100. Those skilled in the art will be familiar with patterning processes including, but not limited to, the formation of hard masks and / or photoresist layers, masking, and etching processes. Optional operation 108 can be performed at any suitable stage in method 100 and is not limited to occurring between operation 106 and operation 110. For example, in some embodiments, optional operation 108 occurs before operation 106.

[0042] In some embodiments, an n-type metal oxide semiconductor (NMOS) portion of a complementary metal oxide semiconductor (CMOS) device is formed prior to one or more of operations 102 through 106. For example, in some embodiments, the NMOS portion of the CMOS device is formed first and then covered with a suitable hard mask. An opening is created in the hard mask for subsequent formation of a p-type metal oxide semiconductor (PMOS) portion of the CMOS without interfering with the previously formed NMOS portion. In some embodiments, the PMOS portion of the CMOS is formed prior to forming the NMOS portion of the CMOS.

[0043] At optional operation 110, as Figure 6 As shown, the nanosheets 244 are exposed to an optional treatment, wherein the nanosheets 244 of the first material 224 are reduced from an initial thickness T0 (eg, Figure 5 ) is trimmed to have a reduced thickness T1 of the nanosheet 244 (as shown Figure 6 as shown).

[0044] Nanosheets 244 are trimmed by any suitable etching process known to those skilled in the art that is compatible with first material 224. In some embodiments, nanosheets 244 are trimmed by exposure to a wet etching process, such as an aqueous alkaline medium, like KOH-, NaOH-, or TMAH-solution.

[0045] The reduction in thickness of the nanosheet according to some embodiments is greater than or equal to 50% of the initial thickness T0. In some embodiments, the initial thickness T0 is in the range of 4 nm to 10 nm, or in the range of 5 nm to 9 nm, or in the range of 6 nm to 8 nm. In some embodiments, the reduced thickness T1 is in the range of 1 / 3 to 1 / 5 of the initial thickness T0, or in the range of 1 nm to 3 nm. In some embodiments, trimming the nanosheet reduces the thickness of the nanosheet from the initial thickness T0 in the range of 6 nm to 8 nm to the reduced thickness T1 in the range of 1 nm to 3 nm.

[0046] At operation 112, a cladding material 150 is formed to surround each of the plurality of first layers 224 of the nanosheet 244. Whether or not the optional operation 110 is performed, the cladding material 150 is formed on the nanosheet. The cladding material 150 may be formed by any suitable process known to those skilled in the art. In some embodiments, the cladding material 150 comprises silicon germanium (SiGe) or Ge. In some embodiments, the cladding material 150 is epitaxially grown on the plurality of first layers 224 of the nanosheet 244. The cladding material is manufactured via CVD epitaxy, with a temperature range of from 450°C to 850°C.

[0047] refer to Fig. 8AIn some embodiments, the first layer 224 is trimmed so that the nanosheets 244 closer to the substrate 200 have a greater reduced thickness T1 than the nanosheets 244 farther from the substrate 200. In some embodiments, the thickness of the cladding material 250 remains uniform around each first layer.

[0048] See also Figure 8B In some embodiments where the thickness of the nanosheet 244 varies, the thickness of the cladding material 250 varies inversely to the thickness of the nanosheet. For example, as shown, the nanosheet 244 further away from the substrate has a smaller first layer 244 of reduced thickness and a thicker layer of the cladding material 250.

[0049] In some embodiments, Fig. 9 As shown, forming the cladding material 250 on the first layer 224 of the nanosheet 244 results in a cladding having a non-uniform thickness. For example, as shown, the cladding material 250 formed on the nanosheet 244 closest to the substrate 200 has a smaller thickness than the cladding material 250 formed on the nanosheet farthest from the substrate 200.

[0050] At operation 118 of method 100, as Fig.10 As shown, the nanosheet 244 undergoes a dry oxidation process. The dry oxidation process converts the nanosheet 244 into a cladding material 250 having an oxide 227 surrounded by the first material 224. For example, in an embodiment where the first layer 224 comprises silicon (Si) and the cladding material 250 comprises silicon germanium (SiGe), the dry oxidation causes the materials to rearrange so that the silicon germanium (SiGe) cladding material 250 is in the center of the nanosheet 244 surrounded by the silicon (Si) first layer 224, with a small layer of silicon oxide 227 on the surface of the silicon (Si) first layer 224.

[0051] The dry oxidation may be performed by any suitable technique known to those skilled in the art. In some embodiments, the dry oxidation process is performed by exposing the semiconductor device to a rapid thermal oxidation (RTO) process. In some embodiments, the RTO process ramps the temperature of the substrate from a starting temperature (e.g., room temperature) to a maximum temperature in the range of 700°C to 1050°C at a rate greater than or equal to 25°C / second, 50°C / second, or more at 5-780 torr during 1 to 5 minutes. During the dry oxidation process, the processing environment of some embodiments includes one or more of water vapor, oxygen (O2), or ozone (O3), and in some cases, is under a mixture of O2 / N2 gases.

[0052] The dry oxidation process of operation 118 results in a rearrangement of the layers of nanosheets 244 such that the cladding material 250 effectively replaces the first layer 224. In this configuration, the cladding material 250 becomes the semiconductor material layer 245.

[0053] At operation 120 of method 100, as Fig.11 As shown, first layer 224 and oxide 227 of first layer 224 are removed from semiconductor material layer 245 by any suitable etching process. In some embodiments, removing oxide 227 and first layer 224 comprises exposing the substrate to a solution of dilute hydrofluoric acid (-1:100-1:150 HF:H2O) at room temperature.

[0054] Some embodiments of the method 100 include an operation 114 in which an oxide is formed on the cladding material 250 prior to dry oxidation at operation 118 . Fig. 12A An embodiment is shown in which the first layer 224 of the nanosheet 244 is surrounded by a cladding material 250 and an oxide 251 of the cladding material 250. The oxide 251 of the cladding material 250 can be formed by any suitable oxidation process known to those skilled in the art. In some embodiments, the oxide 251 of the cladding material 250 is formed by an atomic layer deposition (ALD) process, which utilizes a low processing temperature ranging from 250° C. to 450° C., and in some cases, utilizes a plasma treatment or enhancement function. In some embodiments, the oxide 251 of the cladding material 250 is formed by rapid plasma oxidation (RPO). In some embodiments, the RPO process exposes the substrate 200 to an oxygen-containing plasma (e.g., molecular oxygen (O2), ozone (O3)) at a temperature in the range of 350° C. to 650° C., with a pressure varying from 5 to 300 torr.

[0055] Fig. 12B The diagram shows the rearrangement of the various material layers after exposure to a dry oxidation process at operation 118. Fig. 12A For example, if the first layer 224 comprises silicon and the cladding material 250 comprises SiGe, the oxide 251 of the cladding material comprises silicon germanium oxide (SiGeO), and the dry oxidation process moves the SiGe to the center of the nanosheet surrounded by silicon and the oxide layer 229 comprising silicon, germanium, and oxygen atoms.

[0056] Fig.13A Another embodiment of an oxide formation process according to operation 114 of method 100 is illustrated. In the illustrated embodiment, the nanosheets 244 of the first layer 224 and the encapsulating material 250 are surrounded by a flowable oxide 253. In some embodiments, the flowable oxide 253 is formed by a high density plasma process, wherein the film density is from about 2.1 to about 2.3 g-cm -3The flowable oxide 253 of some embodiments comprises silicon oxide.

[0057] Fig. 13B FIG. 1 shows a schematic diagram of a dry oxidation process after exposure to the dry oxidation process at operation 118 of method 100. Fig.13A The dry oxidation process causes a rearrangement of the various material layers. For example, if the first layer 224 comprises silicon, the cladding material 250 comprises SiGe, and the flowable oxide 253 comprises silicon oxide, the dry oxidation process causes a rearrangement such that the SiGe moves to the center of the nanosheet surrounded by the silicon and the flowable oxide 253.

[0058] Some embodiments of the method 100 further include an operation 116, wherein the oxide is removed prior to the dry oxidation (at operation 118). Fig. 12A or Fig.13A The oxides are removed prior to dry oxidation. In some embodiments, the oxides are removed by exposure to a dilute HF / H2O2 solution (~1:100-1:150 HF:H2O) prior to dry oxidation.

[0059] Operations 120, 122, and / or 126 of method 100 represent one or more post-oxide removal processes according to some embodiments. The one or more post-oxide removal processes may be performed by any of the processes known to those skilled in the art for completing the hGAA device. Fig.14 and Fig.15 In some embodiments, at operation 122, an oxide layer 252 (also referred to as a capping layer) is formed or grown on the semiconductor material layer 245. The oxide layer 252 can be any suitable oxide formed by any suitable technique known to those skilled in the art. In some embodiments, the oxide layer comprises a silicon capping layer. In some embodiments, a separate selective CVD epitaxially grows a Si layer (e.g., 5-30 Å) at a temperature of 500°C to 800°C.

[0060] At optional operation 124, the hard mask formed during optional operation 108 (PMOS patterning) is removed. Optional operation 124 can be formed at any suitable time during method 100 and is not limited to occurring between operation 122 and operation 126. The hard mask can be removed by any suitable technique known to those skilled in the art. For example, in some embodiments, the hard mask is removed by a wet etching process.

[0061] In the illustrated embodiment, at operation 126, a high dielectric constant dielectric 254 is formed on the oxide layer 252. The high dielectric constant dielectric 254 can be any suitable high dielectric constant dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high dielectric constant dielectric 254 of some embodiments includes hafnium oxide. In some embodiments, a conductive material 256 (such as titanium nitride, tungsten, cobalt, aluminum, or the like) is on the high dielectric constant dielectric 254. The conductive material 256 is formed using any suitable deposition process, such as atomic layer deposition (ALD), so as to ensure that a layer with uniform thickness is formed around each of the semiconductor material layers 245.

[0062] In some embodiments, a gate electrode 242 is formed on the substrate 200 and surrounds each of the doped semiconductor material layers 245. The gate electrode 242 may be formed of any suitable gate electrode material known in the art. The gate electrode material is deposited using any suitable deposition process, such as atomic layer deposition (ALD), to ensure that the gate electrode 242 is formed around and between each of the semiconductor material layers 245. According to embodiments of the present disclosure, the resulting device formed using the methods described herein is a horizontal all-around gate device. Some embodiments of the present disclosure relate to a horizontal all-around gate device that includes a semiconductor material layer 245 as a nanowire or nanosheet in a channel between source and drain regions.

[0063] like Fig.16 , some embodiments of the present disclosure relate to an electronic device 300 including a PMOS 310 and an NMOS 320. The PMOS 310 includes a SiGe nanowire 312 between a p-type source region 332 and a p-type drain region 334. Those skilled in the art will recognize that the p-type source region 332 and the p-type drain region 334 can be positioned in any particular order and will be familiar with their construction. As discussed above, the SiGe nanowire 312 is separated by an oxide layer 252, a high dielectric constant dielectric 254, and a conductive material 256. The NMOS 320 includes a Si nanowire 314 between an n-type source region 342 and an n-type drain region 344. Those skilled in the art will recognize that the n-type source region 342 and the n-type drain region 344 can be positioned in any particular order and will be familiar with their construction. As discussed above, the Si nanowire 314 is separated by an oxide layer 252, a high dielectric constant dielectric 254, and a conductive material 256.

[0064] Some implementations of the present disclosure relate to integrated processing performed within a single cluster tool. Fig.17 is a schematic top view illustration of an example multi-chamber processing system according to one or more implementations. Fig.17A schematic top view illustration of an example of a multi-chamber processing system 400 according to an embodiment of the present disclosure is illustrated. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with corresponding transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in each chamber and transferred between each chamber without exposing the wafer to an ambient environment (e.g., an atmospheric ambient environment, such as may exist in a wafer fab) external to the processing system 400. For example, the wafer can be processed in each chamber and transferred between each chamber under a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment, so that the low pressure or vacuum environment is not broken between each process performed on the wafer in the processing system 400. Thus, the processing system 400 can provide an integrated solution for some processing of the wafer.

[0065] exist Fig.17 In the illustrated example, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate the transfer of wafers. The docking station 440 is configured to receive one or more front opening unit (FOUP) 444. In some examples, each factory interface robot 442 generally includes a blade 448 disposed on one end of the corresponding factory interface robot 442, which is configured to transfer the wafer from the factory interface 402 to the load lock chamber 404, 406.

[0066] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to the processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476 may be, for example, slit valve openings with slit valves for transferring wafers therethrough by transfer robots 412, 414 and for providing a seal between the respective chambers to prevent gas from passing therethrough. Typically, any port is opened for transferring a wafer therethrough. Otherwise, the port is closed.

[0067] The load lock chambers 404, 406, the transfer chambers 408, 410, the holding chambers 416, 418, and the processing chambers 420, 422, 424, 426, 428, 430 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 444 through the port 450 or 452 to the load lock chamber 404 or 406. The gas and pressure control system then evacuates the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the holding chambers 416, 418 to have an internal low pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 404 or 406 facilitates transferring wafers between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408 .

[0068] With the wafer in the already evacuated load lock chamber 404 or 406, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 into the transfer chamber 408 through the port 454 or 456. The transfer robot 412 can then transfer the wafer to either of the processing chambers 420, 422 and / or between either of the processing chambers 120, 122 through the respective ports 462, 464 for processing, and to the holding chambers 416, 418 through the respective ports 458, 460 for holding to await further transfer. Similarly, the transfer robot 414 can access wafers in the holding chamber 416 or 418 through the port 466 or 468, and can transfer wafers to any of the processing chambers 424, 426, 428, 430 and / or between any of these processing chambers for processing through the corresponding ports 470, 472, 474, 476, and transfer to the holding chamber 416, 418 through the corresponding ports 466, 468 for holding to await further transfer. The transfer and holding of wafers within and between the various chambers can be in a low pressure or vacuum environment provided by a gas and pressure control system.

[0069] Processing chambers 420, 422, 424, 426, 428, 430 may be any suitable chambers for processing wafers. In some embodiments, processing chamber 420 may be capable of performing an annealing process, processing chamber 422 may be capable of performing a cleaning process, and processing chambers 424, 426, 428, 430 may be capable of performing an epitaxial growth process. In some examples, processing chamber 422 may be capable of performing a cleaning process, processing chamber 420 may be capable of performing an etching process, and processing chambers 424, 426, 428, 430 may be capable of performing a corresponding epitaxial growth process.

[0070] A system controller 490 is coupled to the processing system 400 for controlling the processing system 400 or components thereof. For example, the system controller 490 may control the operation of the processing system 400 using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. In operation, the system controller 490 enables data collection and feedback from the respective chambers to coordinate the performance of the processing system 400.

[0071] The system controller 490 typically includes a central processing unit (CPU) 492, a memory 494, and support circuits 496. The CPU 492 may be one of any form of general purpose processor that may be used in an industrial setting. The memory 494 or non-transitory computer readable medium is accessible by the CPU 492 and may be one or more memories, such as a random access memory (RAM), a read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage device (local or remote). The support circuits 496 are coupled to the CPU 492 and may include caches, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may be implemented by the CPU 492 executing computer instruction codes (e.g., as software routines) stored in the memory 494 (or in the memory of a particular processing chamber), typically under the control of the CPU 492. When the computer instruction codes are executed by the CPU 492, the CPU 492 controls the chamber to perform processing according to the various methods.

[0072] Other processing systems may be other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the example shown, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer device in a processing system.

[0073] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "certain embodiments," "in an embodiment," or "in an embodiment" that appear in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in one or more embodiments in any suitable manner.

[0074] Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, comprising the following steps: selectively etching a superlattice structure on a substrate, the superlattice structure comprising a plurality of first layers of a first material and a corresponding plurality of second layers of a second material alternately arranged as a plurality of stacked pairs, for removing each of the second layers to form a plurality of voids in the superlattice structure and a plurality of nanoflakes, the plurality of nanoflakes comprising the first layer extending between a source region and a drain region; forming a cladding material around each of the plurality of first layers of the nanoflakes to form a nanoflake having a first material, wherein the first material is surrounded by the cladding material; dry oxidizing the nanoflakes to convert the nanoflakes into the coating material surrounded by the oxide of the first material; as well as The first material is removed to leave nanoflakes of the encapsulating material.

2. The method of claim 1, wherein the first material comprises silicon dry oxide (Si). The method of claim 1 , wherein the second material comprises silicon germanium (SiGe). The method of claim 1 , wherein the cladding material comprises silicon germanium (SiGe). The method of claim 4 , wherein the cladding material is epitaxially grown on the plurality of first layers of the nanoflakes.

6. The method of claim 1, wherein the step of dry oxidizing the nanoflakes comprises the step of exposing the semiconductor device to a rapid thermal oxidation process at a temperature in the range of 700°C to 950°C.

7. The method of claim 1, removing the oxide of the first material comprising exposing the first material to a dilute HF solution.

8. The method of claim 1, further comprising the step of trimming the nanoflakes prior to forming the cladding material to reduce the thickness of the nanoflakes from an initial thickness in the range of 6 nm to 8 nm to a reduced thickness in the range of 2 nm to 3 nm. 9 . The method of claim 8 , wherein nanoflakes closer to the substrate have a greater reduced thickness than nanoflakes farther from the substrate.

10. The method of claim 1, further comprising the step of forming an oxide on the cladding material prior to dry oxidation. The method of claim 10 , wherein the oxide on the cladding material is formed by atomic layer deposition.

12. The method of claim 10, wherein the oxide on the cladding material comprises a flowable oxide formed by a high density plasma.

13. The method of claim 10, wherein the oxide on the cladding material is formed by fast plasma oxidation at a temperature in the range of 400°C to 600°C.

14. The method of claim 10, further comprising the step of removing the oxide by exposure to a dilute HF / H2O2 solution prior to dry oxidation.

15. The method of claim 1, further comprising the step of forming a silicon cap on the nanosheets of the cladding material by epitaxial growth or by chemical vapor deposition.

16. The method of claim 15, wherein the silicon cap has a thickness in the range of 2 Å to 20 Å.

17. The method of claim 15, further comprising the step of forming a high dielectric constant metal gate in contact with the nanoflakes of encapsulating material.

18. The method of claim 1, further comprising the step of forming the superlattice structure on a top surface of a substrate, each of the first layer and the second layer having a thickness independently in a range of 3 nm to 20 nm.

19. The method of claim 18, further comprising the step of forming the source region adjacent to a first end of the superlattice structure and forming the drain region adjacent to a second opposing end of the superlattice structure.

20. An electronic device comprising: A PMOS including a SiGe channel between a source region and a drain region; and An NMOS includes a Si channel between a source region and a drain region.

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