Solid state disk channel signal adjusting system and solid state disk

Abstract

The invention provides a solid state disk channel signal adjusting system and a solid state disk, the system further comprises a main control chip, a memory chip, a real-time monitoring module and a time sequence adjusting module, the real-time monitoring module is used for monitoring a read operation error rate corresponding to a flash memory chip in real time, and when the read operation error rate is larger than a preset threshold value, the time sequence adjusting module is used for adjusting the time sequence of the flash memory chip; working environment parameters of the DQS signal and the DQ signal are obtained and transmitted to the main control chip; the main control chip is used for obtaining a time sequence adjusting signal of a DQS signal and a DQ signal corresponding to the flash memory chip according to the working environment parameters and transmitting the time sequence adjusting signal to the time sequence adjusting module; wherein the time sequence adjusting signal is used for realizing alignment of a DQS signal and a DQ signal corresponding to the flash memory chip; and the time sequence adjusting module adjusts the time sequence of the DQS signal and the DQ signal corresponding to the flash memory chip according to the time sequence adjusting signal. According to the solid state disk channel signal adjusting system and the solid state disk, self-adaptive optimization adjustment of the solid state disk channel signals is achieved, the solid state disk channel signal adjusting system and the solid state disk can adapt to complex and changeable working environments, and the reading performance and the data transmission rate of the solid state disk are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a solid state hard disk channel signal adjustment system and a solid state hard disk. Background Art

[0002] With the rapid development of modern computer technology, solid state drives (SSDs) have become the mainstream choice for storage devices. Compared with traditional mechanical hard disks (HDDs), SSDs have higher reading speeds, lower power consumption, and better shock resistance. However, with the increase in storage density and data transmission rate, SSDs face many challenges in signal transmission and data reading. Current SSD signal optimization technology mainly relies on fixed parameter settings and simple feedback control, which is difficult to adapt to complex and changing working environments. Summary of the invention

[0003] The present invention provides a solid-state hard disk channel signal adjustment system and a solid-state hard disk, which are used to solve the defects that the solid-state hard disk signal optimization technology in the prior art mainly relies on fixed parameter settings and simple feedback control, and is difficult to adapt to complex and changeable working environments, and realizes adaptive optimization and adjustment of the solid-state hard disk channel signal, which can adapt to complex and changeable working environments and improve the reading performance and data transmission rate of the solid-state hard disk.

[0004] The present invention provides a solid state hard disk channel signal adjustment system, the system comprises a main control chip and at least one flash memory chip, a channel for transmitting a DQS signal and a DQ signal exists between the main control chip and the flash memory chip, and the system further comprises a real-time monitoring module and a timing adjustment module, wherein: the real-time monitoring module is used to monitor the read operation error rate corresponding to the flash memory chip in real time, and when the read operation error rate is greater than a preset threshold, obtain the working environment parameters of the DQS signal and the DQ signal, and transmit the working environment parameters to the main control chip; the main control chip is used to obtain the timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the working environment parameters, and transmit the timing adjustment signal to the timing adjustment module; wherein the timing adjustment signal is used to realize the alignment of the DQS signal and the DQ signal corresponding to the flash memory chip; the timing adjustment module is used to receive the timing adjustment signal, and adjust the timing of the DQS signal and the DQ signal corresponding to the flash memory chip according to the timing adjustment signal.

[0005] According to a solid state hard disk channel signal adjustment system provided by the present invention, the working environment parameter includes at least one of voltage, temperature and working frequency.

[0006] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the system also includes a voltage adjustment module; the real-time monitoring module is also used to obtain the signal quality parameters of the DQS signal and the DQ signal when the read operation error rate corresponding to the flash memory chip is greater than the preset threshold, and transmit the signal quality parameters to the main control chip; the main control chip is also used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameters, and transmit the voltage adjustment signal to the voltage adjustment module; the voltage adjustment module is used to receive the voltage adjustment signal, and adjust the voltage of the DQS signal and the DQ signal corresponding to the flash memory chip according to the voltage adjustment signal.

[0007] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the signal quality parameter includes signal strength; when the main control chip is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameter, it is specifically used to: in response to the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip being lower than a preset signal strength, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0008] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the signal quality parameter includes a noise level; when the main control chip is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameter, it is specifically used to: in response to the noise level of the DQS signal and the DQ signal corresponding to the flash memory chip being higher than a preset noise level, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0009] According to a solid state drive channel signal adjustment system provided by the present invention, the main control chip is also used to: when the solid state drive is powered on, initialize the parameters of the DQS signal and the DQ signal, and write data of a preset size to the flash memory chip.

[0010] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the real-time monitoring module is also used to: after the solid-state hard disk reaches a preset frequency, read the data of the preset size written by the flash memory chip and calculate the read operation error rate.

[0011] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the real-time monitoring module is also used to: obtain the flash memory chip that achieves the read operation error rate below a preset threshold for the first time after the solid-state hard disk is powered on, and transmit the information of the flash memory chip to the main control chip; the main control chip is also used to configure the DQS signal and the parameters of the DQ signal of other flash memory chips according to the parameters of the DQS signal and the DQ signal of the flash memory chip.

[0012] According to a solid state hard disk channel signal adjustment system provided by the present invention, the parameters of the DQS signal and the DQ signal include a DQ write clock and a delay in a read direction of the DQS.

[0013] The present invention also provides a solid state hard disk, comprising any of the solid state hard disk channel signal adjustment systems described above.

[0014] The solid-state hard disk channel signal adjustment system and the solid-state hard disk provided by the present invention are provided with a real-time monitoring module and a timing adjustment module. The real-time monitoring module is used for real-time monitoring of the read operation error rate corresponding to the flash memory chip. When the read operation error rate is greater than a preset threshold, the working environment parameters of the DQS signal and the DQ signal are obtained, and the working environment parameters are transmitted to the main control chip. The main control chip is used for obtaining the timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the working environment parameters, and transmitting the timing adjustment signal to the timing adjustment module. The timing adjustment module is used for receiving the timing adjustment signal and adjusting the timing of the DQS signal and the DQ signal corresponding to the flash memory chip according to the timing adjustment signal, thereby realizing adaptive optimization and adjustment of the solid-state hard disk channel signal, being able to adapt to complex and changeable working environments, and significantly improving the reading performance and data transmission rate of the solid-state hard disk. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 This is one of the structural schematic diagrams of the solid state hard disk channel signal adjustment system provided by the present invention.

[0017] Figure 2 This is the second structural schematic diagram of the solid state hard disk channel signal adjustment system provided by the present invention.

[0018] Figure 3 It is a schematic diagram of the processing flow of the solid state hard disk channel signal adjustment system provided by the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] Figure 1 is one of the structural schematic diagrams of the solid state hard disk channel signal adjustment system provided by the present invention, such as Figure 1 As shown, the system includes a main control chip 1 and at least one flash memory chip 2, and there is a channel for transmitting DQS signals and DQ signals between the main control chip 1 and the flash memory chip 2. It is characterized in that the system also includes a real-time monitoring module 3 and a timing adjustment module 4, wherein: the real-time monitoring module 3 is used to monitor the read operation error rate corresponding to the flash memory chip 2 in real time, and when the read operation error rate is greater than a preset threshold, obtain the working environment parameters of the DQS signal and the DQ signal, and transmit the working environment parameters to the main control chip 1; the main control chip 1 is used to obtain the timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the working environment parameters, and transmit the timing adjustment signal to the timing adjustment module 4; wherein the timing adjustment signal is used to realize the alignment of the DQS signal and the DQ signal corresponding to the flash memory chip 2; the timing adjustment module 4 is used to receive the timing adjustment signal, and adjust the timing of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the timing adjustment signal.

[0021] The main control chip 1 and at least one flash memory chip 2 may be the main control chip and the flash memory chip in a solid state drive (SSD). There is a channel between the main control chip 1 and the flash memory chip 2 for transmitting DQS signals and DQ signals. In SSD, DQS (Data Strobe) and DQ (Data) are two key signals. DQS is a synchronization signal used to help the receiver accurately align and receive data during data transmission. DQ is a data signal that carries the actual data information to be transmitted. In SSD, DQS and DQ signals are indispensable components in the data reading and writing process. As a synchronization signal, the DQS signal ensures the alignment and accuracy of the data during transmission; while the DQ signal carries the actual data information. The two cooperate with each other to achieve efficient and accurate data transmission in SSD.

[0022] However, in the actual signal transmission process, it will be affected by various noises, interferences and attenuation, resulting in signal distortion, jitter and timing deviation. These problems will directly affect the reading performance and data transmission rate of the SSD. In addition, the SSD will show different signal characteristics under different working environments (such as temperature changes, voltage fluctuations, etc.). Therefore, it is necessary to optimize the SSD channel signal to improve the reading performance and data transmission rate of the SSD.

[0023] The solid state hard disk channel signal adjustment system provided by the present invention includes, in addition to a main control chip 1 and at least one flash memory chip 2 ( Figure 1 Only one flash memory chip 2 is shown), and also includes a real-time monitoring module 3 and a timing adjustment module 4. When the timing adjustment module 4 is working, it receives the control command of the main control chip 1 through the high-speed interface, and adjusts the rising and falling edge time points of the DQS and DQ signals in real time to ensure the synchronization of the signals.

[0024] Among them, the real-time monitoring module 3 is used to monitor the read operation error rate corresponding to the flash memory chip 2 during the operation of the solid-state hard disk in real time. When the read operation error rate is greater than a preset threshold, the working environment parameters of the DQS signal and the DQ signal are obtained, and the working environment parameters are transmitted to the main control chip 1; the main control chip 1 is used to obtain the timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the working environment parameters, and transmit the timing adjustment signal to the timing adjustment module 4; wherein the timing adjustment signal is used to realize the alignment of the DQS signal and the DQ signal corresponding to the flash memory chip; the timing adjustment module 4 is used to receive the timing adjustment signal, and adjust the timing of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the timing adjustment signal, such as by adjusting the time points of the rising edge and the falling edge of the DQS signal and the DQ signal to realize the timing alignment of the DQS signal and the DQ signal, ensure the synchronization of the signal, and ensure that the signal is sampled at the appropriate time point.

[0025] The solid-state hard disk channel signal adjustment system provided by the present invention is provided with a real-time monitoring module and a timing adjustment module. The real-time monitoring module is used for real-time monitoring of the read operation error rate corresponding to the flash memory chip. When the read operation error rate is greater than a preset threshold, the working environment parameters of the DQS signal and the DQ signal are obtained, and the working environment parameters are transmitted to the main control chip. The main control chip is used for obtaining the timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the working environment parameters, and transmitting the timing adjustment signal to the timing adjustment module. The timing adjustment module is used for receiving the timing adjustment signal and adjusting the timing of the DQS signal and the DQ signal corresponding to the flash memory chip according to the timing adjustment signal, thereby realizing adaptive optimization and adjustment of the solid-state hard disk channel signal, being able to adapt to complex and changeable working environments, and significantly improving the reading performance and data transmission rate of the solid-state hard disk.

[0026] According to a solid state hard disk channel signal adjustment system provided by the present invention, the working environment parameter includes at least one of voltage, temperature and working frequency.

[0027] The timing adjustment module 4 can dynamically adjust the timing of the DQS and DQ signals according to real-time monitoring data (such as temperature, voltage, operating frequency, etc.). Specifically, the timing adjustment module 4 ensures the synchronization of the signal by adjusting the time points of the rising edge and the falling edge of the signal. For example, in a high temperature environment, the propagation speed of the signal may slow down. The timing adjustment module 4 can ensure that the signal is sampled at the appropriate time point by delaying the time points of the rising edge and the falling edge.

[0028] The solid state hard disk channel signal adjustment system provided by the present invention improves the reliability of signal timing adjustment by adjusting the timing of DQS signals and DQ signals according to working environment parameters such as voltage, temperature and working frequency.

[0029] Figure 2 FIG. 2 is a second structural diagram of the solid state hard disk channel signal adjustment system provided by the present invention. Figure 2 As shown, the system also includes a voltage adjustment module 5; the real-time monitoring module 3 is also used to obtain the signal quality parameters of the DQS signal and the DQ signal when the read operation error rate corresponding to the flash memory chip 2 is greater than the preset threshold, and transmit the signal quality parameters to the main control chip 1; the main control chip 1 is also used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameters, and transmit the voltage adjustment signal to the voltage adjustment module 5; the voltage adjustment module 5 is used to receive the voltage adjustment signal, and adjust the voltage of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the voltage adjustment signal.

[0030] The solid-state hard disk channel signal adjustment system provided by the present invention not only adjusts the timing of the DQS signal and the DQ signal, but also adjusts the voltage of the DQS signal and the DQ signal to improve the signal quality of the DQS signal and the DQ signal. Therefore, the solid-state hard disk channel signal adjustment system also includes a voltage adjustment module 5. Under the control of the main control chip 1, the voltage adjustment module 5 dynamically adjusts the voltage amplitude of the DQS and DQ signals. When the voltage adjustment module 5 is working, it receives the control command of the main control chip 1 through the high-speed interface and dynamically adjusts the voltage amplitude of the DQS and DQ signals.

[0031] The real-time monitoring module 3 is also used to obtain the signal quality parameters of the DQS signal and the DQ signal when the read operation error rate corresponding to the flash memory chip 2 is greater than the preset threshold, and transmit the signal quality parameters to the main control chip 1; the main control chip 1 is also used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameters, and transmit the voltage adjustment signal to the voltage adjustment module 5; the voltage adjustment module 5 is used to receive the voltage adjustment signal, and adjust the voltage of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the voltage adjustment signal. By adjusting the output voltage of the voltage source of the DQS signal and the DQ signal, it is ensured that the DQS signal and the DQ signal are transmitted at the optimal voltage level.

[0032] The solid-state hard disk channel signal adjustment system provided by the present invention is also used for obtaining signal quality parameters of DQS signals and DQ signals through a real-time monitoring module when the read operation error rate corresponding to the flash memory chip is greater than a preset threshold, and transmitting the signal quality parameters to a main control chip. The main control chip is also used for obtaining voltage adjustment signals of the DQS signals and DQ signals corresponding to the flash memory chip according to the signal quality parameters, and transmitting the voltage adjustment signal to a voltage adjustment module. The voltage adjustment module is used for receiving the voltage adjustment signal and adjusting the voltages of the DQS signals and DQ signals corresponding to the flash memory chip according to the voltage adjustment signal, thereby realizing dynamic adjustment of the voltage amplitudes of the DQS signals and the DQ signals, and ensuring that the signals are transmitted at an optimal voltage level.

[0033] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the signal quality parameter includes signal strength; when the main control chip 1 is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameter, it is specifically used to: in response to the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip 2 being lower than the preset signal strength, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0034] The signal quality parameter may be signal strength. When the signal strength is low, the signal transmission quality may be enhanced by increasing the voltage amplitude. Therefore, when the main control chip 1 is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameter, if it is learned that the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip 2 is lower than the preset signal strength, a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal is generated. The voltage adjustment module 5 increases the supply voltage of the DQS signal and the DQ signal according to the voltage adjustment signal generated by the main control chip 1, thereby improving the signal quality.

[0035] The solid-state hard disk channel signal adjustment system provided by the present invention, through the signal quality parameters including signal strength, generates a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal in response to the signal strength of the DQS signal and the DQ signal corresponding to the flash memory chip being lower than the preset signal strength, thereby effectively improving the signal quality of the DQS signal and the DQ signal.

[0036] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the signal quality parameter includes a noise level; when the main control chip 1 is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameter, it is specifically used to: in response to the noise level of the DQS signal and the DQ signal corresponding to the flash memory chip 2 being higher than a preset noise level, generate a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal.

[0037] The signal quality parameter may also be a noise level. In the case of high signal noise, the anti-interference ability of the signal can be enhanced by increasing the voltage amplitude of the signal. Therefore, when the main control chip 1 is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameter, if it is known that the noise level of the DQS signal and the DQ signal corresponding to the flash memory chip 2 is higher than the preset noise level, a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal is generated. The voltage adjustment module 5 increases the supply voltage of the DQS signal and the DQ signal according to the voltage adjustment signal generated by the main control chip 1, thereby improving the signal quality.

[0038] The solid-state hard disk channel signal adjustment system provided by the present invention includes a noise level through a signal quality parameter. In response to the noise level of a DQS signal and a DQ signal corresponding to a flash memory chip being higher than a preset noise level, a voltage adjustment signal for increasing the voltage of the DQS signal and the DQ signal is generated, thereby effectively improving the signal quality of the DQS signal and the DQ signal.

[0039] According to a solid state drive channel signal adjustment system provided by the present invention, the main control chip 1 is also used to: initialize the parameters of the DQS signal and the DQ signal when the solid state drive is powered on, and write data of a preset size to the flash memory chip 2.

[0040] The initial stage of the SSD power-on is in the low-frequency stage, and then gradually transitions to the preset frequency. In the low-frequency stage of the SSD power-on, the initialization operation is performed, including initializing the parameters of the DQS signal and the DQ signal. The parameters of the DQS signal and the DQ signal can be set to the preset default values. After the configuration is completed, the real-time monitoring module 3 will be turned on, the timing adjustment module 4 and the voltage adjustment module 5 will enter the ready stage, and in the low-frequency stage, data of a preset size will be written to each flash memory chip 2, such as writing a PAGE (page) size of data to the NAND flash memory chip controlled by each channel of the SSD. Among them, the parameters of the DQS signal and the DQ signal include the delay of the DQ write clock and the read direction of the DQS.

[0041] The solid-state hard disk channel signal adjustment system provided by the present invention provides initial working conditions for the solid-state hard disk by initializing the parameters of the DQS signal and the DQ signal when the solid-state hard disk is powered on, and writes data of a preset size to the flash memory chip 2, and provides a basis for subsequent calculation of read operation errors by writing data of a preset size.

[0042] According to a solid state hard disk channel signal adjustment system provided by the present invention, the real-time monitoring module 3 is also used to: after the solid state hard disk reaches a preset frequency, read the data of the preset size written by the flash memory chip 2 and calculate the read operation error rate.

[0043] After the fixed hard disk is powered on and started, it gradually reaches the preset frequency and can work normally. After the solid state hard disk reaches the preset frequency, the real-time monitoring module 3 reads the preset size of data written by each flash memory chip 2, compares the read result with the pre-written data, and calculates the read operation error rate.

[0044] The solid state drive channel signal adjustment system provided by the present invention provides a basis for optimizing the parameters of the initialization setting by reading the data of a preset size written by the flash memory chip after the solid state drive reaches a preset frequency and calculating the read operation error rate.

[0045] According to a solid-state hard disk channel signal adjustment system provided by the present invention, the real-time monitoring module 3 is also used to: obtain the flash memory chip 2 that achieves the read operation error rate below a preset threshold for the first time after the solid-state hard disk is powered on, and transmit the information of the flash memory chip 2 to the main control chip 1; the main control chip 1 is also used to configure the DQS signal and the parameters of the DQ signal of other flash memory chips 2 according to the parameters of the DQS signal and the DQ signal of the flash memory chip 2.

[0046] During the operation of the solid state drive (including the initialization phase), the real-time monitoring module 3 is used to monitor the read operation error rate corresponding to the flash memory chip 2 in real time. When the read operation error rate is greater than the preset threshold, the working environment parameters and signal quality parameters of the DQS signal and the DQ signal are obtained, and the working environment parameters and the signal quality parameters are transmitted to the main control chip 1. The main control chip 1 is used to obtain the timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the working environment parameters, and transmit the timing adjustment signal to the timing adjustment module 4. The timing adjustment module 4 is used to receive the timing adjustment signal, and adjust the timing of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the timing adjustment signal. The main control chip 1 is also used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the signal quality parameters, and transmit the voltage adjustment signal to the voltage adjustment module 5; the voltage adjustment module 5 is used to receive the voltage adjustment signal, and adjust the voltage of the DQS signal and the DQ signal corresponding to the flash memory chip 2 according to the voltage adjustment signal.

[0047] In the above adjustment process, the voltage and timing of the DQS signal and DQ signal corresponding to each flash memory chip 2 are adjusted respectively. During the adjustment process of the voltage and timing of the DQS signal and the DQ signal, the parameters of the DQS signal and the DQ signal also change. Since the preset default values ​​of the DQS signal and the DQ signal parameters set by the power-on initialization are usually quite different from the parameters required during actual operation, it is necessary to adjust the initialized parameters after power-on operation so that the DQS signal and the DQ signal of each flash memory chip 2 operate under reasonable parameters.

[0048] Since the voltage and timing of the DQS signal and DQ signal corresponding to each flash memory chip 2 are adjusted respectively, the real-time monitoring module 3 obtains the flash memory chip 2 that achieves the first read operation error rate lower than the preset threshold after the solid state drive is powered on, and transmits the information of the flash memory chip 2 to the main control chip 1. At this time, it is considered that the parameters of the DQS signal and DQ signal of the flash memory chip 2 are a reasonable value. The parameters of the DQS signal and DQ signal of the flash memory chip 2 are configured using the parameters of the DQS signal and DQ signal of other flash memory chips 2, thereby realizing the optimization of the initialization parameters of each DQS signal and DQ signal in one step, so that each DQS signal and DQ signal runs under reasonable parameter settings, thus achieving the best configuration of the most original DQS and DQ signals of each channel of the SSD.

[0049] When the SSD is running, if it is affected by voltage, temperature, etc., the read operation may have errors. At this time, after the real-time monitoring module 3 of the SSD finds a read error (the read operation error rate is greater than the preset threshold), the monitoring result is sent to the main control chip 1. The main control chip 1 controls the timing adjustment module 4 to adjust the timing of the DQS and DQ signals, and controls the voltage adjustment module 5 to adjust the voltage amplitude of the DQS and DQ signals to achieve the effect of dynamically adjusting the DQS and DQ signals. In the subsequent operation process, the DQS signal and DQ signal corresponding to each flash memory chip 2 can be optimized under the control of the timing adjustment module 4 and the voltage adjustment module 5 respectively. The above steps can ensure that the SSD can maintain the best state under various working conditions and improve the system's adaptability.

[0050] The solid-state hard disk channel signal adjustment system provided by the present invention obtains the flash memory chip that achieves a read operation error rate lower than a preset threshold for the first time after the solid-state hard disk is powered on, and transmits the information of the flash memory chip to the main control chip. The main control chip is also used to configure the parameters of the DQS signal and the DQ signal of other flash memory chips according to the parameters of the DQS signal and the DQ signal of the flash memory chip, thereby quickly optimizing the initialization parameters of the DQS signal and the DQ signal.

[0051] In addition, the present invention also provides a solid state hard disk, which includes the solid state hard disk channel signal adjustment system of any of the above embodiments, that is, the solid state hard disk is a solid state hard disk capable of realizing signal optimization of DQS signal and DQ signal.

[0052] Figure 3 Schematic diagram of the processing flow of the solid state hard disk channel signal adjustment system provided by the present invention. Figure 3 As shown, the process includes: Power on and initialize the solid state drive; Turn on the real-time monitoring module, and the voltage adjustment module and timing adjustment module are ready; Import data into NAND flash memory chip; After obtaining that the working frequency of the solid state drive increases to the set frequency, the pre-written data is read; The real-time monitoring module obtains the read operation error rate; If the read operation error rate is greater than a preset threshold, the working environment parameters and signal quality parameters of the DQS signal and the DQ signal are obtained, and the working environment parameters and the signal quality parameters are transmitted to the main control chip, so that the main control chip generates a timing adjustment signal according to the working environment parameters to control the timing adjustment module to adjust the timing of the DQS signal and the DQ signal, and generates a voltage adjustment signal according to the signal quality parameters to control the voltage adjustment module to adjust the voltage of the DQS signal and the DQ signal; Obtain the flash memory chip that achieves a read operation error rate lower than a preset threshold for the first time after the solid-state hard disk is powered on, and transmit the information of the flash memory chip to the main control chip. The main control chip is also used to configure the parameters of the DQS signal and the DQ signal of other flash memory chips according to the parameters of the DQS signal and the DQ signal of the flash memory chip, thereby realizing the optimization of the initialization parameters of the DQS and DQ signals; During the operation of the solid-state hard disk, the real-time monitoring module monitors the read operation error rate in real time; if the read operation error rate is greater than a preset threshold, the working environment parameters and signal quality parameters of the DQS signal and the DQ signal are obtained, and the working environment parameters and the signal quality parameters are transmitted to the main control chip, so that the main control chip can generate a timing adjustment signal according to the working environment parameters to control the timing adjustment module to adjust the timing of the DQS signal and the DQ signal, and generate a voltage adjustment signal according to the signal quality parameters to control the voltage adjustment module to adjust the voltage of the DQS signal and the DQ signal, so as to realize dynamic optimization of the DQS and DQ signals.

[0053] The solid state hard disk channel signal adjustment system provided by the present invention has the following characteristics: (1) Improve signal quality and stability

[0054] By real-time monitoring of operating data and adaptive dynamic adjustment of voltage and timing parameters, signal noise and distortion are reduced, signal clarity and stability are improved, synchronization of DQS and DQ signals and accuracy of data sampling are ensured, and timing deviation is reduced.

[0055] (2) Enhance system adaptability

[0056] It can automatically adjust voltage and timing parameters based on real-time monitoring data to ensure that the SSD can maintain optimal performance under various working conditions.

[0057] (3) Improving SSD read performance

[0058] By optimizing signal quality, increasing data transfer rate and reliability, the reading performance of SSD is significantly improved.

[0059] (4) Improve the reliability and life of SSD

[0060] By reducing signal noise and distortion, data error rates are reduced and SSD reliability is improved. Dynamically adjust and optimize signal parameters to reduce failures caused by signal quality issues and extend the service life of the SSD.

[0061] (5) Adapt to various working conditions

[0062] Dynamically adjust voltage and timing parameters to adapt to different working conditions (such as temperature changes, voltage fluctuations, etc.), ensuring that the SSD can work stably in various environments. Improve the adaptability of the SSD in complex application scenarios to meet the needs of different users.

[0063] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0064] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A solid state hard disk channel signal adjustment system, the system comprising a main control chip and at least one flash memory chip, a channel for transmitting a DQS signal and a DQ signal exists between the main control chip and the flash memory chip, characterized in that: The system also includes a real-time monitoring module and a timing adjustment module, wherein: The real-time monitoring module is used to monitor the read operation error rate corresponding to the flash memory chip in real time, and when the read operation error rate is greater than a preset threshold, obtain the working environment parameters of the DQS signal and the DQ signal, and transmit the working environment parameters to the main control chip; The main control chip is used to obtain a timing adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the working environment parameters, and transmit the timing adjustment signal to the timing adjustment module; wherein the timing adjustment signal is used to achieve alignment of the DQS signal and the DQ signal corresponding to the flash memory chip; The timing adjustment module is used to receive the timing adjustment signal, and adjust the timing of the DQS signal and the DQ signal corresponding to the flash memory chip according to the timing adjustment signal.

2. The solid state drive channel signal adjustment system according to claim 1, characterized in that: The working environment parameter includes at least one of voltage, temperature and working frequency.

3. The solid state drive channel signal adjustment system according to claim 1, characterized in that: The system also includes a voltage adjustment module; The real-time monitoring module is also used to obtain the signal quality parameters of the DQS signal and the DQ signal when the read operation error rate corresponding to the flash memory chip is greater than the preset threshold, and transmit the signal quality parameters to the main control chip; The main control chip is also used to obtain a voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameter, and transmit the voltage adjustment signal to the voltage adjustment module; The voltage adjustment module is used to receive the voltage adjustment signal, and adjust the voltages of the DQS signal and the DQ signal corresponding to the flash memory chip according to the voltage adjustment signal.

4. The solid state drive channel signal adjustment system according to claim 3, characterized in that: The signal quality parameter includes signal strength; when the main control chip is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameter, it is specifically used to: In response to the signal strengths of the DQS signal and the DQ signal corresponding to the flash memory chip being lower than a preset signal strength, a voltage adjustment signal for increasing the voltages of the DQS signal and the DQ signal is generated.

5. The solid state drive channel signal adjustment system according to claim 3, characterized in that: The signal quality parameter includes a noise level; when the main control chip is used to obtain the voltage adjustment signal of the DQS signal and the DQ signal corresponding to the flash memory chip according to the signal quality parameter, it is specifically used to: In response to the noise levels of the DQS signal and the DQ signal corresponding to the flash memory chip being higher than a preset noise level, a voltage adjustment signal for increasing the voltages of the DQS signal and the DQ signal is generated.

6. The solid state drive channel signal adjustment system according to claim 1, characterized in that: The main control chip is also used for: When the solid state drive is powered on, the parameters of the DQS signal and the DQ signal are initialized and set, and data of a preset size is written to the flash memory chip.

7. The solid state drive channel signal adjustment system according to claim 6, characterized in that: The real-time monitoring module is also used for: After the solid state hard disk reaches a preset frequency, the data of the preset size written by the flash memory chip is read, and a read operation error rate is calculated.

8. The solid state drive channel signal adjustment system according to claim 7, characterized in that: The real-time monitoring module is also used for: Acquire the flash memory chip that realizes the read operation error rate lower than the preset threshold for the first time after the solid state hard disk is powered on, and transmit the information of the flash memory chip to the main control chip; The main control chip is also used to configure the parameters of the DQS signal and the DQ signal of other flash memory chips according to the parameters of the DQS signal and the DQ signal of the flash memory chip.

9. The solid state drive channel signal adjustment system according to claim 6, characterized in that: The parameters of the DQS signal and the DQ signal include a DQ write clock and a delay in a read direction of the DQS.

10. A solid state hard disk, characterized in that: A solid state hard disk channel signal adjustment system comprising any one of claims 1 to 9.

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