Active alternate cutting scheduling method and system for thread blocks, electronic equipment and storage medium

Abstract

The invention provides an active alternate cutting scheduling method and system for thread blocks, electronic equipment and a storage medium, and belongs to the field of GPGPU thread scheduling execution. The method comprises the steps that when a thread bundle of a thread block encounters long-delay memory access operation, feedback from a thread bundle scheduler is received, a corresponding entry of the corresponding thread block is matched through a feedback ID number, 1 is subtracted from an activity value, when the activity value is zero, the thread block is inactivated, and context information of running of the thread block is stored in a shared storage, data of a plurality of thread blocks and alternate cutting context information of each thread block are stored in the shared storage, and meanwhile, the thread block with an active value is selected to be activated and sent to a pipeline to be scheduled and run; when the thread block is activated again, the context information of the thread block is read out from the shared storage so that the thread block can continue to run; the delay of the long delay instruction is covered by polling and switching the active thread blocks, and the operation efficiency of the GPGPU is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of GPGPU thread scheduling and execution, and in particular relates to an active round-trip scheduling method, system, electronic device and storage medium for thread blocks. Background Art

[0002] GPGPU can execute thousands of threads simultaneously. The core of GPGPU is divided into large thread blocks, and GPGPU supports fast context switching between warps to allow other warps to be executed when a warp is paused, thereby hiding instruction latency. At the same time, in order to support fast context switching, GPGPU has a large register file for storing the context of multiple concurrent warps, without the need to restore and save the context.

[0003] However, the number of CTAs that can be executed simultaneously on an SM is determined by various hardware resource limitations, such as the maximum number of thread blocks supported by the hardware, the maximum number of threads supported by the hardware, the size of the register file, and the size of the shared memory. If the cumulative resource requirements of all assigned CTAs reach any of these limitations, no more CTAs can be scheduled to the SM, even if other resources are still available. According to statistics, under the above constraints, the maximum number of thread blocks supported by the hardware and the maximum number of threads supported by the hardware are the main limiting factors affecting thread-level parallelism on GPGPU. However, if the maximum number of thread blocks and threads scheduled by the hardware are blindly increased, the hardware resources of the circuit will be greatly increased. It requires additional scheduling support, such as a larger instruction buffer, scoreboard, and SIMT stack. At the same time, the complexity of the scheduler will increase, and the search time for warps that can be emitted will increase, thereby increasing the latency of the emission. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a thread block active round-robin scheduling method, system, electronic device and storage medium, which are used to utilize the shared memory and register file capacity on the SM to allocate as many thread blocks as possible to the SM until the shared memory or register file is full, and to cover the delay of long-latency instructions by polling and switching active thread blocks, and the context management design is relatively streamlined, thereby improving the operating efficiency of GPGPU.

[0005] In a first aspect, an embodiment of the present application provides a thread block active round-trip scheduling method, comprising: When the thread warp of the thread block encounters a long-delay memory access operation, feedback is received from the thread warp scheduler, the corresponding thread block entry is matched by the feedback ID number, and the activity value is reduced by 1. When the activity value is zero, the thread block is deactivated, and the context information of the thread block operation is stored in the shared storage. At the same time, the thread block with the activity value is selected to be activated and sent to the pipeline for scheduling and operation, wherein the shared storage stores the data of multiple thread blocks and the round-cut context information of each thread block; When the thread block is activated again, its context information is read from the shared storage so that the thread block can continue to run; The context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

[0006] Optionally, the pipeline architecture includes: an instruction fetch module, a decoding module, a scoreboard module, a thread warp scheduling module, a register file, an execution unit, a write-back unit, a thread block rotation module, and a shared storage unit; The instruction fetch module, the decoding module, the scoreboard module and the warp scheduling module are consistent with the pipeline of GPGPU, and use the physical warp ID index when performing thread processing; The register file is indexed by the ID of the logical thread; The execution unit and the write-back unit are consistent with the pipeline of GPGPU; The shared storage unit contains the operation data of the thread block and the context information in the operation process, so as to be used when the thread block is switched.

[0007] Optionally, the thread block rotation module includes a table entry of a thread block and a context management controller, and the table entry of the thread block respectively records the ID of the thread block, the state of the thread block, and the activity value of the thread block; The ID of the thread block is the number of all thread blocks assigned to the shared storage. The state of the thread block includes two states: activation and deactivation. The activity value of the thread block is a program counter whose initial value is the number of thread warps contained in the thread block.

[0008] Optionally, the context information includes: a number for uniquely identifying a warp, a number for uniquely identifying a thread block, a program counter, a SIMT stack, an execution mask and flag, and a memory operation status.

[0009] Optionally, the program counter is used to indicate the current execution position of a thread or warp in a program.

[0010] Optionally, the SIMT stack is used to track branches and loops during thread execution and stores addresses of reconvergence points.

[0011] Optionally, the execution mask and flag are used to indicate threads active in a warp and their status information.

[0012] In a second aspect, an embodiment of the present application further provides an active round-trip scheduling system for thread blocks, including: A scheduling unit, configured to receive feedback from a thread warp scheduler when a thread warp of a thread block encounters a long-delay memory access operation, match the corresponding entry of the corresponding thread block by the feedback ID number, and reduce the activity value by 1. When the activity value is zero, the thread block is deactivated, and the context information of the thread block operation is stored in a shared storage, and at the same time, a thread block with an activity value is selected for activation and sent to the pipeline for scheduling and operation, wherein the shared storage stores data of multiple thread blocks and the context information of the round-cut of each thread block; A reading unit is used to read out the context information of the thread block from the shared storage when the thread block is activated again, so that the thread block can continue to run; wherein the context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned active wheel switching scheduling method for thread blocks when executing the program.

[0014] In a fourth aspect, an embodiment of the present application further provides a storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned active round-trip scheduling method for thread blocks are implemented.

[0015] It can be seen from the above technical solutions that the present invention has the following advantages: The active round-robin scheduling method, system, electronic device and storage medium of thread blocks provided in the present application fully utilize the shared memory and register file capacity on the SM, allocate as many thread blocks as possible to the SM until the shared memory or register file is full, and cover the delay of long-latency instructions by polling and switching active thread blocks. The context management design is relatively streamlined, which improves the operating efficiency of GPGPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 A flowchart of an implementation method of an active round-trip scheduling method for thread blocks provided by an embodiment of the present invention; Figure 2 A schematic diagram of wheel cutting provided by an embodiment of the present invention; Figure 3 An improved water flow diagram provided by an embodiment of the present invention; Figure 4 A functional schematic diagram of a thread block cutting module provided by an embodiment of the present invention; Figure 5 A schematic diagram of the structure of an active round-trip scheduling system for thread blocks provided by an embodiment of the present invention; Figure 6 A schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to better understand the technical solution of this application, the technical terms used in this application are explained as follows: General-purpose computing on graphics processing units (GPGPU) is a graphics processor that uses graphics processing tasks to calculate general computing tasks that were originally handled by the central processing unit. These general-purpose calculations often have nothing to do with graphics processing. Due to the powerful parallel processing capabilities and programmable pipelines of modern graphics processors, stream processors can process non-graphic data. Especially when facing single instruction stream multiple data streams (SIMD), and the amount of data processing operations is far greater than the needs of data scheduling and transmission, general-purpose graphics processors greatly surpass traditional central processing unit applications in performance.

[0019] Streaming Multiprocessor (SM, also known as computing unit) is one of the core components of GPU. A GPU can have one or more SMs. SM is regarded as the heart of GPU and can be compared to the core of CPU.

[0020] Collaborative Thread Array (CTA) refers to a group of threads that execute on the same SM and share some resources, such as shared memory and registers. CTA is the basic unit of parallel execution in CUDA programs.

[0021] In the detailed description below, various embodiments of the present disclosure will be described more fully. The present disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather the present disclosure should be understood to cover all adjustments, equivalents and / or alternatives that fall within the spirit and scope of the various embodiments of the present disclosure.

[0022] Hereinafter, the terms "include" or "may include" that may be used in various embodiments of the present disclosure indicate the presence of the disclosed functions or operations, and do not limit the addition of one or more functions or operations. In addition, as used in various embodiments of the present disclosure, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, or combinations of the foregoing items, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, or combinations of the foregoing items.

[0023] In various embodiments of the present disclosure, the expression "or" or "at least one of A or / and B" includes any combination or all combinations of the words listed at the same time. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] See also Figure 1 The flowchart of the active round-trip scheduling method of thread blocks in a specific embodiment is shown, which includes the following execution steps: Step 100: When the thread warp of the thread block encounters a long-latency memory access operation, feedback is received from the thread warp scheduler, the corresponding thread block entry is matched by the feedback ID number, and the activity value is reduced by 1. When the activity value is zero, the thread block is deactivated, and the context information of the thread block operation is stored in the shared storage. At the same time, the thread block with the activity value is selected for activation and sent to the pipeline for scheduling and operation.

[0026] The shared storage stores data of multiple thread blocks and the rotation context information of each thread block.

[0027] In some embodiments, see Figure 2 As shown in the figure, the shared storage stores the data of thread blocks 1 to N. It also stores the context information of each thread block, up to the upper limit of the shared storage. When the activity value of a thread block is 0, the thread block will be deactivated, and its running context information will be stored in the shared storage. When the thread block is activated again, the context information will be read out for the continued running of the thread block.

[0028] For example, see Figure 3 As shown in the figure, it is a schematic diagram of an improved pipeline, in which the pipeline architecture includes an instruction fetch module, a decoding module, a scoreboard module, a thread warp scheduling module, a register file, an execution unit, a write-back unit, a thread block round-cut module, and a shared storage unit. The instruction fetch, decoding, scoreboard module, and thread warp scheduling module are consistent with the basic GPGPU pipeline and are not modified. When processing thread warps, physical thread warp ID indexes are used (physical thread warps refer to the maximum number of thread warps that can be scheduled by the hardware, which is limited by scheduling resources, including instruction buffers, scoreboards, schedulers, SIMT stacks, and other resources). In order to ensure that the maximum number of threads needs to be supported, the register file uses the logical thread ID (referring to the number of threads that can be supported by the upper limit of the register file capacity) for indexing, because the register file not only stores the data of the currently activated thread, but also stores the data of those inactivated threads. Therefore, the logical thread ID needs to be used for indexing. The execution unit and the write-back unit are consistent with the basic GPGPU pipeline and are not modified. The thread block switching module includes a thread block status table, which records the ID, status, and activity value of all thread blocks stored in the shared storage. It also includes a context management controller that can read the activated thread block information from the shared storage unit when the thread block is switched. The shared storage unit contains the operation data of the thread block and the context information during the operation process for use when the thread block is switched.

[0029] Step 101: When the thread block is activated again, its context information is read from the shared storage so that the thread block can continue to run.

[0030] The context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

[0031] Exemplarily, the context information includes: a number for uniquely identifying a warp, a number for uniquely identifying a thread block, a program counter, a SIMT stack, an execution mask and flag, and a memory operation status.

[0032] In a specific embodiment, for each thread block, the context information includes: 1. A number for uniquely identifying a warp. 2. A number for uniquely identifying a thread block. 3. A program counter, which indicates the current execution location of a thread or warp in a program. 4. A SIMT stack, which is used to track branches and loops during thread execution and stores the addresses of reconvergence points. 5. Execution masks and flags, which indicate which threads are active in a warp and their status information, such as whether a specific execution exception is encountered. 6. Memory operation status, such as the status of unfinished memory operations, such as the queuing and execution of load and store operations. The focus of context switching is to minimize the time and resources required to save and restore this information. Since the register file and shared memory store essentially all thread block information, only a small portion of the status information needs to be saved and restored. This design allows for efficient context switching, reduces the time overhead caused by thread scheduling, and improves the efficiency of overall GPGPU execution.

[0033] In one embodiment, see Figure 4 As shown in the figure, it is a functional diagram of the thread block switching module, which contains a table entry of a thread block and a context management controller. The table entry contains the thread block ID, the thread block state, and the thread block activity value. The thread block ID is the number of all thread blocks assigned to the shared storage (e.g., 0, 1, 2). The thread block state includes two states: activation and deactivation. The thread block activity value is a counter, and its initial value is the number of thread warps contained in the thread block (e.g., 8, 0, 0). When the thread warp of a thread block encounters a long-delay memory access operation, the thread warp scheduler will feedback to the thread block switching module. The thread block switching module matches the corresponding entry of the corresponding thread block through the feedback ID number, and reduces the activity value by 1. When the activity value is 0, the thread block will be deactivated and the corresponding context will be stored in the shared storage. The thread block with a higher activity value is selected for activation and sent to the pipeline for scheduling and operation.

[0034] In this embodiment, the shared memory and register file capacity on the SM are fully utilized, and as many thread blocks as possible are allocated to the SM until the shared memory or register file is full. The delay of long-latency instructions is covered by polling and switching active thread blocks, and the context management design is relatively streamlined, which improves the operating efficiency of GPGPU.

[0035] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0036] like Figure 5 As shown, the following is an embodiment of the active wheel switching scheduling system for thread blocks provided by the embodiments of the present disclosure, which belongs to the same inventive concept as the active wheel switching scheduling method for thread blocks in the above-mentioned embodiments. For details not fully described in the embodiments of the active wheel switching scheduling system for thread blocks, reference can be made to the embodiments of the active wheel switching scheduling method for thread blocks mentioned above.

[0037] The scheduling unit 50 is used to receive feedback from the thread warp scheduler when the thread warp of the thread block encounters a long-delay memory access operation, match the corresponding entry of the corresponding thread block through the feedback ID number, and reduce the activity value by 1. When the activity value is zero, the thread block is deactivated, and the context information of the thread block operation is stored in the shared storage, and the thread block with the activity value is selected to be activated and sent to the pipeline for scheduling and operation, wherein the shared storage stores the data of multiple thread blocks and the context information of the rotation of each thread block; The reading unit 51 is used to read out the context information of the thread block from the shared storage when the thread block is activated again, so that the thread block can continue to run; wherein the context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

[0038] Figure 6 It is a schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention.

[0039] The active wheel-cutting scheduling method of thread blocks provided in the embodiment of the present application can be applied to electronic devices. Those skilled in the art will understand that the electronic device structure involved in the embodiment of the present invention does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange different components. In an embodiment of the present invention, the electronic device includes but is not limited to a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of the present application described and / or required herein.

[0040] The electronic device may include a processor, an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, a wireless communication module, an audio module, a speaker, a microphone, a sensor module, buttons, a camera, a display, and a SIM card interface, etc.

[0041] It is to be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0042] The processor may include one or more processing units, for example, the processor may include a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated into one or more processors.

[0043] The processor can be the nerve center and command center of the electronic device. The controller can generate an operation control signal according to the instruction operation code and timing signal to complete the control of fetching and executing instructions.

[0044] A memory may also be provided in the processor for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. The memory may store instructions or data that the processor has just used or is cyclically used. If the processor needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor, and thus improves system efficiency.

[0045] The external memory interface can be used to connect an external memory card, such as a MicroSD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor through the external memory interface to implement data storage functions. For example, files such as music and videos can be saved in the external memory card.

[0046] The internal memory can be used to store computer executable program codes, which include instructions. The processor executes various functional applications and data processing of the electronic device by running the instructions stored in the internal memory. The internal memory may include a program storage area and a data storage area. The internal memory may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0047] The wireless communication function of an electronic device can be realized through an antenna, a wireless communication module, a modem processor, and a baseband processor.

[0048] The wireless communication module can provide wireless communication solutions for electronic devices, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc.

[0049] Electronic devices can implement audio functions, etc. through audio modules, speakers, receivers, microphones, headphone jacks, and application processors.

[0050] Electronic devices can achieve shooting functions through ISP, camera, video codec, GPU, display and application processor.

[0051] Electronic devices can achieve display functions through GPU, display screen and application processor.

[0052] The GPU is a microprocessor for image processing that connects the display screen and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor may include one or more GPUs that execute program instructions to generate or change display information.

[0053] The display screen is used to display images, videos, etc. The display screen includes a display panel.

[0054] The electronic device implements the active round-cut scheduling method of the thread block of the present application, storing the data of multiple thread blocks and the round-cut context information of each thread block in a shared storage until the upper limit of the shared storage is reached; when the thread warp of the thread block encounters a long-delay memory access operation, receiving feedback from the thread warp scheduler, matching the corresponding entry of the corresponding thread block through the feedback ID number, and reducing the activity value by 1, when the activity value is zero, deactivating the thread block, and storing the context information of the thread block operation in the shared storage, and selecting the thread block with the activity value to activate, and sending it to the pipeline for scheduling and operation; when the thread block is activated again When the thread block is paused or switched from an active state to an inactive state, the context information is read from the shared storage so that the thread block can continue to run; wherein the context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution. The technical solution fully utilizes the shared memory and register file capacity on the SM, allocates as many thread blocks as possible to the SM until the shared memory or register file is full, and masks the delay of long-latency instructions by switching active thread blocks through polling, and the context management design is relatively streamlined, which improves the beneficial effect of improving the operating efficiency of GPGPU.

[0055] The storage medium provided in the present application stores a program product capable of implementing an active round-robin scheduling method for thread blocks.

[0056] The active round-cut scheduling method of thread blocks includes: storing data of multiple thread blocks and round-cut context information of each thread block in a shared storage until the upper limit of the shared storage is reached; when a thread warp of a thread block encounters a long-delay memory access operation, receiving feedback from a thread warp scheduler, matching the corresponding entry of the corresponding thread block through the feedback ID number, and reducing the activity value by 1, when the activity value is zero, deactivating the thread block, and storing the context information of the thread block operation in the shared storage, and selecting a thread block with an activity value to activate and send it to the pipeline for scheduling and operation; when the thread block is activated again, reading its context information from the shared storage for the thread block to continue to run; wherein the context information is a set of data related to the thread execution state, and the set of data is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

[0057] In some possible implementations, the subject name of the present disclosure, the method and system for active round-trip scheduling of thread blocks can be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps described in the above "Exemplary Method" section of this specification according to various exemplary implementations of the present disclosure.

[0058] The storage medium of the present disclosure can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0059] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A thread block active round-trip scheduling method, characterized in that: include: When the thread warp of the thread block encounters a long-delay memory access operation, feedback is received from the thread warp scheduler, the corresponding thread block entry is matched by the feedback ID number, and the activity value is reduced by 1. When the activity value is zero, the thread block is deactivated, and the context information of the thread block operation is stored in the shared storage. At the same time, the thread block with the activity value is selected to be activated and sent to the pipeline for scheduling and operation, wherein the shared storage stores the data of multiple thread blocks and the round-cut context information of each thread block; When the thread block is activated again, its context information is read from the shared storage so that the thread block can continue to run; The context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

2. The thread block active round-trip scheduling method according to claim 1, characterized in that: The pipeline architecture includes: instruction fetch module, decoding module, scoreboard module, thread warp scheduling module, register file, execution unit, write-back unit, thread block round-cut module and shared storage unit; The instruction fetch module, the decoding module, the scoreboard module and the warp scheduling module are consistent with the pipeline of GPGPU, and use the physical warp ID index when performing thread processing; The register file is indexed by the ID of the logical thread; The execution unit and the write-back unit are consistent with the pipeline of GPGPU; The shared storage unit contains the operation data of the thread block and the context information in the operation process, so as to be used when the thread block is switched.

3. The thread block active round-trip scheduling method according to claim 2, characterized in that: The thread block round-cutting module includes a table entry of a thread block and a context management controller, wherein the table entry of the thread block respectively records the ID of the thread block, the state of the thread block and the activity value of the thread block; The ID of the thread block is the number of all thread blocks assigned to the shared storage. The state of the thread block includes two states: activation and deactivation. The activity value of the thread block is a program counter whose initial value is the number of thread warps contained in the thread block.

4. The thread block active round-trip scheduling method according to claim 1, characterized in that: The context information includes: a number for uniquely identifying a warp, a number for uniquely identifying a thread block, a program counter, a SIMT stack, an execution mask and flag, and a memory operation state.

5. The thread block active round-trip scheduling method according to claim 4, characterized in that: The program counter is used to indicate the current execution location of a thread or warp in the program.

6. The thread block active round-trip scheduling method according to claim 4, characterized in that: The SIMT stack is used to track branches and loops during thread execution and stores addresses of reconvergence points.

7. The thread block active round-trip scheduling method according to claim 4, characterized in that: The execution mask and flags are used to indicate threads active in a warp and their status information.

8. An active round-trip scheduling system for thread blocks, characterized in that: include: A scheduling unit, configured to receive feedback from a thread warp scheduler when a thread warp of a thread block encounters a long-delay memory access operation, match the corresponding entry of the corresponding thread block by the feedback ID number, and reduce the activity value by 1. When the activity value is zero, the thread block is deactivated, and the context information of the thread block operation is stored in a shared storage, and at the same time, a thread block with an activity value is selected for activation and sent to the pipeline for scheduling and operation, wherein the shared storage stores data of multiple thread blocks and the context information of the round-cut of each thread block; A reading unit is used to read out the context information of the thread block from the shared storage when the thread block is activated again, so that the thread block can continue to run; wherein the context information is a set of data related to the thread execution state, which is saved when the thread is suspended or switched from an active state to an inactive state, and is reloaded before resuming execution.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the active round-trip scheduling method for thread blocks according to any one of claims 1 to 7 are implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the active round-trip scheduling method for thread blocks according to any one of claims 1 to 7 are implemented.

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