Data storage structure and data storage method

Abstract

The invention provides a data storage structure and a data storage method. The data storage structure comprises a mask circuit, a check coding circuit and a storage circuit which are connected in sequence, wherein the storage circuit comprises M storage arrays; the mask circuit is used for performing mask processing on to-be-written data to obtain to-be-coded data; the check coding circuit is used for splitting data to be coded into N sub-data according to bytes and is used for carrying out check coding on the N sub-data to obtain check coded data corresponding to the N sub-data respectively, any group of check coded data comprises the sub-data and a check code of the sub-data, and N is an integer greater than or equal to 2; the M storage arrays are used for storing N groups of check coding data, M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage arrays is greater than or equal to the bit width of the check coding data. According to the embodiment of the invention, the check coding function and the write mask function can be simultaneously realized in one data storage structure, the data storage logic is simplified, and the data storage efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a data storage structure and a data storage method. Background Art

[0002] When using the storage structure of a chip for data storage, the data is usually split manually and then checked or masked, and then the processed data is stored in a storage circuit, which results in complex data storage logic and low data storage efficiency. Summary of the invention

[0003] The present invention provides a data storage structure and a data storage method to solve the problem that the existing storage circuit cannot simultaneously meet the requirements of the complete verification function and the write mask function, and the data storage logic is complex, resulting in low data storage efficiency.

[0004] In a first aspect, an embodiment of the present application provides a data storage structure, including a mask circuit, a check code circuit, and a storage circuit connected in sequence, wherein the storage circuit includes M storage arrays;

[0005] The mask circuit is used to perform mask processing on the data to be written to obtain the data to be encoded;

[0006] The check coding circuit is used to split the data to be encoded into N sub-data by byte, and to perform check coding on the N sub-data to obtain check coding data corresponding to the N sub-data respectively, any set of check coding data includes sub-data and check codes of the sub-data, and N is an integer greater than or equal to 2;

[0007] The M storage arrays are used to store N groups of check code data, where M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check code data.

[0008] Optionally, the verification coding circuit is further used for:

[0009] Determine M data groups according to N groups of check code data;

[0010] The M data groups are stored in M ​​storage arrays in a one-to-one correspondence.

[0011] Optionally, the verification coding circuit is further used for:

[0012] According to the order of the N sub-data in the data to be encoded, N groups of check code data are merged to obtain the target storage data;

[0013] According to the bit width of each storage array in the storage circuit, the target storage data is split into M data groups, and the bit width of the M data groups corresponds to the bit width of the M storage arrays one by one.

[0014] Optionally, the data storage structure further includes a reading device connected to the M storage arrays and N check decoders;

[0015] The reading device is used to read data from the M storage arrays of the storage circuit to obtain N groups of check code data, and is used to input the N groups of check code data into the N check decoders in a one-to-one correspondence;

[0016] The N check decoders are used to respectively decode and check the check coded data input by the reading device to obtain N sub-data.

[0017] Optionally, the bit width of the storage circuit is determined by the number of check encoders in the check encoding circuit and the number of bits of the check code generated by the check encoder;

[0018] The number and structure of the memory arrays in the memory circuit are determined by the bit width of the memory circuit and the performance data of the memory circuit.

[0019] Optionally, the storage circuit is a circuit to be selected whose performance meets the requirements among multiple circuits to be selected, different circuits to be selected correspond to different storage array combination methods, the number and / or structure of storage arrays in different storage array combination methods are different, and the different storage array combination methods are determined by splitting the storage circuit according to the bit width of the storage circuit.

[0020] Optionally, when the circuit areas of the circuits to be selected are different, the storage circuit is the circuit to be selected with the smallest circuit area; or,

[0021] When the circuit areas of the circuits to be selected are the same, the storage circuit is the circuit to be selected with the smallest leakage among the multiple circuits to be selected; or,

[0022] The storage circuit is a circuit to be selected whose absolute value of power circuit area ratio is the smallest among multiple circuits to be selected. The power circuit area ratio is determined by the circuit area and leakage condition of the circuit to be selected or by the circuit area and circuit power consumption of the circuit to be selected.

[0023] Optionally, the splitting method of the storage circuit includes a single splitting method and an equal splitting method. In the single splitting method, the circuit to be selected includes a storage array, and the bit width of the storage array is the bit width of the storage circuit;

[0024] The equal division method is to equally divide the storage space of the circuit to be selected into multiple storage arrays with the same structure, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected.

[0025] Optionally, different types of storage array splitting methods also include unequal splitting methods, in which the types and logical sizes of the storage arrays of the circuit to be selected are different, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected.

[0026] Optionally, the check coding circuit includes a splitting device and N check encoders, the splitting device is connected to the output of the mask circuit and to the input of the N check encoders, and the output of the N check encoders is connected to the storage circuit;

[0027] The splitting device is used to split the data to be encoded into N sub-data by byte, and input the N sub-data to N check encoders one by one, with one check encoder inputting one sub-data;

[0028] The N check encoders are used to encode the sub-data input by the splitting device respectively to obtain N groups of check code data.

[0029] In a second aspect, an embodiment of the present application provides a data storage method, which is applied to the above data storage structure, and the method includes:

[0030] The mask circuit performs mask processing on the data to be written to obtain the data to be encoded;

[0031] The check coding circuit splits the data to be coded into N sub-data by byte, and performs check coding on the N sub-data to obtain check coding data corresponding to the N sub-data respectively, any set of check coding data includes the sub-data and the check code of the sub-data, and N is an integer greater than or equal to 2;

[0032] The check code circuit stores N groups of check code data in M ​​storage arrays, where M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check code data.

[0033] In a scheme provided by the above data storage structure and data storage method, the data storage structure includes a mask circuit, a check coding circuit and a storage circuit connected in sequence, and the storage circuit includes M storage arrays; wherein the mask circuit is used to perform mask processing on the data to be written to obtain the data to be encoded of the data to be written; the check coding circuit is used to split the data to be encoded into N sub-data by byte, and to perform check coding on the N sub-data to obtain the check coding data corresponding to the N sub-data respectively, any group of check coding data includes sub-data and check codes of the sub-data, and N is an integer greater than or equal to 2; M storage arrays are used to store N groups of check coding data, M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check coding data. In this embodiment, the original input data is masked by the mask circuit, and then the check coding circuit splits and encodes the masked data by byte, so that the check coding function and the write mask function can be realized in one data storage structure at the same time, without artificial data splitting for check or mask processing, and on the basis of ensuring data integrity and security, the data storage logic is simplified and the efficiency of data storage is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0035] Figure 1 is a structural diagram of a data storage structure in one embodiment of the present invention;

[0036] Figure 2 yes Figure 1 A structural schematic diagram of a verification coding circuit;

[0037] Figure 3 is another structural schematic diagram of a data storage structure in one embodiment of the present invention;

[0038] Figure 4 yes Figure 3 A structural schematic diagram of a check decoding circuit;

[0039] Figure 5 is a schematic structural diagram of a storage circuit in one embodiment of the present invention;

[0040] Figure 6 Is adopted Figure 5 A schematic diagram of the process of data storage and reading by the storage circuit;

[0041] Figure 7 is another structural schematic diagram of a storage circuit in one embodiment of the present invention;

[0042] Figure 8 Is adopted Figure 7 Another schematic diagram of the process of data storage and reading by the storage circuit;

[0043] Fig. 9 It is a flowchart of a data storage method in one embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or their collections. It should also be understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0046] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0047] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0048] It should be understood that the order of execution of the steps in the following embodiments does not imply a precedence of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0049] In order to illustrate the technical solution of the present invention, specific embodiments are provided below for illustration.

[0050] It is important to understand that when using chip storage circuits for data storage, especially when using storage circuits on automotive-grade chips for vehicle data storage, in order to protect the integrity of subsequent read data, security checks need to be performed when accessing data, and to ensure data security, masking needs to be performed when writing data. However, it is difficult for existing chip storage circuits to simultaneously implement verification functions or write mask functions, and traditional verification tools themselves do not support such features; in this regard, in order to ensure data integrity and data security, when storing data in chip storage circuits, it is necessary to use other devices (such as external devices) to manually split the data for verification and / or write masking, and then send the processed data to the storage circuit for storage. This method of data storage requires interaction with other devices, resulting in complex data storage logic and low data storage efficiency.

[0051] In view of the above problems, an embodiment of the present invention provides a data storage structure that can achieve the integrity and security of data access without the participation of external devices, which can effectively simplify the data storage logic and improve storage efficiency. Figure 1 As shown, the data storage structure in the embodiment of the present invention includes a mask circuit, a check code circuit and a storage circuit connected in sequence, and the storage circuit includes M storage arrays.

[0052] Among them, the mask circuit is used to perform mask processing on the data to be written to obtain the data to be encoded of the data to be written. The check coding circuit is used to split the data to be encoded into N sub-data by byte, and to perform check coding on the N sub-data to obtain the check coding data corresponding to the N sub-data. Any group of check coding data includes sub-data and check codes of the sub-data, and N is an integer greater than or equal to 2. M storage arrays are used to store N groups of check coding data, M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check coding data, so that the storage array can store a complete set of check coding data.

[0053] When storing data, the mask circuit of the data storage structure of this embodiment receives the data to be written sent by the chip controller or the external device, and performs mask processing on the data to be written, obtains the data to be encoded of the data to be written, and then inputs it into the verification coding circuit. The verification coding circuit splits the data to be encoded into N sub-data by byte, and performs verification coding on the N sub-data to obtain the verification coding data corresponding to the N sub-data, that is, to obtain N groups of verification coding data. Among them, any group of verification coding data includes sub-data and verification code of sub-data, and N is an integer greater than or equal to 2. For example, each byte of the data to be encoded can be split into a sub-data, that is, N is the number of bytes in the data to be encoded, which is convenient for subsequent separate encoding and storage processing and simplifies the storage logic. In other embodiments, 2-3 bytes can also be split into one sub-data to reduce the number of sub-data.

[0054] After obtaining N groups of check code data, the check code circuit outputs the check code data to the storage circuit, stores the N groups of check code data through M storage arrays in the storage circuit, and records the storage address of each group of check code data. For example, when M is 1, that is, the storage circuit includes 1 storage array, the N groups of check code data can be stored in the storage array. When M is an integer greater than 1 and less than or equal to N, the N groups of check code data can be merged and then split into M data groups in sequence, and the M data groups are stored in M ​​storage arrays one by one; in other embodiments, the N groups of check code data can be stored together in one storage array of multiple storage arrays, and when one storage array is full, it is stored in the next storage array.

[0055] In this embodiment, the original input data is masked by a mask circuit, and then the check coding circuit splits and encodes the masked data by bytes. The check coding function and the write mask function can be simultaneously implemented in a data storage structure without the need for manual data splitting for verification or mask processing. On the basis of ensuring data integrity and security, the data storage logic is simplified and the efficiency of data storage is improved.

[0056] In one embodiment, if Figure 2As shown, the check coding circuit includes a splitting device and N check encoders (such as check encoder 1...check encoder N) connected to each other, where N is an integer greater than or equal to 2. The splitting device is connected to the output of the mask circuit and the input of the N check encoders, and the output of the N check encoders is connected to the storage circuit through the splitting device. Among them, the splitting device is used to split the data to be encoded into N sub-data by byte, and input the N sub-data to the N check encoders one by one, that is, one check encoder inputs one sub-data, and N is the number of bytes in the data to be encoded. The N check encoders are used to encode the sub-data input by the splitting device respectively to obtain N groups of check coding data. In other embodiments, the check coding circuit may include a check encoder or a plurality of check encoders less than N, and the N sub-data are encoded in sequence by a check encoder or a plurality of check encoders less than N to obtain N groups of check coding data.

[0057] Specifically, the splitting device of the check coding circuit is used to: merge N groups of check coding data according to the order of N sub-data in the data to be encoded to obtain target storage data, and then split the target storage data according to the bit width of each storage array in the storage circuit to obtain M data groups, so as to ensure that the order of the stored data is correct. Among them, the bit width of the M data groups corresponds to the bit width of the M storage arrays one by one, and the bit width of the M storage arrays is greater than the bit width of the corresponding data group in the M data groups, so as to ensure that each storage array can completely store the data of each data group.

[0058] In this embodiment, N sub-data are encoded respectively by N check encoders. This is simpler than encoding the N sub-data by one or multiple check encoders whose number is less than N. There is no need to control at least one check encoder to perform multiple encodings, which simplifies the encoding logic and thus improves data storage efficiency.

[0059] In one embodiment, if Figure 3 As shown, the data storage structure includes a mask circuit, a check encoding circuit, a storage circuit and a check decoding circuit connected in sequence. Figure 4 As shown, the check decoding circuit includes a reading device and N check decoders (such as check decoder 1...check decoder N), where N is an integer greater than or equal to 2. The input of the reading device is respectively connected to the M storage arrays, and the output of the reading device is respectively connected to the input of each check decoder. The reading device is used to read data from the M storage arrays of the storage circuit to obtain N groups of check code data; the reading device is also used to input the N groups of check code data to the N check decoders one by one, that is, one check decoder inputs a group of check code data. The N check decoders are used to decode and check the check code data input by the reading device respectively to obtain N sub-data.

[0060] Specifically, the reading device of the check decoding circuit is used to: read M data groups from M storage arrays of the storage circuit according to the storage addresses of the M data groups, merge the M data groups in the order of the M storage arrays to obtain the target storage data, and split the target storage data according to the order of the N sub-data in the data to be encoded, obtain N groups of check coded data and input them into N check decoders respectively. The N check decoders are also used to: respectively decode and check the check coded data input by the reading device, and output N sub-data. The reading device is also used to: merge the N sub-data in the order of the N sub-data in the data to be encoded to obtain the target data.

[0061] In this embodiment, a storage array is equivalent to a separate storage circuit. Using N check decoders to read and decode data from the N storage arrays is equivalent to using N storage circuits to encode, store and decode each sub-data separately, thereby ensuring data integrity and security, with simple data storage logic and high data reading efficiency.

[0062] In a specific implementation, the data storage structure includes a mask circuit, a check coding circuit, a storage circuit and a check decoding circuit connected in sequence. Wherein, M is equal to N, that is, the storage circuit includes N storage arrays, and the bit width of the storage array is greater than or equal to the bit width of the check coding data. Figure 5 As shown, the storage circuit includes N storage arrays (such as storage array 1 ... storage array N), the check encoding circuit includes a splitting device and N check encoders (such as check encoder 1 ... check encoder N), and the check decoding circuit includes a reading device and N check decoders (such as check decoder 1 ... check decoder N), where N is an integer greater than or equal to 2. The splitting device is connected to the output of the mask circuit and the input of the N check encoders, and the outputs of the N check encoders are respectively connected to the N storage arrays of the storage circuit in a one-to-one correspondence; the input of the reading device is respectively connected to the output of the N storage arrays, and the output of the reading device is respectively connected to the input of the N check decoders.

[0063] When storing data, the mask circuit is used to perform mask processing on the data to be written, obtain the data to be encoded to be written and output it to the splitting device of the check decoding circuit, the splitting device is used to split the data to be encoded into N sub-data by byte, and input the N sub-data one by one to N check encoders, one check encoder inputs one sub-data, and one sub-data can be one byte. The N check encoders are used to encode the sub-data input by the splitting device respectively, obtain N groups of check code data and store them in the N storage arrays of the storage circuit respectively, and record the storage address of each check code data. Among them, one check encoder encodes one sub-data and outputs a group of check code data, and any group of check code data includes sub-data and check code of sub-data. When reading data, the reading device is used to read from the N storage arrays according to the storage addresses of each check code data recorded in advance to obtain N groups of check code data and input them to N check decoders one by one, that is, one N check decoder inputs a group of check code data. The N check decoders are used to decode and verify the check code data input by the reading device respectively, and obtain N sub-data corresponding to the N groups of check code data. In addition, the reading device is also used to merge the N sub-data according to the order of the N sub-data in the data to be encoded to obtain the target read data.

[0064] For example, the data to be encoded includes N bytes: byte 0, byte 1, ... byte N-1, each byte can be 8 bits, that is, each byte is a group of 8 bits of data. Figure 6 As shown, the splitting device splits N bytes of data to be encoded into N sub-data by byte, each sub-data is a byte of the data to be encoded, and each sub-data is 8-bit data, that is, the bit width of each sub-data is 8; the splitting device will input the split N 8-bit sub-data into N check encoders of the check coding circuit respectively: check encoder 0, check encoder 1...check encoder N-1. The N check encoders encode the input sub-data according to the same encoding algorithm to obtain N groups of check coding data, each group of check coding data includes 8-bit sub-data and 5-bit check code (that is, the bit width of the check code is 5); then, the N check encoders store the N groups of check coding data obtained by encoding respectively into N storage arrays: storage array 0, storage array 1...storage array N-1, and record the storage address of each check coding data; wherein, the bit width of the N storage arrays is at least the bit width of the check coding data, such as 8 bits of sub-data and 5 bits of check code, that is, the bit width of the storage array is 13 bits.

[0065] like Figure 6As shown, when data needs to be read, the reading device reads the data of N storage arrays according to the storage address of each check code data, and obtains N groups of check code data, each group of check code data includes 8 bits of sub-data and 5 bits of check code, and the reading device inputs the N groups of check code data into N check decoders respectively: check decoder 0, check decoder 1...check decoder N-1. The N check decoders respectively decode and check the check code data input by the reading device, and output N 8-bit sub-data, each sub-data is a byte, and N bytes are obtained: byte 0, byte 1...byte N-1. In this embodiment, the number of bits of each byte in the data to be encoded is 8 bits and the number of bits of the check code is 5 bits, which is only for exemplary description. In other embodiments, the number of bits of each byte in the data to be encoded and the number of bits of the check code can be other numbers, which are determined according to the type of data stored and the type of the check encoder, and will not be repeated here.

[0066] In this embodiment, the data to be encoded is split into N sub-data by bytes through a splitting device, and each sub-data is encoded by an independent check encoder and then stored in a corresponding storage array; when reading data, the reading device reads data from the N storage arrays respectively to obtain N groups of check coded data, and decodes and verifies the N groups of check coded data respectively through N check decoders, which is equivalent to using N storage circuits to separately encode, store and decode each sub-data, thereby ensuring data integrity and security, with simple data storage logic and high data storage and reading efficiency.

[0067] In the above implementation, the storage space of the storage circuit is divided into N storage arrays according to the number N of check encoders in the check coding circuit. Each storage array constitutes a storage circuit. Such a storage space division method will result in a large number of storage circuits. For the chip, the more storage arrays there are, the larger the circuit area they occupy when the chip storage space remains unchanged. The more storage circuits mean the larger the total circuit area, which ultimately leads to an excessively large chip circuit area and affects the overall performance of the chip, thereby reducing the market competitiveness of the chip.

[0068] To solve the problem that too many memory arrays lead to excessive chip circuit area and affect the overall performance of the chip, in one embodiment, Figure 7 As shown, the storage circuit of the data storage structure includes M storage arrays, where M is an integer less than N, that is, the number of storage arrays in the storage circuit is greater than or equal to 1 and less than N, and the bit width of the storage array is greater than or equal to the bit width of the check code data. After respectively encoding the N sub-data to obtain N groups of check code data, the splitting device of the check code circuit is further used to: determine M data groups according to the N groups of check code data, and store the M data groups in the M storage arrays in a one-to-one correspondence.

[0069] Specifically, the splitting device of the check coding circuit is used to: merge N groups of check coding data according to the order of N sub-data in the data to be encoded to obtain target storage data, and then split the target storage data according to the bit width of each storage array in the storage circuit to obtain M data groups, so as to ensure that the order of the stored data is correct. Among them, the bit width of the M data groups corresponds to the bit width of the M storage arrays one by one, and the bit width of the M storage arrays is greater than the bit width of the corresponding data group in the M data groups, so as to ensure that each storage array can completely store the data of each data group.

[0070] Specifically, the reading device of the check decoding circuit is used to: read M data groups from M storage arrays of the storage circuit according to the storage addresses of the M data groups, merge the M data groups in the order of the M storage arrays to obtain the target storage data, and split the target storage data according to the order of the N sub-data in the data to be encoded, obtain N groups of check coded data and input them into N check decoders respectively. The N check decoders are also used to: respectively decode and check the check coded data input by the reading device, and output N sub-data. The reading device is also used to: merge the N sub-data in the order of the N sub-data in the data to be encoded to obtain the target data.

[0071] For example, the data to be encoded includes N bytes: byte 0, byte 1, byte 2, ... byte N-1, each byte can be 8 bits, that is, each byte is a group of 8-bit data, and N is an integer greater than 3. M is less than N, such as Figure 8As shown, the storage circuit includes M storage arrays: storage array 1...storage array M, where M can be an integer greater than 1 (in other embodiments, M can also be equal to 1). The splitting device splits the N bytes of data to be encoded into N sub-data by byte, each of which can be a byte of the data to be encoded, and each sub-data is 8-bit data, that is, each sub-data is a group of 8 bits wide; then the splitting device will input the split N 8-bit sub-data into the N check encoders of the check coding circuit respectively: check encoder 0, check encoder 1, check encoder 2...check encoder N-1. The N check encoders encode the input sub-data according to the same coding algorithm to obtain N groups of check code data, each group of check code data includes 8 bits of sub-data and 5 bits of check code. The splitting device combines the N groups of check code data obtained by encoding by N check encoders according to the order of the N sub-data in the data to be encoded to obtain the target storage data, and splits the target storage data according to the bit width of each storage array in the storage circuit to obtain M data groups: data group 1...data group M, and stores the M data groups in M ​​storage arrays: storage array 1...storage array M in a one-to-one correspondence, and records the storage address of each data group. Among them, the bit width of each storage array needs to be greater than the bit width of the check code data, and the bit width of the storage circuit needs to be greater than or equal to N times the bit width of the check code data. For example, if the sub-data is 8 bits and the check code is 5 bits, the bit width of the storage circuit needs to be greater than or equal to 13*N, and the bit width of each storage array needs to be greater than 13. Among them, when the data to be encoded is split into N sub-data for encoding, 1 bit of data is valid in every 8 bits, that is, 1 bit of data is valid in each sub-data; when the encoded N groups of check code data are stored, 1 bit of data is valid in every 13 bits, that is, 1 bit of data is valid in each group of check code data.

[0072] like Figure 8 As shown, when data needs to be read, the reading device reads M data groups from the M storage arrays of the storage circuit according to the storage addresses of the M data groups, merges the M data groups in the order of the M storage arrays, and obtains the target storage data; splits the target storage data according to the order of the N sub-data in the data to be encoded, and obtains N groups of verification code data, each group of verification code data includes 8 bits of sub-data and 5 bits of verification code. Then, the reading device inputs the N groups of verification code data into N verification decoders respectively: verification decoder 0, verification decoder 1, verification decoder 2... verification decoder N-1. The N verification decoders respectively decode and verify the verification code data input by the reading device, and output N 8-bit sub-data, each sub-data is a byte, and N bytes are obtained: byte 0, byte 1, byte 2... byte N-1. As mentioned above Figure 6 compared to, Figure 8The number of storage arrays is reduced, and the area of ​​the storage circuit can be reduced.

[0073] The data storage structure in this embodiment integrates a write mask function, a codec verification function, and a storage array with a number less than N. The storage array splitting method of the data storage structure in this embodiment reduces the number of storage arrays in the storage circuit, thereby reducing the circuit area of ​​the storage circuit, improving the overall performance of the chip, and increasing the market competitiveness of the chip. It is found through measured data that compared with the aforementioned solution of splitting the storage circuit into N storage arrays for separate data storage, the storage array splitting method in this embodiment can reduce the circuit area consumption by about 50%.

[0074] In one embodiment, the bit width of the storage circuit is determined by the number of check encoders in the check coding circuit and the number of bits of the check code generated by the check encoder, wherein the bit width of the storage circuit needs to be greater than (b+a)*N, wherein a is the number of bits (bit width) of the check code for the sub-data to be encoded by the check encoder, b is the number of bits of each sub-data, and N is the number of check encoders. When the splitting device splits the data to be encoded into N sub-data by byte, any sub-data is one byte, and the number of check encoders is N, N is the number of bytes in the data to be encoded. After encoding to obtain N groups of check code data, they are directly sent to a storage circuit with a width of (b+a)*N, and the N groups of check code data are stored through M storage arrays. According to the number of check encoders in the check coding circuit and the number of bits of the check code generated by the check encoder, the bit width of the storage circuit is determined to ensure that the storage circuit can completely store N groups of check code data. The storage array splitting method of the data storage structure in this embodiment can flexibly configure the data bit width of the storage array bit width according to different needs, and has high scalability.

[0075] In one embodiment, the number and structure of the storage arrays in the storage circuit are determined by the bit width of the storage circuit and the performance data of the storage circuit, wherein the performance data at least includes the circuit area of ​​the storage circuit. In other embodiments, the performance data may also include the leakage and / or energy consumption of the storage circuit. The bit width of the storage circuit and the performance data of the storage circuit determine the number of storage arrays, which can effectively improve the performance of the storage circuit, thereby improving the overall performance of the chip and increasing the market competitiveness of the chip.

[0076] In one embodiment, the storage circuit is a circuit to be selected whose performance meets the requirements among multiple circuits to be selected, and the number and / or structure of storage arrays included in different circuits to be selected are different. Among them, different circuits to be selected correspond to different storage array combination methods, and the number and / or structure of storage arrays in different storage array combination methods are different. Different storage array combination methods are determined by splitting the storage circuit according to the bit width of the storage circuit. Among them, the structure of the storage circuit can be selected according to the bit width and circuit performance data of the storage circuit, and the circuit to be selected that meets the performance requirements is determined from multiple circuits to be selected whose bit widths meet the requirements as the storage circuit, so that the storage circuit meets the storage requirements and has good performance, thereby improving the overall performance of the chip.

[0077] Specifically, when selecting a circuit to obtain a storage circuit, it is necessary to use the bit width of the storage circuit as a constraint, and determine multiple circuits to be selected according to different types of storage array splitting methods, and the number or structure of the storage arrays in the multiple circuits to be selected is different. Then, the performance of the multiple circuits to be selected is tested to obtain circuit performance test data of each circuit to be selected, and the circuit performance test data includes at least one of the circuit area, leakage condition, and circuit power consumption. Finally, according to the circuit performance test data of each circuit to be selected, the circuit to be selected that meets the performance requirements is determined as a storage circuit among the multiple circuits to be selected, thereby determining the number and structure of the storage arrays in the storage circuit, and obtaining a storage circuit that meets the performance requirements for storage.

[0078] In this embodiment, a candidate circuit whose performance meets the requirements is determined from among multiple candidate circuits, so that the performance of the storage circuit in the data storage structure can be guaranteed, and a storage circuit in which the number and structure of the storage array are optimal can be obtained, thereby improving the overall performance of the chip; and when the data storage structure including the storage circuit is used for data storage, data integrity and security can also be guaranteed, data storage logic can be simplified, and the efficiency of data storage and reading can be improved.

[0079] In one embodiment, the splitting method of the storage circuit includes a single splitting method and an equal splitting method. In the single splitting method, the circuit to be selected includes a storage array, and the bit width of the storage array is the bit width of the storage circuit. The equal splitting method (i.e., repeated splitting method) is to equally split the storage space of the circuit to be selected into multiple storage arrays with the same structure, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected. When the equal splitting method is used to split multiple circuits to be selected, the number of storage arrays in each circuit to be selected is 2 n, n is an integer greater than or equal to 1; the circuit is divided into multiple circuits to be selected by equal division, and then a circuit to be selected that meets the performance requirements is determined as a storage circuit among the multiple circuits to be selected, and when the storage circuit is subsequently used for data storage, the storage circuit can be used for chip selection logic of low-bit address decoding.

[0080] In this embodiment, a single splitting method and an equal splitting method are used to split multiple circuits to be selected, which can maximize the number of storage arrays and the composition of the structure in the circuits to be selected, increase the number of circuits to be selected, and thus select candidate circuits with better performance as storage circuits, thereby improving the performance of the storage circuits.

[0081] In one embodiment, different types of storage array splitting methods include a single splitting method, an equal splitting method, and an unequal splitting method. In the unequal splitting method, the types and logical sizes of the storage arrays of the circuits to be selected are different, that is, storage arrays of different types and different logical sizes are mixed together to obtain multiple circuits to be selected, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected. When the equal splitting method is used to split multiple circuits to be selected, the depth of the storage array in each circuit to be selected is 2 n , n is an integer greater than or equal to 1. The circuit is split into multiple circuits to be selected by unequal splitting, and then a circuit to be selected that meets the performance requirements is determined as a storage circuit among the multiple circuits to be selected. When the storage circuit is used for data storage later, the storage circuit can be used for the chip selection logic of the high-bit decoding of the address.

[0082] In this embodiment, a single splitting method, an equal splitting method, and an unequal splitting method are used to split multiple circuits to be selected, which expands the number of storage arrays and the composition of the structure, increases the number of circuits to be selected, and thus enables the candidate circuit with the best performance to be selected as the storage circuit, thereby improving the performance of the storage circuit.

[0083] In one embodiment, when the circuit areas of the selected circuits are different, the storage circuit is the selected circuit with the smallest circuit area. Selecting the selected circuit with the smallest circuit area as the storage circuit can effectively reduce the circuit area of ​​the storage circuit, improve the overall performance of the chip, and further improve the market competitiveness of the chip.

[0084] In one embodiment, when the circuit areas of the candidate circuits are the same, the storage circuit can be the candidate circuit with the smallest leakage among the multiple candidate circuits. Selecting the candidate circuit with the smallest circuit area and the smallest leakage as the storage circuit reduces the leakage risk of the storage circuit while ensuring the circuit area of ​​the storage circuit, thereby improving the overall performance of the chip and the market competitiveness of the chip.

[0085] In one embodiment, the storage circuit may also be a circuit to be selected whose absolute value of power circuit area ratio is the smallest among multiple circuits to be selected, wherein the power circuit area ratio is determined by the circuit area and leakage condition of the circuit to be selected.

[0086] For example, the process of determining the power circuit area ratio is as follows: according to the circuit area of ​​the circuit to be selected, determine the area increase or decrease ratio of the circuit to be selected relative to the reference circuit, and according to the leakage situation (leakage value) of the circuit to be selected, determine the leakage increase or decrease ratio of the circuit to be selected relative to the reference circuit, and divide the leakage increase or decrease ratio of the circuit to be selected by the area increase or decrease ratio to obtain the power area ratio of the circuit to be selected. Among them, the reference circuit is the circuit to be selected with the smallest circuit area among multiple circuits to be selected; the area increase or decrease ratio is: (circuit area of ​​the circuit to be selected-circuit area of ​​the reference circuit) / circuit area of ​​the reference circuit. The leakage increase or decrease ratio is: (leakage value of the circuit to be selected-leakage value of the reference circuit) / leakage value of the reference circuit.

[0087] In this embodiment, the circuit area and leakage conditions of each candidate circuit are balanced, and the candidate circuit with the smallest absolute value of the power circuit area ratio among multiple candidate circuits is selected as the storage circuit. This can ensure that the area and leakage conditions of the storage circuit are optimal, improve the performance of the storage circuit, and improve the overall performance of the chip as well as the market competitiveness of the chip.

[0088] In one embodiment, the storage circuit may also be a circuit to be selected whose absolute value of power circuit area ratio is the smallest among multiple circuits to be selected, wherein the power circuit area ratio is determined by the circuit area and circuit power consumption of the circuit to be selected.

[0089] For example, the process of determining the area ratio of the power circuit is as follows: determine the area increase or decrease ratio of the circuit to be selected relative to the reference circuit, and determine the power consumption increase or decrease ratio of the circuit to be selected relative to the reference circuit based on the circuit power consumption of the circuit to be selected, and then divide the power consumption increase or decrease ratio of the circuit to be selected by the area increase or decrease ratio to obtain the power area ratio of the circuit to be selected. Among them, the reference circuit is the circuit to be selected with the smallest circuit area among multiple circuits to be selected; the area increase or decrease ratio is: (circuit area of ​​the circuit to be selected - circuit area of ​​the reference circuit) / circuit area of ​​the reference circuit. The power consumption increase or decrease ratio is: (power consumption value of the circuit to be selected - power consumption value of the reference circuit) / power consumption value of the reference circuit.

[0090] Among them, the power consumption values ​​of the circuit to be selected and the reference circuit can be the dynamic power consumption values ​​of the circuit. The dynamic power consumption of the circuit mainly refers to the power consumption generated when the transistor is in a jump state during the operation of the circuit. This type of power consumption is mainly composed of the dynamic switching power consumption caused by the dynamic switching current and the power consumption generated by the short-circuit current. The static power consumption of the circuit refers to the power consumption generated by the leakage current when the circuit is in a waiting or inactive state. In this embodiment, the dynamic power consumption value of the circuit is used as a measurement indicator, which can effectively measure the power consumption of the storage circuit when it is working, and can select a storage circuit with more appropriate power consumption to ensure that the performance of the storage circuit is better.

[0091] In other embodiments, the power consumption values ​​of the circuit to be selected and the reference circuit may also be the total power consumption value of the circuit, wherein the total power consumption value is a dynamic power consumption value and a static power consumption value. Using the total power consumption value of the circuit as a measurement indicator further increases the accuracy of the power consumption calculation, thereby improving the accuracy of the selection of the storage circuit and ensuring the optimal performance of the storage circuit. In addition, the power consumption values ​​of the circuit to be selected and the reference circuit may also be the static power consumption value of the circuit.

[0092] In this embodiment, the circuit area and circuit power consumption of each candidate circuit are balanced, and the candidate circuit with the smallest absolute value of the power circuit area ratio among multiple candidate circuits is selected as the storage circuit. This can ensure that the area and power consumption of the storage circuit are optimal, improve the performance of the storage circuit, and improve the overall performance of the chip as well as the market competitiveness of the chip.

[0093] In one embodiment, if Fig. 9 As shown, a data storage method is provided, which is applied in Figures 1 to 6 The data storage structure is taken as an example to illustrate, including the following steps:

[0094] S10: The mask circuit performs mask processing on the data to be written to obtain the data to be encoded.

[0095] When storing data, the mask circuit receives the data to be written sent by the chip controller or an external device, and performs mask processing on the data to be written, obtains the encoded data to be written, and then inputs it into the verification coding circuit.

[0096] S20: The check coding circuit splits the data to be coded into N sub-data by byte, and performs check coding on the N sub-data to obtain check coding data corresponding to the N sub-data respectively.

[0097] The check coding circuit splits the data to be encoded into N sub-data by byte, and performs check coding on the N sub-data to obtain check coding data corresponding to the N sub-data, that is, to obtain N groups of check coding data. Among them, any group of check coding data includes sub-data and check codes of sub-data, and N is an integer greater than or equal to 2. For example, each byte of the data to be encoded can be split into one sub-data, that is, N is the number of bytes in the data to be encoded, which is convenient for subsequent separate encoding and storage processing and simplifies storage logic. In other embodiments, 2-3 bytes can also be split into one sub-data to reduce the number of sub-data.

[0098] S30: The check code circuit stores N groups of check code data in M ​​storage arrays.

[0099] The check code circuit stores N groups of check code data in M ​​storage arrays to complete data storage, wherein M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check code data.

[0100] In this embodiment, the original input data is masked by a mask circuit, and then the check coding circuit splits and encodes the masked data by bytes. The check coding function and the write mask function can be simultaneously implemented in a data storage structure without the need for manual data splitting for verification or mask processing. On the basis of ensuring data integrity and security, the data storage logic is simplified and the efficiency of data storage is improved.

[0101] In one embodiment, the check coding circuit includes a splitting device and N check encoders. In step S20, the check coding circuit splits the data to be encoded into N sub-data by byte, and performs check coding on the N sub-data to obtain check coding data corresponding to the N sub-data, which specifically includes the following steps:

[0102] S21: The splitting device splits the data to be encoded into N sub-data by byte, and inputs the N sub-data into N verification encoders one by one.

[0103] The check coding circuit includes a splitting device and N check encoders; the splitting device is connected to the output of the mask circuit and the input of the N check encoders, and the output of the N check encoders is connected to the storage circuit. After receiving the data to be encoded inputted by the mask circuit, the splitting device splits the data to be encoded into N sub-data by byte, and inputs the N sub-data to the N check encoders one by one. One check encoder inputs one sub-data, and N is the number of bytes in the data to be encoded.

[0104] S22: N check encoders respectively encode the sub-data input by the splitting device to obtain N groups of check code data.

[0105] After receiving the sub-data input by the splitting device, each of the N check encoders encodes the sub-data input by the splitting device and outputs the check coded data corresponding to the sub-data, thereby obtaining N groups of check coded data.

[0106] In this embodiment, the check coding circuit includes a splitting device and N check encoders. The splitting device splits the data to be encoded into N sub-data by bytes, and the N sub-data are input into the N check encoders one by one. One check encoder inputs one sub-data, and the N check encoders encode the sub-data input by the splitting device respectively to obtain N groups of check coding data. Compared with the method of encoding N sub-data with one or more check encoders whose number is less than N, it is simpler and there is no need to control at least one check encoder to perform multiple encodings, which simplifies the encoding logic and thereby improves data storage efficiency.

[0107] In one embodiment, M is an integer less than N. In step S30, the check code circuit stores N groups of check code data in M ​​storage arrays, which specifically includes the following steps:

[0108] S31: the check coding circuit determines M data groups according to N groups of check coding data, and stores the M data groups in M ​​storage arrays in a one-to-one correspondence.

[0109] Specifically, the splitting device of the check coding circuit merges N groups of check coding data according to the order of the N sub-data in the data to be encoded to obtain the target storage data; the splitting device of the check coding circuit splits the target storage data according to the bit width of each storage array in the storage circuit to obtain M data groups, and the M data groups are stored in the M storage arrays one by one to ensure that the order of the stored data is correct. Among them, the bit width of the M data groups corresponds to the bit width of the M storage arrays one by one, and the bit width of the M storage arrays is greater than the bit width of the corresponding data group in the M data groups, ensuring that each storage array can completely store the data of each data group.

[0110] In this embodiment, M data groups are determined based on N groups of verification code data, and then the M data groups are stored one-to-one in M ​​storage arrays. A data storage structure that integrates a write mask function, a coding verification function, and a storage array whose number is less than N is used for data storage. The number of storage arrays in the storage circuit is reduced to reduce the circuit area, and the data is divided into a smaller number of data groups for storage during data storage, thereby ensuring that the data storage logic is normal and that the data integrity and security are guaranteed.

[0111] In one embodiment, the data storage structure further includes a check decoding circuit, and the check decoding circuit includes a reading device and N check decoders. After step S30, the method further includes the following steps:

[0112] S40: The reading device reads data from the M storage arrays of the storage circuit to obtain N groups of check code data, and inputs the N groups of check code data into N check decoders in a one-to-one correspondence.

[0113] In this embodiment, the check decoding circuit of the data storage structure includes a reading device and N check decoders. The input of the reading device is respectively connected to the M storage arrays, and the output of the reading device is respectively connected to the input of each check decoder.

[0114] When reading data, the reading device reads data from the M storage arrays of the storage circuit to obtain N groups of check code data, and inputs the N groups of check code data to N check decoders one by one. One check decoder inputs one group of check code data.

[0115] Specifically, the reading device reads M data groups from M storage arrays of the storage circuit according to the storage addresses of the pre-recorded M data groups, merges the M data groups in the order of the M storage arrays to obtain target storage data; splits the target storage data according to the order of the N sub-data in the data to be encoded, obtains N groups of verification coding data and respectively inputs N corresponding verification decoders.

[0116] S50: N check decoders are used to respectively decode and check the check coded data input by the reading device to obtain N sub-data.

[0117] N check decoders respectively decode and check the check coded data input by the reading device, output N sub-data and send them to the reading device. The reading device merges the N sub-data according to the order of the N sub-data in the data to be encoded, obtains the target data and outputs it.

[0118] In this embodiment, data is read from M storage arrays of the storage circuit by a reading device to obtain N groups of check code data, and the N groups of check code data are input into N check decoders one by one, and then the N storage arrays are read and decoded by the N check decoders respectively, which is equivalent to using N storage circuits to encode, store and decode each sub-data separately, thereby ensuring data integrity and security, with simple data storage logic and high data reading efficiency.

[0119] In one embodiment, the number and structure of the storage array in the storage circuit are determined by the bit width of the storage circuit and the performance data of the storage circuit. Before using the data storage structure for data storage, the storage circuit needs to be selected to obtain a data storage structure with performance that meets the requirements. The structure of the storage circuit is determined by:

[0120] S01: Determine a target bit width of a storage circuit according to the number of check encoders and the number of check code bits generated by the check encoders.

[0121] Among them, the bit width of the storage circuit needs to be greater than (b+a)*N, where a is the number of bits (bit width) of the check code for the sub-data encoded by the check encoder, b is the number of bits for each sub-data, and N is the number of check encoders. According to the number of check encoders in the check coding circuit and the number of bits of the check code generated by the check encoder, the bit width of the storage circuit is determined to ensure that the storage circuit can completely store N groups of check code data. The storage array splitting method of the data storage structure in this embodiment can flexibly configure the data bit width of the storage array according to different needs, and has high scalability.

[0122] S02: Selecting a structure of a storage circuit according to a target bit width and circuit performance data to determine the number and structure of storage arrays in the storage circuit.

[0123] After determining the target bit width of the storage circuit, the storage circuit is structured according to the target bit width and circuit performance data to determine the number and structure of storage arrays in the storage circuit. The circuit performance data at least includes the circuit area.

[0124] In this embodiment, the target bit width of the storage circuit is determined based on the number of check encoders and the number of check code bits generated by the check encoder, and the structure of the storage circuit is selected based on the target bit width and circuit performance data to determine the number and structure of storage arrays in the storage circuit. The process of determining the structure of the storage circuit is clarified, and a candidate circuit with performance that meets the requirements is determined as the storage circuit from multiple candidate circuits with multiple bit widths that meet the requirements, thereby determining the number and structure of storage arrays in the storage circuit.

[0125] In one embodiment, as in step S02, the structure of the storage circuit is selected according to the target bit width and circuit performance data to determine the number and structure of the storage array in the storage circuit, which specifically includes the following steps:

[0126] S021: Taking the target bit width of the storage circuit as a constraint, determining a plurality of circuits to be selected according to different types of storage array splitting methods.

[0127] In this embodiment, the target bit width of the storage circuit is used as a constraint, and multiple circuits to be selected are determined according to different types of storage array splitting methods. The multiple circuits to be selected have different storage array combination methods, that is, the number or structure of storage arrays in the multiple circuits to be selected is different.

[0128] The splitting method of the storage circuit may include a single splitting method and an equal splitting method. In the single splitting method, the circuit to be selected includes a storage array, and the bit width of the storage array is the bit width of the storage circuit. The equal splitting method is to equally split the storage space of the circuit to be selected into multiple storage arrays with the same structure, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected.

[0129] In other embodiments, different types of memory array splitting methods may include a single splitting method, an equal splitting method, and an unequal splitting method. In the unequal splitting method, the types and logical sizes of the memory arrays of the circuit to be selected are different, that is, memory arrays of different types and different logical sizes are mixed together to obtain a plurality of circuits to be selected, and the bit width of each memory array is the bit width of the memory circuit divided by the number of memory arrays in the circuit to be selected.

[0130] S022: Performing performance tests on multiple circuits to be selected to obtain circuit performance test data of each circuit to be selected, and determining, based on the circuit performance test data of each circuit to be selected, that a circuit to be selected that meets performance requirements among the multiple circuits to be selected is a storage circuit.

[0131] After obtaining a plurality of circuits to be selected, a performance test is performed on the plurality of circuits to be selected to obtain circuit performance test data of each circuit to be selected, and based on the circuit performance test data of each circuit to be selected, a circuit to be selected that meets the performance requirements is determined to be a storage circuit among the plurality of circuits to be selected. The circuit performance test data includes at least one of circuit area, leakage condition, and circuit power consumption.

[0132] In this embodiment, the bit width of the storage circuit is constrained, and a plurality of circuits to be selected are determined according to different types of storage array splitting methods, and the number or structure of the storage arrays in the plurality of circuits to be selected is different; then, performance tests are performed on the plurality of circuits to be selected to obtain circuit performance test data of each circuit to be selected, and the circuit performance test data includes at least one of circuit area, leakage condition, and circuit power consumption; finally, based on the circuit performance test data of each circuit to be selected, a circuit to be selected that meets the performance requirements is determined as the storage circuit among the plurality of circuits to be selected, and the process of determining the number and structure of the storage arrays in the storage circuit is clarified, so that a storage circuit that meets the performance requirements can be obtained for subsequent data storage, thereby improving the overall performance of the chip.

[0133] In one embodiment, the circuit performance test data includes circuit area and leakage. In step S022, that is, according to the circuit performance test data of each circuit to be selected, determining that the circuit to be selected that meets the performance requirements is a storage circuit among multiple circuits to be selected, specifically includes the following steps:

[0134] SA221: When the circuit areas of the circuits to be selected are different, the circuit to be selected with the smallest circuit area is used as the target storage circuit;

[0135] SB221: When the circuit areas of the circuits to be selected are the same, the circuit to be selected with the smallest leakage is selected as the target storage circuit according to the leakage conditions of the circuits to be selected.

[0136] In this embodiment, when the circuit areas of each circuit to be selected are different, the circuit to be selected with the smallest circuit area is used as the target storage circuit, which can effectively reduce the circuit area of ​​the storage circuit, improve the overall performance of the chip, and further improve the market competitiveness of the chip; when the circuit areas of each circuit to be selected are the same, according to the leakage conditions of each circuit to be selected, the circuit to be selected with the smallest leakage is used as the target storage circuit, which reduces the leakage risk of the storage circuit while ensuring the circuit area of ​​the storage circuit, thereby improving the overall performance of the chip, and further improving the market competitiveness of the chip.

[0137] In one embodiment, the circuit performance test data includes the circuit area, leakage condition or circuit power consumption. In step S022, that is, according to the circuit performance test data of each circuit to be selected, determining that the circuit to be selected that meets the performance requirements is a storage circuit among multiple circuits to be selected, specifically includes the following steps:

[0138] SB221: Determine the power circuit area ratio of each circuit to be selected based on the circuit area of ​​each circuit to be selected, as well as the leakage condition or circuit power consumption of each circuit to be selected.

[0139] After obtaining the circuit performance test data of each circuit to be selected, the power circuit area ratio of each circuit to be selected is determined according to the circuit area of ​​each circuit to be selected and the leakage condition or circuit power consumption of each circuit to be selected.

[0140] Wherein, when the circuit performance test data includes the circuit area and the leakage condition, the process of determining the power circuit area ratio of each circuit to be selected is as follows: according to the circuit area of ​​the circuit to be selected, determine the area increase or decrease ratio of the circuit to be selected relative to the reference circuit, and according to the leakage condition (leakage value) of the circuit to be selected, determine the leakage increase or decrease ratio of the circuit to be selected relative to the reference circuit, and divide the leakage increase or decrease ratio of the circuit to be selected by the area increase or decrease ratio to obtain the power area ratio of the circuit to be selected. Wherein, the reference circuit is the circuit to be selected with the smallest circuit area among multiple circuits to be selected; the area increase or decrease ratio is: (circuit area of ​​the circuit to be selected-circuit area of ​​the reference circuit) / circuit area of ​​the reference circuit. The leakage increase or decrease ratio is: (leakage value of the circuit to be selected-leakage value of the reference circuit) / leakage value of the reference circuit.

[0141] Wherein, when the circuit performance test data includes the circuit area and the circuit power consumption, the process of determining the power circuit area ratio of each circuit to be selected is as follows: determine the area increase or decrease ratio of the circuit to be selected relative to the reference circuit, and determine the power consumption increase or decrease ratio of the circuit to be selected relative to the reference circuit based on the circuit power consumption of the circuit to be selected, and then divide the power consumption increase or decrease ratio of the circuit to be selected by the area increase or decrease ratio to obtain the power area ratio of the circuit to be selected. Wherein, the area increase or decrease ratio is: (circuit area of ​​the circuit to be selected - circuit area of ​​the reference circuit) / circuit area of ​​the reference circuit. The power consumption increase or decrease ratio is: (power consumption value of the circuit to be selected - power consumption value of the reference circuit) / power consumption value of the reference circuit.

[0142] SB221: Based on the power circuit area ratio of each candidate circuit, the candidate circuit with the smallest absolute value of the power circuit area ratio among the multiple candidate circuits is selected as the storage circuit.

[0143] After determining the power circuit area ratios of each candidate circuit, the candidate circuit with the smallest absolute value of the power circuit area ratio among the multiple candidate circuits is selected as the storage circuit according to the power circuit area ratios of each candidate circuit.

[0144] In this embodiment, the circuit area and leakage condition (or circuit power consumption) of each candidate circuit are balanced, and the candidate circuit with the smallest absolute value of the power circuit area ratio among multiple candidate circuits is selected as the storage circuit. This can ensure that the area and leakage condition (or circuit power consumption) of the storage circuit are optimal, improve the performance of the storage circuit, thereby improving the overall performance of the chip, and further improving the market competitiveness of the chip.

[0145] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0146] It should be noted that, since the information interaction, execution process and other contents between the various devices / units in the above method embodiments are based on the same concept as the data storage structure embodiment of the present application, their specific functions and technical effects can be found in the data storage structure embodiment part and will not be repeated here.

[0147] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned data storage structure embodiment, which will not be repeated here.

[0148] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0149] Those of ordinary skill in the art will appreciate that the devices and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0150] In the embodiments provided in the present application, it should be understood that the disclosed devices / structures and methods can be implemented in other ways. For example, the device / structure embodiments described above are merely schematic. For example, the division of the circuit or device is only a logical function division. There may be other division methods in actual implementation, such as multiple devices or components can be combined or integrated into another circuit, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or structure, which can be electrical, mechanical or other forms.

[0151] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0152] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A data storage structure, characterized in that: It includes a mask circuit, a check code circuit and a storage circuit connected in sequence, wherein the storage circuit includes M storage arrays; The mask circuit is used to perform mask processing on the data to be written to obtain the data to be encoded of the data to be written; The check coding circuit is used to split the data to be encoded into N sub-data by byte, and to perform check coding on the N sub-data to obtain check coding data corresponding to the N sub-data respectively, any group of the check coding data includes the sub-data and the check code of the sub-data, and N is an integer greater than or equal to 2; The M storage arrays are used to store N groups of the check code data, M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check code data.

2. The data storage structure according to claim 1, characterized in that: The verification coding circuit is also used for: Determine M data groups according to N groups of check code data; The M data groups are stored in the M storage arrays in a one-to-one correspondence.

3. The data storage structure according to claim 2, characterized in that: The verification coding circuit is also specifically used for: According to the order of the N sub-data in the data to be encoded, merge the N groups of the verification code data to obtain the target storage data; According to the bit width of each storage array in the storage circuit, the target storage data is split into M data groups, and the bit widths of the M data groups correspond one to one with the bit widths of the M storage arrays.

4. The data storage structure according to claim 1, characterized in that: The data storage structure also includes a reading device and N check decoders connected to the M storage arrays; The reading device is used for reading data from the M storage arrays of the storage circuit to obtain N groups of the check code data, and for inputting the N groups of the check code data into the N check decoders in a one-to-one correspondence; The N check decoders are used to respectively decode and check the check coded data input by the reading device to obtain N sub-data.

5. The data storage structure according to claim 1, characterized in that: The bit width of the storage circuit is determined by the number of check encoders in the check encoding circuit and the number of bits of the check code generated by the check encoder; The number and structure of the memory arrays in the memory circuit are determined by the bit width of the memory circuit and the performance data of the memory circuit.

6. The data storage structure according to claim 5, characterized in that: The storage circuit is a circuit to be selected whose performance meets the requirements among multiple circuits to be selected, different circuits to be selected correspond to different storage array combination methods, the number and / or structure of the storage arrays in different storage array combination methods are different, and different storage array combination methods are determined by splitting the storage circuit according to the bit width of the storage circuit.

7. The data storage structure according to claim 6, characterized in that: When the circuit areas of the circuits to be selected are different, the storage circuit is the circuit to be selected with the smallest circuit area; or, When the circuit areas of the circuits to be selected are the same, the storage circuit is the circuit to be selected with the smallest leakage among the multiple circuits to be selected; or, The storage circuit is the circuit to be selected whose absolute value of the power circuit area ratio is the smallest among the multiple circuits to be selected, and the power circuit area ratio is determined by the circuit area and leakage condition of the circuit to be selected, or by the circuit area and circuit power consumption of the circuit to be selected.

8. The data storage structure according to claim 6, characterized in that: The splitting method of the storage circuit includes a single splitting method and an equal splitting method. In the single splitting method, the circuit to be selected includes one storage array, and the bit width of the storage array is the bit width of the storage circuit. The equal division method is to equally divide the storage space of the circuit to be selected into a plurality of storage arrays with the same structure, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected.

9. The data storage structure according to claim 8, characterized in that: Different types of storage array splitting methods also include unequal splitting methods, in which the types and logical sizes of the storage arrays of the circuit to be selected are different, and the bit width of each storage array is the bit width of the storage circuit divided by the number of storage arrays in the circuit to be selected.

10. The data storage structure according to any one of claims 1 to 9, characterized in that: The check coding circuit comprises a splitting device and N check encoders, the splitting device is connected to the output of the mask circuit and to the input of the N check encoders, and the output of the N check encoders is connected to the storage circuit through the splitting device; The splitting device is used to split the data to be encoded into N sub-data by byte, and input the N sub-data into the N verification encoders in a one-to-one correspondence; The N check encoders are used to encode the sub-data input by the splitting device respectively to obtain N groups of the check code data.

11. A data storage method, characterized in that: Applied to the data storage structure according to any one of claims 1 to 10, the method comprises: The mask circuit performs mask processing on the data to be written to obtain the data to be encoded of the data to be written; The check coding circuit splits the data to be encoded into N sub-data by byte, and performs check coding on the N sub-data to obtain check coding data corresponding to the N sub-data respectively, any group of the check coding data includes the sub-data and the check code of the sub-data, and N is an integer greater than or equal to 2; The check coding circuit stores N groups of the check coding data in M ​​storage arrays, where M is an integer greater than or equal to 1 and less than or equal to N, and the bit width of the storage array is greater than or equal to the bit width of the check coding data.

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