Power failure test circuit and system
By designing a power-down test circuit for multiple bus standard interfaces and independent output voltage control circuits, the problem of insufficient testing flexibility in the prior art is solved, and the flexible testing requirements for multi-interface devices are realized.
Patent Information
- Application Number
- CN202411332643.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-02-11
AI Technical Summary
Existing power-down testing devices are difficult to meet the diverse testing needs, especially in the testing of multi-interface equipment, and the testing flexibility is insufficient.
A power-down test circuit and system is designed, using multiple bus standard interfaces, equipped with independent output voltage control circuits and main control chips, which can be controlled according to the target power-up time and power-down time information, and supports multi-interface equipment test.
By setting up interfaces with multiple bus standards, different types of interfaces can be tested at the same time, meeting the testing needs of multi-interface devices, with high testing flexibility and adapting to different test scenarios.
Smart Images
Figure CN119415342A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of hardware testing, and in particular, relates to a power-off testing circuit and system. Background Art
[0002] With the continuous development of computer hardware, there are more and more interfaces on computer devices. In order to ensure the stability and reliability of the device under different power supply states, a device that can simulate the power failure of different interface devices is needed. The existing power failure test device is difficult to meet the diverse test needs. Summary of the invention
[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a power-off test circuit and system, which has interfaces of multiple bus standards to meet the test requirements of multi-interface devices, and has high test flexibility to meet the requirements of different test scenarios.
[0004] In a first aspect, the present application provides a power-off test circuit, comprising:
[0005] Multiple interfaces with multiple bus standards;
[0006] A plurality of output voltage control circuits are configured to provide a plurality of output voltages, each output voltage control circuit being electrically connected to each interface correspondingly;
[0007] A power supply circuit, electrically connected to each output voltage control circuit and configured to convert an input power supply into a supply voltage required by each output voltage control circuit;
[0008] The main control chip is electrically connected to each output voltage control circuit and is configured to control each output voltage control circuit to power on or off according to target power-on time information and target power-off time information.
[0009] According to one embodiment of the present application, the power-off test circuit further includes:
[0010] The serial communication circuit is connected to the main control chip and is used to connect to the host computer and transmit the power-off test configuration information sent by the host computer to the main control chip. The power-off test configuration information includes target power-on time information and target power-off time information.
[0011] According to one embodiment of the present application, the power-off test configuration information also includes the total experiment time, the target power-on time information includes the power-on duration corresponding to each output voltage control circuit, and the target power-off time information includes the power-off duration corresponding to each output voltage control circuit.
[0012] According to an embodiment of the present application, the main control chip is further configured to control the output voltage control circuit to power on when the power-off duration of the output voltage control circuit ends.
[0013] According to one embodiment of the present application, the power-off test circuit further includes:
[0014] The indication circuit is electrically connected to the main control chip, and the indication circuit is configured to indicate the working state of the output voltage control circuit and / or the power supply circuit, and the working state includes a power-on state and a power-off state.
[0015] According to one embodiment of the present application, the indication circuit includes:
[0016] A plurality of light emitting diode units, each light emitting diode unit comprising a resistor and a light emitting diode connected in series;
[0017] Among them, one end of the resistor in at least one light-emitting diode unit is electrically connected to the power input node of the power supply circuit, and the cathode of the light-emitting diode is electrically connected to the ground node; and / or one end of the resistor in multiple light-emitting diode units is electrically connected to the reference voltage node, and the cathode of the light-emitting diode is electrically connected to the main control chip.
[0018] According to one embodiment of the present application, the power-off test circuit further includes:
[0019] The overcurrent detection circuit is electrically connected to the power circuit and the main control chip respectively, and is configured to feed back an overcurrent signal to the main control chip when detecting that the power circuit is in an overcurrent state;
[0020] The main control chip is also configured to control each output voltage control circuit to cut off the output when receiving an overcurrent signal.
[0021] According to one embodiment of the present application, an output voltage control circuit includes:
[0022] A P-type MOS tube, a source of the P-type MOS tube is electrically connected to the interface, and a drain of the P-type MOS tube is electrically connected to an output end of the power supply circuit;
[0023] The transistor has a collector electrically connected to the gate of the P-type MOS tube, an emitter electrically connected to the ground node, and a base electrically connected to the main control chip.
[0024] According to one embodiment of the present application, the accuracy of the clock unit in the main control chip is at the millisecond level.
[0025] According to one embodiment of the present application, the multiple interfaces include a PCI-E interface, a USB interface and an M.2 interface.
[0026] In the second aspect, the present application provides a power-off test system, including a test device, a host computer and a power supply. The test device includes the power-off test circuit according to the above-mentioned, the host computer is communicatively connected to the main control chip in the power-off test circuit, and the power supply is electrically connected to the power supply circuit in the power-off test circuit.
[0027] According to the power-off test circuit and system of the present application, different types of interfaces can be tested simultaneously by setting interfaces of multiple bus standards to meet the testing requirements of multi-interface devices. At the same time, each interface is controlled by an independent control circuit, with high testing flexibility to meet the needs of different testing scenarios.
[0028] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0030] Figure 1 It is one of the structural schematic diagrams of the power-off test circuit provided in the embodiment of the present application;
[0031] Figure 2 is a circuit diagram of an output voltage control circuit of a PCI-E interface provided in an embodiment of the present application;
[0032] Figure 3 is a circuit diagram of an output voltage control circuit of a USB interface provided in an embodiment of the present application;
[0033] Figure 4 is a circuit diagram of an output voltage control circuit of an M.2 interface provided in an embodiment of the present application;
[0034] Figure 5 This is the second structural schematic diagram of the power-off test circuit provided in the embodiment of the present application;
[0035] Figure 6 It is a configuration interface diagram of the host computer provided in the embodiment of the present application;
[0036] Figure 7 is a circuit structure diagram of a serial communication circuit provided in an embodiment of the present application;
[0037] Figure 8 is a circuit structure diagram of an indication circuit provided in an embodiment of the present application;
[0038] Fig. 9 is a circuit structure diagram of an overcurrent detection circuit provided in an embodiment of the present application;
[0039] Fig.10 is a circuit structure diagram of the main control chip provided in an embodiment of the present application;
[0040] Fig.11 is a circuit structure diagram of a power supply circuit provided in an embodiment of the present application;
[0041] Fig.12 It is a circuit structure diagram of the external power supply circuit provided in an embodiment of the present application.
[0042] Reference numerals:
[0043] Interface 10, output voltage control circuit 20, power supply circuit 30, main control chip 40, serial communication circuit 50, host computer 60, indication circuit 70, overcurrent detection circuit 80, first to third MOS tubes M1~M3, first to third triodes Q1~Q3, first to fifteenth resistors R1~R15, first to fourth light-emitting diodes D1~D4. DETAILED DESCRIPTION
[0044] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0045] In the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "coupled to" or "connected to" another element or an element / circuit is said to be "coupled to" or "connected to" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0046] In the description, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the numerical descriptors used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0047] In addition, descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0048] Reference Figure 1 , Figure 1 A structural block diagram of a power-off test circuit is shown, and an embodiment of the present application proposes a power-off test circuit. In this embodiment, the power-off test circuit includes multiple interfaces 10, multiple output voltage control circuits 20, a power supply circuit 30 and a main control chip 40, and the multiple interfaces 10 have multiple bus standards; the multiple output voltage control circuits 20 are configured to provide multiple output voltages, and each output voltage control circuit 20 is electrically connected to each interface 10; the power supply circuit 30 is electrically connected to each output voltage control circuit 20, and is configured to convert the connected power supply into the power supply voltage required by each output voltage control circuit 20; the main control chip 40 is electrically connected to each output voltage control circuit 20, and is configured to control each output voltage control circuit 20 to power on or off according to the target power-on time information and the target power-off time information.
[0049] The power-off test circuit can be used to perform power-off tests on target devices. Power-off testing is a test method used to evaluate the performance and recovery capabilities of a device or system when the power supply is suddenly interrupted or the voltage is abnormally reduced. This test is essential to ensure the data security, stability and reliability of the device. The target device can be a personal terminal, computer and other devices.
[0050] The interface 10 is used to connect to the interface to be tested on the target device. Under the control of the output voltage control circuit 20, the interface 10 can transmit power to the interface to be tested, interrupt power or reduce power. Usually, the interface to be tested on the target device has multiple bus standards. The power-off test circuit is provided with interfaces 10 of multiple bus standards to implement the test of different interfaces to be tested.
[0051] As an example, the multiple interfaces 10 may include a PCI-E (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus) interface, a USB (Universal Serial Bus, a universal serial bus) interface, and an M.2 (Next Generation Form Factor, a next-generation size specification) interface. Of course, the interface 10 may also adopt other types of bus standards, which are not limited in this embodiment.
[0052] The number of output voltage control circuits 20 is the same as the number of interfaces 10, and each interface 10 is controlled by a separate output voltage control circuit 20. The main control chip 40 realizes power-on and power-off of the interface 10 by adjusting the output voltage control circuit 20. Among them, power-on refers to providing power to the interface 10, and power-off refers to cutting off the power supply of the interface 10, or reducing the power supply voltage of the interface 10. The output voltage control circuit 20 may include a switch unit to control the on and off of the power supply circuit between the power supply circuit 30 and the interface 10. Alternatively, the output voltage control circuit 20 may also include a step-down circuit to reduce the voltage provided to the interface 10.
[0053] The main control chip 40 can obtain the target power-on time information and the target power-off time information from the hardware interface or the software interface, and generate corresponding control signals according to the target power-on time information and the target power-off time information to control each output voltage control circuit 20 .
[0054] In this embodiment, each output voltage control circuit 20 is independently controlled, that is, the main control chip 40 can control one or more output voltage control circuits 20 to supply power to the interface 10 , or control one or more output voltage control circuits 20 to stop supplying power to the interface 10 .
[0055] As an example, the power-off test circuit includes interface A, interface B, and interface C. When the test starts, the control chip 40 can power on interface A and interface B, and then power on interface C after a period of time; then, interface A can be controlled to power off, and then interface B and interface C can be controlled to power off.
[0056] As another example, each interface 10 of the power-off test circuit may be powered on and off periodically to implement the test, wherein the power-on and power-off time periods corresponding to each interface 10 may be different or the same.
[0057] In some embodiments, the accuracy of the clock unit in the main control chip 40 is at the millisecond level.
[0058] The accuracy of the control signal transmitted by the main control chip 40 to the output voltage control circuit 20 can reach the millisecond level, that is, the duration or interruption of the control signal is at least 1ms. For example, the main control chip 40 can output the control signal and maintain it for 13ms, and then interrupt the output of the control signal at the 14th ms.
[0059] According to the power-off test circuit of the present application, different types of interfaces can be tested simultaneously by setting interfaces of multiple bus standards to meet the testing requirements of multi-interface devices. At the same time, each interface is controlled by an independent control circuit, with high testing flexibility to meet the needs of different testing scenarios.
[0060] Reference Figures 2 to 4 , Figure 2 A circuit diagram of an output voltage control circuit of a PCI-E interface is shown. Figure 3 A circuit diagram of an output voltage control circuit of a USB interface is shown. Figure 4 A circuit diagram of an output voltage control circuit of an M.2 interface is shown.
[0061] As an example, the output voltage control circuit 20 may include a P-type MOS tube and a transistor, the source of the P-type MOS tube is electrically connected to the interface, the drain of the P-type MOS tube is electrically connected to the output end of the power supply circuit; the collector of the transistor is electrically connected to the gate of the P-type MOS tube, the emitter of the transistor is electrically connected to the ground node, and the base of the transistor is electrically connected to the main control chip.
[0062] like Figure 2 As shown, the interface 10 is a PCI-E interface, the source of the first MOS tube M1 is electrically connected to the second end of the PCI-E interface, the drain of the first MOS tube M1 is electrically connected to the voltage node of 12V, the drain of the first MOS tube M1 is electrically connected to the gate through the first resistor R1, and the voltage node is connected to the power supply from the power supply circuit 30. The gate of the first MOS tube M1 is electrically connected to the collector of the first triode Q1, the base of the first triode Q1 is ventilated through the fourth resistor R4 and is electrically connected to the main control chip 40 to access the control signal CTRL_12V, the end of the fourth resistor R4 away from the base of the first triode Q1 is electrically connected to the emitter of the first triode Q1 through the seventh resistor R7, and the emitter of the first triode Q1 and the first end of the PCI-E interface are electrically connected to the ground node.
[0063] like Figure 3As shown, the interface 10 is a USB interface, the source of the second MOS tube M2 is electrically connected to the second end of the USB interface, the drain of the second MOS tube M2 is electrically connected to the voltage node of 5V, the drain of the second MOS tube M2 is electrically connected to the gate through the second resistor R2, and the voltage node is connected to the power supply from the power supply circuit 30. The gate of the second MOS tube M2 is electrically connected to the collector of the second triode Q2, the base of the second triode Q2 is ventilated through the fifth resistor R5 and is electrically connected to the main control chip 40 to access the control signal CTRL_5V, the end of the fifth resistor R5 away from the base of the second triode Q2 is electrically connected to the emitter of the second triode Q2 through the eighth resistor R8, and the emitter of the second triode Q2 and the first end of the USB interface are electrically connected to the ground node.
[0064] like Figure 4 As shown, the interface 10 is an M.2 interface, the source of the third MOS tube M3 is electrically connected to the second end of the M.2 interface, the drain of the third MOS tube M3 is electrically connected to the voltage node of 3.3V, the drain of the third MOS tube M3 is electrically connected to the gate through the third resistor R3, and the voltage node is connected to the power supply from the power supply circuit 30. The gate of the third MOS tube M3 is electrically connected to the collector of the third triode Q3, the base of the third triode Q3 is ventilated through the sixth resistor R6 and is electrically connected to the main control chip 40 to access the control signal CTRL_3.3V, the end of the sixth resistor R6 away from the base of the third triode Q3 is electrically connected to the emitter of the third triode Q3 through the ninth resistor R9, and the emitter of the third triode Q3 and the first end of the M.2 interface are electrically connected to the ground node.
[0065] In the above example, when the main control chip 40 does not output a control signal, the transistor is in an off state, the gate voltage of the P-type MOS tube is pulled up by the voltage of the voltage node, the P-type MOS tube is turned on, and the power of the voltage node is transmitted to the interface 10 through the P-type MOS tube. When the main control chip 40 outputs a control signal, the transistor is in an on state, the gate voltage of the P-type MOS tube is pulled down by the ground node, the P-type MOS tube is turned off, and no power is input to the interface 10, thereby realizing power-on and power-off control.
[0066] Reference Figure 5 , Figure 5 A block diagram of a power-off test circuit is shown. In some embodiments, the power-off test circuit further includes a serial communication circuit 50, which is connected to the main control chip 40, and is used to connect to the host computer 60 and transmit the power-off test configuration information sent by the host computer 60 to the main control chip 40, and the power-off test configuration information includes target power-on time information and target power-off time information.
[0067] The host computer 60 may be a computer device with data processing, communication and other functions, such as a computer or a mobile phone, etc. The host computer 60 may allow the tester to configure corresponding target power-on time information and target power-off time information, and generate power-off test configuration information according to the information configured by the tester.
[0068] As an example, the power-off test configuration information also includes the total experiment time, the target power-on time information includes the power-on duration corresponding to each output voltage control circuit, and the target power-off time information includes the power-off duration corresponding to each output voltage control circuit.
[0069] Reference Figure 6 , Figure 6 A configuration interface of a host computer 60 is shown. Taking the aforementioned three interfaces 10 as an example, the user can perform power-off test control, power-on control and power-off control on the host computer 60. Among them, in the power-off test control, the outputs of 12V, 5V and 3.3V can be configured separately. The experimental time refers to the total test time of the corresponding output, and the power-on duration and power-off duration refer to the duration of the corresponding output in each power-on or power-off stage. Through the corresponding time setting, the corresponding output can be continuously powered on and off during the experimental time. In the power-on control, the corresponding output can be directly controlled to remain in the power-on state. In the power-off control, the corresponding output can be directly controlled to remain in the power-off state.
[0070] In some embodiments, the main control chip 40 is further configured to control the output voltage control circuit 20 to power on when the power-off duration of the output voltage control circuit 20 ends.
[0071] In the above example, during the experimental time, after the main control chip 40 controls the output voltage control circuit 20 to power off, it can immediately control the output voltage control circuit 20 to power on again, so that the target device can resume working state. Or after the experimental time is over, if the last state of the output voltage control circuit 20 is the power-off state, the output voltage control circuit 20 is controlled to power on again immediately.
[0072] In other embodiments, after the main control chip 40 controls the output voltage control circuit 20 to power off, it can control the output voltage control circuit 20 to power on again after a target delay, so that the target device resumes working state. Among them, the target delay can be set according to demand, and this embodiment does not limit this.
[0073] Reference Figure 7 , Figure 7The circuit structure of a serial communication circuit 50 is shown. As an example, the serial communication circuit 50 can communicate using the RS232 interface standard, and mainly includes a communication chip and a connector. The connector is used to connect to the host computer 60, and the ROUT2 and DIN2 ports of the communication chip are respectively connected to the tenth resistor R10 and the eleventh resistor R11, and are both connected to the RXD and TXD ports of the main control chip 40.
[0074] In some embodiments, the power-off test circuit also includes an indication circuit 70, which is electrically connected to the main control chip 40. The indication circuit 70 is configured to indicate the working status of the output voltage control circuit 20 and / or the power supply circuit 30, and the working status includes a power-on state and a power-off state.
[0075] The indicator circuit 70 is used to present the working status of the output voltage control circuit 20 and / or the power circuit 30, so that the tester can understand the actual working status of the output voltage control circuit 20 and / or the power circuit 30. The indicator circuit 70 can be displayed in the form of text or images.
[0076] In some embodiments, the indicator circuit 70 may use a light-emitting diode to display the actual working conditions of each circuit. The indicator circuit 70 includes a plurality of light-emitting diode units, and the light-emitting diode unit includes a resistor and a light-emitting diode connected in series; wherein one end of the resistor in at least one light-emitting diode unit is electrically connected to the power input node of the power circuit, and the cathode of the light-emitting diode is electrically connected to the ground node; and / or one end of the resistor in the plurality of light-emitting diode units is electrically connected to the reference voltage node, and the cathode of the light-emitting diode is electrically connected to the main control chip 40.
[0077] As an example, see Figure 8 , Figure 8 The circuit structure of an indicating circuit 70 is shown. One end of the twelfth resistor R12 is electrically connected to the voltage node, the other end of the twelfth resistor R12 is electrically connected to the anode of the first light-emitting diode D1, and the cathode of the first light-emitting diode D1 is electrically connected to the ground node. When there is power at the voltage node, the first light-emitting diode D1 will emit light. Thus, the light-emitting diode unit can directly display whether the voltage is connected or not. For example, the 12V voltage node can be the input end of the power supply circuit 30. When the first light-emitting diode D1 emits light, it indicates that the power supply circuit 30 starts to work. Of course, the light-emitting diode unit can also be electrically connected to the output end of each output voltage control circuit 20. When each output voltage control circuit 20 outputs a voltage, the first light-emitting diode D1 emits light.
[0078] A section of the thirteenth resistor R13, the fourteenth resistor R14 and the fifteenth resistor R15 are all electrically connected to the voltage node, the other end of the thirteenth resistor R13 is electrically connected to the anode of the second light-emitting diode D2, the other end of the fourteenth resistor R14 is electrically connected to the anode of the third light-emitting diode D3, the other end of the fifteenth resistor R15 is electrically connected to the anode of the fourth light-emitting diode D4, and the cathodes of the second light-emitting diode D2, the third light-emitting diode D3 and the fourth light-emitting diode D4 are all electrically connected to the main control chip 40. The light emission of the second light-emitting diode D2, the third light-emitting diode D3 and the fourth light-emitting diode D4 is controlled by the main control chip 40. When the main control chip 40 controls the corresponding circuit action, when the cathode voltage of the light-emitting diode is pulled off, the corresponding light-emitting diode emits light. For example, when the main control chip 40 controls the output voltage control circuit 20 to output a 12V voltage to the interface 10, the cathode voltage of the second light-emitting diode D2 is controlled to be a low voltage, and the second light-emitting diode D2 emits light to indicate that the output voltage control circuit 20 is outputting 12V to the interface 10.
[0079] In some embodiments, the power-off test circuit also includes an overcurrent detection circuit 80, which is electrically connected to the power supply circuit 30 and the main control chip 40, respectively, and is configured to feedback an overcurrent signal to the main control chip 40 when it is detected that the power supply circuit 30 is in an overcurrent state; the main control chip 40 is also configured to control each output voltage control circuit 20 to cut off the output when receiving the overcurrent signal.
[0080] The overcurrent detection circuit 80 can detect the instantaneous current value of the power supply connected to the power supply circuit 30, and when the instantaneous current value exceeds the threshold, it determines that the power supply circuit 30 is in an overcurrent state and generates an overcurrent signal. The main control chip 40 cuts off the output of each output voltage control circuit 20 to avoid transmitting excessive current to the target device and protect the safety of the target device.
[0081] In other embodiments, when receiving an overcurrent signal, the main control chip 40 may also switch the connection loop between the power supply circuit 30 and the external power supply to protect the safety of the power-off test circuit.
[0082] Reference Fig. 9 , Fig. 9 The circuit structure of an overcurrent detection circuit 80 is shown. The overcurrent detection circuit 80 uses an overcurrent detection chip to detect the current. Taking 12V input as an example, the detection ports IP+ and IP- of the overcurrent detection chip are electrically connected to the detection node of the 12V power supply. The VOUT port of the overcurrent detection chip is used to feed back an overcurrent signal to the main control chip 40.
[0083] Reference Fig.10 , Fig.10A main control chip 40 is shown. As an example, the RXD port and the TXD port of the main control chip 40 can be connected to Figure 7 The CTRL ports of the main control chip 40 are electrically connected to the bases of the transistors in the output voltage control circuit 20. The VOL_DET ports of the main control chip 40 are electrically connected to the bases of the transistors in the output voltage control circuit 20. Fig. 9 The over-current detection chip in is electrically connected.
[0084] Reference Fig.11 , Fig.11 The circuit structure of a power supply circuit 30 is shown. As an example, the power supply circuit 30 may include multiple switching power supply chips. Taking the access to a 12V power supply as an example, the input end of the switching power supply chip is electrically connected to the 12V voltage node, and the output end of the switching power supply chip provides a 5V voltage or a 3.3V voltage. For the output voltage control circuit 20 that needs to be accessed to 12V, it can be directly connected to the 12V electrical connection.
[0085] Reference Fig.12 , Fig.12 Another circuit structure of an external power supply circuit is shown. As an example, the terminal in the circuit is used to directly contact the external power supply to access the power supply. 12V_IN is an external voltage access node of the power-off test circuit, which can be electrically connected to the aforementioned switching power supply chip, or other nodes that require 12V input.
[0086] An embodiment of the present application further provides a power failure test system, including a test device, a host computer 60 and a power supply, wherein the test device includes the power failure test circuit according to the above, the host computer 60 is communicatively connected with the main control chip 40 in the power failure test circuit, and the power supply is electrically connected with the power supply circuit 30 in the power failure test circuit. The circuit structure and principle of the power failure test circuit can refer to the above embodiments and have corresponding technical effects.
[0087] According to the power-off test system of the present application, different types of interfaces can be tested simultaneously by setting interfaces of multiple bus standards to meet the testing requirements of multi-interface devices. At the same time, each interface is controlled by an independent control circuit, with high testing flexibility to meet the needs of different testing scenarios.
[0088] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A power-off test circuit, characterized in that: include: Multiple interfaces with multiple bus standards; A plurality of output voltage control circuits, configured to provide a plurality of output voltages, each of the output voltage control circuits being electrically connected to each of the interfaces correspondingly; A power supply circuit, electrically connected to each of the output voltage control circuits, and configured to convert an input power supply into a supply voltage required by each of the output voltage control circuits; The main control chip is electrically connected to each of the output voltage control circuits and is configured to control each of the output voltage control circuits to power on or off according to target power-on time information and target power-off time information.
2. The power-off test circuit according to claim 1, characterized in that: The power-off test circuit further includes: The serial communication circuit is connected to the main control chip and is used to connect to a host computer and transmit the power-off test configuration information sent by the host computer to the main control chip, wherein the power-off test configuration information includes the target power-on time information and the target power-off time information.
3. The power-off test circuit according to claim 2, characterized in that: The power-off test configuration information also includes the total experiment time, the target power-on time information includes the power-on duration corresponding to each of the output voltage control circuits, and the target power-off time information includes the power-off duration corresponding to each of the output voltage control circuits.
4. The power-off test circuit according to claim 3, characterized in that: The main control chip is further configured to control the output voltage control circuit to power on when the power-off duration of the output voltage control circuit ends.
5. The power-off test circuit according to any one of claims 1 to 4, characterized in that: The power-off test circuit further includes: An indication circuit is electrically connected to the main control chip, and the indication circuit is configured to indicate the working state of the output voltage control circuit and / or the power supply circuit, and the working state includes a power-on state and a power-off state.
6. The power-off test circuit according to claim 5, characterized in that: The indicating circuit comprises: A plurality of light emitting diode units, each light emitting diode unit comprising a resistor and a light emitting diode connected in series; Among them, one end of the resistor in at least one of the light-emitting diode units is electrically connected to the power input node of the power supply circuit, and the cathode of the light-emitting diode is electrically connected to the ground node; and / or one end of the resistor in multiple light-emitting diode units is electrically connected to the reference voltage node, and the cathode of the light-emitting diode is electrically connected to the main control chip.
7. The power-off test circuit according to any one of claims 1 to 4, characterized in that: The power-off test circuit further includes: an overcurrent detection circuit, electrically connected to the power supply circuit and the main control chip respectively, and configured to feed back an overcurrent signal to the main control chip when detecting that the power supply circuit is in an overcurrent state; The main control chip is also configured to control each of the output voltage control circuits to cut off output when receiving the overcurrent signal.
8. The power-off test circuit according to any one of claims 1 to 4, characterized in that: The output voltage control circuit comprises: A P-type MOS tube, wherein the source of the P-type MOS tube is electrically connected to the interface, and the drain of the P-type MOS tube is electrically connected to the output end of the power supply circuit; A transistor, wherein the collector of the transistor is electrically connected to the gate of the P-type MOS transistor, the emitter of the transistor is electrically connected to the ground node, and the base of the transistor is electrically connected to the main control chip.
9. The power-off test circuit according to any one of claims 1 to 4, characterized in that: The accuracy of the clock unit in the main control chip is at the millisecond level.
10. The power-off test circuit according to any one of claims 1 to 4, characterized in that: The multiple interfaces include a PCI-E interface, a USB interface and an M.2 interface.
11. A power failure test system, characterized in that: The invention comprises a test device, a host computer and a power supply, wherein the test device comprises a power-off test circuit according to any one of claims 1 to 10, the host computer is communicatively connected with a main control chip in the power-off test circuit, and the power supply is electrically connected with a power supply circuit in the power-off test circuit.