Packet bus interconnection architecture of SoC system

Abstract

The invention belongs to the field of chip design, and provides a packet bus interconnection architecture of an SoC system, which comprises a system bus matrix SYSBUSMatrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, the CBM, the HPBM, the RBM and the SPBM are all connected with the SYSBUSMatrix through a bus bridge; the embedded processor is mounted on the CBM, and meanwhile, the CBM is connected with the RMB; a high-speed peripheral is mounted on the HPBM, and meanwhile, the HPBM is connected with the RMB; a random access memory (RAM) is mounted on the RBM, and meanwhile, the RBM is connected with the CBM and the HPBM; the SPBM is connected with a plurality of paths of AHB buses through an AXI-AHB bridge, the SPBM is connected with a plurality of paths of APB buses through an AXI-APB bridge, meanwhile, the SPBM is connected with SYSBUSMatrix, and a plurality of paths of low-speed peripherals are mounted on the AHB buses or the APB buses. According to the method, bus transmission among modules such as a processor, a high-speed peripheral and a storage can be balanced, bus competition among high-speed interfaces is effectively reduced, data transmission efficiency is improved, chip rear-end implementation is simplified, and therefore the performance of the whole SOC is optimized.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a packet bus interconnection architecture of a SoC system. Background Art

[0002] With the development of semiconductor technology, the integration level on a single chip has also increased significantly. As a result, SoC (System on Chip) chips have also developed iteratively. They currently dominate the field of terminal chips that are sensitive to performance and power consumption, and are also the development direction of integrated circuits. In order to meet the ever-changing application needs, the number and types of processors, memories, and peripherals integrated in a single SoC chip are gradually increasing. The increase in the number of integrated IP cores will inevitably bring about a key problem, that is, how to ensure that so many IP cores can ensure the rationalization of the internal transmission bandwidth of the entire SoC system without sacrificing performance. Among them, the SoC system bus interconnection architecture has become the key to directly affecting the performance and transmission efficiency of SoC chips. Choosing a reasonable and efficient bus structure has become one of the important factors in designing high-speed SoC chips.

[0003] In the prior art, the SOC system bus architecture can be divided into ring connection, mesh connection and matrix connection, etc. Most of them are based on the system bus matrix to achieve connection, such as Figure 1 As shown in the figure, the processor, memory, peripherals and other modules are directly mounted on the system bus matrix, and all modules and memories communicate with each other through the system bus. The system bus carries too many host operations, and it is difficult to meet high requirements in terms of bus arbitration strategy and timing convergence, which affects the transmission efficiency of the bus itself, resulting in low efficiency and performance of the SoC system.

[0004] The conventional SoC chip architecture mentioned in the prior art has two main disadvantages: first, multiple processors, memories, and high-speed peripherals are mounted on a main bus matrix. The concentration of the number of buses will lead to difficulties in back-end wiring, and the bus frequency is not easy to reach the front-end design frequency; second, multiple master devices access the memory / peripherals through the bus, and competition occurs between high-speed buses and between high-speed buses and low-speed buses, seriously affecting the bus transmission efficiency. Summary of the invention

[0005] In order to solve the technical problems existing in the above-mentioned prior art, the present invention proposes a packet bus interconnection architecture of a SoC system, including a system bus matrix SYS_BUS_Matrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, wherein the CBM, HPBM, RBM and SPBM are all connected to the SYS_BUS_Matrix through a bus bridge, and the CBM, HPBM, RBM, SPBM and SYS_BUS_Matrix all support the AXI protocol; an embedded processor is mounted on the CBM, and the CBM is connected to RMB; a high-speed peripheral is mounted on the HPBM, and the HPBM is connected to RMB; a RAM memory is mounted on the RBM, and the RBM is connected to the CBM and the HPBM; the SPBM is connected to multiple AHB buses through an AXI-AHB bridge, the SPBM is connected to multiple APB buses through an AXI-APB bridge, and the SPBM is connected to the SYS_BUS_Matrix, and multiple low-speed peripherals are mounted on the AHB bus or the APB bus.

[0006] Furthermore, the sum of data throughputs required by all processors mounted on a single-channel CBM is less than or equal to the maximum bandwidth supported by the CBM bus, and the single-channel CBM and the processor mounted thereon use the same source clock to reduce the reduction in transmission efficiency caused by asynchronous delay.

[0007] Furthermore, the sum of the data throughputs required by all high-speed peripherals mounted on a single-channel HPBM is less than or equal to the maximum bandwidth supported by the HPBM bus, and the single-channel HPBM and the high-speed peripherals mounted thereon use the same source clock to reduce the reduction in transmission efficiency caused by asynchronous delay.

[0008] Furthermore, it is ensured that the memories mounted on a single RBM are memories of the same type, and the conflict occurring on the RBM when the master device accesses the memories is reduced.

[0009] Furthermore, different frequency clocks are used for each AHB bus or APB bus to meet the requirements of peripherals with different frequencies, and low-frequency peripherals are placed on the same AHB bus or APB bus, so that when the peripherals of this group of APB buses are not accessed, the clock of the entire APB bus is turned off to reduce the dynamic power consumption of the chip.

[0010] Furthermore, high-speed master devices such as processors and high-speed peripherals directly access the memory on the RBM bus through their corresponding CBM and HPBM, without accessing the memory through SYS_BUS_Matrix; the processor can access the low-speed peripherals on the SPBM through CBM and then through SYS_BUS_Matrix; the processor can access the high-speed peripherals on the HPBM through CBM and then through SYS_BUS_Matrix; the low-speed peripheral data can be transferred to the memory through SYS_BUS_Matrix.

[0011] Furthermore, the high-speed peripheral is an external module with a faster speed and a higher bandwidth requirement, and the interface supports the AXI protocol.

[0012] Furthermore, the low-speed peripheral is an external module with a slower speed and lower bandwidth requirement, and the interface supports the AHB protocol or the APB protocol.

[0013] While being compatible with common bus structures, the present invention can balance bus transmission between processors, high-speed peripherals, storage and other modules, effectively reduce bus competition between high-speed interfaces, improve data transmission efficiency, simplify chip back-end implementation, and thus optimize the performance of the entire SOC system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a conventional SoC chip architecture diagram in the prior art;

[0015] Figure 2 This is a diagram of the SoC bus structure of the present invention. DETAILED DESCRIPTION

[0016] In order to better understand the purpose, technical solution and function of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings, but the present invention can be implemented in a variety of different ways as defined and covered by the claims. The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention, and the exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0017] The present invention proposes a high-efficiency bus architecture for SoC, such as Figure 2As shown, it includes a system bus matrix (SYS_BUS_Matrix), several processor bus matrices (CPU bus matrix), CBM, several high-speed peripheral bus matrices (HPBM), several memory bus matrices (RAM bus matrix), RBM, and a slow peripheral interface bus matrix (SPBM).

[0018] 1. Connection status of each bus

[0019] 1)CBM, HPBM, RBM, and SPBM are all connected to SYS_BUS_Matrix through a bus bridge. CBM, HPBM, RBM, SPBM, and SYS_BUS_Matrix all support the AXI protocol.

[0020] 2) An embedded processor is mounted on the CBM, and the bus matrix is ​​connected to the RMB bus matrix.

[0021] 3) High-speed peripherals are mounted on the HPBM, and the bus matrix is ​​connected to the RMB bus matrix.

[0022] 4) RAM memory is mounted on the RBM, and the bus matrix is ​​connected to the CBM and HPBM bus matrices.

[0023] 5) SPBM connects multiple AHB / APB buses through AXI-AHB / AXI-APB bridges, and SPBM connects to the SYS_BUS_Matrix bus matrix. Multiple low-speed peripherals are mounted on the AHB / APB bus.

[0024] 2. Connection principles of each bus

[0025] 1) CBM can be designed with one or more channels. A single-channel CBM can be equipped with one or more processors. The multiple processors can be homogeneous or heterogeneous, including but not limited to CPU and DSP. The specific design principle is to calculate the CBM bandwidth based on the data throughput of all processors mounted on the single-channel CBM so that its bandwidth is greater than the total throughput. The bit width and clock frequency are designed based on the CBM bandwidth. In addition, the single-channel CBM and the processor mounted on it use the same clock to reduce the reduction in transmission efficiency caused by asynchronous delay.

[0026] 2) HPBM can be designed with one or more channels. A single-channel HPBM can mount one or more high-speed peripheral interfaces, including but not limited to SRIO and PCIe. The specific design principle is to calculate the HPBM bandwidth based on the sum of the data throughput of all high-speed peripherals mounted on the single-channel HPBM, so that its bandwidth is greater than the total throughput. The bit width and clock frequency are designed based on the HPBM bandwidth, and the single-channel HPBM and its mounted high-speed peripherals use the same clock to reduce the reduction in transmission efficiency caused by asynchronous delay.

[0027] 3) RBM can be designed with one or more channels. A single-channel RBM can mount one or more memories, including but not limited to SRAM and DRAM. The specific design principle is to ensure that the memories mounted on a single-channel RBM are of the same type as much as possible, and to minimize the conflicts that occur on the RBM when the master device accesses the memory.

[0028] 4) SPBM is designed with 1 channel. SPBM can mount one or more AHB / APB buses. A single AHB / APB bus can mount multiple low-speed peripherals, including but not limited to UART, SPI, IIC, etc. The specific design principle is that each AHB / APB bus uses a different frequency clock to meet the needs of peripherals with different frequencies, and try to put low-frequency peripherals on the same AHB / APB bus, so that when the peripherals of this group of APB buses are not accessed, the clock of the entire APB bus can be turned off to reduce the dynamic power consumption of the chip.

[0029] 5) High-speed master devices such as processors and high-speed peripherals directly access the memory on the RBM through their corresponding bus matrices CBM and HPBM, without accessing the memory through SYS_BUS_Matrix. The processor can access the low-speed peripherals on the SPBM through CBM and then through SYS_BUS_Matrix. The processor can access the high-speed peripherals on the HPBM through CBM and then through SYS_BUS_Matrix. The low-speed peripheral data can be transferred to the memory through SYS_BUS_Matrix.

[0030] 6) The high-speed peripherals described herein refer to external modules with relatively fast speed and high bandwidth requirements, and the interface supports the AXI protocol.

[0031] 7) The low-speed peripherals described herein refer to external modules with a slower speed and lower bandwidth requirements, and the interface supports the AHB / APB protocol.

[0032] The present invention has the following beneficial technical effects:

[0033] 1. The processor, high-speed peripherals, memory, low-speed peripherals and other modules are mounted on the system bus through the packet bus instead of directly mounting them on the system bus, which reduces the number of master and slave devices on the system bus, simplifies the difficulty of bus back-end wiring, and increases the system bus frequency.

[0034] 2. The use of packet bus not only improves the achievable frequency of the system bus, but also improves the implementation frequency of CBM, HPBM, RBM, and SPBM, ensuring that the performance of the modules mounted on it is not limited by the bus bandwidth.

[0035] 3. The processor and high-speed peripheral modules directly access the memory on the RBM through their corresponding bus matrices CBM and HPBM. Each processor or high-speed peripheral can access the memory in parallel, so that the access competition occurs on the RBM instead of the system bus, avoiding competition with other transmissions on the system bus.

[0036] The present invention can meet the needs of large-scale SoC system bus architecture design, covers a wide range of protocols, has strong applicability, can reduce the difficulty of bus back-end design and wiring, and increase the bus frequency. At the same time, it solves the bus competition problem when multiple master-slave devices interact, optimizes the transmission bandwidth, and improves the overall performance of the SoC chip.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art may make various changes or modifications within the scope of the claims, which should all be included in the protection scope of the present invention.

Claims

1. A packet bus interconnection architecture of a SoC system, characterized in that: It includes a system bus matrix SYS_BUS_Matrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, wherein CBM, HPBM, RBM and SPBM are all connected to SYS_BUS_Matrix through a bus bridge, and CBM, HPBM, RBM, SPBM and SYS_BUS_Matrix all support AXI protocol; an embedded processor is mounted on CBM, and CBM is connected to RMB; high-speed peripherals are mounted on HPBM, and HPBM is connected to RMB; RAM memory is mounted on RBM, and RBM is connected to CBM and HPBM; SPBM is connected to multiple AHB buses through an AXI-AHB bridge, SPBM is connected to multiple APB buses through an AXI-APB bridge, and SPBM is connected to SYS_BUS_Matrix, and multiple low-speed peripherals are mounted on the AHB bus or APB bus.

2. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: The sum of data throughputs required by all processors mounted on a single-channel CBM is less than or equal to the maximum bandwidth supported by the CBM bus, and the single-channel CBM and the processor mounted thereon use the same source clock to reduce the reduction in transmission efficiency caused by asynchronous delay.

3. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: The sum of data throughputs required by all high-speed peripherals mounted on a single-channel HPBM is less than or equal to the maximum bandwidth supported by the HPBM bus, and the single-channel HPBM and the high-speed peripherals mounted thereon use the same source clock to reduce the reduction in transmission efficiency caused by asynchronous delay.

4. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: It is ensured that the storage mounted on a single RBM is of the same type, and the conflict occurring on the RBM when the master device accesses the storage is reduced.

5. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: Different frequency clocks are used for each AHB bus or APB bus to meet the needs of peripherals with different frequencies, and low-frequency peripherals are placed on the same AHB bus or APB bus. When the peripherals of this group of APB buses are not accessed, the clock of the entire APB bus is turned off to reduce the dynamic power consumption of the chip.

6. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: The processor, high-speed peripherals and other high-speed master devices directly access the memory on the RBM bus through their corresponding CBM and HPBM, without accessing the memory through SYS_BUS_Matrix; the processor can access the low-speed peripherals on the SPBM through CBM and then through SYS_BUS_Matrix; the processor can access the high-speed peripherals on the HPBM through CBM and then through SYS_BUS_Matrix; the low-speed peripheral data can be transferred to the memory through SYS_BUS_Matrix.

7. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: The high-speed peripheral is an external module with a relatively fast speed and a relatively high bandwidth requirement, and its interface supports the AXI protocol.

8. The packet bus interconnection architecture of a SoC system according to claim 1, characterized in that: The low-speed peripheral is an external module with a relatively slow speed and a relatively low bandwidth requirement, and its interface supports the AHB protocol or the APB protocol.

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