Pixel driving circuit with Vth self-compensation

Abstract

The invention discloses a pixel driving circuit with Vth self-compensation, which comprises a first transistor, a second transistor, a third transistor and a fourth transistor, and is characterized in that a first source drain electrode of the first transistor is coupled to a data signal line, a second source drain electrode of the first transistor is coupled to a pre-storage node, and a grid electrode of the first transistor is coupled to a control signal line; a first source-drain electrode of the third transistor is coupled to the pre-storage node, a second source-drain electrode is coupled to the pixel node, and a grid electrode is coupled to a transfer signal line; a first source-drain electrode of the second transistor is coupled to the reference signal line, a second source-drain electrode is coupled to the pixel node, and a grid electrode is coupled to the self-compensation node; a first source-drain electrode of the fourth transistor is coupled to the data signal line, a second source-drain electrode is coupled to the self-compensation node, and a grid electrode is coupled to the reset signal line; one end of the self-compensation capacitor is coupled to the pre-storage node, and the other end of the self-compensation capacitor is coupled to the self-compensation node; one end of the pre-storage capacitor is coupled to the coupling signal line, and the other end of the pre-storage capacitor is coupled to the pre-storage node.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel driving, and in particular to a pixel driving circuit with Vth self-compensation. Background Art

[0002] In traditional field sequential or color sequential display driving technology, the backlight can only be turned on after all screen data is written and the liquid crystal is deflected to a stable state, otherwise the screen will be chaotic. Therefore, the data writing and liquid crystal deflection time will greatly compress the backlight turn-on time, resulting in difficulties in improving the brightness of the display, as well as difficulties in improving the refresh rate and resolution, increased power consumption and increased backlight material costs. Therefore, how to speed up the liquid crystal driving time and increase the backlight turn-on time is a very important issue.

[0003] Canon proposed a pixel driving circuit in its U.S. Patent No. 6181311. The difference between this circuit and the traditional 1T2C pixel design is that, in addition to writing the pixel signal into the switch TFT T1, there is an additional data storage capacitor Cs1, a signal transfer TFT T2, and a reset TFT T3. The signal storage capacitor Cs1 is used to pre-store the pixel data voltage required for the next picture, and the signal transfer TFT T2 is used to transfer the pixel data voltage pre-stored in the signal storage capacitor Cs1 to the corresponding pixel voltage storage capacitor Cs2. The reset TFT T3 is used to eliminate the charge originally remaining on the pixel capacitor to prevent the effects of color deviation and brightness difference caused by the residual charge. This circuit design can use the signal storage capacitor Cs1 to pre-store the pixel data voltage of the next frame during the backlight emission time, and when switching the picture, all pixels synchronously read the pixel data voltage in the corresponding Cs1. Through the design of this pixel data voltage register, the pixel number writing time can be saved and the backlight emission time can be correspondingly increased.

[0004] However, this pixel circuit design faces the problem of voltage reduction associated with charge sharing. Assuming that the pre-charge capacitor Cs1=Cs2+Clc, Vcom=0V (i.e., the pixel electrode is reset to 0V before charging), if Clc is to be charged to 5V, then according to the principle of charge conservation, Cs1 needs to be pre-charged to 10V to achieve this. Therefore, this driving method needs to increase the Data voltage supply range to meet the liquid crystal operating voltage range, put forward higher requirements on the Source IC output voltage range, and greatly increase power consumption. When the Source IC does not meet the requirements, a larger Cs1 capacitor is required. When Cs1 is much larger than Cs2+Clc, the voltage drop will be smaller during charge sharing, but this will reduce the aperture ratio and increase the difficulty of Cs1 pre-charging, which is not conducive to the realization of high refresh rate and high resolution.

[0005] In summary, the conventional pixel driving circuit has the problem of being unable to take into account high refresh rate, high light-on time and high aperture ratio at the same time. Summary of the invention

[0006] In view of this, the present invention provides a pixel driving circuit with Vth self-compensation, which solves the problem of the traditional pixel driving circuit that it cannot take into account high refresh rate, high light time and high aperture ratio by improving the circuit structure and driving timing.

[0007] To solve the above problems, the technical solution of the present invention is to adopt a pixel driving circuit with Vth self-compensation, including: a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first source and drain of the first transistor are coupled to the data signal line, the second source and drain are coupled to the pre-storage node, and the gate is coupled to the control signal line; the first source and drain of the third transistor are coupled to the pre-storage node, the second source and drain are coupled to the pixel node, and the gate is coupled to the transfer signal line; the first source and drain of the second transistor are coupled to the reference signal line, the second source and drain are coupled to the pixel node, and the gate is coupled to the self-compensation node; the first source and drain of the fourth transistor are coupled to the data signal line, the second source and drain are coupled to the self-compensation node, and the gate is coupled to the reset signal line; one end of the self-compensation capacitor is coupled to the pre-storage node, and the other end is coupled to the self-compensation node; one end of the pre-storage capacitor is coupled to the coupling signal line, and the other end is coupled to the pre-storage node.

[0008] Optionally, the driving timing of the pixel driving circuit is configured as follows: in the first frame, the backlight is kept off throughout the whole process, the reset signal first jumps to a high potential, the fourth transistor is turned on, the data signal is written to the self-compensation node, the reset signal first jumps back to a low potential, and the fourth transistor is turned off, wherein, affected by the potential change of the self-compensation node, the potential of the pre-storage node changes to V2, and the potential of the self-compensation node is expressed as V1, V1>V2; the reference signal line jumps to a high potential, the second transistor is turned on, until the second transistor operates in the saturation region, and the potential of the pixel node becomes V1-Vth, wherein Vth is the threshold voltage of the second transistor, V1-Vth>V2 ; The transfer signal jumps to a high potential, the third transistor is turned on, the pixel node shares charge with the pre-storage node, and while the potential of the pre-storage node increases, the potential of the self-compensation node is synchronously affected and increased, further affecting the potential increase of the pixel node, until the potential difference between the self-compensation node and the pixel node is Vth and the potential of the pre-storage node is the same as that of the pixel node. At this time, the voltage on the self-compensation capacitor is Vth, and the threshold voltage extraction of the second transistor is completed.

[0009] Optionally, the driving timing of the pixel driving circuit is configured as follows: in the backlight turn-on stage of the Nth frame, the control signal jumps to a high potential, the first transistor is turned on, the data signal is written to the pre-storage node, the control signal jumps back to a low potential, and the first transistor is turned off, wherein the potential of the pre-storage node changes to Vdata-VH, and is affected by the potential change of the pre-storage node. When the voltage difference across the self-compensation capacitor is Vth, the potential change of the self-compensation node is Vdata-VH+Vth; the coupling signal jumps to a high potential, the potential change of the pre-storage node is Vdata, and the potential change of the self-compensation node is Vdata-+Vth; the reference signal jumps to a low potential, the second transistor is turned on, and after the potential of the pixel node is reset to a low potential, the reference signal jumps to a high potential until the second transistor operates in the saturation region, the potential of the pixel node becomes Vdata, and the writing of the data signal is completed.

[0010] Optionally, when the threshold voltage of the second transistor decreases, the potential of the pixel node is Vdata', Vdata' is greater than Vdata, and after the pixel node completes writing of the data signal, the transfer signal jumps to a high potential, and the third transistor is turned on. At this time, the potential of the pixel node decreases, and the potentials of the pre-storage node and the self-compensation node increase, and then the voltage difference between the self-compensation node and the pixel node is greater than Vth, and the working state of the second transistor becomes a linear region; until the working state of the second transistor becomes a saturation region again, at this time, the voltage difference across the self-compensation capacitor is the threshold voltage of the second transistor in the current frame, so that the pixel driving circuit performs self-compensation according to the change of Vth.

[0011] Optionally, the pixel driving circuit further includes a holding capacitor and a pixel capacitor, one end of the holding capacitor and the pixel capacitor is coupled to the pixel node, and the other end of the holding capacitor and the pixel capacitor is coupled to a common signal.

[0012] Optionally, the pixel driving circuit also includes a fifth transistor, a holding capacitor and a pixel capacitor, the first source and drain of the fifth transistor are coupled to the pixel node, and the gate is coupled to the second transfer signal line; one end of the holding capacitor and the pixel capacitor is coupled to the second source and drain of the fifth transistor, and the other end is coupled to the common signal.

[0013] Optionally, in the case where the pixel driving circuit is provided with the fifth transistor, the second transfer signal jumps to a high potential at the same time as the reference signal jumps to a high potential, so that the fifth transistor and the second transistor are both turned on until the second transistor operates in the saturation region, and the potentials of the pixel node and the upper plate of the pixel capacitor are both changed to Vdata, completing the writing of the data signal; and before the transfer signal jumps to a high potential, the second transfer signal jumps back to a low potential, so that the potential of the upper plate of the pixel capacitor is locked and does not participate in the subsequent circuit self-compensation working process.

[0014] Optionally, in a negative polarity frame, the low potential of the reference signal is configured as: Vcom-Vop_max; the high potential of the reference signal is configured as: higher than Vcom; wherein Vcom is a common signal, and Vop_max is a driving voltage of the highest grayscale of a pixel.

[0015] Optionally, in a positive polarity frame, the low potential of the reference signal is configured to be lower than Vcom; the high potential of the reference signal is configured to be Vcom+Vop_max; wherein Vcom is a common signal, and Vop_max is a driving voltage of the highest gray scale of a pixel. The primary improvement of the present invention is the pixel driving circuit with Vth self-compensation. By setting a pre-storage capacitor in cooperation with the transistor, the grayscale voltage of the next frame is stored by the pre-storage capacitor during the backlight emission time of the current frame, so that all pixels can synchronously realize the grayscale voltage when the backlight is turned off, which greatly reduces the writing time of the pixel voltage and relatively increases the backlight emission time.

[0016] At the same time, the present invention realizes the extraction of the threshold voltage of the second transistor in the first frame by cooperating with the fourth transistor, the second transistor and the third transistor and the capacitor, thereby ensuring the elimination of interference caused by the threshold voltage when the gate controls the grayscale voltage to be written, effectively ensuring the accuracy of the grayscale voltage writing, and avoiding the problem of the pre-storage capacitor requiring a larger capacitor in the charge sharing scheme, effectively improving the aperture ratio and reducing the difficulty of pre-charging.

[0017] And when the subsequent circuit is working, the first transistor, the second transistor, the third transistor and the capacitor cooperate to achieve a threshold voltage change based on the second transistor, and dynamically update the voltage difference across the self-compensating capacitor, thereby solving the pain point problem under the gate control technology route, that is, the threshold voltage drift problem that will occur when the second transistor works for a long time, and further ensuring the accuracy of the grayscale voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 1 of the present invention; Figure 2is a simplified driving timing diagram of the first frame of the pixel driving circuit of Embodiment 1 of the present invention; Figure 3 is a simplified driving timing diagram of the Nth frame of the pixel driving circuit of Embodiment 1 of the present invention; Figure 4 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0024] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. Example 1

[0027] Specifically, Figure 1 As shown, a pixel driving circuit with Vth self-compensation includes: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, wherein the first source and drain of the first transistor T1 are coupled to the data signal line Data, the second source and drain are coupled to the pre-storage node VA, and the gate is coupled to the control signal line scan; the first source and drain of the third transistor T3 are coupled to the pre-storage node VA, the second source and drain are coupled to the pixel node VQ, and the gate is coupled to the transfer signal line Tran; the first source and drain of the second transistor T2 are coupled to the data signal line Data, the second source and drain are coupled to the pre-storage node VA, and the gate is coupled to the transfer signal line Tran; The source and drain are coupled to the reference signal line Vref, the second source and drain are coupled to the pixel node VQ, and the gate is coupled to the self-compensation node VP; the first source and drain of the fourth transistor T4 are coupled to the data signal line Data, the second source and drain are coupled to the self-compensation node VP, and the gate is coupled to the reset signal line Reset; one end of the self-compensation capacitor Cs1 is coupled to the pre-storage node VA, and the other end is coupled to the self-compensation node VP; one end of the pre-storage capacitor Cs3 is coupled to the coupling signal line Couple, and the other end is coupled to the pre-storage node VA.

[0028] Furthermore, the pixel driving circuit further includes a holding capacitor Cs2 and a pixel capacitor Clc, one end of the holding capacitor Cs2 and the pixel capacitor Clc are coupled to the pixel node VQ, and the other end of the holding capacitor Cs2 and the pixel capacitor Clc are coupled to the common signal Vcom.

[0029] Specifically, the driving timing of the pixel driving circuit is configured as follows: In the first frame, Figure 2As shown, the backlight is kept off throughout the whole process, the reset signal first jumps to a high potential, the fourth transistor T4 is turned on, the data signal is written into the self-compensation node VP, the reset signal first jumps back to a low potential, and the fourth transistor T4 is turned off, wherein, affected by the potential change of the self-compensation node VP, the potential of the pre-storage node VA changes to V2, and the potential of the self-compensation node VP is expressed as V1, V1>V2; the reference signal line Vref jumps to a high potential, the second transistor T2 is turned on, until the second transistor T2 works in the saturation region, and the potential of the pixel node VQ becomes V1-Vth, wherein Vth is the threshold voltage of the second transistor T2, V1-Vth>V2 ; The transfer signal jumps to a high potential, the third transistor T3 is turned on, the pixel node VQ shares charge with the pre-storage node VA, and while the potential of the pre-storage node VA increases, the potential of the self-compensation node VP is synchronously affected and increased, further affecting the increase in the potential of the pixel node VQ, until the potential difference between the self-compensation node VP and the pixel node VQ is Vth and the potential of the pre-storage node VA is the same as that of the pixel node VQ. At this time, the voltage on the self-compensation capacitor Cs1 is Vth, and the threshold voltage extraction of the second transistor T2 is completed.

[0030] like Figure 3 As shown, in the backlight-on stage of the Nth (N is greater than 2) frame, the control signal jumps to a high potential, the first transistor T1 is turned on, the data signal is written into the pre-storage node VA, the control signal jumps back to a low potential, and the first transistor T1 is turned off, wherein the potential of the pre-storage node VA changes to Vdata-VH, and under the influence of the potential change of the pre-storage node VA, when the voltage difference across the self-compensation capacitor Cs1 is Vth, the potential of the self-compensation node VP changes to Vdata-VH+Vth; in the backlight-off stage of the Nth frame, the coupling signal jumps to a high potential, the potential of the pre-storage node VA changes to Vdata, and the potential of the self-compensation node VP changes to Vdata-+Vth; the reference signal jumps to a low potential, the second transistor T2 is turned on, and after the potential of the pixel node VQ is reset to a low potential, the reference signal jumps to a high potential until the second transistor T2 operates in the saturation region, the potential of the pixel node VQ changes to Vdata, and the writing of the data signal is completed. The driving timing of the second frame is similar to the driving timing of the Nth frame (N is greater than 2), except that the backlight is kept off throughout the whole process, so it will not be described in detail.

[0031] When the threshold voltage of the second transistor T2 decreases, the potential of the pixel node VQ is Vdata', and Vdata' is greater than Vdata. After the pixel node VQ completes writing of the data signal, the transfer signal jumps to a high potential, and the third transistor T3 is turned on. At this time, the potential of the pixel node VQ decreases, and the potentials of the pre-storage node VA and the self-compensation node VP rise, so that the voltage difference between the self-compensation node VP and the pixel node VQ is greater than Vth, and the working state of the second transistor T2 becomes a linear region; until the working state of the second transistor T2 becomes a saturation region again, at this time, the voltage difference across the self-compensation capacitor Cs1 is the threshold voltage of the second transistor T2 of the current frame, so that the pixel driving circuit performs self-compensation according to the change of Vth, and the transfer signal, the reference signal and the coupling signal jump to a low potential, entering the backlight start-up stage of the next frame.

[0032] Furthermore, the low potential of the coupling signal is -VH+Vcom, the high potential is Vcom, VH>Vcom+Vop_max-(Vcom-Vop_max)=2Vop_max, so as to ensure that the backlight is in the off state in the positive and negative frame backlight on phase T2.

[0033] To facilitate understanding of the potential linkage principle of VA and VP in this case, the three working conditions involved are explained below: When the voltage is coupled upward by VH voltage, since T1, T2, T3, and T4 are turned off, VA and VP are in floating state, and therefore are coupled by VH voltage in the same direction; ② When T1 is turned on and T3 and T4 are turned off, Vdata voltage is written, the voltage Vth on Cs1 is fixed, and Vp point is rewritten as Vdata+Vth; ③ When VD is written when T4 is turned on and T1 and T3 are turned off, VA is divided by couple to VD*Cs1 / (Cs1+Cs3).

[0034] Furthermore, in the negative polarity frame, the low potential of the reference signal is configured as: Vcom-Vop_max; the high potential of the reference signal is configured as: higher than Vcom; wherein Vcom is a common signal, and Vop_max is a driving voltage of the highest grayscale of the pixel.

[0035] Furthermore, in the positive polarity frame, the low potential of the reference signal is configured to be lower than Vcom; the high potential of the reference signal is configured to be Vcom+Vop_max; wherein Vcom is a common signal, and Vop_max is a driving voltage of the highest grayscale of the pixel.

[0036] The present invention sets a pre-storage capacitor in cooperation with a transistor so that during the backlight emission time of the current frame, the grayscale voltage of the next frame is stored by the pre-storage capacitor, so that all pixels can synchronously realize the grayscale voltage when the backlight is turned off, which greatly reduces the writing time of the pixel voltage and relatively increases the backlight emission time.

[0037] At the same time, the present invention realizes the extraction of the threshold voltage of the second transistor in the first frame by cooperating with the fourth transistor, the second transistor and the third transistor and the capacitor, thereby ensuring the elimination of interference caused by the threshold voltage when the gate controls the grayscale voltage to be written, effectively ensuring the accuracy of the grayscale voltage writing, and avoiding the problem of the pre-storage capacitor requiring a larger capacitor in the charge sharing scheme, effectively improving the aperture ratio and reducing the difficulty of pre-charging.

[0038] And when the subsequent circuit is working, the first transistor, the second transistor, the third transistor and the capacitor cooperate to achieve a threshold voltage change based on the second transistor, and dynamically update the voltage difference across the self-compensating capacitor, thereby solving the pain point problem under the gate control technology route, that is, the threshold voltage drift problem that will occur when the second transistor works for a long time, and further ensuring the accuracy of the grayscale voltage. Example 2

[0039] like Figure 4 As shown, the difference between the pixel driving circuit in this embodiment and the pixel driving circuit in Embodiment 1 is that: the pixel driving circuit also includes a fifth transistor T5, a holding capacitor Cs2 and a pixel capacitor Clc, the first source and drain of the fifth transistor T5 are coupled to the pixel node VQ, and the gate is coupled to the second transfer signal line Tran2; one end of the holding capacitor Cs2 and the pixel capacitor Clc are coupled to the second source and drain of the fifth transistor T5, and the other end is coupled to the common signal Vcom.

[0040] Furthermore, the driving timing of the pixel driving circuit of this embodiment differs from the driving timing of the pixel driving circuit of Embodiment 1 in that: when the pixel driving circuit is provided with the fifth transistor T5, the reference signal jumps to a high potential at the same time as the second transfer signal jumps to a high potential, so that the fifth transistor T5 and the second transistor T2 are both turned on until the second transistor T2 operates in the saturation region, and the potentials of the pixel node VQ and the upper plate of the pixel capacitor Clc are both changed to Vdata, completing the writing of the data signal; and before the transfer signal jumps to a high potential, the second transfer signal jumps back to a low potential, so that the potential of the upper plate of the pixel capacitor Clc is locked and does not participate in the subsequent circuit self-compensation working process.

[0041] At the same time, since the potential of the upper plate of the pixel capacitor Clc is locked, it does not participate in the subsequent circuit self-compensation process. Therefore, in this embodiment, the coupling signal does not need to jump, that is, one end of the pre-storage capacitor Cs3 does not need to be connected to the coupling signal line Couple, and can be directly connected to the common signal line (Vcom), which saves the coupling signal line Couple compared to embodiment 1. The above is a pixel driving circuit with Vth self-compensation provided in an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0042] Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented with a software module executed by a hardware or processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

Claims

1. A pixel driving circuit with Vth self-compensation, characterized in that: include: a first transistor (T1), a second transistor (T2), a third transistor (T3) and a fourth transistor (T4), wherein: The first source and drain of the first transistor (T1) are coupled to a data signal line (Data), the second source and drain are coupled to a pre-storage node (VA), and the gate is coupled to a control signal line (scan); the first source and drain of the third transistor (T3) are coupled to the pre-storage node (VA), the second source and drain are coupled to a pixel node (VQ), and the gate is coupled to a transfer signal line (Tran); the first source and drain of the second transistor (T2) are coupled to a reference signal line (Vref), the second source and drain are coupled to the pixel node (VQ), and the gate is coupled to a self-compensation node (VP); the first source and drain of the fourth transistor (T4) are coupled to a data signal line (Data), the second source and drain are coupled to the self-compensation node (VP), and the gate is coupled to a reset signal line (Reset); One end of the self-compensation capacitor (Cs1) is coupled to the pre-storage node (VA), and the other end is coupled to the self-compensation node (VP); one end of the pre-storage capacitor (Cs3) is coupled to the coupling signal line (Couple), and the other end is coupled to the pre-storage node (VA).

2. The pixel driving circuit according to claim 1, characterized in that: The driving timing of the pixel driving circuit is configured as follows: In the first frame, the backlight is kept off all the time, the reset signal first jumps to a high potential, the fourth transistor (T4) is turned on, the data signal is written into the self-compensation node (VP), the reset signal first jumps back to a low potential, the fourth transistor (T4) is turned off, wherein, affected by the potential change of the self-compensation node (VP), the potential of the pre-storage node (VA) changes to V2, the potential of the self-compensation node (VP) is expressed as V1, and V1>V2; The reference signal line (Vref) jumps to a high potential, and the second transistor (T2) is turned on until the second transistor (T2) operates in a saturation region, and the potential of the pixel node (VQ) becomes V1-Vth, wherein Vth is a threshold voltage of the second transistor (T2), and V1-Vth>V2; The transfer signal jumps to a high potential, the third transistor (T3) is turned on, the pixel node (VQ) shares charge with the pre-storage node (VA), and while the potential of the pre-storage node (VA) increases, the potential of the self-compensation node (VP) is synchronously affected and increased, further affecting the increase in the potential of the pixel node (VQ), until the potential difference between the self-compensation node (VP) and the pixel node (VQ) is Vth and the potential of the pre-storage node (VA) is the same as that of the pixel node (VQ). At this time, the voltage on the self-compensation capacitor (Cs1) is Vth, and the threshold voltage extraction of the second transistor (T2) is completed.

3. The pixel driving circuit according to claim 1, characterized in that: The driving timing of the pixel driving circuit is configured as follows: In the backlight-on stage of the Nth (N is greater than 2) frame, the control signal jumps to a high potential, the first transistor (T1) is turned on, the data signal is written into the pre-storage node (VA), the control signal jumps back to a low potential, and the first transistor (T1) is turned off, wherein the potential of the pre-storage node (VA) changes to Vdata-VH, and under the influence of the potential change of the pre-storage node (VA), when the voltage difference across the self-compensation capacitor (Cs1) is Vth, the potential of the self-compensation node (VP) changes to Vdata-VH+Vth; In the backlight off stage of the Nth frame, the coupling signal jumps to a high potential, the potential of the pre-storage node (VA) changes to Vdata, and the potential of the self-compensation node (VP) changes to Vdata-+Vth; The reference signal jumps to a low potential, the second transistor (T2) is turned on, and after the potential of the pixel node (VQ) is reset to a low potential, the reference signal jumps to a high potential until the second transistor (T2) operates in a saturation region, the potential of the pixel node (VQ) becomes Vdata, and the writing of the data signal is completed.

4. The pixel driving circuit according to claim 3, characterized in that: When the threshold voltage of the second transistor (T2) decreases, the potential of the pixel node (VQ) is Vdata', and Vdata' is greater than Vdata. After the pixel node (VQ) completes writing of the data signal, the transfer signal jumps to a high potential, and the third transistor (T3) is turned on. At this time, the potential of the pixel node (VQ) decreases, and the potentials of the pre-storage node (VA) and the self-compensation node (VP) increase, so that the voltage difference between the self-compensation node (VP) and the pixel node (VQ) is greater than Vth, and the working state of the second transistor (T2) changes to a linear region; Until the working state of the second transistor (T2) returns to the saturation zone, at which time, the voltage difference across the self-compensation capacitor (Cs1) is the threshold voltage of the second transistor (T2) in the current frame, so that the pixel driving circuit performs self-compensation according to the change of Vth.

5. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a holding capacitor (Cs2) and a pixel capacitor (Clc). One end of the holding capacitor (Cs2) and the pixel capacitor (Clc) is coupled to the pixel node (VQ), and the other end is coupled to a common signal (Vcom).

6. The pixel driving circuit according to claim 2, characterized in that: The pixel driving circuit further includes a fifth transistor (T5), a holding capacitor (Cs2) and a pixel capacitor (Clc). The first source and drain of the fifth transistor (T5) are coupled to the pixel node (VQ), and the gate is coupled to the second transfer signal line (Tran2); One end of the holding capacitor (Cs2) and the pixel capacitor (Clc) is coupled to the second source and drain of the fifth transistor (T5), and the other end is coupled to the common signal (Vcom).

7. The pixel driving circuit according to claim 6, characterized in that: In the case where the pixel driving circuit is provided with the fifth transistor (T5), When the reference signal jumps to a high potential, the second transfer signal jumps to a high potential synchronously, so that the fifth transistor (T5) and the second transistor (T2) are both turned on, until the second transistor (T2) works in a saturation region, and the potentials of the pixel node (VQ) and the upper plate of the pixel capacitor (Clc) are both changed to Vdata, completing the writing of the data signal; Before the transfer signal jumps to a high potential, the second transfer signal jumps back to a low potential, so that the potential of the upper plate of the pixel capacitor (Clc) is locked and does not participate in the subsequent circuit self-compensation process.

8. The pixel driving circuit according to claim 1, characterized in that: In the negative polarity frame, the low potential of the reference signal is configured as: Vcom-Vop_max; the high potential of the reference signal is configured as: higher than Vcom; wherein Vcom is a common signal, and Vop_max is a driving voltage of the highest gray scale of a pixel.

9. The pixel driving circuit according to claim 1, characterized in that: In the positive polarity frame, the low potential of the reference signal is configured to be lower than Vcom; the high potential of the reference signal is configured to be Vcom+Vop_max; wherein Vcom is a common signal, and Vop_max is a driving voltage of the highest gray scale of a pixel.

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