Integrated circuit structure and manufacturing method thereof

Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure including: a first substrate having a first surface having a normal direction along a first direction; a first IC chip bonded to the first substrate; and a second IC chip electrically connected to the first IC chip. The first IC chip and the second IC chip are sealed in the same package having a sealing material layer, and the sealing material layer includes a first anisotropic heat dissipation material. The first anisotropic heat dissipating material is thermally conductive and has a first thermal conductivity in a first direction and a second thermal conductivity in a second direction perpendicular to the first direction. The second thermal conductivity is substantially greater than the first thermal conductivity. The embodiment of the invention also relates to an integrated circuit structure and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit structures and methods for manufacturing the same. Background Art

[0002] Many technological advances have occurred in the field of three-dimensional IC (3DIC) packaging, which involves stacking and bonding multiple chips together. Each chip includes at least one functional IC, such as an IC configured to implement logic functions, memory functions, digital functions, analog functions, mixed signal functions, radio frequency (RF) functions, input / output (I / O) functions, communication functions (e.g., by implementing desired communication protocols, such as 5G (i.e., fifth generation) wireless communication protocols, Ethernet communication protocols, IB communication protocols, etc., to provide support for wired communication and / or wireless communication), power management functions, other functions, or combinations thereof. Memory devices and some of these involve capacitors. With continued developments in 3DIC stacking technology, integrated chips may experience various problems including heat dissipation problems, which may further cause other problems, such as bonding, stress, and delamination problems.

[0003] In other areas, as multi-gate devices are used in advanced IC structures and continue to scale, challenges arise in several areas, including current leakage and heat dissipation issues, especially when the IC structures have high current, high voltage, or high speed.

[0004] Thus, while existing 3DIC structures (or advanced IC structures) and methods of manufacturing the same are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide an integrated circuit (IC) structure, including: a first field effect transistor (FET) of a first type of conductivity, wherein the first field effect transistor also includes: a first channel, vertically stacked along a first direction, the first channel extending longitudinally along a second direction perpendicular to the first direction; a first source and a first drain, arranged on opposite sides of the first channel and contacting each of the first channels; and a first gate, interposed between the first source and the first drain, and extending to wrap around each of the first channels; a second field effect transistor of a second type of conductivity opposite to the first type of conductivity, wherein the second field effect transistor is stacked along the first direction on the first drain. A first field effect transistor is provided above the first field effect transistor, and further includes: a second channel vertically stacked along the first direction, the second channel longitudinally extending along the second direction; a second source and a second drain disposed on opposite sides of the second channel and contacting each of the second channels; and a second gate disposed between the second source and the second drain and extending to wrap each of the second channels; and an anisotropic heat dissipation structure disposed below the first field effect transistor, wherein the anisotropic heat dissipation structure includes an electrically insulating and thermally conductive anisotropic heat dissipation material having a first thermal conductivity along the first direction and a second thermal conductivity along the second direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

[0006] Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a first substrate having a first surface, the first surface having a normal direction along a first direction; a first integrated circuit chip bonded to the first substrate; and a second integrated circuit chip electrically connected to the first integrated circuit chip, wherein the first integrated circuit chip and the second integrated circuit chip are sealed in the same package having a sealing material layer, and the sealing material layer comprises a first anisotropic heat dissipation material, wherein the first anisotropic heat dissipation material is thermally conductive, having a first thermal conductivity along the first direction and a second thermal conductivity along a second direction perpendicular to the first direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

[0007] Still other embodiments of the present application provide a method for manufacturing an integrated circuit (IC) structure, comprising: forming a circuit structure having a semiconductor device located on a front side of a substrate and an interconnection structure located above the semiconductor device; applying a solution to a back side of the substrate, the solution comprising a photosensitive material and a liquid crystal material; applying an electric field to the solution; and curing the solution while the electric field is applied to the solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the accompanying drawings illustrate only typical embodiments of the disclosed embodiments and, therefore, should not be considered to be limiting in scope, as the disclosed embodiments may be equally well adapted to other embodiments.

[0009] Figure 1 , FIG. 2A to FIG. 2E Schematic diagrams of anisotropic heat dissipating polymer materials according to various embodiments are shown.

[0010] Figure 3A and Figure 3B Schematic diagrams of anisotropic heat dissipation liquid crystal materials according to various embodiments are shown.

[0011] Figure 4 The invention is a flow chart of a method for forming anisotropic heat dissipating liquid crystal material on a substrate according to various aspects of the embodiments of the present disclosure.

[0012] FIG. 4A to FIG. 4E Cross-sectional views of an IC structure with anisotropic heat dissipating liquid crystal material at various intermediate stages of fabrication are shown in accordance with some embodiments.

[0013] Figure 5 Cross-sectional views of integrated circuit (IC) structures according to various aspects of embodiments of the present disclosure are shown.

[0014] FIG. 6A to FIG. 6B The formation of various aspects according to the embodiments of the present disclosure is shown Figure 5 A partial or complete flow chart of a method of IC construction.

[0015] Figures 7 to 14 The IC structure according to the embodiment of the present disclosure is shown in FIG. FIG. 6A to FIG. 6B Cross-sectional views of various intermediate stages of fabrication and processing of the method.

[0016] Fig.15 is a flowchart of part or all of a method of forming an IC structure according to various aspects of an embodiment of the present disclosure.

[0017] Figures 16 to 19 The IC structure according to the embodiment of the present disclosure is shown in FIG. Fig.15 Cross-sectional views of various intermediate stages of fabrication and processing of the method.

[0018] Fig. 20 According to various aspects of the embodiments of the present disclosure, Fig.15 A partial or complete flow chart of a method of IC construction.

[0019] Figure 21 to Figure 23 The IC structure according to the embodiment of the present disclosure is shown in FIG. Fig. 20 Cross-sectional views of various intermediate stages of fabrication and processing of the method.

[0020] Figure 24 to Figure 27 A cross-sectional view of an IC structure constructed according to various embodiments is shown.

[0021] Figure 28 to Figure 29 A cross-sectional view of an IC structure constructed according to various embodiments is shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0024] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Embodiments of the present disclosure relate to integrated circuit (IC) structures and methods for manufacturing the same, and more specifically, to complementary field effect transistor (CFET) devices with directional heat dissipation structures. Embodiments of the present disclosure also relate to methods and structures for IC structures with advanced packaging structures, such as three-dimensional IC (3DIC) structures and methods for manufacturing the same. The 3DIC structure is a stacked structure with heterogeneous integration, such as a logic device stacked above a memory device, or vice versa. In the disclosed embodiments, the IC structure includes a transistor structure having a plurality of vertically stacked transistors, each of the plurality of vertically stacked transistors including a plurality of vertically stacked nanowires or nanosheets as a channel and a gate structure wrapping each of the channels. More specifically, the IC structure includes a complementary field effect transistor (CFET) structure and a method for manufacturing the CFET. The CFET may include an N-type FET vertically located above a P-type FET or a P-type FET vertically located above an N-type FET.

[0026] The disclosed IC structure and the manufacturing method thereof relate to an integrated circuit structure with a multi-gate device, in particular a CFET structure and / or a 3DIC structure integrated with a heat dissipation structure having anisotropic heat dissipation material. The disclosed IC structure includes various components, materials and configurations to enhance directional heat dissipation. The disclosed IC structure and the manufacturing method thereof provide more efficient heat dissipation and prevent heat from flowing to structures with poor thermal stability.

[0027] The disclosed IC structure and the method for manufacturing the same are described in detail according to various embodiments.

[0028] In some embodiments, the IC structure includes a carrier substrate bonded to a semiconductor substrate having an integrated circuit formed thereon, such as a FET having multiple channels stacked vertically, such as a CFET. A heat dissipation structure is further formed on the back side of the semiconductor substrate to provide heat dissipation. It should be understood that the structures provided are only some embodiments, and the IC structure may include more than two semiconductor structures bonded together with similar bonding structures. The IC structure includes a heat dissipation structure of an anisotropic heat dissipation material (ATDM) layer for directional heat dissipation.

[0029] The ATDM layer is a thermal material with anisotropic thermal properties. In particular, due to the anisotropic thermal properties of ATDM, the thermal conductivity of ATDM is different along different directions. In ATDM, the thermal conductivity along a certain direction (referred to as the thermal direction) is substantially greater than the thermal conductivity along other directions. In some embodiments, the thermal conductivity along the thermal direction is greater than 0.5 W / m·K, and the thermal conductivity along other directions is less than 0.1 W / m·K. This thermal property of ATDM is incorporated into the integrated circuit structure to direct heat in a certain direction and prevent heat from flowing to undesired directions and regions, thereby more effectively dissipating the thermal energy generated in the IC structure, maintaining the IC structure at a low temperature, and enhancing the performance and reliability of the IC structure.

[0030] In some embodiments, the ATDM is electrically insulating (or dielectric) and thermally conductive so that it will properly dissipate heat without interfering with electrical routing.

[0031] In some embodiments, ATDM is a conical bottle brush polymer 20, such as Figure 1 as shown in . Figure 1 is a schematic diagram of a conical bottle brush polymer 20 constructed according to some embodiments. The conical bottle brush polymer 20 has a tree-like structure, having a trunk 22 along the x-direction and branches 24 extending from the trunk 22. The branches 24 are oriented along an inclined direction. Therefore, the conical bottle brush polymer 20 has an anisotropic structure, especially having different properties along the X-direction and the -X-direction, resulting in different thermal behaviors along the X-direction and the -X-direction. Figure 1 The structure of the conical bottle brush polymer 20 shown in the experiment and simulation found that the thermal conductivity along the -X direction is substantially greater than the thermal conductivity along the X direction. Therefore, heat mainly flows along the -X direction relative to the X direction. In some embodiments, the trunk 22 of the conical bottle brush polymer 20 is further chemically bonded to the chemical group R. In some embodiments, the chemical group R includes an organic functional group, such as an alkyl group having hydrogen attached to a hydrocarbon, which may have a linear, branched or cyclic structure, and may also include heteroatoms, such as nitrogen or oxygen atoms. In some embodiments, the chemical group R includes at least one of an alkyl group, a fluoro group and a benzyl group. In some embodiments, the chemical group R includes a carboxyl group, a hydroxyl group, a thiol group, an enol group, a phenolic group, a sulfonyl group and / or a SO2 The inorganic acid may include perchloric acid, hydrogen iodide, hydrogen bromide, hydrogen chloride, nitric acid, thiocyanic acid, chloric acid, iodic acid, hypophosphorous acid, hydrogen fluoride, nitrous acid, cyanic acid, hydrazine, hypochlorous acid, hypobromous acid, hydrocyanic acid, hypoiodous acid, sulfuric acid, chromic acid, sulfurous acid, phosphoric acid, phosphorous acid, pyrophosphoric acid, carbonic acid, hydrogen sulfide and / or boric acid.

[0032] The conical bottle brush polymer 20 is attached to an IC structure (such as IC structure 250 or 280 described later) by chemical bonding. In the disclosed embodiment, the IC structure includes a dielectric surface layer, and the conical bottle brush polymer 20 is bonded to the dielectric surface of the IC structure. In a further embodiment, the IC structure includes a dielectric surface layer of a dielectric material, such as silicon oxide (SiO 2 ), silicon nitride (SiN) or silicon oxycarbonitride (SiOCN). The dielectric surface of the IC structure includes some chemical groups that are inherently present or introduced by appropriate chemical treatment. Those chemical groups can chemically react with the chemical groups R of the conical bottle brush polymer 20, thereby forming chemical bonds and fixing the conical bottle brush polymer 20 on the IC structure with increased adhesion.

[0033] refer to Figure 2A In some embodiments, the IC structure includes a dielectric surface layer 26 of silicon oxide having OH groups, which are inherently present on the surface. The OH groups on the dielectric surface layer 26 of silicon oxide chemically react with the chemical groups R of the conical bottle brush polymer 20 to form a chemical bond therebetween. In some embodiments, the dielectric surface layer 26 of silicon oxide is further treated using an appropriate treatment, such as an ozone or hydrogen peroxide treatment, to introduce OH groups to the dielectric surface layer 26. For example, the IC structure is placed in an ozone or hydrogen peroxide environment at an elevated temperature for a certain duration.

[0034] refer to Figure 2B In some embodiments, the IC structure includes a NH 2 The dielectric surface layer 28 of silicon nitride or silicon carbonitride oxide of the group, NH 2 The NH groups are inherently present on the surface. 2 The group chemically reacts with the chemical group R of the conical bottle brush polymer 20, thereby forming a chemical bond therebetween.

[0035] In some embodiments, the conical bottle brush polymer 20 includes Figure 2C The chemical structure 30 is shown in FIG. The chemical structure 30 includes polynorbornene 32 as a main chain and polystyrene 34 as a side chain.

[0036] In some embodiments, the bottle brush polymer 20 comprises a dendritic polymer structure such as Figure 2D and Figure 2E 36 and 38 shown in Figure 3, respectively. It should be noted that polymers 36 and 38 are different in topological structure. For example, polymer 36 includes a regular structure in which each node has two branches and each chain has the same length from root to tip. Polymer 38 includes an irregular structure in which each node has one or two branches and each chain has a different length from root to tip.

[0037] Polymer 36 or polymer 38 includes chemical groups 40 as nodes of the dendritic polymer structure; chemical groups B as the root of the dendritic polymer structure, which can be fixed on the material by reacting with surface amines or hydroxyls; and chemical groups A as the ends of the branches. In some embodiments, chemical groups A, B and 40 are the same chemical groups, such as carbon, oxygen or nitrogen. In various embodiments, chemical group 40 represents a bond formed by a coupling reaction of chemical groups A and B, and includes ether, ester, borate, peptide bonds; chemical reaction pairs A / B include acrylate / amine, boric acid / alcohol, carboxylic acid / alcohol, etc. This polymer-based ATDM is also called anisotropic heat dissipation polymer (ATD-P).

[0038] In some embodiments, the ATDM is a layer of liquid crystal material or a material doped with liquid crystal, such as Figure 3A as shown in . Figure 3A is a schematic diagram of a liquid crystal material layer 50 constructed according to some embodiments. The liquid crystal material layer 50 has a Figure 3A The anisotropic chemical structure shown in , or other suitable liquid crystal materials. Liquid crystal is a thermodynamically stable phase characterized by anisotropy of properties without the presence of a three-dimensional lattice, usually in a temperature range between the solid phase and the isotropic liquid phase, and is therefore called an intermediate phase. In some embodiments, liquid crystal materials have some common characteristic features, including a rod-like molecular structure, rigidity of the long axis, and strong dipoles and easily polarizable substituents.

[0039] Specifically, the liquid crystal material layer 50 provides anisotropic thermal conductivity. For example, the thermal conductivity along the X direction (or -X direction) is substantially greater than the thermal conductivity along the Z direction (or -Z direction). More specifically, heat energy mainly flows along the X direction. This will refer to Figure 3B Further description. A layer of liquid crystal material 50 is formed on a substrate 52. The heat transport is directional and mainly in the X direction, with substantially less or negligible heat transport in the Z direction. Such liquid crystal ATDM is also known as anisotropic heat dissipating liquid crystal (ATD-LC).

[0040] refer to Figure 4 and FIG. 4A to FIG. 4EThe method of forming the liquid crystal material layer 50 on the substrate is further described. Figure 4 is a flow chart of a method 60 of forming anisotropic heat dissipating liquid crystal material on a substrate. FIG. 4A to FIG. 4E is a cross-sectional view of a portion of an IC structure constructed in accordance with some embodiments.

[0041] refer to Figure 4 and Figure 4A In operation 62 of method 60, a mixed liquid crystal solution 54 is applied to substrate 52 by a suitable method, such as a syringe 56 or other suitable technique. In the disclosed embodiment, the mixed liquid crystal solution 54 is a mixture of a liquid crystal material and a photoresist material in a solution. In some embodiments, the photoresist material includes a photosensitive chemical, such as a chemically amplified photoresist (CAR). In some embodiments, the photoresist material may include a polymer material; a photoacid generator (PAG) that provides a solubility change to a developer; a solvent and / or other suitable composition. In some embodiments, the liquid crystal material includes any suitable liquid material, such as Figure 3A The liquid crystal material 50 shown in FIG. 5 , cholesteryl benzoate molecules or N-(4-methoxybenzylidene)-4-butylaniline (MBBA) molecules.

[0042] refer to Figure 4 and Figure 4B In operation 64 of method 60 , the mixed solution 54 is uniformly distributed on the top surface of the substrate 52 by a suitable method (such as spin coating, other suitable methods, or combinations thereof).

[0043] refer to Figure 4 and Figure 4C In operation 66 of method 60, an external electric field E is applied to the mixed solution 54. The external electric field E is configured in a direction such that heat transfer is along a pre-designed direction. In this example, the external electric field E is along the X direction, so that the director of the liquid crystal material in the mixed solution 54 is aligned along the external electric field E in the X direction.

[0044] refer to Figure 4 and Figure 4D In operation 68 of method 60, radiation such as ultraviolet (UV) radiation is applied to the mixed solution 54 to cure the mixed solution 54, thereby forming the liquid crystal material layer 50. In particular, when the UV radiation is applied to the mixed solution 54, the external electric field E remains unchanged. Therefore, the liquid crystal material layer 50 is anisotropic, and the heat transfer of the liquid crystal material layer 50 is directional and mainly along a pre-designed direction. In this example, the external electric field E is along the X direction, so that the director of the liquid crystal material layer 50 is aligned along the external electric field E in the X direction, and the heat transfer of the liquid crystal material layer 50 is mainly along the X direction.

[0045] refer to Figure 4E, whereby the liquid crystal material layer 50 formed on the substrate 52 provides anisotropic thermal conductivity. More specifically, thermal energy flows primarily along the X direction, while there is less or negligible heat transfer along the Z direction.

[0046] The disclosed embodiments provide various anisotropic heat dissipation materials, such as a liquid crystal material layer or a polymer material layer having anisotropic thermal conductivity, collectively referred to as anisotropic heat dissipation materials (AHDM). Those anisotropic heat dissipation materials can be applied to a semiconductor substrate on which various IC devices are formed; or applied as bottom filling materials in a 3DIC package, which will be further described below in conjunction with other drawings.

[0047] In some embodiments, the disclosed IC structure includes a semiconductor substrate on which a CFET is formed and doped with an anisotropic heat dissipation material layer. The IC structure is formed by appropriate procedures at various manufacturing stages, such as a monolithic process. According to some embodiments, the monolithic process is described below. A semiconductor stack of Si / SiGe is formed and patterned on a first substrate to form a fin active area, a dummy gate stack is formed by deposition and patterning, a source / drain (S / D) region is recessed by etching, a bottom gate isolation layer is formed, an internal spacer is formed by deposition and etching, a bottom S / D component is formed by epitaxial growth, a bottom S / D isolation layer is formed, a top S / D component is formed on the bottom S / D isolation layer, the dummy gate is removed, the SiGe layer is removed by etching to release the channel, a bottom metal gate stack is formed to wrap the bottom channel, a top metal gate stack is formed to wrap the top channel, a self-aligned cap (SAC) is formed, and an interconnect structure is formed.

[0048] The second substrate (e.g., a carrier substrate) is bonded to the first substrate. The first substrate is thinned downward from the back side, and an anisotropic heat dissipation material layer is formed on the back side of the first substrate. Other structures such as backside vias and backside interconnect structures may be further formed on the anisotropic heat dissipation material layer. Optionally, backside vias and backside interconnect structures are formed on the back side of the first substrate. Thereafter, an anisotropic heat dissipation material layer is formed on the backside interconnect structures.

[0049] In some embodiments, the first substrate is a semiconductor substrate, such as a silicon substrate, and the second substrate is a semiconductor substrate or alternatively a dielectric substrate, such as one of a silicon nitride substrate, a silicon oxide substrate, and an aluminum oxide substrate.

[0050] The IC structure with anisotropic heat dissipation material layer and the method for manufacturing the same are described in further detail below. According to some embodiments, an IC structure formed by a monolithic process is described below. Figure 5 is a cross-sectional view of an IC structure 100 having a CFET, according to some embodiments.

[0051] refer to Figure 5 , the IC structure 100 with CFET is formed by a monolithic method. As an exemplary embodiment, Figure 5 A CFET device formed on a substrate 102 is shown, wherein an n-type FET (NFET) and a p-type FET (PFET) are stacked vertically on each other, with reduced circuit area and improved device performance. The CFET device can be formed in any suitable procedure, such as a monolithic process, a sequential process, a parallel process, other suitable processes, or a combination thereof. Taking a monolithic process as an example, in a monolithic process, an NFET and a PFET are formed on the same substrate, such as forming the NFET first, and then forming the PFET on the same substrate 102.

[0052] IC structure 100 includes various field effect transistors formed on substrate 102, each FET device having multiple channels stacked vertically, such as a gate all around (GAA) structure. Specifically, bottom device 104B (such as a PFET) and top device 104T (such as an NFET) are stacked vertically on each other.

[0053] More specifically, the bottom device 104B of the IC structure 100 includes a plurality of channels 106; a gate stack 108 surrounding the channels 106; and a source / drain (S / D) feature 110 disposed on both sides of the channels 106 and connected to the vertically stacked channels 106. The bottom device 104B also includes an internal spacer 112 between the gate stack 108 and the S / D feature 110 to provide isolation therebetween. The internal spacer 112 includes one or more dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0054] The gate stack 108 also includes a gate dielectric layer 108b and a gate electrode 108a disposed on the gate dielectric layer. In the present embodiment, the gate dielectric layer 108b includes a high-k dielectric material, and the gate electrode 108a includes a metal or a metal alloy. In some examples, the gate electrode 108a may include a plurality of sublayers. The high-k dielectric material may include metal oxides, metal nitrides, such as LaO, AlO, ZrO, TiO, Ta, etc. 2 O 5 , Y 2 O 3 、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 、Si 3 N4 , oxynitride (SiON) or other suitable dielectric materials. The gate electrode 108a may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Ru, Co, any suitable conductive material or a combination thereof. In some embodiments, different metal materials are used for nFET and pFET devices with corresponding work functions to enhance device performance. In some embodiments, the gate stack 108 may also include an interface layer 108c between the channel 106 and the high-k dielectric material for improved integration. The interface layer 108c is a dielectric layer and may include silicon oxide.

[0055] Similarly, the top device 104T of the IC structure 100 includes a plurality of channels 206; a gate stack 208 surrounding the channels 206; and a source / drain (S / D) feature 210 disposed on both sides of the channels 206 and connected to the vertically stacked channels 206. The top device 104T also includes an internal spacer 212 between the gate stack 208 and the S / D feature 210 to provide isolation therebetween. The internal spacer 212 includes one or more dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0056] The gate stack 208 also includes a gate dielectric layer 208b and a gate electrode 208a disposed on the gate dielectric layer. In the present embodiment, the gate dielectric layer 208b includes a high-k dielectric material, and the gate electrode 208a includes a metal or a metal alloy. In some examples, the gate electrode 208a may include a plurality of sublayers. In some embodiments, different metal materials are used for nFET and pFET devices with corresponding work functions to enhance device performance. In some embodiments, the gate stack 208 may also include an interface layer 208c between the channel 206 and the high-k dielectric material for improved integration. The interface layer 208c may include silicon oxide.

[0057] The top device 104T (such as an NFET) and the bottom device 104B (such as a PFET) are vertically stacked and isolated from each other by isolation features (such as an S / D isolation feature 114 of one or more dielectric materials and a gate isolation layer 118 of one or more dielectric materials). In some embodiments, an etch stop layer 116 may be disposed around the S / D isolation feature 114 and include different dielectric materials to achieve etching selectivity.

[0058] The IC structure 100 also includes a gate spacer 220 of one or more dielectric materials disposed on the sidewalls of the gate stack 208; an S / D contact 222 of one or more conductive materials bonded to the S / D component 210 to couple the S / D component 210 to a power source; and a self-aligned cap (SAC) 226 of one or more dielectric materials aligned with and bonded to the gate stack 208. The S / D contact 222 can be further surrounded by a barrier layer 224 of one or more dielectric materials or optional conductive materials. In some examples, the barrier layer 224 includes a conductive material such as a titanium film and a titanium nitride film or a tantalum film and a tantalum nitride film. In some other examples, the barrier layer 224 includes a dielectric material such as silicon nitride, other suitable dielectric materials, or a combination thereof. In this example, the dielectric layer is deposited and etched by a plasma etching process to remove the bottom portion of the barrier layer to have good electrical routing.

[0059] Fig. 6A and Figure 6B is a process flow diagram of a method 300 of fabricating the IC structure 100 . Figures 7 to 14 3 is a cross-sectional view of the IC structure 100 at various stages of fabrication according to some embodiments. The IC structure 100 and the method 300 are collectively described below with reference to those figures.

[0060] refer to Fig. 6A and Figure 7 In operation 302, the method 300 receives or provides a workpiece having a substrate 102 and a semiconductor stack 120 having an alternating first semiconductor layer 120a and a second semiconductor layer 120b on the substrate 102. The first semiconductor layer 120a includes a first semiconductor material, the second semiconductor layer 120b includes a second semiconductor material, and an intermediate layer 120c of the first semiconductor layer 120a has a higher concentration of the first semiconductor material than the rest of the first semiconductor layer 120a. The first semiconductor layer and the second semiconductor layer are patterned to form one or more semiconductor stacks as active regions, such as fin active regions.

[0061] In the disclosed embodiment, substrate 102 is a semiconductor substrate, such as a silicon substrate. In some other embodiments, substrate 102 includes germanium, silicon germanium, or other suitable semiconductor materials. Substrate 102 may alternatively be made of: some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

[0062] In some embodiments, the first semiconductor material is silicon germanium, the second semiconductor is silicon, and the intermediate layer 120 c includes silicon germanium and has a higher germanium concentration than the rest of the first semiconductor layer 120 a .

[0063] In operation 304, the method 300 forms a dummy gate structure 124 over a channel region (CR) of the semiconductor stack 120. The dummy gate structure 124 includes a gate spacer 220 and a dummy gate stack 126. In operation 306, the method 300 forms a source / drain (S / D) trench 128 adjacent to the channel region CR, thereby exposing a side surface of the semiconductor stack 120.

[0064] refer to Fig. 6A and Figure 8 In operation 308 , the method 300 forms the inner spacer 112 in the channel region CR by a method such as a procedure including: selectively etching the first semiconductor layer 120 a ; depositing one or more dielectric materials; and plasma etching.

[0065] refer to Fig. 6A and Fig. 9 In operation 310, the method 300 epitaxially grows the first S / D feature 110 in the S / D trench 128. In operation 312, the method 300 forms S / D isolation layers 114, 116 over the first S / D feature 110 by a method such as a procedure including: depositing an etch stop layer 116; depositing a dielectric material layer 114; performing a chemical mechanical polishing (CMP) process; and etching back to recess the S / D isolation layers 114, 116.

[0066] Still reference Fig. 6A and Fig. 9 At operation 314 , the method 300 epitaxially grows the second S / D feature 210 in the S / D trench 128 and over the S / D isolation layers 114 , 116 .

[0067] refer to Figure 6B and Fig. 9 In operation 316, the method 300 forms an interlayer dielectric (ILD) layer 130 over the second S / D feature 210 by a method such as a process including deposition and CMP. The ILD structure may also include an etch stop layer 132 having a dielectric material different from the bulk dielectric material of the ILD layer 130 to achieve etch selectivity.

[0068] refer to Figure 6B and Fig.10 In operation 318 , the method 300 removes the dummy gate stack 126 from the dummy gate structure 124 , creating the gate trench 134 . In operation 320 , the method 300 removes the intermediate layer 120 c and replaces it with the gate isolation layer 118 .

[0069] refer to Figure 6B and Fig.11In operation 322 , the method 300 forms suspended semiconductor channels 106 , 206 by removing the remaining first semiconductor layer 120 a and leaving the second semiconductor layer 120 b as the suspended semiconductor channels 106 , 206 , respectively.

[0070] refer to Figure 6B and Fig.12 In operation 324, the method 300 forms a gate dielectric layer (referred to as 108b, 108c and 208b, 208c, respectively) over the channel region CR, wrapping each or a subset of the suspended semiconductor channels 106, 206. In particular, the dielectric layers 108c, 208c are interface layers; and the dielectric layers 108b, 208b are high-k dielectric material layers.

[0071] refer to Figure 6B and Fig.13 In operation 326, method 300 may perform a treatment on the gate dielectric layer, such as thermal annealing. In operation 328, method 300 deposits one or more gate electrode materials (such as metals or metal alloys) over the gate dielectric layer. After forming the gate electrodes 108a, 208a, metal gate structures 108, 208 are formed. The gate electrode may include one or more metal layers having different compositions. In addition, the materials used for the gate electrodes 108a and 208a may have different materials, such as metals having different work functions.

[0072] refer to Figure 6B and Fig.14In operation 330, the method 300 forms S / D contacts 222, 224 over the first S / D component and the second S / D component by an appropriate method, such as a procedure including patterning, deposition, and CMP processes. In operation 332, the method 300 may form a SAC component 226 that is self-aligned with the gate stack 208 by a method, such as a procedure including etching to recess the gate stack, depositing one or more dielectric materials, and performing a CMP process. The method 300 may perform other operations to complete the manufacture of the IC structure 100. The disclosed embodiments contemplate additional processing. Additional operations may be provided before, during, and after the method 300, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 300. For example, an interconnect structure 230 may be further formed to couple various devices into the integrated circuit, and other components such as a bonding layer 232 may be further formed on the interconnect structure to provide a bonding surface. In some embodiments, the interconnect structure 230 includes contacts, vias, and metal lines distributed in multiple metal layers. In a copper interconnect, the conductive component includes copper and may also include a barrier layer. The copper interconnect structure is formed by a damascene process. The damascene process includes: depositing an ILD layer; patterning the ILD layer to form a groove; depositing various materials (such as a barrier layer and copper); and performing a CMP process. The damascene process can be a single damascene process or a dual damascene process. The deposition of copper can include PVD to form a seed layer and plating to form bulk copper on the copper seed layer. Other metals such as ruthenium, cobalt, tungsten, or aluminum can be used to form the interconnect structure.

[0073] The IC structure 100 thus formed is further bonded to a carrier substrate and incorporated with an anisotropic heat dissipation material layer by the disclosed method. Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 Described in further detail. Fig.15 is a flow chart of method 350, Fig.16 , Fig.17 , Fig.18 and Fig.19 is a cross-sectional view of an IC structure (or workpiece) 250 at various stages of fabrication, constructed in accordance with some embodiments.

[0074] refer to Fig.15 and Fig.16, the method 350 continues in block 352 by receiving or providing a carrier substrate 240. In some embodiments, the carrier substrate (or second substrate) 240 is a dielectric substrate, such as a silicon nitride substrate, a silicon oxide substrate, or an aluminum oxide substrate. In some embodiments, the carrier substrate 240 is a semiconductor substrate (such as a silicon substrate) or alternatively a substrate having other suitable materials. In yet other embodiments, the carrier substrate 240 is a semiconductor substrate on which various devices are formed.

[0075] Still reference Fig.15 and Fig.16 In operation 354, method 350 bonds carrier substrate 240 to the front side of IC structure 100 (via Fig. 6A and Figure 6B The method 300 is formed as follows Fig.14 ), so that the carrier substrate 240 is bonded to the bonding layer 232 of the IC structure 100, resulting in a bonded IC structure 250. In some embodiments, the carrier substrate 240 also includes various devices formed thereon; interconnect structures formed on the corresponding devices; and a passivation layer formed on the interconnect structures. In an advancement of the embodiment, the carrier substrate 240 is bonded to the IC structure 100 in a front-to-front bonding mode, so that the IC structure 100 and the carrier substrate 240 are electrically connected through a bonding interface having a hybrid bonding structure, resulting in a bonded IC structure 250.

[0076] refer to Fig.15 and Fig.17 After bonding, the method 350 proceeds to operation 356 to thin the first substrate 102 from the back side downward. In some embodiments, operation 356 includes: performing a grinding process to reduce the thickness of the first substrate 102; and performing a chemical mechanical polishing (CMP) process to planarize the surface.

[0077] Still reference Fig.15 and Fig.17 In operation 358, an anisotropic heat dissipation material layer 242 is formed on the back side of the first substrate 102 by a suitable method. In some embodiments, the anisotropic heat dissipation material layer 242 can be a liquid crystal material, such as Figure 3A The anisotropic heat dissipation material layer 242 of the liquid crystal material is formed by a suitable method, such as FIG. 4A to FIG. 4E The method described in .

[0078] In some embodiments, the anisotropic heat dissipation material layer 242 may be a polymeric material such as Figure 1 and FIG. 2C to FIG. 2EThe polymer anisotropic heat dissipation material layer 242 is formed on the IC structure by a suitable method. In an embodiment, the first substrate 102 includes a dielectric surface layer (or simply a dielectric layer) of one or more dielectric materials disposed on the back side, such as Figure 2A The dielectric surface layer 26 of silicon oxide or Figure 2B The dielectric surface layer 28 of silicon nitride or silicon carbon nitride oxide in the first substrate 102 is formed by a suitable method, such as chemical vapor deposition (CVD). In this example, operation 358 also includes depositing a dielectric surface layer on the back side of the first substrate 102. The dielectric surface layer also includes chemical groups (such as OH groups or NH 2 group).

[0079] In some embodiments, the first substrate 102 includes a dielectric surface layer of silicon oxide having OH groups, which are inherently present on the surface. The OH groups on the dielectric surface layer of silicon oxide chemically react with the chemical groups R of the conical bottle brush polymer 20, thereby forming a chemical bond and fixing the conical bottle brush polymer 20 on the first substrate 102. In some embodiments, the dielectric surface layer of silicon oxide is further treated with an appropriate treatment (such as ozone or hydrogen peroxide treatment) to introduce OH groups into the dielectric surface layer 26. For example, the IC structure 250 is placed in an ozone or hydrogen peroxide environment for a certain duration at an elevated temperature to form a silicon oxide layer on the back side of the first substrate 102 before forming the anisotropic heat dissipation material layer 242 on the first substrate 102. In this example, operation 358 also includes a step of treating the dielectric surface layer with ozone or hydrogen peroxide.

[0080] In some embodiments, the first substrate 102 includes NH 2 The dielectric surface layer of silicon nitride or silicon oxycarbonitride, NH 2 The NH groups are inherently present on the surface. 2 The groups chemically react with the chemical groups R of the conical bottle brush polymer 20 , thereby forming chemical bonds and fixing the conical bottle brush polymer 20 on the first substrate 102 .

[0081] refer to Fig.15 and Fig.18In operation 360, a backside interconnect structure 244 may be formed on the back side of the first substrate 102 (such as above the anisotropic heat dissipation material layer 242). In some embodiments, the backside interconnect structure 244 is configured to couple to the CFET on the front side of the first substrate 102. The backside interconnect structure 244 includes various conductive features, such as metal lines and metal vias distributed through one or more layers. In some embodiments, the backside vias are formed through the anisotropic heat dissipation material layer 242 to electrically couple with the CFET.

[0082] In some optional embodiments, operation 356 thins the first substrate 102 downward from the back side, thereby exposing the CFET from the back side. In this example, an anisotropic heat dissipation material layer 242 is formed on the back side of the IC structure and is configured to be close to the CFET for effective heat dissipation, such as Fig.19 . Other structures or components (such as backside interconnect structure 244) can be formed on the back side of IC structure 100 and disposed on anisotropic heat dissipation material layer 242. Method 350 can include other manufacturing operations 362 before, during, or after the operations described above. The disclosed IC structure 250 provides a mechanism for transferring heat laterally in a direction parallel to the surface of substrate 102 (such as in the X direction), thereby effectively dissipating heat and reducing the thermal energy generated from IC devices (such as CFETs).

[0083] In some embodiments, the IC structure may be formed differently in structure and method, such as Figure 20 to Figure 23 as shown in . Fig. 20 is a flow chart of method 380, Fig.21 , Fig. 22 and Fig.23 is a cross-sectional view of an IC structure (or workpiece) 280 constructed in accordance with some embodiments at various stages of fabrication.

[0084] refer to Fig. 20 and Fig.21 The method 380 begins at operation 382 by receiving or providing a carrier substrate 240. In some embodiments, the carrier substrate (or second substrate) 240 is a dielectric substrate, such as a silicon nitride substrate, a silicon oxide substrate, or an aluminum oxide substrate. In some embodiments, the carrier substrate 240 is a semiconductor substrate (such as a silicon substrate) or optionally a substrate having other suitable materials.

[0085] Still reference Fig. 20 and Fig.21 , the method 380 proceeds to operation 384. In operation 384, an anisotropic heat dissipation material layer 242 is formed on the carrier substrate 240, thereby forming a carrier substrate structure 246. The process of forming the anisotropic heat dissipation material layer 242 on the carrier substrate 240 can be any suitable method, such as FIG. 4A to FIG. 4EIn some embodiments, the anisotropic heat dissipation material layer 242 may be a polymer material or a liquid crystal material, such as Figure 1 , FIG. 2C to FIG. 2E and Figure 3A Those described in .

[0086] refer to Fig. 20 and Fig. 22 The method 380 proceeds to operation 386 to thin the first substrate 102 of the IC structure 100 downward from the back side (via Fig. 6A and Figure 6B The method 300 is formed as follows Fig.14 In some embodiments, the downward thinning process includes grinding and CMP processes. In some embodiments, the downward thinning process continues until the CFET of the IC structure 100 is exposed from the back side.

[0087] refer to Fig. 20 and Fig.23 In operation 388, the method 380 bonds the carrier substrate structure 246 to the IC structure 100 in a front-to-back bonding mode, so that the anisotropic heat dissipation material layer 242 is bonded to the back side of the substrate 102 of the IC structure 100, resulting in a bonded IC structure 280. The anisotropic heat dissipation material layer 242 is similar in composition, configuration, and formation to the IC structure 100. Figures 17 to 19 The anisotropic heat dissipation material layer 242 is formed in the heat dissipation device.

[0088] Method 380 may include other manufacturing operations 390 before, during, or after the operations described above. For example, in operation 390, IC structure 280 is stacked to another IC structure (or bonded to another substrate) and further sealed in the same package structure by a 2.5D or 3D IC package structure.

[0089] Anisotropic heat dissipation materials can be incorporated into other IC structures, such as 2.5D or 3D IC packaging structures, such as Fig.24 and Fig.25 as shown in . Fig.24 and Fig.25 are cross-sectional views of IC structures 400 and 450 , respectively, constructed according to various embodiments.

[0090] refer to Fig.24, IC structure 400 includes substrates 402 and 404. In some embodiments, substrate 402 (or substrate 404) is a dielectric substrate, such as a silicon nitride substrate, a silicon oxide substrate, or an aluminum oxide substrate. In some embodiments, substrate 402 (or substrate 404) is a semiconductor substrate (such as a silicon substrate) or optionally a substrate having other suitable materials. In some other embodiments, substrate 402 (or substrate 404) is an IC structure having various IC devices (such as FETs or CFETs) formed on the corresponding substrate; interconnect structures formed on the devices; and passivation structures formed on the interconnect structures.

[0091] IC structure 400 also includes various IC chips (or IC dies) 406 disposed between substrates 402 and 404. One or more of IC chips 406 may have a Fig.19 or Fig.23 The structure of the IC structure 100 in FIG. Those IC chips 406 are configured to be located laterally on the substrate or vertically in the stack or a combination thereof. For example, the IC chip 406 includes three IC chips 406A, 406B and 406C. However, this only shows a specific example. The IC structure 400 may include any appropriate number of IC chips 406, such as 4 or 5 IC chips 406. The IC chip 406 may be any suitable chip, such as a memory chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input / output (I / O) chip or a combination thereof. For example, the IC chip 406 includes an IC chip 406A as a CPU chip, an IC chip 406B as a memory chip, and an IC chip 406C as an I / O chip, collectively referred to as IC chips 406. Those IC chips 406 are electrically connected and integrated into the integrated circuit. The electrical connections between those IC chips 406 are achieved through any suitable structure, such as flip chip, hybrid bonding, controlled collapse chip connection (C4), through substrate via (TSV), or a combination thereof.

[0092] Those IC chips 406 are integrated in any suitable configuration. For example, IC chip 406B is stacked on IC chip 406A to form a chip stack, and IC chip 406C is configured above IC chips 406A and 406B. In some embodiments, one or more spacers 408 are incorporated, such as vertically between IC chips 406A and 406C to support IC chip 406C. Spacer 408 is a component with a suitable shape and size to be placed in the interval between IC chips 406A and 406C. Spacer 408 can be made of any suitable material, such as metal.

[0093] The IC structure 400 is sealed in the same package using one or more sealing materials, one or more bottom filling materials, or a combination thereof. In the disclosed embodiment, the IC structure 400 includes a sealing material 410, which is an anisotropic heat dissipation material or a sealing material in which an anisotropic heat dissipation material is incorporated. For example, the sealing material 410 includes an anisotropic heat dissipation polymer material dispersed therein. In another example, the sealing material 410 is an anisotropic heat dissipation liquid crystal material in which the sealing material is dispersed.

[0094] Therefore, the sealing material 410 provides anisotropic thermal conductivity and can also provide a sealing effect. Fig.24 The IC structure 400 can effectively transfer heat in a directional or lateral manner, dissipate heat, reduce heat accumulation, and prevent thermal damage.

[0095] IC structure 400 also includes conductive bumps 412 formed on the back side of substrate 402, to provide electrical wiring to package substrate, another substrate or printed circuit board. In some embodiments, conductive bumps 412 are solder balls. Conductive bumps 412 are electrically connected to the IC chip by suitable structure or mechanism (such as TSV formed in substrate 402). In the disclosed embodiment, IC chip 406A is bonded to substrate 402, and IC chip 406B is stacked on IC chip 406A. IC chip 406A, 406B and substrate 402 are sealed in a first sealed package. IC chip 406C is bonded to substrate 404, and is sealed in a second sealed package. Two sealed packages are further bonded and sealed to have a package in package (PIP) structure.

[0096] refer to Fig.25 , IC structure 450 includes substrates 402 and 404. In some embodiments, substrate 402 (or substrate 404) is a dielectric substrate, such as a silicon nitride substrate, a silicon oxide substrate, or an aluminum oxide substrate. In some embodiments, substrate 402 (or substrate 404) is a semiconductor substrate (such as a silicon substrate) or optionally a substrate having other suitable materials. In some other embodiments, substrate 402 (or substrate 404) is an IC structure having various IC devices (such as FETs or CFETs) formed on the corresponding substrate; interconnect structures formed on the devices; and passivation structures formed on the interconnect structures.

[0097] IC structure 450 also includes individual IC chips (or IC dies) 406 disposed between substrates 402 and 404. Those IC chips 406 are configured to be located laterally on the substrate or vertically in a stack or a combination thereof. For example, IC chip 406 includes three IC chips 406A, 406B, and 406C. However, this is merely a specific example. IC structure 450 may include any appropriate number of IC chips 406, such as 4 or 5 IC chips 406. One or more IC chips 406 have a configuration such as Fig.19 or Fig.23 The structure of the IC structure 100 in FIG. The IC chip 406 can be any appropriate chip, such as a memory chip, a CPU chip, a GPU chip, an I / O chip, or a combination thereof. For example, the IC chip 406 includes an IC chip 406A as a CPU chip, an IC chip 406B as a memory chip, and an IC chip 406C as an I / O chip, collectively referred to as IC chips 406. Those IC chips 406 are electrically connected and integrated into an integrated circuit. The electrical connection between those IC chips 406 is achieved by any appropriate structure, such as a flip chip, a hybrid bond, C4, TSV, or a combination thereof.

[0098] Those IC chips 406 are integrated in any suitable configuration. For example, IC chip 406B is stacked on IC chip 406A to form a chip stack, and IC chip 406C is bonded to and electrically connected to substrate 404 .

[0099] The IC structure 450 is sealed using one or more sealing materials. In the disclosed embodiment, the IC structure 450 includes a sealing material 410, which is an anisotropic heat dissipation material or a sealing material in which an anisotropic heat dissipation material is incorporated. For example, the sealing material 410 includes an anisotropic thermal polymer material dispersed therein. In another example, the sealing material 410 is an anisotropic heat dissipation liquid crystal material in which the sealing material is dispersed.

[0100] Thus, the sealing material 410 provides anisotropic thermal conduction and can transfer heat directionally in addition to the sealing effect, such as Fig.25 The arrows in the figure show the lateral heat transfer.

[0101] IC structure 450 also includes conductive bumps 412 formed on the back side of substrate 402 to provide electrical routing to a package substrate, another substrate, or a printed circuit board. In some embodiments, conductive bumps 412 are solder balls. Conductive bumps 412 are electrically connected to the IC chip by appropriate structures or mechanisms (such as TSVs formed in substrate 402).

[0102] In the disclosed embodiment, IC chip 406A is bonded to substrate 402, and IC chip 406B is stacked on IC chip 406A. IC chip 406A, 406B and substrate 402 are sealed in a first sealed package using sealing material 410A. IC chip 406C is bonded to substrate 404, and is sealed in a second sealed package using sealing material 410B. The second sealed package is stacked on a first sealed package (POP) structure. IC chip 406C is electrically connected to IC chip 406A and 406B by a suitable mechanism. For example, IC structure 450 also includes a conductive bump 416 formed between substrates 402 and 404, to provide electrical wiring between them and further to IC chip 406. For example, substrate 404 includes TSVs that electrically connect conductive bump 416 to IC chip 406C, and substrate 402 includes TSVs that electrically connect conductive bump 416 to conductive bump 412 and that electrically connect IC chips 406A and 406B to conductive bump 412. An underfill material may be filled in the space between substrates 402 and 404 to reinforce and seal conductive bump 416.

[0103] In some embodiments, the sealing materials 410A and 410B are different. For example, the sealing material 410A includes an anisotropic heat dissipation liquid crystal material, while the sealing material 410B includes an anisotropic heat dissipation polymer material. The IC structure 450 can effectively transfer heat in a directional manner, dissipate heat, reduce heat accumulation, and prevent thermal damage.

[0104] Fig.24 and Fig.25 Two embodiments are shown in which anisotropic heat dissipation materials are incorporated into 3DIC structures for directional heat dissipation. However, this is not intended to be limiting. Other 3DIC structures with anisotropic heat dissipation materials incorporated into IC packages are within the scope of the disclosed embodiments. According to some embodiments, the following reference Fig.26 and Fig. 27 Other IC structures are further described.

[0105] Fig.26 5 is a schematic diagram of an IC structure 500 constructed according to some embodiments. The IC structure 500 includes: a substrate 510, such as a semiconductor substrate or other suitable substrate; a first IC chip 512 and a second IC chip 514 formed on the substrate 510 in the same package 516. In some embodiments, at least one of the IC chips 512 and 514 has a Fig.19 or Fig.23The structure of the IC structure 100 in the package. In some embodiments, the packaged IC structure is mounted and connected to a printed circuit board (PCB) 518 or other suitable circuit board. In some embodiments, the first IC chip 512 and the second IC chip 514 are directly formed on the same substrate 510, or are formed at different levels in the 3D structure, but in the same package 516. In some embodiments, the first IC chip 512 is a CPU die, and the second IC chip 514 is a memory chip. The IC chips 512 and 514 are packaged together in a 3DIC structure, such as a chip on wafer (COW), a chip on wafer on substrate (CoWoS), and other suitable 3D structures. In the disclosed IC structure, each of the IC chips 512 and 514 also includes various active and passive electronic devices, such as FETs, FinFETs, and other multi-gate devices, such multi-gate devices including full-ring gate (GAA) devices. In particular, the package 516 incorporates anisotropic heat dissipation materials, such as anisotropic heat dissipation materials dispersed with sealing materials. IC structure 500 may effectively transfer heat directionally, such as transferring heat horizontally over substrate 510 .

[0106] Fig. 27 6 is a partial cross-sectional view of part or all of an IC structure 600 provided by arranging a chipset using a combination of multi-chip packaging technologies (such as a chip-on-wafer-on-substrate (CoWoS) packaging technology, a system-on-integrated-chip (SoIC) multi-chip packaging technology, an integrated fan-out (InFO) package) according to various aspects of the embodiments of the present disclosure. It should be noted that Fig. 27The IC structure 100 in FIG. 6 is for illustration only, and the IC structure 600 may have other structures, such as other 3D structures. The IC structure 600 (which may be referred to as a 3D IC package and / or a 3D IC module) includes a CoW structure 602 attached to a substrate 604 (e.g., a package substrate), which includes a package component 604A and a package component 604B in the depicted embodiment. The CoW structure 602 includes a chipset (e.g., a core chip 606-1, a core chip 606-2, a photonic chip 607, a memory chip 608-1, a memory chip 608-2, an input / output (I / O) chip 610-1, and an I / O chip 610-2) attached to an interposer 615. The chipset is arranged into at least one chip stack, such as a chip stack 620A and a chip stack 620B. Chip stack 620A includes core chip 606-2 and photonic chip 607, and chip stack 620B includes I / O chip 610-1 and I / O chip 610-2. In the depicted embodiment, the chips of chip stack 620A and chip stack 620B are directly bonded face-to-face and / or face-to-back to provide a SoIC package of a multi-chip package. In some embodiments, the chip stack of the multi-chip package includes a combination of chip types, such as a core chip with one or more memory chips disposed thereon. The schematic diagram has been simplified for clarity. Fig. 27 , to better understand the inventive concepts of the disclosed embodiments. Additional components may be added in a multi-chip package, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-chip package.

[0107] Core chip 606-1 and core chip 606-2 are central processing unit (CPU) chips and / or other chips. In some embodiments, core chip 606-1 is a CPU chip that forms at least part of a CPU cluster, and core chip 606-2 is a GPU chip. In some embodiments, core chip 606-1 and core chip 606-2 or a combination thereof represent a stack of CPU dies, which can be joined and / or sealed in a manner that provides a CPU package and / or a CPU-based SoIC package. In some embodiments, core chip 606-1 and core chip 606-2 or a combination thereof represent a stack of dies, which can be joined and / or sealed in a manner that provides a GPU package and / or a SoIC package (e.g., a GPU-based SoIC package). In some embodiments, core chip 606-1, core chip 606-2 or a combination thereof represent a stack of CPU dies, which can be joined and / or sealed in a manner that provides a core package and / or a core-based SoIC package. In some embodiments, core chip 606 - 1 , core chip 606 - 2 , or a combination thereof is a SOC.

[0108] Memory chip 608-1 and memory chip 608-2 are high bandwidth memory (HBM) chips, graphic double data rate (GDDR) memory chips, dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, magnetoresistive random access memory (MRAM) chips, resistive random access memory (RRAM) chips, other suitable memory chips, or combinations thereof. In some embodiments, memory chip 608-1 and memory chip 608-2 are HBM chips that form at least part of a memory device. In some embodiments, memory chip 608-1 and memory chip 608-2 are GDDR memory chips that form at least part of a memory device. In some embodiments, memory chip 608-1 is an HBM chip, and memory chip 608-2 is a GDDR memory chip that forms at least part of a memory device, or vice versa. In some embodiments, memory chip 608-1 and / or memory chip 608-2 represent a stack of memory dies that can be bonded and / or sealed in a manner that provides a memory package and / or a memory-based SoIC package. The memory package may be an HBM package (also referred to as an HBM cube) or a GDDR memory package.

[0109] The core chip 606-1, the core chip 606-2 and the photonic chip 607 (and therefore the chip stack 620A), the memory chip 608-1, the memory chip 608-2 and the I / O chip 610-1 and the I / O chip 610-2 (and therefore the chip stack 620B) are attached and / or interconnected to the interposer 615. The interposer 615 is attached and / or interconnected to the substrate 604. Various bonding mechanisms such as conductive bumps 622 (e.g., metal bumps), semiconductor through vias (TSVs) 624, bonding pads 626, or combinations thereof can be implemented in the multi-chip package. For example, the conductive bumps 622 physically and / or electrically connect the core chip 606-1, the photonic chip 607 (and therefore the chip stack 620A), the memory chip 608-1, the memory chip 608-2 and the I / O chip 610-1 (and therefore the chip stack 620B) to the interposer 615. Conductive bumps 622 and TSVs 624 physically and / or electrically connect the interposer 615 to the substrate 604. The TSVs 624 of the interposer 615 are electrically connected to the conductive bumps 622 of the chips and / or chip stacks of the CoW structure 602 through the conductive wiring structures (paths) 628 of the interposer 615. The bonding pads 626 physically and / or electrically connect the photonic chips 607 and the core chips 606-2 of the chip stack 620A and the I / O chips 610-1 and 610-2 of the chip stack 620B. In addition, the dielectric bonding layer adjacent to the bonding pads 626 can physically contact the photonic chips 607 and the core chips 606-2 of the chip stack 620A and / or the I / O chips 610-1 and 610-2 of the chip stack 620B. In some embodiments, the conductive bumps 622 connecting the chip and / or chip stack to the interposer 615 may be microbumps, and the conductive bumps 622 connecting the interposer 615 to the substrate 604 may be controlled collapse chip connections (referred to as C4 bonds) (e.g., solder bumps and / or solder balls). In some embodiments, at least one of those IC chips has a Fig.19 or Fig.23 1. The structure of the IC structure 100 in FIG.

[0110] In some embodiments, substrate 604 is a package substrate, such as a coreless substrate or a substrate with a core, that can be physically and / or electrically connected to another component through electrical connector 630. Electrical connector 630 is electrically connected to conductive bump 622 of interposer 615 through conductive wiring structure (path) 632 of substrate 604. In some embodiments, package component 604A and package component 604B are parts of a single package substrate. In some embodiments, package component 604A and package component 604B are separate package substrates arranged side by side. In some embodiments, substrate 604 is an interposer. In some embodiments, substrate 604 is a printed circuit board (PCB).

[0111] In some embodiments, the interposer 615 is a semiconductor substrate, such as a silicon wafer (which may be generally referred to as a silicon interposer). In some embodiments, the interposer 615 is a laminate substrate, a core package substrate, a coreless package substrate, etc. In some embodiments, the interposer 615 may include an organic dielectric material, such as a polymer, which may include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer-based materials, or combinations thereof. In some embodiments, a redistribution line (layer) (RDL) may be formed in the interposer 615 (such as within the organic dielectric material of the interposer 615). The RDL may form part of the conductive wiring structure 628 of the interposer 615. In some embodiments, the RDL electrically connects the bonding pads on one side of the interposer 615 (e.g., the top side of the interposer 615 to which the chipset is attached) to the bonding pads on the other side of the interposer 615 (e.g., the bottom side of the interposer 615 to which the substrate 604 is attached). In some embodiments, the RDL electrically connects the bonding pads on the top side of the interposer 615, which may electrically connect the chips of the chipset. In the disclosed embodiments, one or more deep trench capacitors 616 may be embedded in the interposer 615 .

[0112] In some embodiments, the multi-chip package can be configured as a 2.5D IC package and / or a 2.5D IC module by rearranging the chipset so that each chip is bonded and / or attached to the interposer 615. In other words, the 2.5D IC module does not include chip stacks, such as chip stack 620A and chip stack 620B, and the chips of the chipset are arranged in a single plane. In such an embodiment, the core chip 606-2 and the I / O chip 610-2 are electrically connected and / or physically connected to the interposer through the conductive bumps 622.

[0113] In particular, the IC structure 600 is sealed in the package using a sealing material 636. In this embodiment, the sealing material 636 includes the anisotropic heat dissipation material described above. The IC structure 600 with the anisotropic heat dissipation material in the sealed package provides a mechanism for effectively transferring heat in a directional manner, such as transferring heat horizontally above the substrate 604.

[0114] Fig.28 is a cross-sectional view of a portion of an IC structure 100 constructed in accordance with some embodiments. Fig.29 is a cross-sectional view of a portion of an IC structure 100 constructed according to some embodiments. The IC structure 100 is similar to Figure 5 IC structure 100. However, in Fig.28 and Fig.29 Only a portion of the interconnect structure 230 in the IC structure 100 is shown.

[0115] refer to Fig.28 , IC structure 100 (such as Figure 5 The IC structure 100 in FIG. 1 includes an interconnect structure 230 formed on the CFET and coupling the CFET and other devices to the integrated circuit. The interconnect structure 230 includes metal lines distributed in multiple metal layers, such as a metal line M1 in a first metal layer, a metal line M2 in a second metal layer above the first metal layer, ..., a metal line Mn in an n-th metal layer, a metal line Mn+1 in an (n+1)-th metal layer above the n-th metal layer, ..., and so on. Metal lines in adjacent metal layers are connected by via features, such as V1, V2, ..., Vn, ..., and so on. Fig.28 as shown in .

[0116] refer to Fig.29 The interconnect structure 230 is further described. Fig.29 , metal lines Mn, Mn+1, and Mn+2 and vias Vn and Vn+1 are shown. The metal lines and vias are formed in an interlayer dielectric (ILD) layer 652. The metal lines and vias may include metals, metal alloys, other conductive materials, or combinations thereof. For example, the metal lines and vias may include copper, aluminum, copper alloys, nickel, cobalt, tungsten, or combinations thereof. The ILD layer 652 includes one or more dielectric materials, such as silicon oxycarbide (SiOC), silicon oxide (SiO x ), organic silicate glass (SiCOH), SiCNH, low-k dielectric materials, or combinations thereof. Metal lines and vias are formed by any suitable method, such as a damascene process, such as a dual damascene process and a single damascene process. In the damascene process, an ILD layer is deposited and patterned to form a trench; one or more conductive materials are deposited to fill in the trench; and a CMP process is applied to remove excess metal and planarize the top surface.

[0117] The interconnect structure 230 may also include one or more etch stop layers (such as etch stop layers 650 and 656) to stop etching during the process of forming metal lines and vias, such as in a damascene process. The etch stop layer (such as 650 or 656) includes one or more dielectric materials that are different from the material of the ILD layer to achieve etch selectivity and effectively stop the etching process applied to the ILD layer. The etch stop layer may include SiCO, AlO x , AlN, SiCON, SiCH, SiCOH, SiCNH, other suitable dielectric materials or combinations thereof. In some embodiments, each etch stop layer may include two or more dielectric films to enhance etching selectivity. For example, the etch stop layer 650 includes an AlN film, a SiCO film on the AlN film, an AlO film on the SiCO film, and a SiO film on the SiCO film. x Film and AlO xAnother SiCO film on top of the membrane.

[0118] In order to prevent metal from diffusing from the metal lines and vias to the ILD layer, a barrier layer 654 is further formed to surround the corresponding metal lines and vias. For example, after a trench is formed in the ILD layer during a damascene process, a barrier layer is formed on the sidewalls of the trench (such as by deposition and plasma etching), and thereafter, a metal (or metal alloy) is deposited on the barrier layer to fill the trench. In some embodiments, the barrier layer 654 may include AlN, AlO, or a plurality of other metals. x , SiCN, SiOC, other dielectric materials or combinations thereof.

[0119] In addition, anisotropic heat dissipation materials can be incorporated into the ILD layer 652, the etch stop layers 650, 656, the barrier layer 654, or a subset of the above layers to enhance heat dissipation. For example, anisotropic heat dissipation materials (such as the anisotropic heat dissipation liquid crystal materials or anisotropic heat dissipation polymer materials described above) are incorporated into the ILD layer 652. As described above, those anisotropic heat dissipation materials are electrically insulating but thermally conductive, and the ILD layer 652 (barrier layer 654 and / or etch stop layer 650 / 656) formed in this way can effectively transfer heat in a direction without interrupting the electrical insulation function of the ILD layer 652 (barrier layer 654 and / or etch stop layer 650 / 656).

[0120] According to various embodiments, the present disclosure provides an IC structure having a CFET device and an anisotropic heat dissipation material layer and a method for manufacturing the same. The anisotropic heat dissipation material layer is used for directional heat dissipation and can be additionally used for sealing, blocking, isolating, stopping etching, or a combination thereof. The disclosed IC structure can effectively transfer heat in a directional manner, dissipate heat, reduce heat accumulation, prevent thermal damage, and enhance the performance and reliability of the IC structure.

[0121] In one exemplary aspect, an embodiment of the present disclosure provides an integrated circuit (IC) structure. The IC structure includes a FET of a first type of conductivity, a second FET of a second type of conductivity opposite to the first type of conductivity, and an anisotropic heat dissipation structure disposed below the first FET. The second FET is stacked above the first FET along a first direction. The first FET also includes: a first channel, vertically stacked along the first direction, the first channel extending longitudinally along a second direction perpendicular to the first direction; a first source and a first drain, disposed on opposite sides of the first channel and contacting each of the first channel; and a first gate, between the first source and the first drain, and extending to wrap around each of the first channel. The second FET also includes: a second channel, vertically stacked along the first direction, the second channel extending longitudinally along the second direction; a second source and a second drain, disposed on opposite sides of the second channel and contacting each of the second channel; and a second gate, between the second source and the second drain, and extending to wrap around each of the second channel. The anisotropic heat dissipation structure includes an electrically insulating and thermally conductive anisotropic heat dissipation material having a first thermal conductivity along a first direction and a second thermal conductivity along a second direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

[0122] In another exemplary aspect, an embodiment of the present disclosure provides an integrated circuit (IC) structure. The IC structure includes: a first substrate having a first surface, the first surface having a normal direction along a first direction; a first IC chip bonded to the first substrate; and a second IC chip electrically connected to the first IC chip. The first IC chip and the second IC chip are sealed in the same package having a sealing material layer, and the sealing material layer includes a first anisotropic heat dissipation material. The first anisotropic heat dissipation material is thermally conductive, having a first thermal conductivity along the first direction and a second thermal conductivity along a second direction perpendicular to the first direction. The second thermal conductivity is substantially greater than the first thermal conductivity.

[0123] In another exemplary aspect, the disclosed embodiments provide a method for manufacturing an integrated circuit (IC) structure. The method includes: forming a circuit structure having a semiconductor device located on a front side of a substrate and an interconnect structure located above the semiconductor device; applying a solution to a back side of the substrate, the solution including a photosensitive material and a liquid crystal material; applying an electric field to the solution; and curing the solution when the electric field is applied to the solution.

[0124] Some embodiments of the present application provide an integrated circuit (IC) structure, including: a first field effect transistor (FET) of a first type of conductivity, wherein the first field effect transistor also includes: a first channel, vertically stacked along a first direction, the first channel extending longitudinally along a second direction perpendicular to the first direction; a first source and a first drain, arranged on opposite sides of the first channel and contacting each of the first channels; and a first gate, interposed between the first source and the first drain, and extending to wrap around each of the first channels; a second field effect transistor of a second type of conductivity opposite to the first type of conductivity, wherein the second field effect transistor is stacked along the first direction on the first drain. A first field effect transistor is provided above the first field effect transistor, and further includes: a second channel vertically stacked along the first direction, the second channel longitudinally extending along the second direction; a second source and a second drain disposed on opposite sides of the second channel and contacting each of the second channels; and a second gate disposed between the second source and the second drain and extending to wrap each of the second channels; and an anisotropic heat dissipation structure disposed below the first field effect transistor, wherein the anisotropic heat dissipation structure includes an electrically insulating and thermally conductive anisotropic heat dissipation material having a first thermal conductivity along the first direction and a second thermal conductivity along the second direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

[0125] In some embodiments, the anisotropic heat dissipation material comprises an anisotropic heat dissipation polymer. In some embodiments, the anisotropic heat dissipation polymer is a conical bottle brush polymer. In some embodiments, the integrated circuit structure comprises silicon oxide (SiO 2 ) dielectric surface layer; and the anisotropic heat dissipation polymer includes a chemical group R chemically bonded to the OH chemical group of the dielectric surface layer. In some embodiments, the integrated circuit structure includes a NH 2 A dielectric surface layer of silicon nitride (SiN) having a chemical group; and the anisotropic heat dissipation polymer includes the NH 2 In some embodiments, the integrated circuit structure includes a chemical group R having NH 2 A dielectric surface of silicon oxycarbon nitride (SiOCN) having a chemical group; and the anisotropic heat dissipation polymer includes the NH 2Chemical groups R chemically bonded to chemical groups. In some embodiments, the anisotropic heat dissipation material includes anisotropic heat dissipation liquid crystal. In some embodiments, the anisotropic heat dissipation material also includes a photoresist material mixed with the anisotropic heat dissipation liquid crystal. In some embodiments, the integrated circuit structure also includes an interconnect structure formed above the second field effect transistor and electrically connected to the first field effect transistor and the second field effect transistor, wherein the interconnect structure includes: an interlayer dielectric material (ILD) structure; and metal lines, distributed in a plurality of metal layers spaced apart along the first direction, the metal lines embedded in the interlayer dielectric material structure, wherein the anisotropic heat dissipation material is a first anisotropic heat dissipation material, and wherein the interlayer dielectric material structure also includes a second anisotropic heat dissipation material. In some embodiments, the interconnect structure also includes a dielectric barrier layer disposed on the sidewalls of the metal line; and the dielectric barrier layer includes a third anisotropic heat dissipation material. In some embodiments, the interlayer dielectric material structure further includes a first interlayer dielectric material layer, a second interlayer dielectric material layer, and an etch stop layer disposed between the first interlayer dielectric material layer and the second interlayer dielectric material layer, and wherein the etch stop layer includes a fourth anisotropic heat dissipation material. In some embodiments, the integrated circuit structure further includes: an integrated circuit chip electrically connected to the first field effect transistor and the second field effect transistor, wherein the integrated circuit chip, the first field effect transistor, and the second field effect transistor are sealed in the same package using a sealing material, and the sealing material includes another anisotropic heat dissipation material.

[0126] Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a first substrate having a first surface, the first surface having a normal direction along a first direction; a first integrated circuit chip bonded to the first substrate; and a second integrated circuit chip electrically connected to the first integrated circuit chip, wherein the first integrated circuit chip and the second integrated circuit chip are sealed in the same package having a sealing material layer, and the sealing material layer comprises a first anisotropic heat dissipation material, wherein the first anisotropic heat dissipation material is thermally conductive, having a first thermal conductivity along the first direction and a second thermal conductivity along a second direction perpendicular to the first direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

[0127] In some embodiments, the second integrated circuit chip is bonded to the first integrated circuit chip. In some embodiments, the integrated circuit structure further comprises: a second substrate; and a third integrated circuit chip bonded to the second substrate, wherein the third integrated circuit chip is electrically connected to the first integrated circuit chip and the second integrated circuit chip, and the second substrate, the first integrated circuit chip, the second integrated circuit chip and the third integrated circuit chip are sealed in a sealed package using a second sealing material, and the second sealing material comprises another anisotropic heat dissipation material. In some embodiments, one of the first integrated circuit chip and the second integrated circuit chip includes: a first field effect transistor (FET) of a first type of conductivity, wherein the first field effect transistor also includes: a first channel, vertically stacked along the first direction, and the first channel extends longitudinally along the second direction; a first source and a first drain, arranged on opposite sides of the first channel and contacting each of the first channels; and a first gate, interposed between the first source and the first drain, and extending to wrap each of the first channels; a second field effect transistor of a second type of conductivity opposite to the first type of conductivity, wherein the second field effect transistor also includes: a second channel, vertically stacked along the first direction, and the second channel extends longitudinally along the second direction; a second source and a second drain, arranged on opposite sides of the second channel and contacting each of the second channels; and a second gate, interposed between the second source and the second drain, and extending to wrap each of the second channels; and a second anisotropic heat dissipation material, arranged under the first field effect transistor.

[0128] In some embodiments, the first anisotropic heat dissipation material comprises an anisotropic heat dissipation polymer. In some embodiments, the integrated circuit structure comprises a NH 2 A dielectric surface layer of silicon nitride (SiN) having a chemical group; and the anisotropic heat dissipation polymer includes the NH 2 Chemical Groups Chemically bonded chemical groups R.

[0129] Still other embodiments of the present application provide a method for manufacturing an integrated circuit (IC) structure, comprising: forming a circuit structure having a semiconductor device located on a front side of a substrate and an interconnection structure located above the semiconductor device; applying a solution to a back side of the substrate, the solution comprising a photosensitive material and a liquid crystal material; applying an electric field to the solution; and curing the solution while the electric field is applied to the solution.

[0130] In some embodiments, the semiconductor device comprises a complementary field effect transistor (CFET); curing the solution comprises applying ultraviolet (UV) radiation; and applying the electric field such that the electric field is parallel to the substrate.

[0131] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated circuit (IC) structure, comprising: a first field effect transistor (FET) of a first type of conductivity, wherein the first field effect transistor further comprises: first channels, stacked vertically along a first direction, the first channels extending longitudinally along a second direction perpendicular to the first direction; a first source and a first drain disposed on opposite sides of the first channel and contacting each of the first channels; and a first gate, interposed between the first source and the first drain, and extending to wrap around each of the first channels; a second field effect transistor of a second type of conductivity opposite to the first type of conductivity, wherein the second field effect transistor is stacked above the first field effect transistor along the first direction, and further comprising: second channels, vertically stacked along the first direction, the second channels extending longitudinally along the second direction; a second source and a second drain disposed on opposite sides of the second channel and contacting each of the second channels; and a second gate interposed between the second source and the second drain and extending to wrap around each of the second channels; and An anisotropic heat dissipation structure is arranged below the first field effect transistor, wherein the anisotropic heat dissipation structure comprises an electrically insulating and thermally conductive anisotropic heat dissipation material, has a first thermal conductivity along the first direction and a second thermal conductivity along the second direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

2. The integrated circuit structure according to claim 1, wherein: The anisotropic heat dissipation material includes anisotropic heat dissipation polymer.

3. The integrated circuit structure according to claim 2, wherein: The anisotropic heat dissipating polymer is a conical bottle brush polymer.

4. The integrated circuit structure according to claim 3, wherein: The integrated circuit structure includes a dielectric surface layer of silicon oxide (SiO2) having OH chemical groups; and The anisotropic heat dissipation polymer includes chemical groups R chemically bonded to the OH chemical groups of the dielectric surface layer.

5. The integrated circuit structure according to claim 3, wherein: The integrated circuit structure includes a dielectric surface layer of silicon nitride (SiN) having NH2 chemical groups; and The anisotropic heat dissipation polymer includes a chemical group R chemically bonded to the NH2 chemical group of the dielectric surface layer.

6. The integrated circuit structure according to claim 3, wherein: The integrated circuit structure includes a dielectric surface of silicon oxycarbon nitride (SiOCN) having NH2 chemical groups; and The anisotropic heat dissipation polymer includes chemical groups R chemically bonded to the NH2 chemical groups of the dielectric surface.

7. The integrated circuit structure according to claim 1, wherein: The anisotropic heat dissipation material includes anisotropic heat dissipation liquid crystal.

8. The integrated circuit structure according to claim 7, wherein: The anisotropic heat dissipation material further includes a photoresist material mixed with the anisotropic heat dissipation liquid crystal.

9. An integrated circuit (IC) structure comprising: A first substrate having a first surface, wherein the first surface has a normal direction along a first direction; a first integrated circuit chip bonded to the first substrate; as well as A second integrated circuit chip is electrically connected to the first integrated circuit chip, wherein: The first integrated circuit chip and the second integrated circuit chip are sealed in the same package having a sealing material layer, and The sealing material layer includes a first anisotropic heat dissipation material, wherein the first anisotropic heat dissipation material is thermally conductive, has a first thermal conductivity along the first direction and a second thermal conductivity along a second direction perpendicular to the first direction, and wherein the second thermal conductivity is substantially greater than the first thermal conductivity.

10. A method of manufacturing an integrated circuit (IC) structure, comprising: forming a circuit structure having a semiconductor device on a front side of a substrate and an interconnect structure above the semiconductor device; applying a solution to the back side of the substrate, the solution comprising a photosensitive material and a liquid crystal material; applying an electric field to the solution; as well as The solution is solidified when the electric field is applied to the solution.

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