Novel low-voltage anti-ESD detection circuit
By designing a new low-voltage anti-ESD detection circuit, including a shutdown module, a detection module and an ESD bleed module, the problem of the ESD protection unit in the chip quickly turning on the protection during ESD events and avoiding the latch effect caused by mistaken triggering. It realizes the effect of turning on the protection in time when the ESD pulse current reaches and automatically turning off after the end.
Patent Information
- Application Number
- CN202411565500.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-02-11
AI Technical Summary
In the chip, the ESD protection unit needs to be quickly turned on when an ESD event occurs to protect the internal circuit, but the prior art is difficult to prevent the latch effect caused by false triggering during normal power-on operation.
A new low-voltage anti-ESD detection circuit was designed, including a shutdown module, a detection module and an ESD discharge module. If the shutdown module is accidentally triggered during normal power-on, it can be turned off in time to unlock the latch state; the detection module can detect the ESD pulse current in time and turn on the ESD drain module.
This circuit can be turned on earlier than the internal circuit when the ESD pulse current arrives, fully protecting the internal circuit, and automatically closing after the ESD pulse is over to avoid the formation of a latch effect.
Smart Images
Figure CN119419710A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a detection circuit, in particular to a novel low-voltage ESD protection detection circuit. Background Art
[0002] Electrostatic discharge (ESD) poses a huge threat to the entire life cycle of circuit components. As the scale and integration of integrated circuit manufacturing electronic products continue to increase, the role of the ESD protection unit in the chip will become more and more important in the overall chip, which determines whether the entire chip protection design can be successfully completed. As the chip scale gradually increases, when an ESD event occurs, in order to ensure that the ESD protection unit can be turned on in time, it is necessary to add a fast detection circuit in front of the ESD protection unit to assist in turning on the ESD protection device. Summary of the invention
[0003] The present invention provides a novel low-voltage ESD protection detection circuit. When an ESD pulse current arrives, the ESD circuit will be turned on earlier than the internal circuit to fully protect the device. When the ESD pulse current ends, it can be automatically turned off to prevent the formation of a latch effect.
[0004] The technical solution to achieve the purpose of the present invention is: a new low-voltage ESD protection detection circuit, comprising:
[0005] A shutdown module is used to shut down the ESD discharge module in time to release the latch state if the ESD discharge module is triggered by mistake during normal power-on operation;
[0006] The detection module is used to detect the ESD pulse current in time and turn on the ESD discharge module when the ESD pulse current arrives;
[0007] The ESD discharge module can discharge ESD pulse current when turned on.
[0008] Further, the shutdown module includes a resistor R0, an inverter INV1, an inverter INV2, an inverter INV3, a hysteresis inverter INV4, a PMOS tube PM1, an NMOS tube NM1 and a resistor R1; the detection module includes an inverter INV5, a PMOS tube PM2, an NMOS tube NM2 and an NMOS tube NM3; the ESD discharge module includes an NMOS tube NM4;
[0009] One end of the resistor R0 is connected to the power supply VCC, and the other end is connected to the input end of the inverter INV1; the output of the inverter INV1 is connected to the input end of the hysteresis inverter INV4, the gate end of the PMOS tube PM1, and the drain end of the NMOS tube NM1; the source and drain ends of the PMOS tube PM1 are connected to the power supply VCC; the gate end of the NMOS tube NM1 is connected to the first end of the resistor R1, and the source end is connected to GND; the second end of the resistor R1 is connected to GND; the output end of the hysteresis inverter INV4 is connected to the input end of the inverter INV2; the output of the inverter INV2 is connected to the input end of the inverter INV3;
[0010] The input of the inverter INV5 is connected to the output of the inverter INV3, and the output of the inverter INV5 is connected to the gate terminal of the PMOS tube PM2, the gate terminal source terminal of the NMOS tube NM2, and the gate terminal of the NMOS tube NM4; the source terminal and drain terminal of the PMOS tube PM2 are connected to the power supply VCC. The drain terminal of the NMOS tube NM2 is connected to the gate terminal and drain terminal of the NMOS tube NM3; the source terminal of the NMOS tube NM3 is connected to GND; the drain terminal of the NMOS tube NM4 is connected to the power supply VCC, and the drain terminal is connected to GND.
[0011] Compared with the prior art, the significant advantages of the present invention are: the present invention adds a shutdown module on the basis of the traditional RCNMOS anti-ESD structure. The circuit structure can not only turn on the protection in time when the ESD pulse current arrives, but also can shut down the anti-ESD module in time to release the latched state if the anti-ESD module is mistakenly triggered during normal power-on operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 This is the logic diagram of the new low-voltage ESD protection detection circuit.
[0013] Figure 2 This is a logic diagram of the traditional RCNMOS ESD protection structure circuit. DETAILED DESCRIPTION
[0014] In order to make the purpose, structure and characteristics of the present invention easy to understand, the specific implementation methods of the present invention are described in detail below with reference to the accompanying drawings.
[0015] The present invention proposes a novel low voltage ESD protection detection circuit. Figure 1 As shown, the circuit includes:
[0016] A shutdown module is used to shut down the ESD discharge module in time to release the latch state if the ESD discharge module is triggered by mistake during normal power-on operation;
[0017] The detection module is used to detect the ESD pulse current in time and turn on the ESD discharge module when the ESD pulse current arrives;
[0018] ESD discharge module, which can quickly discharge ESD pulse current after being turned on;
[0019] When the ESD pulse current arrives, the ESD detection circuit will be turned on earlier than the internal circuit to fully protect the internal circuit. When the ESD pulse current ends, it can automatically turn off to prevent the formation of a latching effect. The present invention adds a shutdown module on the basis of the traditional RCNMOS anti-ESD structure. This circuit structure can not only turn on the protection in time when the ESD pulse current arrives, but also turn off the ESD discharge module in time to release the latching state if the anti-ESD module is triggered by mistake during normal power-on operation. The traditional RCNMOS anti-ESD structure circuit is as follows: Figure 2 shown.
[0020] The shutdown module includes a resistor R0, an inverter INV1, an inverter INV2, an inverter INV3, a hysteresis inverter INV4, a PMOS tube PM1, an NMOS tube NM1, and a resistor R1. The detection module includes an inverter INV5, a PMOS tube PM2, an NMOS tube NM2, and an NMOS tube NM3. The ESD discharge module includes an NMOS tube NM4.
[0021] The first end of the resistor R0 is connected to the power supply VCC, and the second end is connected to the input end of the inverter INV1. The output of the inverter INV1 is connected to the input end of the hysteresis inverter INV4, the gate end of the PMOS tube PM1, and the drain end of the NMOS tube NM1. The source and drain ends of the PMOS tube PM1 are connected to the power supply VCC. The gate end of the NMOS tube NM1 is connected to the first end of the resistor R1, and the source end is connected to GND. The second end of the resistor R1 is connected to GND. The output end of the hysteresis inverter INV4 is connected to the input end of the inverter INV2. The output of the inverter INV2 is connected to the input end of the inverter INV3.
[0022] The inverter INV5 input is connected to the inverter INV3 output, and the inverter INV5 output is connected to the gate end of the PMOS tube PM2, the gate end and source end of the NMOS tube NM2, and the gate end of the NMOS tube NM4. The source end and drain end of the PMOS tube PM2 are connected to the power supply VCC. The drain end of the NMOS tube NM2 is connected to the gate end and drain end of the NMOS tube NM3. The source end of the NMOS tube NM3 is connected to GND. The drain end of the NMOS tube NM4 is connected to the power supply VCC, and the drain end is connected to GND.
[0023] The working principle of the novel low-voltage ESD protection detection circuit of the present invention is analyzed as follows:
[0024] When the circuit is not powered on, the gate potential of the NMOS tube NM4 in the ESD discharge module remains low, and the source and drain of the NMOS tube remain open. When an ESD pulse arrives, the input end of INV5 in the detection module does not have time to respond to the ESD pulse due to the existence of the shutdown module. At this time, the input voltage of INV5 is still at a low level. After passing through the inverter, the gate end of the NMOS tube NM4 in the discharge module is high, and NM4 is turned on to discharge the ESD charge.
[0025] As time goes by, the VCC high voltage passes through the resistor R0, inverter INV1, hysteresis inverter INV4, inverter INV2, inverter INV3 in the shutdown module, and finally reaches the input end of the inverter INV5 in the detection module, causing the potential of the inverter INV5 input end to be gradually raised until the inverter output signal is reversed, and the NMOS tube NM4 is turned off. At this time, the ESD pulse has also been discharged and will not affect the internal chip module.
[0026] Since the energy of the ESD pulse signal is relatively large, the output of the inverter INV5 in the detection module will generate a high-energy pulse. If this pulse is directly transmitted to the gate end of the NMOS tube NM4 in the ESD discharge module, the gate end of NM4 is easily damaged, affecting the subsequent ESD energy discharge. In order to protect the NMOS tube NM4, we designed PMOS tube PM2, NMOS tube NM2, and NMOS tube NM3 after the output end of the inverter INV5 in the detection module. The function of these three MOS tubes is to pull down the high-level pulse output by the inverter INV5. This design can not only ensure that the NMOS tube NM4 in the discharge module is turned on, but also protect the gate end of the NMOS tube NM4 from being damaged by the high pulse energy impact.
[0027] Figure 2 The present invention adds a shutdown module to the traditional RCNMOS anti-ESD structure. The circuit structure can not only turn on the protection in time when the ESD pulse current arrives, but also can turn off the anti-ESD module in time to release the latch state if the anti-ESD module is triggered by mistake during normal power-on operation.
[0028] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A novel low voltage ESD protection detection circuit, characterized in that: include: A shutdown module is used to shut down the ESD discharge module in time to release the latch state if the ESD discharge module is triggered by mistake during normal power-on operation; The detection module is used to detect the ESD pulse current in time and turn on the ESD discharge module when the ESD pulse current arrives; The ESD discharge module can discharge ESD pulse current when turned on.
2. The novel low voltage ESD protection detection circuit according to claim 1 is characterized in that: When the ESD pulse current arrives, the ESD detection circuit will be turned on earlier than the internal circuit to fully protect the internal circuit. When the ESD pulse current ends, it can automatically turn off to prevent the formation of a latch effect.
3. A novel low voltage ESD protection detection circuit as claimed in claim 1, characterized in that: The shutdown module includes a resistor R0, an inverter INV1, an inverter INV2, an inverter INV3, a hysteresis inverter INV4, a PMOS tube PM1, an NMOS tube NM1 and a resistor R1; the detection module includes an inverter INV5, a PMOS tube PM2, an NMOS tube NM2 and an NMOS tube NM3; the ESD discharge module includes an NMOS tube NM4; One end of the resistor R0 is connected to the power supply VCC, and the other end is connected to the input end of the inverter INV1; the output of the inverter INV1 is connected to the input end of the hysteresis inverter INV4, the gate end of the PMOS tube PM1, and the drain end of the NMOS tube NM1; the source and drain ends of the PMOS tube PM1 are connected to the power supply VCC; the gate end of the NMOS tube NM1 is connected to the first end of the resistor R1, and the source end is connected to GND; the second end of the resistor R1 is connected to GND; the output end of the hysteresis inverter INV4 is connected to the input end of the inverter INV2; the output of the inverter INV2 is connected to the input end of the inverter INV3; The input of the inverter INV5 is connected to the output of the inverter INV3, and the output of the inverter INV5 is connected to the gate terminal of the PMOS tube PM2, the gate terminal source terminal of the NMOS tube NM2, and the gate terminal of the NMOS tube NM4; the source terminal and drain terminal of the PMOS tube PM2 are connected to the power supply VCC. The drain terminal of the NMOS tube NM2 is connected to the gate terminal and drain terminal of the NMOS tube NM3; the source terminal of the NMOS tube NM3 is connected to GND; the drain terminal of the NMOS tube NM4 is connected to the power supply VCC, and the drain terminal is connected to GND.