Trigger for determining initial state

Abstract

The invention provides a trigger for determining an initial state. The trigger comprises a transmission circuit, a first initial state circuit and a second initial state circuit, the transmission circuit is connected with the first initial state circuit and the second initial state circuit. The transmission circuit comprises a first three-state phase inverter, a second three-state phase inverter and a first phase inverter which are connected in sequence; the first initial state circuit comprises a first gate circuit and a second phase inverter; the first initial state circuit is used for accelerating the overturning speed and latching the output of the first tri-state inverter; the second initial state circuit comprises a second gate circuit and a third phase inverter; and the second initial state circuit is used for accelerating the overturning speed and latching the output of the second tri-state inverter. According to the invention, the number of gate circuits is reduced by removing a reset circuit, the anti-interference capability of the trigger is improved, and the area utilization rate of the trigger is also improved.

Description

Technical Field

[0001] The present invention relates to the technical field of triggers, and in particular to a trigger for determining an initial state. Background Art

[0002] As the scale of digital circuits becomes larger and larger, a very large-scale integrated circuit requires a large number of triggers. Traditional triggers require RSTN reset signals, and the reset signal is used to define the initial state of the trigger. In this way, it is necessary to provide some reset circuits for the reset signal to realize its function. The area inside the trigger is very precious. As the area of ​​the trigger is reduced a little, the integration and density of the integrated circuit will be well optimized.

[0003] However, the reset circuit occupies a certain number of logic gates in the trigger. The traditional trigger with reset requires a total of 28 MOS tubes, which is difficult to meet the current requirements of high speed, low power consumption and small area of ​​integrated circuits. Therefore, it is necessary to design a trigger that determines the initial state. Summary of the invention

[0004] The purpose of the present invention is to provide a trigger with a determined initial state, so as to reduce the number of gate circuits by removing a reset circuit, improve the anti-interference ability of the trigger and improve the area utilization of the trigger.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A trigger for determining an initial state, comprising: a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is connected to the first initial state circuit and the second initial state circuit respectively;

[0007] The transmission circuit includes a first tri-state inverter, a second tri-state inverter and a first inverter connected in sequence;

[0008] The first initial state circuit includes a first gate circuit and a second inverter; the first initial state circuit is used to accelerate the flipping speed to latch the output of the first tri-state inverter;

[0009] The second initial state circuit includes a second gate circuit and a third inverter; the second initial state circuit is used to accelerate the flipping speed and latch the output of the second three-state inverter.

[0010] Optionally, the first three-state inverter includes a pmos tube P1, a pmos tube P2, a nmos tube N1 and a nmos tube N2 connected in sequence; the source of the pmos tube P1 is connected to the power supply, the gate of the pmos tube P1 is connected to the first initial state circuit, the source of the nmos tube N2 is grounded, and the connecting ends of the pmos tube P2 and the nmos tube N1 are respectively connected to the second three-state inverter and the first initial state circuit.

[0011] Optionally, the second three-state inverter includes a pmos tube P6, a pmos tube P7, a nmos tube N6 and a nmos tube N5 connected in sequence; the source of the pmos tube P6 is connected to the power supply, the gate of the pmos tube P6 is respectively connected to the first three-state inverter and the second initial state circuit, the source of the nmos tube N5 is grounded, and the connecting ends of the pmos tube P7 and the nmos tube N6 are respectively connected to the first inverter and the second initial state circuit.

[0012] Optionally, the first inverter includes a connected pmos tube P11 and a nmos tube N9; the source of the pmos tube P11 is connected to the power supply, the source of the nmos tube N9 is grounded, and the gate connection ends of the pmos tube P11 and the nmos tube N9 are connected to the second three-state inverter.

[0013] Optionally, the first gate circuit includes: pmos tube P3, pmos tube P4 and nmos tube N3, and the second inverter includes: pmos tube P5 and nmos tube N4; the gate of pmos tube P3 is connected to the first three-state inverter, the drain of pmos tube P3 is connected to the gate of pmos tube P4, the source of pmos tube P3 is connected to the power supply, the sources of pmos tube P4 and pmos tube P5 are both connected to the power supply, the gate of pmos tube P4 is connected to the gate of nmos tube N3, the drain of pmos tube P5, the drain of nmos tube N4, the transmission circuit and the first gate circuit, the drain of pmos tube P4 is respectively connected to the drain of nmos tube N3, the gate of pmos tube P5 and the gate of nmos tube N4, and the sources of nmos tube N3 and nmos tube N4 are both grounded.

[0014] Optionally, the second gate circuit includes: pmos tube P8, pmos tube P9 and nmos tube N7, and the third inverter includes: pmos tube P10 and nmos tube N8; the gate of pmos tube P8 is connected to the second three-state inverter, the drain of pmos tube P8 is connected to the gate of pmos tube P9, the source of pmos tube P8 is connected to the power supply, the sources of pmos tube P9 and pmos tube P10 are both connected to the power supply, the gate of pmos tube P9 is connected to the gate of nmos tube N7, the drain of pmos tube P10, the drain of nmos tube N8, the transmission circuit and the second gate circuit, the drain of pmos tube P9 is respectively connected to the drain of nmos tube N7, the gate of pmos tube P10 and the gate of nmos tube N8, and the sources of nmos tube N7 and nmos tube N8 are both grounded.

[0015] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: the trigger for determining the initial state provided by the present invention comprises: a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is respectively connected to the first initial state circuit and the second initial state circuit; the transmission circuit comprises a first three-state inverter, a second three-state inverter and a first inverter connected in sequence; the first initial state circuit comprises a first gate circuit and a second inverter; the first initial state circuit is used to accelerate the flipping speed to latch the output of the first three-state inverter; the second initial state circuit comprises a second gate circuit and a third inverter; the second initial state circuit is used to accelerate the flipping speed to latch the output of the second three-state inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A structure diagram of a trigger according to an embodiment of the present invention;

[0018] Figure 2 is a circuit structure diagram of an embodiment of the present invention;

[0019] Figure 3 4 is a trigger timing diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The present invention proposes a trigger that does not require an additional reset signal, and can reset the internal latch state by close input signal, and only 7 circuit transistors, a total of 20 MOS tubes, are required. Figure 1As shown, inv1 and inv2 are three-state inverters, inv3, inv4 and inv5 are inverters, nand1 and nand2 are NAND gates, A is an input signal, Y is an output signal, and CLKP and CLKN are complementary clocks. A trigger for determining an initial state provided by an embodiment of the present invention includes: a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is connected to the first initial state circuit and the second initial state circuit respectively. The transmission circuit includes a first three-state inverter, a second three-state inverter and a first inverter connected in sequence; the first initial state circuit includes a first gate circuit and a second inverter; the first initial state circuit is used to accelerate the flipping speed to latch the output of the first three-state inverter; the second initial state circuit includes a second gate circuit and a third inverter; the second initial state circuit is used to accelerate the flipping speed to latch the output of the second three-state inverter.

[0023] Specifically, when CLKN is high, inv1 transmits input signal A to node B, and nand1 and inv4 form a latch circuit to accelerate the flipping speed to latch the state of point B, so that the initial state of point B is controlled by input signal A of nand1 without the need for reset signal for reset control. When CLKN is low, inv1 outputs high impedance state Z, and the potential of point B is maintained by nand1 and inv4. When CLKP is high, inv2 transmits input signal B to node C, and nand2 and inv5 form a latch circuit to accelerate the flipping speed to latch the state of point C, so that the initial state of point C is controlled by input signal B of nand2 without the need for reset signal for reset control. When CLKP is low, inv2 outputs high impedance state Z, and the potential of point C is maintained by latches nand2 and inv5, and finally outputs state Y through inv3.

[0024] like Figure 2 As shown, the first three-state inverter includes: pmos tube P1, pmos tube P2, nmos tube N1 and nmos tube N2. The source of pmos tube P1 is connected to the power supply, the gate of pmos tube P1 is connected to the input signal A, and the drain of pmos tube P1 is connected to the source of pmos tube P2 to form a common node e. The gate of pmos tube P2 is connected to the clock CLKP, and the drain of pmos tube P2 is connected to the drain of nmos tube N1 to form a common node B. The gate of nmos tube N1 is connected to the clock CLKN, and the source of nmos tube N1 is connected to the drain of nmos tube N2 to form a common node f. The gate of nmos tube N2 is connected to the input signal A, and the source of nmos tube N2 is grounded.

[0025] The second three-state inverter includes: pmos tube P6, pmos tube P7, nmos tube N6 and nmos tube N5. The source of pmos tube P6 is connected to the power supply, the gate of pmos tube P6 is connected to the common node B, and the drain of pmos tube P6 is connected to the source of pmos tube P7 to form a common node h. The gate of pmos tube P7 is connected to the clock CLKN, and the drain of pmos tube P7 is connected to the drain of nmos tube N6 to form a common node C. The gate of nmos tube N6 is connected to the clock CLKP, and the source of nmos tube N6 is connected to the drain of nmos tube N5 to form a common node i. The gate of nmos tube N5 is connected to the common node B, and the source of nmos tube N5 is grounded.

[0026] The first inverter includes: a pmos transistor P11 and an nmos transistor N9. The source of the pmos transistor P11 is connected to the power supply, the source of the nmos transistor N9 is grounded, and the gate of the pmos transistor P11 and the gate of the nmos transistor N9 are connected to a common node C. The drain of the pmos transistor P11 is connected to the drain of the nmos transistor N9 to form a common node and output a signal Y.

[0027] The first gate circuit includes: pmos transistor P3, pmos transistor P4 and nmos transistor N3. The second inverter includes: pmos transistor P5 and nmos transistor N4. The source of pmos transistor P3 is connected to the power supply, the gate of pmos transistor P3 is connected to the input signal A, and the drain of pmos transistor P3 is connected to the gate of pmos transistor P4 to form a common node B. The source of pmos transistor P4 is connected to the power supply, and the drain of pmos transistor P4 is connected to the drain of nmos transistor N3 to form a common node g. The source of nmos transistor N3 is connected to the ground, and the gate of nmos transistor N3 is connected to the drain of pmos transistor P3 to form a common node B. The source of pmos transistor P5 is connected to the power supply, the gate of pmos transistor P5 is connected to the drain of nmos transistor N3 to form a common node g, and the drain of pmos transistor P5 is connected to the gate of nmos transistor N3 to form a common node B. The drain of nmos transistor N4 is connected to the drain of pmos transistor P3 to form a common node B, the gate of nmos transistor N4 is connected to the drain of pmos transistor P4 to form a common node g, and the source of nmos transistor N4 is grounded.

[0028] The second gate circuit includes: pmos transistor P8, pmos transistor P9 and nmos transistor N7. The third inverter includes: pmos transistor P10 and nmos transistor N8. The source of pmos transistor P8 is connected to the power supply, the gate of pmos transistor P8 is connected to the common node B, and the drain of pmos transistor P8 is connected to the gate of pmos transistor P9 to form a common node C. The source of pmos transistor P9 is connected to the power supply, and the drain of pmos transistor P9 is connected to the drain of nmos transistor N7 to form a common node j. The source of nmos transistor N7 is connected to the ground, and the gate of nmos transistor N7 is connected to the drain of pmos transistor P8 to form a common node C. The source of pmos transistor P10 is connected to the power supply, the gate of pmos transistor P10 is connected to the drain of nmos transistor N7 to form a common node j, and the drain of pmos transistor P10 is connected to the gate of nmos transistor N7 to form a common node C. The drain of nmos transistor N8 is connected to the drain of pmos transistor P8 to form a common node C, the gate of nmos transistor N8 is connected to the drain of pmos transistor P9 to form a common node j, and the source of nmos transistor N8 is grounded.

[0029] It should be noted that all MOS tubes used in the embodiments of the present invention are ULVT MOS tubes. There are no special requirements for the power supply voltage except that the power supply voltage should not exceed the tube withstand voltage value of the MOS tube, which greatly improves the adaptability of the trigger in actual manufacturing.

[0030] Specifically, Figure 3 As shown, when the A input at time t1 is at a high level, the clock CLKN remains stable within the time t1-t2 after the rising edge, during which P1, P3, P5, N3, N5, N6, N8, P7, P9, and P11 are in the off state, P2, P4, N1, N2, N4, N7, N9, P6, P8, and P10 are in the on state, and the potential at point B is set to a low level, the potential at point C is set to a high level through P8, and the output signal Y is a low level. After the falling edge of the clock CLKN, it remains stable within the time t1-t2. During this period, P2, N1, P1, P3, P5, N3, N5, N8, P9, and P11 are in the off state, P7, N6, P4, N2, N4, N7, N9, P6, P8, and P10 are in the on state, and point B maintains a low level state, point C maintains a high level state, and the output signal Y maintains a low level state.

[0031] When the input A is low at time t1, the clock CLKN remains stable within t1-t2 after the rising edge, during which N2, N4, N6, P4, P6, P7, and P8 are off, N1, N3, P1, P2, P3, and P5 are on, point B is set to a high level, and point C remains in the state of the previous cycle, so that the switch states of N7, N8, N9, P9, P10, and P11 are controlled by the state of the previous cycle of point C. After the falling edge of the clock CLKN, it remains stable within t1-t2, during which N1, N2, N4, N7, N9, P2, P4, P6, P8, and P10 are off, N3, N5, N6, N8, P1, P3, P5, P7, P9, and P11 are on, point B maintains a high level, point C maintains a low level, and the output signal Y is a high level.

[0032] The beneficial effects of the present invention are as follows:

[0033] 1) Compared with the traditional trigger, the present invention reduces nearly 30% of unnecessary circuits, greatly improves the utilization rate of the trigger area, reduces area waste, and improves design efficiency;

[0034] 2) The present invention retains two latch circuits to the maximum extent, improves the anti-interference ability of the trigger, and reduces the logic error problem caused by node leakage;

[0035] 3) The speed requirement range has been greatly improved, taking into account the simultaneous needs of high-speed and low-speed work without causing logical misjudgment.

[0036] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0037] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A trigger for determining an initial state, characterized in that: include: A transmission circuit, a first initial state circuit, and a second initial state circuit; The transmission circuit is connected to the first initial state circuit and the second initial state circuit respectively; The transmission circuit comprises a first tri-state inverter, a second tri-state inverter and a first inverter connected in sequence; The first initial state circuit includes a first gate circuit and a second inverter; the first initial state circuit is used to accelerate the flipping speed to latch the output of the first tri-state inverter; The second initial state circuit includes a second gate circuit and a third inverter; the second initial state circuit is used to accelerate the flipping speed and latch the output of the second three-state inverter.

2. The trigger for determining the initial state according to claim 1, characterized in that: The first three-state inverter includes a pmos tube P1, a pmos tube P2, a nmos tube N1 and a nmos tube N2 connected in sequence; the source of the pmos tube P1 is connected to a power supply, the gate of the pmos tube P1 is connected to the first initial state circuit, the source of the nmos tube N2 is grounded, and the connecting ends of the pmos tube P2 and the nmos tube N1 are respectively connected to the second three-state inverter and the first initial state circuit.

3. The trigger for determining the initial state according to claim 1, characterized in that: The second three-state inverter includes a pmos tube P6, a pmos tube P7, an nmos tube N6 and an nmos tube N5 connected in sequence; the source of the pmos tube P6 is connected to the power supply, the gate of the pmos tube P6 is respectively connected to the first three-state inverter and the second initial state circuit, the source of the nmos tube N5 is grounded, and the connecting ends of the pmos tube P7 and the nmos tube N6 are respectively connected to the first inverter and the second initial state circuit.

4. The trigger for determining the initial state according to claim 1, characterized in that: The first inverter includes a connected pmos tube P11 and a nmos tube N9; the source of the pmos tube P11 is connected to a power supply, the source of the nmos tube N9 is grounded, and the gate connection ends of the pmos tube P11 and the nmos tube N9 are connected to the second three-state inverter.

5. The trigger for determining the initial state according to claim 1, characterized in that: The first gate circuit includes: pmos tube P3, pmos tube P4 and nmos tube N3, and the second inverter includes: pmos tube P5 and nmos tube N4; the gate of the pmos tube P3 is connected to the first three-state inverter, the drain of the pmos tube P3 is connected to the gate of the pmos tube P4, the source of the pmos tube P3 is connected to the power supply, the sources of the pmos tube P4 and the pmos tube P5 are both connected to the power supply, the gate of the pmos tube P4 is connected to the gate of the nmos tube N3, the drain of the pmos tube P5, the drain of the nmos tube N4, the transmission circuit and the first gate circuit, the drain of the pmos tube P4 is respectively connected to the drain of the nmos tube N3, the gate of the pmos tube P5 and the gate of the nmos tube N4, and the sources of the nmos tube N3 and the nmos tube N4 are both grounded.

6. The trigger for determining the initial state according to claim 1, characterized in that: The second gate circuit includes: pmos tube P8, pmos tube P9 and nmos tube N7, and the third inverter includes: pmos tube P10 and nmos tube N8; the gate of the pmos tube P8 is connected to the second three-state inverter, the drain of the pmos tube P8 is connected to the gate of the pmos tube P9, the source of the pmos tube P8 is connected to the power supply, the sources of the pmos tube P9 and the pmos tube P10 are both connected to the power supply, the gate of the pmos tube P9 is connected to the gate of the nmos tube N7, the drain of the pmos tube P10, the drain of the nmos tube N8, the transmission circuit and the second gate circuit, the drain of the pmos tube P9 is respectively connected to the drain of the nmos tube N7, the gate of the pmos tube P10 and the gate of the nmos tube N8, and the sources of the nmos tube N7 and the nmos tube N8 are both grounded.

Images