A Successive Approximation Analog-to-Digital Converter Based on Dual Threshold Comparator

Abstract

The invention discloses a successive approximation analog-to-digital converter based on a dual-threshold comparator, comprising: a switched capacitor DAC array, a dual-threshold comparator, and a SAR logic circuit; the input voltage outputs a differential signal to the differential input end of the dual-threshold comparator after passing through the switched capacitor DAC array; the dual-threshold comparator divides three comparison intervals by setting two thresholds, judges the interval corresponding to the input differential input signal, obtains an output code and sends it to the SAR logic circuit; the SAR logic circuit controls the switches of the corresponding bit capacitors in the switched capacitor DAC array to convert, so that the differential input signal jumps in the approaching direction one by one. The successive approximation analog-to-digital converter of the invention solves the problem that the traditional comparator is prone to error when the input signal is close to 0V, resulting in a decrease in ADC performance, and at the same time achieves the same conversion accuracy with fewer conversion cycles, lower power consumption, and smaller area.

Description

Technical Field

[0001] The present invention relates to the technical field of high-precision analog-to-digital converters in the field of integrated circuits, and in particular to a successive approximation analog-to-digital converter based on a dual-threshold comparator. Background Art

[0002] In the field of successive approximation register ADC (SAR ADC), the comparator is one of the key circuits, and its performance directly affects the accuracy of the ADC. The traditional SAR ADC is based on a single-threshold comparator, that is, the comparator has only one comparison threshold, usually 0V. When the input signal is greater than 0V, the comparator outputs logic 1; when the input signal is less than 0V, the comparator outputs logic 0.

[0003] The basic working principle of the traditional SAR ADC is that the SAR logic circuit controls the switching direction of the corresponding bit capacitor in the DAC according to the output result of the comparator, and finally makes the DAC output approach the common mode level or 0V. The output results of each comparator are combined according to the corresponding weights to obtain the conversion result of the ADC. However, during the conversion process, when the comparator input signal is close to the threshold of 0V, due to the existence of noise and offset, the comparator will be difficult to judge, which requires a longer comparison time for judgment, and may even obtain an erroneous comparison result, resulting in a decrease in the speed and accuracy of the SAR ADC.

[0004] To solve the above problems, a DAC with a redundant structure or a sub-binary DAC is usually used, but this requires more conversion cycles and power consumption. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a successive approximation analog-to-digital converter based on a dual-threshold comparator, which solves the problem that the comparator input signal is prone to error when it is close to 0V, resulting in a decrease in ADC performance; at the same time, the conversion speed can be improved, the power consumption can be reduced, and the conversion cycle can be shortened.

[0006] The present invention adopts the following technical solution: a successive approximation analog-to-digital converter based on a dual-threshold comparator, comprising: a switched capacitor DAC array DAC_P and DAC_N, a dual-threshold comparator, and a SAR logic circuit;

[0007] The input voltages of the successive approximation analog-to-digital converter are Vip and Vin; the input voltage Vip outputs a voltage Vxp after passing through DAC_P, and the input voltage Vin outputs a voltage Vxn after passing through DAC_N, and Vxp and Vxn are input as differential input signals to the differential input terminal of the dual threshold comparator;

[0008] The dual-threshold comparator divides into three comparison intervals by setting two thresholds Vth1 and Vth2, determines the comparison interval corresponding to the input differential input signal, obtains the output code, and outputs it to the SAR logic circuit;

[0009] According to the output code result of the dual-threshold comparator, the SAR logic circuit controls the switches of the corresponding-bit capacitors in the switched-capacitor DAC array to perform conversion, so that the differential input signals Vxp and Vxn gradually jump in the approaching direction, and converge within the range of Vth1 to Vth2 after n conversions, obtaining the digital signal finally output by the successive approximation analog-to-digital converter.

[0010] Preferably, the two thresholds of the dual-threshold comparator satisfy Vth1 < 0 < Vth2, and the differential input signal is divided into three intervals:

[0011] The first interval is the interval where the differential input signal is less than Vth1, and the dual-threshold comparator outputs the code Q<1:0> = 2b’01;

[0012] The second interval is the interval where the differential input signal is greater than Vth2, and the dual-threshold comparator outputs the code Q<1:0> = 2b’10;

[0013] The zero interval is the interval where the differential input signal is between Vth1 and Vth2, and the dual-threshold comparator outputs the code Q<1:0> = 2b’00.

[0014] Preferably, for an n-bit successive approximation analog-to-digital converter, in the switched-capacitor DAC array, DAC_P and DAC_N respectively include capacitors Cd, C0, C1, C2, …, Cn-1, and the upper plate of each capacitor is connected to a corresponding switch. By setting the values of Vth1 and Vth2, after n conversions, the n + 1-bit digital signal finally output by the successive approximation analog-to-digital converter is obtained.

[0015] Preferably, for any conversion, the dual-threshold comparator compares the differential input signals Vxp and Vxn, calculates the voltage difference Vxp - Vxn, and determines the interval of the differential input signal according to the voltage difference;

[0016] If the differential input signal is in the first interval, the SAR logic circuit controls the switch of the corresponding-bit capacitor in the switched-capacitor DAC array to jump upward in the subsequent conversion cycle, so that the differential output of the switched-capacitor DAC array adds a voltage amount;

[0017] If the differential input signal is in the second interval, the SAR logic circuit controls the switch of the corresponding-bit capacitor in the switched-capacitor DAC array to jump downward in the subsequent conversion cycle, so that the differential output of the switched-capacitor DAC array subtracts a voltage amount;

[0018] If the differential input signal is in the zero interval, the switches of the switched capacitor DAC array remain unchanged in the following conversion cycle, and the conversion of the lower bit is directly entered.

[0019] Preferably, the dual threshold comparator has three output coding states, using a ternary coding method, and the method is as follows:

[0020] ;

[0021] ;

[0022] in, k j Determined by the output result of the dual threshold comparator; w j is the corresponding capacitance C j The weight of , using a binary weight structure, w j =2 j-1 , j The capacitor numbers are consistent with those in the switched capacitor DAC array; Dout Represents the output of the analog-to-digital converter, with a range of -2 n -1~+2 n -1.

[0023] Preferably, the two thresholds of the dual-threshold comparator can be set to fixed values ​​or gradually decrease with the conversion process. The difference between the two thresholds determines the performance of the successive approximation analog-to-digital converter, and the sum of the two thresholds affects the offset of the successive approximation analog-to-digital converter.

[0024] Preferably, for an n-bit successive approximation analog-to-digital converter, the two thresholds Vth1 and Vth2 of the dual-threshold comparator satisfy the following conditions at each conversion:

[0025] ;

[0026] in,( Vth2-Vth1) j represents the switched capacitor DAC array capacitance Cj The threshold difference of the dual threshold comparator when the corresponding bit is converted, the first conversion j =n-1, the last conversion j =0; V FS Represents the full scale of the successive approximation analog-to-digital converter.

[0027] Preferably, the dual-threshold comparator circuit comprises: a MOS tube M1, a MOS tube M2, a MOS tube M3, two groups of resistance units R1 and R2, and two groups of latch circuits LATCH1 and LATCH2;

[0028] MOS tube M1 and MOS tube M2 are differential input pair tubes; power supply vdd is connected to the drain of MOS tube M1 through resistance unit R2, output terminal Vop2, resistance unit R1, and output terminal Vop1, and power supply vdd is connected to the drain of MOS tube M2 through resistance unit R2, output terminal Von2, resistance unit R1, and output terminal Von1; the gate of MOS tube M1 is connected to input signal Vxn, and the gate of MOS tube M2 is connected to input voltage Vxp; the source of MOS tube M1 and the source of MOS tube M2 are input to the drain of MOS tube M3, the gate of MOS tube M3 is connected to bias voltage Vb, and the source of MOS tube M3 is grounded;

[0029] The output terminals Vop1 and Von2 are input into the latch circuit LATCH1, and the output code Q <1> The output terminals Von1 and Vop2 are input into the latch circuit LATCH2, and the output code Q <0> .

[0030] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0031] 1. The successive approximation analog-to-digital converter of the present invention replaces the traditional single-threshold comparator with a dual-threshold comparator, which solves the problem that the comparator input signal is prone to error when it is close to 0V, resulting in a decrease in ADC performance. The dual threshold is divided into three comparison intervals, and there is no need to compare the result for the signal between the two thresholds (area 0), thereby reducing the requirements for the speed and accuracy of the comparator and improving the speed and accuracy of the ADC.

[0032] 2. The successive approximation analog-to-digital converter of the present invention is based on a dual-threshold comparator. The switch of the capacitor array is not switched after each comparison. If the comparison result is in area 0, the capacitor switch is not switched and directly enters the lower bit conversion, which can save the power consumption of the switch switching.

[0033] 3. The successive approximation analog-to-digital converter based on the dual-threshold comparator of the present invention obtains an n+1 bit output result through n conversions, which can be used to improve accuracy or increase conversion speed and reduce conversion cycle; and the SARADC based on the dual-threshold comparator itself has redundancy, and there is no need to add additional redundant bit capacitors to compensate for high-bit establishment errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of a SAR ADC based on a dual-threshold comparator of the present invention;

[0035] Figure 2 A schematic diagram showing the relationship between the output code of the dual-threshold comparator of the present invention and the differential input signal;

[0036] Figure 3 A schematic diagram of the threshold and conversion process of the SAR ADC based on the fixed-threshold dual-threshold comparator of the present invention;

[0037] Figure 4 The Vcm-based upper plate sampling single-ended input SAR ADC based on the dual threshold comparator of the present invention;

[0038] Figure 5 It is a schematic diagram of the SAR ADC conversion process based on the dual-threshold comparator of the present invention;

[0039] Figure 6 is a transfer function curve of the SAR ADC based on the dual-threshold comparator of the present invention;

[0040] Figure 7 The transfer function curve of the SAR ADC based on the dual-threshold comparator when the threshold value has deviation in the present invention;

[0041] Figure 8 A schematic diagram of the threshold and conversion process of the SAR ADC based on the variable threshold dual threshold comparator of the present invention;

[0042] Fig. 9 The present invention is based on the variable threshold dual threshold comparator SAR ADC different signal conversion process;

[0043] Fig.10 Schematic diagram of the dual-threshold comparator circuit structure of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0045] The present invention proposes a successive approximation analog-to-digital converter based on a dual-threshold comparator. By reasonably designing two thresholds, n conversions can achieve n+1 bit accuracy, and the circuit itself has a redundant effect, does not require additional redundant bits and redundant cycles, and can achieve the same conversion accuracy with fewer conversion cycles, lower power consumption, and smaller area compared to traditional structures or redundant structures or sub-binary structures.

[0046] In one embodiment of the present invention, a fully differential SAR ADC is taken as an example for description. The circuit of the present invention is also applicable to single-ended, pseudo-differential structure SAR ADC and other switch switching SAR ADCs.

[0047] In this embodiment, the SAR ADC circuit structure based on the dual-threshold comparator is as follows: Figure 1 As shown, it includes: switched capacitor DAC arrays DAC_P and DAC_N, a dual threshold comparator, and a SAR logic circuit.

[0048] Specifically, the input voltages of the successive approximation analog-to-digital converter are Vip and Vin, the reference voltage is Vref, and in the switched capacitor DAC array, DAC_P and DAC_N include capacitors Cd, C0, C1, C2, ..., Cn-1 respectively, and the upper plate of each capacitor is connected to a corresponding switch.

[0049] The upper plate of the capacitor of DAC_P is respectively connected to the reference voltage Vref, GND, and input voltage Vip through switch selection, and the upper plate of the capacitor of DAC_N is respectively connected to the reference voltage Vref, GND, and input voltage Vin through switch selection.

[0050] The lower plates of the capacitors of DAC_P are coupled together and connected to the non-inverting input of the dual-threshold comparator, and connected to the common-mode level Vcm through a non-inverting switch; the lower plates of the capacitors of DAC_N are coupled together and connected to the inverting input of the dual-threshold comparator, and connected to the common-mode level Vcm through an inverting switch.

[0051] The input voltage Vip outputs the voltage Vxp after passing through the switch capacitor DAC array DAC_P, and the input voltage Vin outputs the voltage Vxn after passing through the switch capacitor DAC array DAC_N. Vxp and Vxn are input as differential input signals to the differential input end of the dual threshold comparator; the dual threshold comparator divides three comparison intervals by setting two thresholds Vth1 and Vth2, judges the comparison interval corresponding to the input differential input signal, obtains the output code, and outputs it to the SAR logic circuit.

[0052] Furthermore, the output code of the dual threshold comparator varies with the differential input signal, such as Figure 2As shown. The two thresholds Vth1 and Vth2 of the dual-threshold comparator satisfy the relationship Vth1 < 0 < Vth2, thus dividing the input signal from -Vref to +Vref into three intervals: the interval less than Vth1 is called interval 1, and the comparator output code Q<1:0> = 2b’01; the interval greater than Vth2 is called interval 2, and the comparator output code Q<1:0> = 2b’10; the interval between Vth1 and Vth2 is called interval 0, and the comparator output code Q<1:0> = 2b’00.

[0053] Furthermore, the SAR logic circuit controls the switching of the corresponding-bit capacitors in the switched-capacitor DAC array according to the output coding result of the dual-threshold comparator, so that the differential input signals Vxp and Vxn jump successively in the direction of approaching.

[0054] Similar to the traditional SAR ADC, without considering other non-ideal factors, the variation process of the comparator differential input voltage during the conversion process of this embodiment is as Figure 3 shown. By calculating the difference between Vxp and Vxn, the input signal at the differential end of the comparator (i.e., the differential DAC output signal) jumps successively in the direction of approaching and finally converges within the range of Vth1 to Vth2.

[0055] Different from the traditional SAR ADC, in the SAR ADC based on dual thresholds of this embodiment, during the conversion process, the jump direction of the DAC output voltage is determined according to the result of the comparator, and there are three possibilities: jump upward, jump downward, and remain unchanged.

[0056] For any conversion, when the differential input signal of the comparator is in region 1 and the comparator output result Q<1:0> is 2b’01, the SAR logic circuit controls the switching of the switched-capacitor DAC, making the DAC differential output jump upward in the subsequent conversion cycle, that is, adding a voltage amount; when the differential input signal of the comparator is in region 2 and the comparator output result Q<1:0> is 2b’10, the SAR logic circuit controls the switching of the switched-capacitor DAC, making the DAC differential output jump downward in the subsequent conversion cycle, that is, subtracting a voltage amount; when the differential input signal of the comparator is in region 0 and the comparator output result Q<1:0> is 2b’00, the switch of the capacitor DAC remains unchanged in the subsequent conversion cycle and directly performs the comparison operation, thus saving the energy of capacitor switch switching.

[0057] During each conversion, the voltage amount of the change in the DAC differential output is obtained according to the ratio of the capacitor corresponding to the current conversion to the total capacitance of the switched-capacitor DAC array, which is used to implement the addition / subtraction operation of the current-bit coding in the analog domain at the output end of the switched-capacitor DAC, making the differential input signals Vxp and Vxn of the dual-threshold comparator jump successively in the direction of approaching.

[0058] In particular, compared with the traditional SAR ADC, the SAR ADC based on the dual-threshold comparator in this embodiment does not need to spend a long time on comparison when the comparator input signal is close to 0V (in region 0), and can directly output the comparison result 2b'00, and quantize the residual transfer value in the subsequent conversion cycle, thereby improving the conversion speed.

[0059] Furthermore, the dual-threshold comparator of this embodiment has three output states, and the traditional binary encoding method is no longer applicable. Therefore, this embodiment proposes a ternary encoding method for the proposed dual-threshold comparator-based SAR ADC, and the formula is as follows:

[0060] ;

[0061]

[0062] in, k j Determined by the output of the dual threshold comparator, w j is the corresponding bit capacitance weight, and a binary weight structure is typically used, that is, w j =2 j-1 , j and Figure 2 The capacitor numbers in the table are consistent. For an n-bit SAR ADC, j The maximum is n-1, then Dout The range is -2 n -1~+2 n -1, 2 may appear n+1 -1 code.

[0063] By properly setting the values ​​of Vth1 and Vth2, an n+1 bit SAR ADC can be realized, where Vth2-Vth1=0.5LSB (LSB here refers to 1 LSB of the n-bit SAR ADC).

[0064] Further, taking the single-ended input SAR ADC based on Vcm upper plate sampling as an example, the ADC circuit structure based on the dual threshold comparator is as follows: Figure 4 As shown, in the switched capacitor DAC array, DAC_P and DAC_N include capacitors Cd, C0, C1, and C2, respectively, with corresponding capacitance values ​​of C, C, 2C, and 4C, respectively, and the upper plate of each capacitor is connected to a corresponding switch.

[0065] The upper plate of the capacitor of DAC_P is connected to the reference voltage Vref, the common mode level Vcm, and GND respectively through switch selection. The full scale of the signal is 0~Vref, Vth2-Vth1=1 / 16*Vref, here Vth2=1 / 32*Vref, Vth1=-1 / 32*Vref, and the ADC needs three conversions to get a 4-bit output result.

[0066] Part of the input signal conversion process is as follows Figure 5 As shown, the transfer function of the ADC is Figure 6 As shown. Using a SAR ADC based on a dual-threshold comparator, n conversions can get n+1 bits of conversion results, which can further improve the conversion speed and save power. If the DNL requirement is not high, the requirement for the absolute value of Vth2-Vth1 can be reduced. Figure 4 For the circuit in the example, as long as Vth2-Vth1<1 / 8*Vref, a conversion result of more than 3 bits can be obtained, or a 4-bit conversion result with DNL error. At this time, the transfer function of the ADC is as follows: Figure 7 shown.

[0067] It should be particularly noted that the SAR ADC based on the dual-threshold comparator of the present invention outputs three states each time comparison is performed, which is equivalent to a ternary system, and the capacitor array adopts a binary coding structure, so the capacitor array itself has redundancy, which can reduce the requirements for high-bit establishment speed, comparator threshold, comparator noise, etc.

[0068] The two thresholds of the dual-threshold comparator of the present invention can be fixed values, or amplifiers with different gains can be added before the dual-threshold comparator to achieve that the two thresholds gradually decrease during the conversion process.

[0069] In order to further improve the conversion speed, the present embodiment sets the comparator threshold value to gradually decrease with the conversion process. The threshold value and conversion process of the SAR ADC based on the variable threshold dual threshold comparator are as follows: Figure 8 shown.

[0070] For an ADC circuit that converts n times and outputs n+1 bits, regardless of whether the two thresholds of the dual-threshold comparator are fixed or gradually reduced, the two thresholds must meet the following conditions for each conversion:

[0071] ;

[0072] in, (Vth2-Vth1) j Represents a capacitor array C j The threshold difference of the dual threshold comparator when the corresponding bit is converted. For a SAR ADC with n conversions, 0≤ j≤n-1, when the first conversion j =n-1, the last conversion j =0; (Vth2-Vth1) 0 Represents the threshold difference of the dual threshold comparator at the last conversion; V FS Indicates the full scale of ADC; w j Indicates capacitance C j The weight of .

[0073] The conversion process and conversion results of a SAR ADC with 3-conversion 4-bit output based on a variable dual threshold comparator under different input signals, such as Fig. 9 The threshold difference of the dual-threshold comparator determines the performance of the ADC, and the sum of the two thresholds affects the offset of the ADC, but has no effect on the nonlinear performance.

[0074] Preferably, the schematic diagram of the dual threshold comparator circuit structure proposed in this embodiment is as follows: Fig.10 As shown, the dual threshold comparator circuit includes: a MOS tube M1, a MOS tube M2, a MOS tube M3, two groups of resistance units R1 and R2, and two groups of latch circuits LATCH1 and LATCH2;

[0075] Among them, the MOS transistor M1 and the MOS transistor M2 are a differential input pair of transistors; the power supply vdd is connected to the drain of the MOS transistor M1 through the resistor unit R2, the output terminal Vop2, the resistor unit R1, and the output terminal Vop1, and the power supply vdd is connected to the drain of the MOS transistor M2 through the resistor unit R2, the output terminal Von2, the resistor unit R1, and the output terminal Von1; the gate of the MOS transistor M1 is connected to the input signal Vxn, and the gate of the MOS transistor M2 is connected to the input voltage Vxp; the source of the MOS transistor M1 and the source of the MOS transistor M2 are commonly input to the drain of the MOS transistor M3, the gate of the MOS transistor M3 is connected to the bias voltage Vb, and the source of the MOS transistor M3 is grounded.

[0076] Furthermore, the output terminal Vop1 and the output terminal Von2 are input into the latch circuit LATCH1, and the output code Q <1> The output terminals Von1 and Vop2 are input into the latch circuit LATCH2, and the output code Q <0> .

[0077] Based on the above dual threshold comparator circuit, assuming that the threshold voltage of the latch circuit LATCH1 and LATCH2 is V T , then Vth2 and Vth1 do not change with the conversion process, and are:

[0078] ;

[0079] ;

[0080] in, V T is the threshold voltage of the latch circuit, R is the resistance value of the resistor units R1 and R2, g m is the transconductance of MOS tubes M and M2.

[0081] In summary, the present invention replaces the traditional single-threshold comparator with a dual-threshold comparator. The dual threshold is divided into three comparison intervals. There is no need to compare the result for the signal between the two thresholds (area 0), thereby reducing the requirements for the speed and accuracy of the comparator and improving the speed and accuracy of the ADC. At the same time, the SAR ADC based on the dual-threshold comparator does not switch the switch of the capacitor array after each comparison. If the comparison result is in area 0, the capacitor switch does not switch and directly enters the lower bit conversion, which can save the power consumption of the switch switching. An n+1 bit output result can be obtained through n conversions, which effectively improves the accuracy or conversion speed. Moreover, the SAR ADC based on the dual-threshold comparator itself has redundancy, and there is no need to add additional redundant bit capacitors to compensate for the high-bit establishment error.

[0082] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A successive approximation analog-to-digital converter based on a dual-threshold comparator, characterized in that: The successive approximation analog-to-digital converter includes: a switched-capacitor DAC array DAC_P and DAC_N, a dual-threshold comparator, and a SAR logic circuit; The input voltages of the successive approximation analog-to-digital converter are Vip and Vin; the input voltage Vip outputs the voltage Vxp after passing through DAC_P, and the input voltage Vin outputs the voltage Vxn after passing through DAC_N. Vxp and Vxn are input to the differential input terminals of the dual-threshold comparator as differential input signals; The dual-threshold comparator divides three comparison intervals by setting two thresholds Vth1 and Vth2, determines the comparison interval corresponding to the input differential input signal, obtains the output code, and outputs it to the SAR logic circuit; The two thresholds of the dual-threshold comparator satisfy Vth1 < 0 < Vth2, dividing the differential input signal into three intervals: The first interval is the interval where the differential input signal is less than Vth1, and the dual-threshold comparator outputs the code Q<1:0> = 2b’01; The second interval is the interval where the differential input signal is greater than Vth2, and the dual-threshold comparator outputs the code Q<1:0> = 2b’10; The zero interval is the interval where the differential input signal is between Vth1 and Vth2, and the dual-threshold comparator outputs the code Q<1:0> = 2b’00; The SAR logic circuit controls the switches of the corresponding-bit capacitors in the switched-capacitor DAC array to perform conversion according to the output code result of the dual-threshold comparator, so that the differential input signals Vxp and Vxn jump successively in the direction of approaching, and converge within the range of Vth1~Vth2 after n conversions, obtaining the digital signal finally output by the successive approximation analog-to-digital converter.

2. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 1, characterized in that: For an n-bit successive approximation analog-to-digital converter, in the switched-capacitor DAC array, DAC_P and DAC_N respectively include capacitors Cd, C0, C1, C2, …, Cn-1. The upper plate of each capacitor is connected to a corresponding switch. By setting the values of Vth1 and Vth2, after n conversions, the n+1-bit digital signal finally output by the successive approximation analog-to-digital converter is obtained.

3. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 2, characterized in that: For any conversion, the dual-threshold comparator compares the differential input signals Vxp and Vxn, calculates the voltage difference Vxp - Vxn, and determines the interval of the differential input signal according to the voltage difference; If the differential input signal is in the first interval, the SAR logic circuit controls the switch of the corresponding-bit capacitor in the switched-capacitor DAC array to jump upward in the subsequent conversion cycle, adding a voltage amount to the differential output of the switched-capacitor DAC array; If the differential input signal is in the second interval, the SAR logic circuit controls the switch of the corresponding-bit capacitor in the switched-capacitor DAC array to jump downward in the subsequent conversion cycle, subtracting a voltage amount from the differential output of the switched-capacitor DAC array; If the differential input signal is in the zero interval, the switches of the switched-capacitor DAC array remain unchanged in the subsequent conversion cycle and directly enter the lower-bit conversion.

4. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 3, characterized in that: The voltage quantity is obtained according to the ratio of the capacitance corresponding to the current conversion to the total capacitance of the switched capacitor DAC array, and is used to implement the addition / subtraction operation of the current bit encoding in the analog domain at the output end of the switched capacitor DAC array, so that the differential input signals Vxp and Vxn of the dual threshold comparator jump in the direction of approaching one after another.

5. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 3, characterized in that: The dual threshold comparator has three output coding states, using a ternary coding method, the method is as follows: ； ； in, k j Determined by the output result of the dual threshold comparator; w j is the corresponding capacitance C j The weight of , using a binary weight structure, w j =2 j-1 , j The capacitor numbers are consistent with those in the switched capacitor DAC array; Dout Represents the output of the analog-to-digital converter, with a range of -2 n -1~+2 n -1.

6. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 5, characterized in that: The two thresholds of the dual-threshold comparator are set to fixed values ​​or gradually decrease with the conversion process. The difference between the two thresholds determines the performance of the successive approximation analog-to-digital converter, and the sum of the two thresholds affects the offset of the successive approximation analog-to-digital converter.

7. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 6, characterized in that: For an n-bit successive approximation analog-to-digital converter, the two thresholds Vth1 and Vth2 of the dual-threshold comparator need to meet the following conditions for each conversion: ； in, (Vth2-Vth1) j represents the switched capacitor DAC array capacitance C j The threshold difference of the dual threshold comparator when the corresponding bit is converted, the first conversion j =n-1, the last conversion j =0; V FS Represents the full scale of the successive approximation analog-to-digital converter.

8. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 6, characterized in that: The dual-threshold comparator circuit comprises: a MOS tube M1, a MOS tube M2, a MOS tube M3, two groups of resistance units each comprising a resistor R1 and a resistor R2, and two groups of latch circuits LATCH1 and LATCH2; The MOS tube M1 and the MOS tube M2 are a differential input pair of tubes; the power supply vdd is connected to the drain of the MOS tube M1 through the resistor R2 of the first resistor unit, the output terminal Vop2, the resistor R1 of the first resistor unit, and the output terminal Vop1, and the power supply vdd is connected to the drain of the MOS tube M2 through the resistor R2 of the second resistor unit, the output terminal Von2, the resistor R1 of the second resistor unit, and the output terminal Von1; the gate of the MOS tube M1 is connected to the input signal Vxn, and the gate of the MOS tube M2 is connected to the input voltage Vxp; the source of the MOS tube M1 and the source of the MOS tube M2 are input to the drain of the MOS tube M3, the gate of the MOS tube M3 is connected to the bias voltage Vb, and the source of the MOS tube M3 is grounded; The output terminals Vop1 and Von2 are input into the latch circuit LATCH1, and the output code Q <1> The output terminals Von1 and Vop2 are input into the latch circuit LATCH2, and the output code Q <0> .

9. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 8, characterized in that: The two thresholds Vth2 and Vth1 of the dual threshold comparator are set as follows: ； ； in, V T is the threshold voltage of the latch circuit, R is the resistance value of the resistor units R1 and R2, g m is the transconductance of MOS tubes M1 and M2.

10. The successive approximation analog-to-digital converter based on a dual-threshold comparator according to claim 1, characterized in that: The successive approximation analog-to-digital converter includes: a fully differential structure SAR ADC, a single-ended structure SAR ADC, and a pseudo-differential structure SAR ADC.

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