Contact hole and preparation method thereof, semiconductor device and electronic equipment

Abstract

The invention relates to a contact hole and a preparation method thereof, a semiconductor device and electronic equipment. The method comprises the following steps: providing a substrate; forming a plurality of grooves in the substrate, wherein each groove is filled with a polycrystalline silicon layer; forming ion implantation regions on the two sides of each groove in the substrate; performing thermal oxidation on the ion implantation region, forming an oxide layer on the side wall of the groove, and forming an inverted trapezoidal region on the top of the groove; forming a barrier layer in the inverted trapezoidal region in the trench, wherein the target opening exposes the barrier layer; and forming a plurality of contact holes among the plurality of grooves by taking the barrier layer as a mask layer. According to the invention, under the condition that the precision of the contact hole is not reduced, the dependence on a high-performance photoetching machine is reduced, the consistency of in-wafer and inter-wafer Vcesat (saturation conduction voltage) of the hybrid power device wafer is improved, and the preparation cost and complexity are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a contact hole and a preparation method thereof, a semiconductor device, and an electronic device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, device size has gradually decreased according to Moore's Law, and the requirements for contact hole etching have become increasingly higher.

[0003] Especially for hybrid power devices, hybrid power devices (such as IGBT, etc.) have the characteristics of MOS structure input and bipolar structure output, so they have the advantages of high input impedance of MOSFET, low drive circuit power, simple drive, fast switching speed, and low switching loss, and have the advantages of high current density, strong current handling capacity, and low on-saturation voltage drop of bipolar power transistors. Since the early 1980s, it has been widely studied at home and abroad. At present, IGBT has broad application prospects and is widely used in new energy vehicles, industrial frequency conversion, photovoltaics, smart grids, locomotives and other fields. In addition, the Chinese IGBT market accounts for about one-third of the global IGBT market.

[0004] After nearly four decades of development, hybrid power devices have evolved from planar type to trench type, and the pitch (minimum repeating unit) of the cell has become smaller and smaller, and the distance from the active area contact hole to the trench gate has also become smaller and smaller, and the alignment accuracy requirements for the contact hole mask and the trench gate mask have become higher and higher.

[0005] In the related art, the consistency of the distance from the contact hole to the trench gate depends entirely on the alignment consistency of the contact hole mask and the trench gate mask, which undoubtedly increases the dependence on high-performance lithography machines and increases the cost and complexity of preparation. Summary of the invention

[0006] Based on this, it is necessary to provide a contact hole and its preparation method, a semiconductor device, and an electronic device to address the above-mentioned technical problems, which can at least reduce the dependence on high-performance lithography machines without reducing the accuracy of the contact holes, improve the consistency of Vcesat (saturation conduction voltage) within and between hybrid power device wafers, and reduce the cost and complexity of preparation.

[0007] In order to achieve the above-mentioned purpose and other purposes, in a first aspect, the present disclosure provides a method for preparing a contact hole, comprising: providing a substrate; forming a plurality of grooves in the substrate, each groove being filled with a polysilicon layer; forming ion implantation regions on both sides of each groove in the substrate, the bottom of the ion implantation region being higher than the bottom of the groove, and the ion concentration of the ion implantation region being higher as it is closer to the top; thermally oxidizing the ion implantation region to form an oxide layer on the sidewall of the groove, and forming an inverted trapezoidal region at the top of the groove, the inverted trapezoidal region forming a target opening at the top of the substrate; forming a blocking layer in the inverted trapezoidal region in the groove, the target opening exposing the blocking layer; using the blocking layer as a mask layer to form a plurality of contact holes between the plurality of grooves.

[0008] In the method for preparing the contact holes in the above-mentioned embodiment, ions of different ion concentrations are injected into the ion implantation regions on both sides of each groove in the substrate, and the ion implantation regions are thermally oxidized by utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer, so as to form an inverted trapezoidal region at the top of the groove, and the substrate is etched using the barrier layer in the inverted trapezoidal region as a mask layer to form multiple contact holes between the multiple grooves. Therefore, without reducing the accuracy of the contact holes, the barrier layer is formed by utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer, which can significantly reduce the dependence on high-performance lithography machines and improve the consistency of Vcesat (saturation conduction voltage) within and between wafers of hybrid power devices. Therefore, the disclosed embodiment also effectively reduces the cost and complexity of preparation.

[0009] In one embodiment, a groove is formed in a substrate, including: forming a mask layer covering the substrate and a patterned photoresist layer covering the mask layer; using the patterned photoresist layer as a mask plate, etching the mask layer to form a patterned mask layer; using the patterned mask layer as a mask plate, etching a plurality of grooves in the substrate.

[0010] In one of the embodiments, the method further includes: etching the patterned mask layer using a wet etching technique to form a target mask layer; wherein the target mask layer includes a plurality of mask openings, and the width of each mask opening is greater than the opening width of the groove.

[0011] In the method for preparing the contact hole in the above embodiment, a portion of the mask layer is consumed by wet etching to form a target mask layer in which the width of each mask opening is larger than the opening width of the groove, thereby ensuring protection of the substrate during the subsequent ion implantation process. In addition, an ion implantation space is formed between each groove opening and each grinding opening, which facilitates the subsequent ion implantation step and further reduces the cost and complexity of contact hole preparation.

[0012] In one embodiment, ion implantation regions are formed on both sides of each trench in the substrate, including: performing multiple ion implantations using a target mask layer as a mask; wherein the energy and ion concentration of each ion implantation are related to the number of ion implantations.

[0013] In the method for preparing the contact hole in the above embodiment, the target mask layer is used as a mask plate, and multiple ion implantations are performed to ensure that ion implantation regions with different concentration gradients are formed on both sides of each trench in the substrate.

[0014] In one embodiment, the thickness of the oxide layer is 1000Å-1500Å, and the oxidation temperature of the thermal oxidation is 1000°C-1150°C.

[0015] In the method for preparing the contact hole in the above embodiment, by limiting the thermal oxidation temperature and the thickness of the formed oxide layer, the angles of the two waists of the inverted trapezoidal region formed on the top of the groove are guaranteed, thereby ensuring the accuracy of the formed contact hole.

[0016] In one embodiment, a barrier layer is formed in an inverted trapezoidal region in a groove, including: etching back a portion of the polysilicon multilayer in each groove, and depositing a borophosphosilicate glass layer on a substrate; based on a borophosphosilicate glass reflow process, filling the etched back portion in each groove with borophosphosilicate glass; removing the borophosphosilicate glass on the top surface of the substrate, and forming a barrier layer in the inverted trapezoidal region in the groove.

[0017] In the contact hole preparation method in the above embodiment, a barrier layer is formed in the inverted trapezoidal area in the groove by etching back the polysilicon layer in each groove and performing a borophosphosilicate glass reflow process, thereby ensuring that a complete barrier layer is formed to protect the groove before etching the contact hole.

[0018] In one embodiment, the thickness of the borophosphosilicate glass layer is 8 kÅ-15 kÅ, the reflux temperature of the borophosphosilicate glass reflux process is 900°C-1000°C, and the reflux time of the borophosphosilicate glass reflux process is 30 minutes-240 minutes.

[0019] In the contact hole preparation method in the above embodiment, by limiting the thickness of the borophosphosilicate glass layer, the reflow temperature of the borophosphosilicate glass reflow process and the reflow time of the borophosphosilicate glass reflow process, it is ensured that the borophosphosilicate glass fills the etched back part in each groove, forming a barrier layer in the inverted trapezoidal area in the groove.

[0020] In the second aspect, the embodiments of the present disclosure also provide a contact hole, comprising: a substrate; a plurality of grooves located in the substrate; an oxide layer located on the sidewalls of each groove; a plurality of contact holes located between the plurality of grooves; wherein each groove is filled with a polysilicon layer and a barrier layer, an inverted trapezoidal region is formed at the top of each groove, the inverted trapezoidal region forms a target opening at the top of the substrate, the barrier layer is located in the inverted trapezoidal region, and the target opening exposes the barrier layer.

[0021] The contact holes in the above-mentioned embodiments are formed by injecting ions of different ion concentrations into the ion implantation regions on both sides of each groove in the substrate, utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer to thermally oxidize the ion implantation regions, forming an inverted trapezoidal region at the top of the groove, and etching the substrate using the barrier layer in the inverted trapezoidal region as a mask layer to form multiple contact holes between the multiple grooves. Therefore, without reducing the accuracy of the contact holes, the barrier layer is formed by utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer, which significantly reduces the dependence on high-performance lithography machines and improves the consistency of Vcesat (saturation conduction voltage) within and between wafers of hybrid power devices. Therefore, the disclosed embodiments also effectively reduce the cost and complexity of preparation.

[0022] On the third aspect, the embodiments of the present disclosure also provide a semiconductor device, including: the contact hole in any of the above embodiments, which can at least reduce the dependence on high-performance lithography machines without reducing the accuracy of the contact holes, improve the consistency of Vcesat (saturation conduction voltage) within and between hybrid power device wafers, and reduce the cost and complexity of preparation.

[0023] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising: a semiconductor device in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a schematic flow chart of a method for preparing a contact hole provided in an embodiment;

[0026] Figure 2 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S2000 in a method for preparing a contact hole provided in an embodiment Figure 1 ;

[0027] Figure 3A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S2000 in a method for preparing a contact hole provided in an embodiment Figure 2 ;

[0028] Figure 4 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S2000 in a method for preparing a contact hole provided in an embodiment Figure 3 ;

[0029] Figure 5 It is a schematic diagram of the longitudinal cross-section structure of the structure obtained in step S3000 in the method for preparing a contact hole provided in one embodiment;

[0030] Figure 6 It is a schematic diagram of the longitudinal cross-section structure of the structure obtained in step S4000 in the method for preparing a contact hole provided in one embodiment;

[0031] Figure 7 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S5000 in a method for preparing a contact hole provided in an embodiment Figure 1 ;

[0032] Figure 8 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S5000 in a method for preparing a contact hole provided in an embodiment Figure 2 ;

[0033] Fig. 9 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S6000 in a method for preparing a contact hole provided in an embodiment Figure 1 ;

[0034] Fig.10 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S6000 in a method for preparing a contact hole provided in an embodiment Figure 2 .

[0035] Description of reference numerals:

[0036] 201, substrate; 202, mask layer; 203, photoresist layer; 301, patterned mask layer; 302, groove; 303, polysilicon layer; 401, target mask layer; 501, ion implantation area; a, a area; b, b area; c, c area; 601, oxide layer; 801, borophosphosilicate glass layer; 901, barrier layer; 1001, contact hole. DETAILED DESCRIPTION

[0037] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0039] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0041] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0043] Please refer to Figure 1-Figure 10 The present disclosure provides a method for preparing a contact hole 1001, comprising the following steps:

[0044] Step S1000: providing a substrate 201 .

[0045] Wherein, the substrate 201 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 201 can be a single-layer structure or a multi-layer structure. For example, the substrate 201 can be a silicon substrate 201, a silicon germanium substrate 201, a silicon germanium carbon substrate 201, a silicon carbide substrate 201, a gallium arsenide substrate 201, an indium arsenide substrate 201, an indium phosphide substrate 201 or other III / V semiconductor substrates 201 or II / VI semiconductor substrates 201. Alternatively, for example, the substrate 201 can be a layered substrate 201 including silicon / silicon carbide, silicon on insulator or silicon germanium on insulator. Therefore, the type of substrate 201 should not limit the scope of protection of the present disclosure.

[0046] Step S2000 : forming a plurality of trenches 302 in the substrate 201 , each trench 302 being filled with a polysilicon layer 303 .

[0047] Step S3000 : forming ion implantation regions 501 on both sides of each trench 302 in the substrate 201 .

[0048] The bottom of the ion implantation region 501 is higher than the bottom of the trench 302 , and the ion concentration of the ion implantation region 501 is higher as it is closer to the top.

[0049] Step S4000 : thermally oxidizing the ion implantation region 501 to form an oxide layer 601 on the sidewall of the trench 302 and to form an inverted trapezoidal region on the top of the trench 302 .

[0050] The inverted trapezoidal region forms a target opening at the top of the substrate 201 .

[0051] Step S5000 : forming a barrier layer 901 in the inverted trapezoidal region in the trench 302 .

[0052] The target opening exposes the blocking layer 901 .

[0053] Step S6000 : Using the barrier layer 901 as the mask layer 202 , a plurality of contact holes 1001 are formed between the plurality of trenches 302 .

[0054] In the method for preparing the contact hole 1001 in the above embodiment, ions of different ion concentrations are implanted into the ion implantation regions 501 on both sides of each groove 302 in the substrate 201, and the ion implantation regions 501 are thermally oxidized by utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer 601, so as to form an inverted trapezoidal region at the top of the groove 302, and the substrate 201 is etched using the barrier layer 901 in the inverted trapezoidal region as the mask layer 202, so as to form a plurality of contact holes 1001 between the plurality of grooves 302. Therefore, without reducing the accuracy of the contact hole 1001, the barrier layer 901 is formed by utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer 601, which significantly reduces the dependence on high-performance lithography machines and improves the consistency of Vcesat (saturation conduction voltage) within and between wafers of the hybrid power device. Therefore, the embodiment of the present disclosure also effectively reduces the cost and complexity of preparation.

[0055] In step S2000, please refer to Figure 1-Figure 3 , forming grooves 302 in the substrate 201, including: forming a mask layer 202 covering the substrate 201, and a patterned photoresist layer 203 covering the mask layer 202; using the patterned photoresist layer 203 as a mask, etching the mask layer 202 to form a patterned mask layer 301; using the patterned mask layer 301 as a mask, etching a plurality of grooves 302 in the substrate 201.

[0056] As an example, see Figure 2-Figure 3 In the present application, a mask layer 202 is formed on a substrate 201, and a patterned photoresist layer 203 is formed on the mask layer 202. After etching the mask layer 202 using the patterned photoresist layer 203 as a mask, a Figure 3 A patterned mask layer 301 is shown.

[0057] Taking an IGBT device as an example, an N-type doped silicon wafer may be used as the substrate 201 , wherein the doping concentration and thickness of the substrate 201 depend on the withstand voltage requirement of the IGBT device.

[0058] Here, the etching depth of each trench 302 is 2 um-6 um.

[0059] As an example, the etching depth of each trench 302 may be 2 um, 3 um, 5 um, 6 um, etc.

[0060] Please refer to Figure 1-Figure 4 The method for preparing the contact hole 1001 further includes: etching the patterned mask layer 301 using a wet etching technique to form a target mask layer 401 .

[0061] The target mask layer 401 includes a plurality of mask openings, and the width of each mask opening is greater than the opening width of the trench 302 .

[0062] In this way, when ion implantation is performed on the sidewall of the trench 302 , the ion implantation to other positions except the sidewall and the bottom of the trench 302 is avoided by blocking by the target mask layer 401 .

[0063] In the method for preparing the contact hole 1001 in the above embodiment, a portion of the mask layer 202 is consumed by wet etching to form a target mask layer 401 in which the width of each mask opening is greater than the opening width of the groove 302, thereby ensuring protection of the substrate 201 during the subsequent ion implantation process. In addition, an ion implantation space is formed between each groove 302 opening and each polishing opening, which facilitates the subsequent ion implantation step and further reduces the cost and complexity of preparing the contact hole 1001.

[0064] As an example, see Figure 4 , Figure 4 The longitudinal cross-sectional structure schematic diagram of the structure obtained in step S2000 is shown. After the wet etching technology is adopted, the width of each opening of the target mask layer 401 is larger than the width of each trench 302 , so as to facilitate ion implantation on the sidewall of the trench 302 .

[0065] In step S3000, please continue to refer to Figure 1 , Figure 5 , Figure 5 The schematic longitudinal cross-sectional structure diagram of the structure obtained in step S3000 forms ion implantation regions 501 on both sides of each trench 302 in the substrate 201 , including: performing multiple ion implantations using the target mask layer 401 as a mask.

[0066] The energy and ion concentration of each ion implantation are related to the number of ion implantations.

[0067] Specifically, taking an IGBT device as an example, an N-type doped silicon wafer may be used as the substrate 201 , and N-type ion implantation may be performed through the target mask layer 401 .

[0068] The number of ion implantations may be 2-3 times, forming different concentration gradients from top to bottom on the sidewalls of the trench 302 .

[0069] Here, in the process of performing multiple ion implantations, as the number of ion implantations increases, the energy of the ion implantations becomes smaller and smaller, and the ion concentration of the ion implantations becomes larger and larger.

[0070] Taking three ion implantations as an example, the energy of the first ion implantation is greater than the energy of the second ion implantation, which is greater than the energy of the third ion implantation, and the ion concentration of the first ion implantation is less than the ion concentration of the second ion implantation, which is less than the ion concentration of the third ion implantation.

[0071] For example, see the following three-step ion implantation procedure. Figure 5 Through three ion implantations, three ion doping regions with different ion concentrations, namely region a, region b, and region c, can be formed on the sidewall of the trench 302 .

[0072] In the method for preparing the contact hole 1001 in the above embodiment, the target mask layer 401 is used as a mask, and multiple ion implantations are performed to ensure that ion implantation regions 501 with different concentration gradients are formed on both sides of each trench 302 in the substrate 201 .

[0073] In step S4000, please continue to refer to Figure 1 , Figure 6 and Figure 7 , the thickness of the oxide layer 601 is 1000Å-1500Å, and the oxidation temperature of thermal oxidation is 1000℃-1150℃.

[0074] As an example, the thickness of the oxide layer 601 may be 1000 Å, 1100 Å, 1200 Å, 1300 Å, 1400 Å, 1500 Å, etc.

[0075] As an example, the oxidation temperature of the thermal oxidation may be 1000° C., 1030° C., 1100° C., 1120° C., 1150° C., and so on.

[0076] In the method for preparing the contact hole 1001 in the above embodiment, by limiting the thermal oxidation temperature and the thickness of the formed oxide layer 601, the angles of the two waists of the inverted trapezoidal area formed at the top of the groove 302 are guaranteed, thereby ensuring the accuracy of the formed contact hole 1001.

[0077] Specifically, in the thermal oxidation process, Figure 6 After the oxide layer is formed, it is necessary to etch away the excess oxide layer on the top surface of the substrate to form a Figure 7 The structure shown.

[0078] Here, thermal oxidation may be performed by a furnace process. Due to the difference in ion concentrations injected at different positions in the substrate 201 , the oxidation rate of the oxidized layer 601 is inconsistent, so that a certain angle is formed at the top of the trench 302 .

[0079] Before forming the oxide layer 601 , the surface lattice defects of the groove 302 may be repaired by sacrificing the oxide layer 601 once or twice.

[0080] In step S5000, a barrier layer 901 is formed in the inverted trapezoidal region within the groove 302, including: etching back a portion of the polysilicon multilayer in each groove 302; depositing a borophosphosilicate glass layer 801 on the substrate 201; based on a borophosphosilicate glass reflow process, filling the etched back portion in each groove 302 with borophosphosilicate glass; removing the borophosphosilicate glass on the top surface of the substrate 201, and forming a barrier layer 901 in the inverted trapezoidal region within the groove 302.

[0081] In the method for preparing the contact hole 1001 in the above embodiment, a barrier layer 901 is formed in the inverted trapezoidal region of the groove 302 by etching back the polysilicon layer 303 in each groove 302 and performing a borophosphosilicate glass reflow process, thereby ensuring that a complete barrier layer 901 is formed to protect the groove 302 before etching the contact hole 1001.

[0082] The thickness of the borophosphosilicate glass layer 801 is 8 kÅ-15 kÅ, the reflux temperature of the borophosphosilicate glass reflux process is 900° C.-1000° C., and the reflux time of the borophosphosilicate glass reflux process is 30 minutes-240 minutes.

[0083] As an example, the thickness of the borophosphosilicate glass layer 801 is 8 kÅ, 10 kÅ, 12 kÅ, 13 kÅ, 15 kÅ, and so on.

[0084] As an example, the reflow temperature of the borophosphosilicate glass reflow process may be 900° C., 950° C., 1000° C., etc.

[0085] As an example, the reflow time of the borophosphosilicate glass reflow process may be 30 minutes, 90 minutes, 120 minutes, 170 minutes, 200 minutes, 240 minutes, etc.

[0086] In the method for preparing the contact hole 1001 in the above embodiment, by limiting the thickness of the borophosphosilicate glass layer 801, the reflow temperature of the borophosphosilicate glass reflow process, and the reflow time of the borophosphosilicate glass reflow process, it is ensured that the borophosphosilicate glass fills the etched portion in each groove 302, and a blocking layer 901 is formed in the inverted trapezoidal area in the groove 302.

[0087] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0088] Based on the same inventive concept, the embodiment of the present disclosure also provides a method for preparing the contact hole 1001 in the above embodiment, thereby obtaining a contact hole 1001. The implementation scheme for solving the problem provided by the contact hole 1001 is similar to the implementation scheme recorded in the above method, so the specific definition of one or more embodiments of the contact hole 1001 provided below can refer to the definition of the method for preparing the contact hole 1001 in the above text, and will not be repeated here.

[0089] In some embodiments, please refer to Fig.10 A contact hole comprises: a substrate 201; a plurality of trenches 302 located in the substrate 201; an oxide layer 601 located on a sidewall of each trench 302; and a plurality of contact holes 1001 located between the plurality of trenches 302.

[0090] Each trench 302 is filled with a polysilicon layer 303 and a barrier layer 901 , and an inverted trapezoidal region is formed at the top of each trench 302 . The inverted trapezoidal region forms a target opening at the top of the substrate 201 . The barrier layer 901 is located in the inverted trapezoidal region, and the target opening exposes the barrier layer 901 .

[0091] The contact hole 1001 in the above embodiment is formed by injecting ions of different ion concentrations into the ion implantation region 501 on both sides of each groove 302 in the substrate 201, and utilizing the difference in oxidation rate of silicon with different doping concentrations by the thermal oxide layer 601 to thermally oxidize the ion implantation region 501, forming an inverted trapezoidal region at the top of the groove 302, and etching the substrate 201 using the barrier layer 901 in the inverted trapezoidal region as the mask layer 202, so as to form a plurality of contact holes 1001 between the plurality of grooves 302. Therefore, without reducing the accuracy of the contact hole 1001, the barrier layer 901 is formed by utilizing the difference in oxidation rate of silicon with different doping concentrations by the thermal oxide layer 601, which can significantly reduce the dependence on high-performance lithography machines and improve the consistency of Vcesat (saturation conduction voltage) within and between wafers of hybrid power devices. Therefore, the embodiment of the present disclosure also effectively reduces the cost and complexity of preparation.

[0092] For example, please continue to refer to Fig.10, by injecting ions of different ion concentrations into the ion implantation regions 501 on both sides of each trench 302 in the substrate 201, utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer 601, thermally oxidizing the ion implantation regions 501, forming an inverted trapezoidal region at the top of the trench 302, and etching the substrate 201 using the barrier layer 901 in the inverted trapezoidal region as the mask layer 202, and forming a plurality of contact holes 1001 between the plurality of trenches 302. Therefore, without reducing the accuracy of the contact holes 1001, utilizing the difference in oxidation rates of silicon with different doping concentrations by the thermal oxide layer 601 to form the barrier layer 901, the dependence on high-performance lithography machines is significantly reduced, and the consistency of Vcesat (saturation conduction voltage) within and between wafers of hybrid power devices is improved. Therefore, the disclosed embodiments also effectively reduce the cost and complexity of preparation. In some embodiments, the embodiments of the present disclosure also provide a semiconductor device, including: the contact hole in any of the above embodiments, which can reduce the dependence on high-performance lithography machines, improve the consistency of Vcesat (saturation conduction voltage) within and between hybrid power device wafers, and effectively reduce the cost and complexity of preparation.

[0093] In some embodiments, the present disclosure provides an electronic device, including a semiconductor device of any one of the disclosed embodiments. The electronic device is, for example but not limited to, a suitable type of electronic product such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, etc. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0094] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a contact hole, characterized in that: include: providing a substrate; forming a plurality of trenches in the substrate, each trench being filled with a polysilicon layer; forming ion implantation regions on both sides of each trench in the substrate, wherein the bottom of the ion implantation region is higher than the bottom of the trench, and the ion concentration of the ion implantation region is higher as it is closer to the top; Thermally oxidizing the ion implantation region to form an oxide layer on the sidewall of the trench and to form an inverted trapezoidal region on the top of the trench, wherein the inverted trapezoidal region forms a target opening on the top of the substrate; forming a barrier layer in an inverted trapezoidal region in the trench, wherein the target opening exposes the barrier layer; The barrier layer is used as a mask layer to form a plurality of contact holes between the plurality of trenches.

2. The preparation method according to claim 1, characterized in that: Forming a groove in the substrate, comprising: forming a mask layer covering the substrate, and a patterned photoresist layer covering the mask layer; Using the patterned photoresist layer as a mask, etching the mask layer to form a patterned mask layer; Using the patterned mask layer as a mask, a plurality of grooves are etched in the substrate.

3. The preparation method according to claim 2, characterized in that: Also includes: Etching the patterned mask layer using a wet etching technique to form a target mask layer; Wherein, the target mask layer includes a plurality of mask openings, and the width of each mask opening is greater than the opening width of the groove.

4. The preparation method according to claim 1, characterized in that: An ion implantation region is formed on both sides of each trench in the substrate, comprising: Performing multiple ion implantations using the target mask layer as a mask; The energy and ion concentration of each ion implantation are related to the number of ion implantations.

5. The preparation method according to claim 1, characterized in that: The thickness of the oxide layer is 1000Å-1500Å, and the oxidation temperature of the thermal oxidation is 1000°C-1150°C.

6. The preparation method according to claim 1, characterized in that: Forming a barrier layer in the inverted trapezoidal region in the trench, comprising: etching back a portion of the polysilicon multilayer in each trench, depositing a borophosphosilicate glass layer on the substrate; Based on the borophosphosilicate glass reflow process, the borophosphosilicate glass is used to fill the back-etched part in each groove; The borophosphosilicate glass on the top surface of the substrate is removed to form a barrier layer in the inverted trapezoidal region in the trench.

7. The preparation method according to claim 6, characterized in that: The thickness of the borophosphosilicate glass layer is 8 kÅ-15 kÅ, the reflux temperature of the borophosphosilicate glass reflux process is 900° C.-1000° C., and the reflux time of the borophosphosilicate glass reflux process is 30 minutes-240 minutes.

8. A contact hole, characterized in that: include: substrate; a plurality of grooves located in the substrate; an oxide layer, located on the sidewalls of each trench; a plurality of contact holes, located between the plurality of trenches; Each trench is filled with a polysilicon layer and a barrier layer, an inverted trapezoidal region is formed at the top of each trench, the inverted trapezoidal region forms a target opening at the top of the substrate, the barrier layer is located in the inverted trapezoidal region, and the target opening exposes the barrier layer.

9. A semiconductor device, characterized in that: include: The contact hole according to claim 8.

10. An electronic device, characterized in that: include: The semiconductor device according to claim 9.

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