Method for forming semiconductor device

Abstract

A method of forming a source / drain region of a semiconductor device is disclosed. The method includes forming a fin structure over a substrate, forming a polysilicon structure over the fin structure, removing the fin structure adjacent to the polysilicon structure to form an opening, and forming a source / drain region in the opening. Forming the source / drain region includes exposing the fin structure in the opening to: a first flow rate of a precursor gas during a first phase of gas flow circulation; and a second flow rate of the precursor gas during a second phase of the gas flow circulation. The exposure of the fin structure in the opening to a precursor gas, an etching gas, and a plasma is performed in an in-situ process.

Description

Technical Field

[0001] The present disclosure relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device using a gas flow cycle. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), gate-all-around field effect transistors (GAA FETs), complementary field effect transistors (CFETs), and vertical field effect transistors (VFETs). This shrinking increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming a fin structure on a substrate; forming a polysilicon structure on the fin structure; removing a portion of the fin structure adjacent to the polysilicon structure to form an opening; and forming a source / drain (S / D) region in the opening, comprising exposing the fin structure in the opening to: a first flow rate of a precursor gas during a first stage of a gas flow cycle; a second flow rate of the precursor gas during a second stage of the gas flow cycle, wherein the first flow rate is higher than the second flow rate; an etching gas during the gas flow cycle; and plasma during the gas flow cycle, wherein the step of exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.

[0004] An embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming a fin structure on a substrate; forming a dielectric layer on the fin structure; forming an opening in the fin structure and passing through the dielectric layer; and epitaxially growing a semiconductor layer on the fin structure in the opening, comprising: performing a deposition process using a first flow rate of a precursor gas during a first stage of an airflow cycle and a second flow rate of the precursor gas during a second stage of the airflow cycle; performing an etching process using a first flow rate of an etching gas during the first stage of the airflow cycle and a second flow rate of the etching gas during the second stage of the airflow cycle, wherein the first flow rate of the precursor gas is higher than the first flow rate of the etching gas, and wherein the second flow rate of the precursor gas is lower than the second flow rate of the etching gas; and performing a plasma process during the airflow cycle.

[0005] The present embodiment provides a method for forming a semiconductor device, comprising: forming a first superlattice structure on a substrate; forming an isolation layer on the first superlattice structure; forming a second superlattice structure on the isolation layer; forming an opening, the opening passing through the second superlattice structure, the isolation layer and the first superlattice structure; and forming a source / drain region in the opening and the source / drain region is in contact with the first superlattice structure, comprising: performing a deposition process using a first flow rate of a precursor gas during a first stage of an air flow cycle and a second flow rate of the precursor gas during a second stage of the air flow cycle, wherein the first flow rate of the precursor gas is higher than the second flow rate of the precursor gas; performing a doping process using a first flow rate of a dopant precursor gas during the first stage of the air flow cycle and a second flow rate of the dopant precursor gas during the second stage of the air flow cycle, wherein the first flow rate of the dopant precursor gas is higher than the second flow rate of the dopant precursor gas; generating plasma during the second stage of the air flow cycle; and terminating the plasma during the first stage of the air flow cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures.

[0007] Figure 1A An isometric view of a fin field effect transistor (finFET) is shown in accordance with some embodiments.

[0008] Figure 1B and 1C Different cross-sectional views of a FinFET are shown according to some embodiments.

[0009] Figure 2 is a flow chart of a method for manufacturing a FinFET according to some embodiments.

[0010] Figure 3An isometric view of a FinFET during a stage of a FinFET manufacturing process is shown in accordance with some embodiments.

[0011] Figure 4A , 4B , 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 11A, 11B, 12A, 12B, 15A, 15B, 16A, 16B illustrate cross-sectional views of a FinFET at various stages of a manufacturing process of the FinFET according to some embodiments.

[0012] Fig. 9A , 9B , 10A, 10B, 13A, 13B, 14A, and 14B are schematic diagrams showing an epitaxial process for forming source / drain (S / D) regions in a semiconductor device according to some embodiments.

[0013] Fig.17A An isometric view of a complementary field effect transistor (CFET) is shown in accordance with some embodiments.

[0014] Fig. 17B A cross-sectional view of a CFET is shown according to some embodiments.

[0015] Fig.18 is a flow chart of a method for fabricating a CFET according to some embodiments.

[0016] Fig.19 An isometric view of a CFET at a stage in a manufacturing process of the CFET is shown according to some embodiments.

[0017] Figure 20-33 Cross-sectional views of a CFET at various stages of its fabrication process are shown according to some embodiments.

[0018] Fig.34A An isometric view of a vertical field effect transistor (VFET) is shown in accordance with some embodiments.

[0019] Fig.34B A cross-sectional view of a VFET is shown according to some embodiments.

[0020] Fig.35 is a flow chart of a method for fabricating a VFET according to some embodiments.

[0021] Figure 36-45 Cross-sectional views of a VFET at various stages of its fabrication process are shown according to some embodiments.

[0022] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0023] Description of reference numerals:

[0024] 100: Semiconductor devices / finFET

[0025] 102: Field Effect Transistor / NFET / PFET

[0026] 104: Substrate

[0027] 106: Fin structure

[0028] 110: Source / drain region

[0029] 112: Gate structure

[0030] 114: Gate spacer

[0031] 116: STI area

[0032] 117: ESL layer

[0033] 118: ILD layer

[0034] 120: Source / drain contact structure

[0035] 121: Interface oxide layer

[0036] 122: Thermal oxide layer

[0037] 124: Gate oxide layer

[0038] 126: WFM layer

[0039] 128: Gate metal filling layer

[0040] 130: Conductive cover layer

[0041] 132: Insulation cover

[0042] 134: Silicide layer

[0043] 136: Contact plug

[0044] 138: Nitride barrier layer

[0045] 139: Gate contact structure

[0046] 200: Methods

[0047] 205, 210, 215, 220, 225, 230: Operation

[0048] 312: Polysilicon structure

[0049] 322: Thermal oxide layer

[0050] 340: Hard mask layer

[0051] 514: Gate spacer

[0052] 710: Opening

[0053] 810: Source / drain region

[0054] 900A, 900B: Process

[0055] 902: Carrier gas flow rate

[0056] 904: Etching gas flow rate

[0057] 906: Precursor gas flow rate

[0058] 908: Plasma Conditions

[0059] 910: Dopant precursor gas flow rate

[0060] 1000A, 1000B: Process

[0061] 1006: Precursor gas flow rate

[0062] 1010: Dopant precursor gas flow rate

[0063] 1110, 1210: Source / drain region

[0064] 1300A, 1300B: Process

[0065] 1304: Etching gas flow rate

[0066] 1400A, 1400B: Process

[0067] 1408: Plasma Conditions

[0068] 1700: CFET

[0069] 1702a: GAA FET

[0070] 1702b: GAA FET

[0071] 1704: Substrate

[0072] 1706: Fin base

[0073] 1710a: Source / drain region

[0074] 1712a, 1712b: Gate structure

[0075] 1714: Gate spacer

[0076] 1716: STI Zone

[0077] 1717a, 1717b: ESL

[0078] 1718, 1718a, 1718b: ILD layer

[0079] 1720b: Source / drain contact structure

[0080] 1724: IL layer

[0081] 1726: HK gate dielectric layer

[0082] 1728: Conductive layer

[0083] 1734b: Silicide layer

[0084] 1736b: Contact plug

[0085] 1742a, 1742b: Nanostructured layer

[0086] 1746: Channel Isolation Layer

[0087] 1748: Internal spacer

[0088] 1800: Methods

[0089] 1805, 1810, 1820, 1825, 1830, 1835, 1840: Operation

[0090] 1940: Superlattice structures

[0091] 1940a: First superlattice structure

[0092] 1940b: The Second Superlattice Structure

[0093] 1942, 1944: Nanostructured layers

[0094] 1946: Nanostructured barrier layers

[0095] 2012: Polysilicon Structure

[0096] 2110: Opening

[0097] 2210, 2310, 2410, 2510, 2610, 2910, 3010: Source / drain region

[0098] 3011: Air Gap

[0099] 3400: Semiconductor devices

[0100] 3402: VFET

[0101] 3404: Substrate

[0102] 3407: Dielectric layer

[0103] 3410a, 3410b: source / drain region

[0104] 3412: Gate structure

[0105] 3414: Gate spacer

[0106] 3416: STI area

[0107] 3418: ILD layer

[0108] 3420a, 3420b: Source / drain contact structure

[0109] 3424: IL layer

[0110] 3426: HK gate dielectric layer

[0111] 3434a: Silicide layer

[0112] 3436a: Contact plug

[0113] 3439: Gate contact structure

[0114] 3442: Vertical channel layer

[0115] 3500: Methods

[0116] 3505, 3510, 3515, 3520, 3525, 3530: Operation

[0117] 3606: Vertical Structure

[0118] 3608: Silicon Germanium layer

[0119] 3610: Opening

[0120] 3810: Source / drain region

[0121] 3811: Amorphous layer

[0122] 4010, 4110: Source / drain region

[0123] 4310: Opening

[0124] 4318: ILD layer

[0125] AR: Aspect Ratio

[0126] CD: critical dimension

[0127] D: Depth / Width

[0128] D1, D2, E1, E2: non-zero value / value

[0129] H, H1, H2: Height

[0130] L: Width / distance

[0131] N, P: Height

[0132] P1, P2: non-zero value / value

[0133] PH1, PH2, PH3, PH4, PH5: Height

[0134] T1, T2: time

[0135] t1: duration

[0136] t2: duration

[0137] W: Width DETAILED DESCRIPTION

[0138] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0139] Spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0140] Note that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "exemplary embodiment," etc., indicate that the embodiment may include certain components, structures, or characteristics, but each embodiment may not necessarily include certain components, structures, or characteristics. Furthermore, these words do not necessarily refer to the same embodiment. Furthermore, when a certain component, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0141] It should be understood that the phrases or terms in the present disclosure are for the purpose of description rather than limitation, so that the phrases or terms of the present specification should be interpreted by those skilled in the relevant art based on the teachings of the present disclosure.

[0142] In some embodiments, the terms "about" and "substantially" may mean that the numerical value of a given amount varies within 5% of this numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of this numerical value). These numerical values ​​are examples only and are not limiting. The terms "about" and "substantially" may refer to percentages of numerical values ​​interpreted by a person skilled in the relevant art based on the teachings herein.

[0143] The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more optical lithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes may combine optical lithography and self-aligned processes, allowing the creation of patterns having, for example, a smaller pitch than that obtained using a single, direct optical lithography process. For example, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures.

[0144] A gate-all-around (GAA) transistor structure may be patterned by any suitable method. For example, one or more optical lithography processes may be used to pattern such a structure, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes may combine optical lithography with a self-aligned process, allowing the creation of patterns having, for example, a smaller pitch than that obtained using a single, direct optical lithography process. For example, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA transistor structure.

[0145] Source / drain regions of a field effect transistor (FET) (e.g., finFET, CFET, or VFET) can be formed by epitaxially growing a single crystal semiconductor material in an opening above a substrate. As the demand for shrinking semiconductor device dimensions continues to increase, the critical dimension (CD) of the opening is decreasing to below about 30 nm, requiring the source / drain regions to be formed in openings with increasing aspect ratios (AR) (e.g., AR greater than about 5).

[0146] However, epitaxial growth of a single crystalline semiconductor material in an opening having a dielectric side surface may also be accompanied by the formation of an amorphous semiconductor material on the dielectric side surface. As the AR of the opening increases, the amorphous semiconductor material formed on the dielectric side surface may lead to nodules and clogs, which may degrade the characteristics of the source / drain region, such as increasing the resistivity of the source / drain region. Therefore, a method of forming a source / drain region may include epitaxially growing a single crystalline semiconductor material and etching or removing the amorphous semiconductor material from the dielectric side surface. One of the challenges of etching or removing the amorphous semiconductor material from the dielectric side surface is to achieve high etch selectivity at low temperatures, that is, to achieve a high ratio between the etch rates of the amorphous semiconductor material and the crystalline semiconductor material at low temperatures. Methods of epitaxially growing semiconductor materials using thermal chemical vapor deposition (CVD) processes suffer from a loss of etch selectivity at temperatures below about 500° C., and require an additional ex-situ etching process to remove the nodules or clogs from the dielectric side surface.

[0147] To address the above challenges, the present disclosure provides an exemplary method for forming source / drain regions or epitaxial regions in a field effect transistor (e.g., finFET, CFET, or VFET) using a plasma-enhanced chemical vapor deposition (PECVD) process at a temperature of about 500° C. or less, wherein the etching selectivity of the etching process of the method is greater than about 6. In some embodiments, the method may include a deposition process and an etching process performed in situ in a PECVD chamber. In some embodiments, the method may include providing plasma, etching gas, and precursor gas in the PECVD chamber during the deposition and / or etching process to form an undoped source / drain region. In some embodiments, the method may also include providing a dopant precursor gas in the PECVD chamber during the deposition and / or etching process to form a p-type or n-type source / drain region.

[0148] In some embodiments, plasma may form radicals of a precursor gas and / or an etching gas during a deposition process and / or an etching process. Also, since radicals are highly reactive, the use of plasma may increase the deposition rate and / or etching rate during a deposition process and / or an etching process at low temperatures (e.g., at a temperature of about 500° C. to about 20° C., at a temperature of about 400° C. or less, or at a temperature of about 400° C. to about 20° C.). Also, due to the highly reactive radicals of the etching gas, an additional ex-situ etching process may be eliminated from the fabrication process of a source / drain region in a field effect transistor or an epitaxial region in a field effect transistor. Therefore, the use of plasma during a deposition process and / or an etching process may reduce the time and cost of fabricating a source / drain region or an epitaxial region in a field effect transistor.

[0149] In some embodiments, plasma conditions, flow rates of etching gases, flow rates of precursor gases, and / or flow rates of dopant precursor gases may be controlled to selectively grow semiconductor material in a single crystalline form in an opening having a CD of less than about 30 nm and an AR of greater than about 5, while substantially preventing defective amorphous semiconductor regions from being formed in source / drain regions or in epitaxial regions, and preventing nodules and blockages from being formed on side surfaces of a dielectric layer of a source / drain region in an adjacent field effect transistor or on side surfaces of a dielectric layer of an epitaxial region in a field effect transistor. Thus, source / drain regions or epitaxial regions in a field effect transistor may be formed with improved quality, such as lower resistivity at lower temperatures, compared to source / drain regions or epitaxial regions formed by other epitaxial processes, by the exemplary method.

[0150] According to some embodiments, Figure 1A 1 shows an isometric view of a semiconductor device 100 including one or more field effect transistors 102. According to some embodiments, Figure 1B Shown along Figure 1A 1 is a cross-sectional view of the field effect transistor 102 along line AA. According to some embodiments, Figure 1C Shown along Figure 1A FIG. 1 is a cross-sectional view of the field effect transistor 102 taken along line BB. Figure 1B and 1C 1 shows a field effect transistor 102 having additional structures which are not shown for simplicity. Figure 1AUnless otherwise noted, the discussion of elements with the same reference numerals applies to each other. In some embodiments, unless otherwise noted, the field effect transistor 102 may represent an n-type finFET ("NFET 102") or a p-type finFET 102 ("PFET 102"), and the discussion of the field effect transistor 102 applies to both NFET 102 and PFET 102. In some embodiments, the field effect transistor 102 may represent a GAA transistor, a nano-sheet transistor, a 2D material transistor, a planar transistor, a back-end-of-line (BEOL) transistor, a NAND (anti-AND) transistor, a 3D NAND transistor, an n-channel metal oxide semiconductor field effect (n-channel MOSFET; NMOS) transistor, or a p-channel metal oxide semiconductor field effect (p-channel MOSFET; PMOS) PMOS transistor. In some embodiments, the field effect transistor 102 may be electrically connected to a transistor not shown in FIG. Figure 1A , 1B , other devices in the 1C. For example, the field effect transistor 102 can be electrically connected to a passive device (such as an inductor, a capacitor and / or a resistor), an amplifier, a filter, a memory or a combination thereof.

[0151] Reference Figure 1A , 1B , 1C, in some embodiments, the field effect transistor 102 may be a finFET, for example Figure 1B as well as Figure 1C In some embodiments, the field effect transistor 102 may include (i) a substrate 104, (ii) a fin structure 106 disposed on the substrate 104, (ii) a gate structure 112 disposed on the fin structure 106, (iv) a gate spacer 114 disposed along a sidewall of the gate structure 112, (v) a thermal oxide layer 122 disposed on the fin structure 106 and below the gate spacer 114, (vi) a source / drain region 110 disposed in a portion of the fin structure 106 not covered by the gate structure 112, (vii) a source / drain contact structure 120 disposed on the source / drain region 110, and (viii) a gate contact structure 139 disposed on the gate structure 112. In some embodiments, the fin structure 106 and the gate structure 112 are electrically active and can be electrically coupled to a power source (not shown) via contact structures, such as source / drain contact structures 120 and gate contact structures 139. Depending on the context, the source / drain regions 110 can individually or collectively represent a source or a drain depending on the context.

[0152] Field effect transistor 102 may be formed on substrate 104. Other field effect transistors and / or structures (e.g., isolation structures) may be formed on substrate 104. Substrate 104 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. In addition, substrate 104 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, the top surface of substrate 104 may be perpendicular to a crystallographic orientation

[100] or

[110] . In some embodiments, fin structure 106 may include a material similar to substrate 104 and may have an elongated side extending along the X-axis. In some embodiments, thermal oxide layer 122 may be disposed on fin structure 106.

[0153] The field effect transistor 102 may further include a shallow trench isolation (STI) region 116, an etch stop layer (ESL) 117, and an interlayer dielectric (ILD) layer 118. The ILD layer 118 may be disposed on the ESL 117. The ESL 117 may be configured to protect the gate structure 112 and / or the source / drain region 110. In some embodiments, the STI region 116, the ESL 117, and the ILD layer 118 may include insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide (SiGeOx).

[0154] Reference Figure 1B , the gate structure 112 may be a multi-layer structure. In some embodiments, the gate structure 112 may include i) an interfacial oxide layer 121 disposed on the fin structure 106; ii) a gate oxide layer 124 disposed on the interfacial oxide layer 121; iii) a work function metal (WFM) layer 126 disposed on the gate oxide layer 124; iv) a gate metal filling layer 128 disposed on the WFM layer 126; v) a conductive cap layer 130 disposed on the gate oxide layer 124, on the WFM layer 126, and on the metal filling layer 128; and vi) an insulating cap layer 132 disposed on the conductive cap layer 130. In some embodiments, the stack of the WFM layer 126 and the gate metal filling layer 128 of the gate structure 112 may be referred to as a “metal gate stack” of the gate structure 112.

[0155] In some embodiments, the interfacial oxide layer 121 may include a thermal oxide layer. That is, the interfacial oxide layer 121 is formed by thermally oxidizing a portion of the fin structure 106 located below the gate structure 112. In some embodiments, the gate oxide layer 124 may include a non-thermal oxide layer. That is, the gate oxide layer 124 is not formed by thermally oxidizing a portion of the fin structure 106 located below the gate structure 112. In some embodiments, the gate oxide layer 124 may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2).

[0156] In some embodiments, the gate structure 112 may represent an NFET gate structure (NFET gate structure 112) or a PFET gate structure (PFET gate structure 112). In some embodiments, the WFM layer 126 of the NFET gate structure 112 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium (Al-doped Ti), aluminum-doped titanium nitride (Al-doped TiN), aluminum-doped tantalum (Al-doped Ta), aluminum-doped tantalum nitride (Al-doped TaN), other suitable aluminum-based (Al-based) materials, or combinations thereof. In some embodiments, the WFM layer 126 of the PFET gate structure 112 may include a substantially aluminum-free (e.g., aluminum-free) titanium-based or tantalum-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, tantalum-copper (Ta-Cu) alloy, and combinations thereof. The gate metal fill layer 128 may include a suitable conductive material, such as tungsten (W), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0157] During subsequent semiconductor device processing, the insulating cap layer 132 protects the underlying conductive cap layer 130 from structural and / or compositional degradation. In some embodiments, the insulating cap layer 132 may include a nitride material, such as silicon nitride, and may have a thickness of about 5 nm to about 10 nm for adequately protecting the underlying conductive cap layer 130. The conductive cap layer 130 provides a conductive interface between the gate contact structure 139 and the gate metal fill layer 128 to electrically connect the metal gate stack of the gate structure 112 to the gate contact structure 139 without forming the gate contact structure 139 directly on or within the metal gate stack. The gate contact structure 139 is not formed directly on or within the metal gate stack to prevent any process materials that form the gate contact structure 139 from contaminating the metal gate stack. Contamination of the metal gate stack may result in degradation of device performance. Therefore, with the use of the conductive cap layer 130, the metal gate stack may be electrically connected to the gate contact structure 139 without affecting the integrity of the gate structure 112. In some embodiments, the conductive cap layer 130 and the gate contact structure 139 may include metal materials, such as W, Ru, Ir, Mo, other suitable metal materials and combinations thereof. In some embodiments, the conductive cap layer 130 and the gate contact structure 139 may include the same metal material or may have different metal materials from each other.

[0158] In some embodiments, the gate spacer 114 may include a vertical portion disposed directly on a sidewall of the gate structure 112. In some embodiments, the gate spacer 114 may include a horizontal portion in contact with the thermal oxide layer 122. In some embodiments, a top surface of the gate spacer 114 may be located above a top surface of the conductive cap layer 130 and below a top surface of the insulating cap layer 132. In some embodiments, a top surface of the gate spacer 114 may be covered by the insulating cap layer 132. In some embodiments, the gate spacer 114 may include a silicon oxycarbide (SiCO) layer, a silicon oxycarbide nitride (SiCON) layer, a silicon nitride (SiN) layer, or a combination thereof. In some embodiments, the gate spacer 114 may have a thickness of about 2 nm to about 10 nm.

[0159] In some embodiments, Figure 1B as well as Figure 1C As shown, the source / drain region 110 may be disposed above the recessed portion of the fin structure 106. In some embodiments, the source / drain region 110 may contact the sidewall of a portion of the fin structure 106 adjacent to the gate structure 112. In some embodiments, the source / drain region 110 may contact the sidewall of the STI region 116. In some embodiments, the source / drain region 110 may contact the side surface of the thermal oxide layer 122. In some embodiments, as Figure 1CAs shown, the width W of the source / drain region 110 between the opposing sidewalls of the STI region 116 may be about 5 nm to about 30 nm. The width W may also be referred to as CD. Figure 1C , the height H of the portion of the source / drain region 110 below the top surface of the thermal oxide layer 122 is indicated. The ratio between the height H and the width W is referred to as the aspect ratio (AR). In some embodiments, the AR of the source / drain region 110 may be greater than about 5.

[0160] In some embodiments, each source / drain region 110 may include an epitaxially grown semiconductor material, such as silicon, germanium, silicon carbide (SiC), silicon germanium, and silicon tin (SiSn). In some embodiments, for NFET 102, each source / drain region 110 may include an epitaxially grown n-type semiconductor material, such as silicon phosphide (SiP), silicon carbon phosphide (SiCP), silicon germanium phosphide (SiGeP), silicon germanium phosphide carbon (SiGeCP), silicon arsenide (SiAs), silicon arsenide carbon (SiCAs), silicon germanium arsenide (SiGeAs), and silicon germanium arsenide carbon (SiGeCAs). In some embodiments, for PFET 102, each source / drain region 110 may include an epitaxially grown p-type semiconductor material, such as silicon boride (SiB), silicon boride carbon (SiCB), silicon germanium boride (SiGeB), and silicon germanium boride carbon (SiGeCB). In some embodiments, the dopant concentration in the source / drain region 110 may be approximately 10 19 Atom / cm 3 to about 10 21 Atom / cm 3 .

[0161] In some embodiments, the source / drain contact structure 120 may include a silicide layer 134 disposed on the source / drain region 110, a contact plug 136 disposed on the silicide layer 134, and a nitride barrier layer 138 along the sidewall of the contact plug 136. In some embodiments, the silicide layer 134 may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si), cobalt silicide (Co x Si y ), tungsten silicide (W x Si y In some embodiments, the contact plug 136 may include a conductive material such as cobalt, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, copper, zirconium, tin, silver, gold, zinc, cadmium, and combinations thereof.

[0162] According to some embodiments, Figure 2 For use in manufacturing a Figures 1A-1CFlowchart of an exemplary method of constructing a field effect transistor 102 in FIG. For illustrative purposes, reference will be made to Figure 3 as well as Figure 4A , 4B , 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, and an exemplary manufacturing process for manufacturing field effect transistor 102 is described. Figure 2 According to some embodiments, Figure 3 An isometric view of a stage in the fabrication of field effect transistor 102 is shown. According to some embodiments, Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.11A , Fig. 12A , Fig.15A as well as Fig.16A For field effect transistor 102 at various stages of manufacture along Figure 1A as well as Figure 3 According to some embodiments, Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 11B , Fig. 12B , Fig. 15B as well as Fig. 16B For field effect transistor 102 at various stages of manufacture along Figure 1A as well as Figure 3 According to some embodiments, Fig. 9A , 9B , 10A, 10B, and Fig.13A , 13B , 13A, 14B show the configuration of plasma conditions for epitaxially growing semiconductor materials and the configuration of the flow rate of process gases during the formation of field effect transistor 102. Depending on the specific application, the operations may be performed in different orders or not performed. It should be noted that method 200 may not produce a complete field effect transistor 102. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only some other processes may be briefly described in this disclosure. Figure 3 as well as Figure 4A , 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B and the components having the same Figure 1A , 1B , the same annotations as those for the components in 1C.

[0163] In operation 205, a fin structure of a field effect transistor is formed on a substrate. Figure 3 As shown, the fin structure 106 of the field effect transistor 102 is formed on the substrate 104. The formation of the fin structure 106 may include sequential operations: (i) forming a patterned mask layer (not shown) on the substrate 104, and (ii) etching the substrate 104 to form the fin structure 106. Figure 3 As shown, after forming the fin structure 106, the STI region 116 may be formed. After forming the STI region 116, a thermal oxide layer may be formed. For example, Figure 3 As shown, a thermal oxide layer 322 is formed on the fin structure 106. The thermal oxide layer 322 may be formed in a thermal oxidation process. In some embodiments, the thermal oxidation process may include oxidizing the surface of the fin structure 106 exposed above the STI region 116 in an oxidizing ambient at a temperature of about 30°C to about 200°C or other suitable oxidation temperatures. In some embodiments, the oxidizing ambient may include a mixture of ozone (O3), ammonium hydroxide, hydrogen peroxide and water, and / or a mixture of hydrochloric acid, hydrogen peroxide and water. In some embodiments, the thermal oxidation process may include oxidizing the surface of the fin structure 106 exposed above the STI region 116 in an oxygen environment or an oxygen vapor environment at a temperature of about 400°C to about 600°C.

[0164] Reference Figure 2 In operation 210, a polysilicon structure is formed on the fin structure. Figure 3 As shown, the polysilicon structure 312 is formed on the fin structure 106 and on the thermal oxide layer 322 . Figure 4A as well as Figure 4B Along the Figure 31 is a cross-sectional view of the field effect transistor 102 along line AA and line BB in FIG. The polysilicon structure 312 is a sacrificial structure and may be replaced in a subsequent replacement process to form the gate structure 112. In some embodiments, a hard mask layer 340 may be formed on the polysilicon structure 312 to pattern the polysilicon structure 312. In some embodiments, the formation of the polysilicon structure may include sequential operations of: i) blanket depositing a film layer of polysilicon material, ii) forming and patterning a hard mask layer 340 on the film layer of polysilicon material, and iii) etching the film layer of polysilicon material through the patterned hard mask layer 340. In some embodiments, the blanket deposition of the film layer of polysilicon material may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or any other suitable deposition process. In some embodiments, the etching of the deposited film layer of polysilicon material may include dry etching, wet etching, or a combination thereof.

[0165] Reference Figure 2 In operation 215, a gate spacer is formed on the polysilicon structure and on the thermal oxide layer. Figure 5A as well as Figure 5B As described above, the gate spacer 514 is formed on the sidewalls of the polysilicon structure 312, on the surface of the thermal oxide layer 322, and on the surface of the STI region 116. In some embodiments, the formation of the gate spacer 514 may include: Figure 4A as well as Figure 4B In some embodiments, forming the gate spacer 114 may include depositing the material of the gate spacer 114 in a CVD process, a PVD process, an ALD process, or any other suitable deposition process.

[0166] Reference Figure 2 In operation 220, source / drain regions are formed on the fin structure. Fig. 6A , 6B As described in FIGS. 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B, a source / drain region 110 is formed on the fin structure 106. The formation of the source / drain region 110 may include the following operations: (i) Fig. 6A as well as Figure 6B As shown, a portion of the gate spacer 514 and a portion of the thermal oxide layer 322 are removed to expose the region of the fin structure 106, (ii) as shown in FIG. Fig. 7A as well as Figure 7B As shown, a source / drain region opening 710 is formed by removing a portion of the fin structure 106, a portion of the thermal oxide layer 32 and a portion of the gate spacer 514, and (iii) Fig. 8A as well as Figure 8B As shown, epitaxially growing semiconductor material in the source / drain openings 710 to form the source / drain region 110. In some embodiments, removing a portion of the gate spacer 514 and a portion of the thermal oxide layer 322 may include patterning the gate spacer 514 using a mask and etching a portion of the gate spacer 514 and a portion of the thermal oxide layer 322 to expose an area of ​​the fin structure 106. In some embodiments, removing a portion of the fin structure 106 may include dry etching, wet etching, or a combination thereof. In some embodiments, a pre-cleaning operation may be performed before epitaxially growing semiconductor material in the source / drain openings 710 to remove residues or contaminants left when forming the source / drain openings 710.

[0167] In some embodiments, epitaxially growing semiconductor material in the source / drain openings 710 may include epitaxially growing semiconductor material having the same crystal orientation as the substrate 104 and / or the fin structure 106. In some embodiments, epitaxially growing semiconductor material in the source / drain openings 710 may include epitaxially growing semiconductor material along a crystal orientation

[100] or

[110] . In some embodiments, epitaxially growing semiconductor material in the source / drain openings 710 may include a deposition process, such as a PECVD process at a temperature of about 500° C. or less (e.g., at a temperature of about 500° C. to about 20° C., at a temperature of about 400° C. or less, or at a temperature of about 400° C. to about 20° C.).

[0168] In some embodiments, the epitaxially grown semiconductor material may include epitaxially grown crystalline form of semiconductor material. In some embodiments, an amorphous form of an unwanted semiconductor material may be deposited in the source / drain opening 710 along with a crystalline form of the semiconductor material. Therefore, as discussed below, the process of epitaxially growing semiconductor material in the source / drain opening 710 may also include an etching process that selectively etches the amorphous form of the unwanted semiconductor material and a deposition process that grows the crystalline form of the semiconductor material. In some embodiments, the deposition process and the etching process may be performed in situ in a PECVD chamber. In some embodiments, the amorphous form of the unwanted semiconductor material may be amorphous silicon (a-Si), and the crystalline form may be crystalline silicon (c-Si). In some embodiments, the etching selectivity between the amorphous form (e.g., a-Si) and the crystalline form (e.g., c-Si) of the semiconductor material during the etching process may be greater than about 6. The term "etching selectivity" is used in the present disclosure to define the ratio of the etching rate of a-Si to the etching rate of c-Si,

[0169] In some embodiments, epitaxially growing semiconductor material in the source / drain openings 710 may include (i) maintaining a base pressure in the PECVD chamber at about 10 -7 (ii) maintaining the process pressure in the PECVD chamber at about 10 -4 Torr to about 1520 Torr, (iii) generating plasma in a PECVD chamber, (iv) controlling the plasma condition to be in an "on" condition (also referred to as "plasma generation condition") or an "off" condition (also referred to as "plasma termination condition") during a deposition process and an etching process as described in detail below, (v) using a plasma frequency of about 1 Hz to about 3 GHz, (vi) using a plasma power of about 1 W to about 10,000 W, and / or (vii) using a plasma source pulsing frequency of about 1 Hz to about 1 MHz. Plasma "on" refers to a state in which plasma is generated, and plasma "off" refers to a state in which plasma is terminated.

[0170] In some embodiments, epitaxially growing semiconductor material in the source / drain openings 710 may include epitaxially growing undoped semiconductor material in a PECVD process. In some embodiments, epitaxially growing undoped semiconductor material may include epitaxially growing silicon (Si), germanium (Ge), tin (Sn), silicon carbide (SiC), silicon germanium (SiGe), silicon tin (SiSn), silicon germanium carbon (SiGeC), silicon germanium tin (SiGeSn), or germanium tin (GeSn). In some embodiments, as described in detail below, epitaxially growing undoped semiconductor material may include flowing process gases in a PECVD chamber during a deposition process and / or an etching process, the process gases including a carrier gas, a precursor gas, and an etching gas. In some embodiments, the carrier gas may include hydrogen (H2), helium (He), argon (Ar), nitrogen (N2), or a combination thereof. In some embodiments, the flow rate of the carrier gas may be from about 1 sccm to about 50,000 sccm. In some embodiments, the precursor gas may be or include a silicon precursor gas, a germanium precursor gas, a tin precursor gas, or a combination thereof. In some embodiments, the silicon precursor gas may include silane (Si m H 2m+2-n X n , where 1≤m≤5 and 0≤n≤(2m+2)), cyclosilane (Si m H 2m-n X n , wherein 3≤m≤5 and 0≤n≤2m) or a combination thereof. In some embodiments, the germanium precursor gas may include germanium (Ge m H 2m+2-n X n , where 1≤m≤5 and 0≤n≤(2m+2)), cyclogermane (Si m H 2m-n X n , wherein 3≤m≤5 and 0≤n≤2m) or a combination thereof. In some embodiments, the tin precursor gas may include a stannous precursor (SnH 2-n X n , where 0≤n≤2), tin precursor (SnH 4-n X n , where 0≤n≤4) or a combination thereof. In the above examples of precursor gases, X may be fluorine (F), chlorine (Cl), bromine (Br), iodine (I) or methyl (CH3). In some embodiments, the flow rate of the precursor gas may be about 0.01 sccm to about 5000 sccm. In some embodiments, the etching gas may include hydrogen, fluorine (F2), chlorine (Cl2), hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr) or a combination thereof. In some embodiments, the flow rate of the etching gas may be about 0.1 sccm to about 5000 sccm.

[0171] In some embodiments, epitaxially growing semiconductor materials in the source / drain regions 710 may include epitaxially growing p-type semiconductor materials using a PECVD process. In some embodiments, epitaxially growing p-type semiconductor materials may include epitaxially growing silicon (Si), silicon boride (SiB), silicon aluminum (SiAl), silicon gallium (SiGa), silicon indium (SiIn), germanium (Ge), germanium boron (GeB), aluminum germanium (GeAl), gallium germanium (GeGa), indium germanium (GeIn), tin (Sn), tin boron (SnB), tin aluminum (SnAl), tin gallium (SnGa), tin indium (SnIn), silicon carbide (SiC), silicon carbon boride (SiCB), silicon carbon aluminum (SiCAl), silicon carbon gallium (SiCGa), silicon carbon indium (SiCIn), silicon germanium (SiGe), silicon germanium boride (SiGeB), silicon germanium aluminum (SiGeAl), silicon germanium gallium (SiGeGa), silicon germanium indium (SiGeIn ), silicon tin (SiSn), silicon tin boride (SiSnB), silicon tin aluminum (SiSnAl), silicon tin gallium (SiSnGa), silicon tin indium (SiSnIn), silicon germanium carbon (SiGeC), silicon germanium carbon boride (SiGeCB), silicon germanium carbon aluminum (SiGeCAl), silicon germanium carbon gallium (SiGeCGa), silicon germanium carbon indium (SiGeCIn), silicon germanium tin (SiGeSn), silicon germanium tin boron (SiGeSnB), silicon germanium tin aluminum (SiGeSnAl), silicon germanium tin gallium (SiGeSnGa), silicon germanium tin indium (SiGeSnIn), germanium tin (GeSn), germanium tin boride (GeSnB), germanium tin aluminum (GeSnAl), germanium tin gallium (GeSnGa), germanium tin indium (GeSnIn), germanium tin (GeSn), germanium tin boride (GeSnB), germanium tin aluminum (GeSnAl), germanium tin gallium (GeSnGa), germanium tin indium (GeSnIn), or a combination thereof.

[0172] In some embodiments, as described in detail below, epitaxially growing a p-type semiconductor material may include flowing process gases in a PECVD chamber during a deposition process and / or an etching process, the process gases including a carrier gas, a precursor gas, an etching gas, and a p-type dopant precursor gas. Unless otherwise noted, the discussion of carrier gases, precursor gases, and etching gases in epitaxially growing undoped semiconductor materials is applicable to epitaxially growing p-type semiconductor materials. In some embodiments, the p-type dopant precursor gas may be or include a boron precursor gas, an aluminum precursor gas, a gallium precursor gas, an indium precursor gas, or a combination thereof. In some embodiments, the boron precursor gas may include borane (BH3, B2H4, B2H6, B3H5, ​​B3H7, B m H m+4 and / or B m H m+6 , wherein m≥3), boron halides (BX3 and / or B2X4), alkylboranes ((C m H2 m+1)3B, wherein m≥1) or a combination thereof. In some embodiments, the aluminum precursor gas may include alane (AlH3 and / or Al2H4), haloalane (AlX3), alkylalane ((C m H 2m+1 AlX 3-n , wherein m ≥ 1, 0 ≤ n ≤ 3) or a combination thereof. In some embodiments, the gallium precursor gas may include gallium alkane (GaH3 and / or Ga2H4), gallium halide (GaX3), alkyl gallium alkane (C m H 2m+1 ) n GaX 3-n , wherein m≥1, 0≤n≤3). In some embodiments, the indium precursor gas may include indium halide (InX3), alkylindium ((C m H 2m+1 ) n InX 3-n , wherein m≥1, 0≤n≤3) or a combination thereof. In the above examples of the p-type dopant precursor gas, X may represent Cl, Br, or I. In some embodiments, the flow rate of the p-type dopant precursor gas may be about 0.001 sccm to about 5000 sccm.

[0173] In some embodiments, epitaxially growing semiconductor materials in the source / drain regions 710 may include epitaxially growing n-type semiconductor materials using a PECVD process. In some embodiments, epitaxially growing n-type semiconductor materials may include epitaxially growing silicon (Si), silicon phosphide (SiP), silicon arsenide (SiAs), silicon antimony (SiSb), silicon bismuth (SiBi), germanium (Ge), germanium phosphide (GeP), germanium arsenide (GeAs), germanium antimony (GeSb), germanium bismuth (GeBi), tin (Sn), tin phosphide (SnP), tin arsenide (SnAs), tin antimony (SnSb), tin bismuth (SnBi), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon carbon arsenide (SiCAs), silicon carbon antimony (SiCSb), silicon carbon bismuth (SiCBi), silicon germanium (SiGe), silicon germanium phosphide (SiGeP), silicon germanium arsenide (SiGeAs), silicon germanium antimony (SiGeSb), silicon germanium bismuth (SiGeB i), silicon tin (SiSn), silicon tin phosphide (SiSnP), silicon tin arsenide (SiSnAs), silicon tin antimony (SiSnSb), silicon tin bismuth (SiSnBi), silicon germanium carbon (SiGeC), silicon germanium carbon phosphide (SiGeCP), silicon germanium carbon arsenide (SiGeCAs), silicon germanium carbon antimony (SiGeCSb), silicon germanium carbon bismuth (SiGeCBi), silicon germanium tin (SiGeSn), silicon germanium tin phosphide (SiGeSnP), silicon germanium tin arsenide (SiGeSnAs), silicon germanium tin antimony (SiGeSnSb), silicon germanium tin bismuth (SiGeSnBi), germanium tin (GeSn), germanium tin phosphide (GeSnP), germanium tin arsenide (GeSnAs), germanium tin antimony (GeSnSb), germanium tin bismuth (SiGeSnBi), germanium tin (GeSn), germanium tin phosphide (GeSnP), germanium tin arsenide (GeSnAs), germanium tin antimony (GeSnSb), germanium tin bismuth (GeSnBi), germanium tin (GeSn), germanium tin

[0174] In some embodiments, as described in detail below, epitaxially growing an n-type semiconductor material may include flowing process gases in a PECVD chamber during a deposition process and / or an etching process, the process gases including a carrier gas, a precursor gas, an etching gas, and an n-type dopant precursor gas. Unless otherwise noted, the discussion of carrier gases, precursor gases, and etching gases in epitaxially growing undoped semiconductor materials is applicable to epitaxially growing n-type semiconductor materials. In some embodiments, the n-type dopant precursor gas may be or include a phosphorus precursor gas, an arsenic precursor gas, an antimony precursor gas, a bismuth precursor gas, or a combination thereof. In some embodiments, the phosphorus precursor gas may include phosphine (PH3 and / or P m H m+2 , wherein m ≥ 1), phosphorus halides (PX3, PX5 and / or P2X4) or a combination thereof. In some embodiments, the arsenic precursor gas may include arsine (AsH3 and / or As m H m+2, wherein m>1) and arsenic halides (AsX3 and / or AsX5), or a combination thereof. In some embodiments, the antimony precursor gas may include antimony alkane (SbH3), antimony halides (SbX3 and / or SbX5), or a combination thereof. In some embodiments, the bismuth precursor gas may include bismuth (BiH3), bismuth halides (BiX3 and / or BiX5), or a combination thereof. In the above examples of n-type dopant precursor gases, X may represent Cl, Br, or I. In some embodiments, the flow rate of the n-type dopant precursor gas may be about 0.001 sccm to about 5000 sccm.

[0175] In some embodiments, as described in detail below, the Fig. 9A Process 900A, Fig. 10A Process 1000A, Fig.13A Process 1300A or Fig.14A The process 1400A is performed as Fig. 8A as well as Figure 8B Epitaxial growth of undoped semiconductor material in the source / drain openings 710 shown. In some embodiments, as described in detail below, Fig. 9B Process 900B, Fig. 10B Process 1000B, Fig. 13B Craft 1300B or Fig. 14B The process 1400B is performed as Fig. 8A as well as Figure 8B Epitaxial growth of doped semiconductor material is shown in source / drain openings 710. In some embodiments, each of process 1000A, process 1000B, process 1300A, process 1300B, 1400A, and process 1400B may be performed in-situ in a PECVD chamber.

[0176] Reference Fig. 9A In some embodiments, epitaxially growing an undoped semiconductor material may include controlling plasma conditions and flow rates of a carrier gas, a precursor gas, and an etching gas during a deposition process and an etching process. For example, as shown in FIG. Fig. 9AAs described in process 900A of the present invention, the process of epitaxially growing undoped semiconductor material in the source / drain opening 710 can start at time T1 and end at time T2. Plasma can be provided between time T1 and time T2, as shown by plasma condition 908, which is "on" between time T1 and time T2 and "off" otherwise. The carrier gas flow rate 902 can be maintained at a non-zero value, starting before time T1 and ending after time T2. The etching gas flow rate 904 and the precursor gas flow rate 906 can both be maintained at non-zero values ​​E1 and non-zero values ​​P1, respectively, starting at time T1 and ending at time T2. In other words, the etching gas and the precursor gas can co-flow between time T1 and time T2. In some embodiments, the ratio between the precursor gas flow rate 906 and the etching gas flow rate 904 (ie, P1:E1) may be about 50,000:1 to about 1:50,000 to sufficiently grow high-quality crystalline semiconductor material within the source / drain openings 710. Fig. 9A As shown, a gas purging process may be performed before time T1 and after time T2.

[0177] In some embodiments, the precursor gas may epitaxially grow a crystalline form of undoped semiconductor material on the fin structure 106. In some embodiments, the precursor gas may also deposit an amorphous form of undoped semiconductor material on dielectric surfaces, such as the surface of the thermal oxide layer 322, the surface of the gate spacer 514, and the surface of the STI region 116. The etching gas may selectively etch the amorphous form of the undoped semiconductor material. In some embodiments, the etching selectivity may be greater than about 6 at a temperature of about 500° C. or less (e.g., at a temperature of about 500° C. to about 20° C., at a temperature of about 400° C. or less, or at a temperature of about 400° C. to about 20° C.). In some embodiments, co-flowing the precursor gas and the etching gas with an etching selectivity of greater than about 6 may epitaxially grow the source / drain region 110 having the undoped semiconductor material and prevent the formation of nodules and blockages on the sidewalls of the source / drain opening 710, the source / drain opening 710 having a CD of about 5 nm to about 30 nm and an AR greater than about 5.

[0178] Reference Fig. 9B In some embodiments, epitaxially growing a p-type semiconductor material or an n-type semiconductor material may include controlling plasma conditions and a flow rate of a carrier gas, a flow rate of a precursor gas, and a flow rate of an etching gas during a deposition process and an etching process. Unless otherwise mentioned, Fig. 9A The discussion in Process 900A applies to Fig. 9B Process 900B. Fig. 9BAs described in process 900B of the embodiment, the dopant precursor gas flow rate 910 may be maintained at a non-zero value D1, starting at time T1 and ending at time T2 together with the etching gas flow rate 904 and the precursor gas flow rate 906. In other words, the etching gas, the precursor gas, and the dopant precursor gas may flow together between time T1 and time T2. In some embodiments, the ratio between the dopant precursor gas flow rate 910 and the precursor gas flow rate 906 (i.e., D1:E1) may be about 1:1000 to about 1000:1 to sufficiently grow high-quality crystalline doped semiconductor material in the source / drain opening 710. In some embodiments, as Fig. 9B As shown, the gas purge process may be performed before time T1 and after time T2.

[0179] In some embodiments, the precursor gas and the dopant precursor gas may epitaxially grow a crystalline form of a p-type or n-type semiconductor material on the fin structure 106. In some embodiments, the precursor gas and the dopant precursor gas may also deposit an amorphous form of a p-type or n-type semiconductor material on dielectric surfaces, such as a surface of the thermal oxide layer 322, a surface of the gate spacer 514, and a surface of the STI region 116. The etching gas may selectively etch an amorphous form of the p-type or n-type semiconductor material. In some embodiments, the etching selectivity may be greater than about 6 at a temperature of about 500° C. or less (e.g., at a temperature of about 500° C. to about 20° C., at a temperature of about 400° C. or less, or at a temperature of about 400° C. to about 20° C.). In some embodiments, co-flowing the precursor gas, dopant precursor gas, and etching gas with an etch selectivity greater than about 6 can epitaxially grow source / drain regions 110 having p-type or n-type semiconductor materials and prevent nodules and blockages from forming on the sidewalls of the source / drain openings 710, which have a CD of about 5 nm to about 30 nm and an AR greater than about 5.

[0180] Reference Fig. 10A In some embodiments, epitaxially growing an undoped semiconductor material may include controlling the flow rate of a precursor gas in a cyclic manner during a deposition process and an etching process, for example, by Fig. 10A Process 1000A. Unless otherwise mentioned, Fig. 9A The discussion in Process 900A applies to Fig. 10A Process 1000A. Fig. 9A as well as Fig. 9BAs shown, during the process of epitaxially growing undoped semiconductor material between time T1 and time T2, the precursor gas flow rate may be changed in the gas flow cycle, rather than being maintained at the P1 value between time T1 and time T2. Each gas flow cycle may include a first and a second phase, and may have a duration of t1+t2. In the first phase having a duration of t1, the precursor gas flow rate 1006 may be maintained at the P1 value, which may be a non-zero value. In the second phase having a duration of t2, the precursor gas flow rate 1006 may be maintained at a P2 value that is different from the P1 value. In some embodiments, the P2 value may be lower than the P1 value. For example, Fig. 10A As shown, the P2 value can be zero.

[0181] In some embodiments, when the precursor gas flow rate 1006 is at a lower value than during the first phase of the gas flow cycle, changing the precursor gas flow rate 1006 during the gas flow cycle can facilitate the etching gas to sufficiently remove a larger amount of the amorphous form of the undoped semiconductor material during the second phase of the gas flow cycle. In some embodiments, changing the precursor gas flow rate 1006 during the gas flow cycle of process 1000A can selectively epitaxially grow the undoped semiconductor material on the fin structure 106 with higher etch selectivity and / or less amorphous form at approximately 500° C. or lower temperature compared to process 900A and process 900B. In some embodiments, the deposition rate (also referred to as the "epitaxial growth rate") during the first phase of each gas flow cycle of process 1000A can be higher than the deposition rate during the second phase of each gas flow cycle of process 1000A. In some embodiments, the deposition rate can be higher than the etching rate during the first phase of each gas flow cycle, and the etching rate can be higher than the deposition rate during the second phase of each gas flow cycle. In some embodiments, as Fig. 10A As shown, the gas purge process may be performed before time T1 and after time T2 and not between gas flow cycles of the precursor gas.

[0182] Reference Fig. 10B In some embodiments, epitaxially growing a p-type or n-type semiconductor material may include controlling the flow rate of a precursor gas in a cyclic manner during a deposition process and an etching process, for example by Fig. 10B Unless otherwise stated, Fig. 10A The discussion in Process 1000A applies to Fig. 10B Process 1000B. Fig. 9BAs shown, during the process of epitaxially growing a p-type or n-type semiconductor material between time T1 and time T2, the dopant precursor gas flow rate 1006 may be changed in the gas flow cycle, rather than maintaining a constant D1 value between time T1 and time T2. In the first stage of each gas flow cycle, the dopant precursor gas flow rate 1010 may be maintained at the D1 value, which may be a non-zero value. In the second stage of each gas flow cycle, the dopant gas flow rate 1010 may be maintained at a D2 value different from the D1 value. In some embodiments, the D2 value may be lower than the D1 value. For example, if Fig. 10B As shown, the D2 value may be zero. Therefore, during the first stage of each gas flow cycle of process 1000B, the dopant precursor gas may flow together with the precursor gas. In some embodiments, varying the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 during the gas flow cycle may sufficiently promote the selective epitaxial growth of p-type or n-type semiconductor material on the fin structure 106.

[0183] Reference Fig.13A In some embodiments, epitaxially growing an undoped semiconductor material may include controlling the flow rate of an etching gas and the flow rate of a precursor gas in a cyclic manner during a deposition process and an etching process, for example, by Fig.13A Process 1300A. Unless otherwise mentioned, Fig. 10A The discussion of process 1000A applies to Fig.13A Process 1300A. Fig. 9A , 9B as well as Fig. 10A , 10B As shown, during the process of epitaxially growing undoped semiconductor material between time T1 and time T2, the etching gas flow rate 1304 may be varied in the gas flow cycle rather than maintained at a constant E1 value. In the first phase of each gas flow cycle, the etching gas flow rate 1304 may be maintained at the E2 value. In the second phase of each gas flow cycle, the etching gas flow rate 1304 may be maintained at an E1 value different from the E2 value. In some embodiments, the E1 value may be greater than the E2 value. For example, Fig.13A As shown, the value E2 of the etching gas flow rate 1304 may be zero in the first stage, while the value E1 may be non-zero in the second stage. Fig.13A As shown, in the first phase of each gas flow cycle of process 1300A, the precursor gas flow rate 1006 may be non-zero, while the etching gas flow rate 1304 may be zero. Fig.13AAs shown, in the second stage of each gas flow cycle of process 1300A, the etching gas flow rate 1304 may be non-zero, while the precursor gas flow rate 1006 may be zero. In other words, the precursor gas and the etching gas may not be supplied to the PECVD chamber at the same time and may not flow together in the PECVD chamber during each gas flow cycle of process 1300A. Between time T1 and time T2, the precursor gas and the etching gas may be alternately supplied to the PECVD chamber and alternately flow in the PECVD chamber. Therefore, in process 1300A, the deposition process may be performed during the first stage of each gas flow cycle instead of during the second stage of each gas flow cycle. On the other hand, in process 1300A, the etching process may be performed during the second stage of each gas flow cycle instead of during the first stage of each gas flow cycle.

[0184] In some embodiments, alternating the flow of the precursor gas and the etching gas during each gas flow cycle of the process 1300A can promote faster growth of the undoped semiconductor material during the first stage of the gas flow cycle compared to the processes 900A, 900B, 1000A, and 1000B. Moreover, alternating the flow of the precursor gas and the etching gas during each gas flow cycle of the process 1300A can epitaxially grow the undoped semiconductor material on the fin structure 106 at a temperature of about 500° C. or less with a higher etch selectivity compared to the processes 900A, 900B, 1000A, and 1000B.

[0185] Reference Fig. 13B In some embodiments, epitaxially growing a p-type or n-type semiconductor material may include controlling the flow rate of an etching gas, the flow rate of a precursor gas, and the flow rate of a dopant precursor gas in a cyclic manner during a deposition process and an etching process, for example, by Fig. 13B Unless otherwise mentioned, Fig. 10B Process 1000B and Fig.13A The discussion of Process 1300A applies to Fig. 13B Process 1300B. Fig. 13B As shown, during the process of epitaxially growing a p-type or n-type semiconductor material between time T1 and time T2, (i) during the first stage of each gas flow cycle, the E2 value of the etching gas flow rate 1304 can be maintained at zero, while the P1 value of the precursor gas flow rate 1006 and the D1 value of the dopant precursor gas flow rate 1010 can be maintained at a non-zero value, and (ii) during the second stage of each gas flow cycle, the E1 value of the etching gas flow rate can be maintained at a non-zero value, while the P2 value of the precursor gas flow rate 1006 and the D2 value of the dopant precursor gas flow rate 1010 can be maintained at zero.

[0186] Reference Fig.14AIn some embodiments, epitaxially growing an undoped semiconductor material may include controlling plasma conditions, etching gas, and precursor gas in a cyclic manner during a deposition process and an etching process, such as by Fig.14A Process 1400A. Unless otherwise mentioned, Fig.13A The discussion of Process 1300A applies to Fig.14A In some embodiments, during the process of epitaxially growing the undoped semiconductor material between time T1 and time T2, the plasma condition 1408 may be changed in the gas flow cycle along with the etching gas flow rate 1304 and the precursor gas flow rate 1006. In some embodiments, as Fig.14A As shown, the plasma condition 1408 may be "off" during the first phase of each gas flow cycle of the process 1400A, and may be "on" during the second phase of each gas flow cycle of the process 1400A. Thus, when the etching gas flow rate 1304 is maintained at the E1 value and the precursor gas flow rate 1006 is maintained at the P2 value, a plasma may be generated in the PECVD chamber (i.e., an "on" condition). When the etching gas flow rate 1304 is maintained at the E2 value and the precursor gas flow rate 1006 is maintained at the value P1, there may be no plasma in the PECVD chamber (i.e., an "off" condition). In some embodiments, generating a plasma during the etching process in the second phase of the process 1400A may provide a higher etching selectivity at a temperature of about 500° C. or less.

[0187] Reference Fig. 14B In some embodiments, epitaxially growing a p-type or n-type semiconductor material may include controlling plasma conditions, etching gas, precursor gas, and dopant precursor gas in a cyclic manner during a deposition process and an etching process, such as by Fig. 14B Unless otherwise mentioned, Fig. 13B Process 1300B and Fig.14A The discussion of Process 1400A applies to Fig.14A In some embodiments, during the process of epitaxially growing a p-type or n-type semiconductor material between time T1 and time T2, the plasma conditions 1408, the etching gas flow rate 1304, and the precursor gas flow rate 1006 may be as described with reference to Fig.14A The dopant precursor gas flow rate 1010 may be changed as discussed above. Fig. 13B The changes discussed were made.

[0188] Reference Fig. 8A , Figure 8B , Fig. 10A , 11A , 12A, 13A, 14A and Fig. 10B , 11B, 12B, 13B, 14B, unless otherwise noted, the following discussion of epitaxially growing semiconductor material in source / drain openings 710 during gas flow cycles applies to each of process 1000A, process 1000B, process 1300A, process 1300B, process 1400A, and process 1400B. The process of epitaxially growing semiconductor material between time T1 and time T2 may include one or more gas flow cycles. In some embodiments, as Fig.11A as well as Fig. 11B As shown, after the first gas flow cycle is completed, a source / drain region 1110 having a height H1 may be formed in the source / drain opening 710. In some embodiments, as Fig. 12A as well as Fig. 12B As shown, after the second gas flow cycle is completed, a source / drain region 1210 having a height H2 may be formed in the source / drain opening 710, and the height H2 is greater than the height H1. Fig. 8A as well as Figure 8B As shown, after multiple gas flow cycles are completed at time T2, source / drain regions 810 may be formed. Fig. 10A , Fig. 10B , Fig.13A , Fig. 13B , Fig.14A as well as Fig. 14B 1000A, process 1000B, process 1300A, process 1300B, process 1400A, and process 1400B are shown in each of the three gas flow cycles. Fig. 10A , Fig. 10B , Fig.13A , Fig. 13B , Fig.14A as well as Fig. 14B There may be any number of air flow cycles.

[0189] like Fig.15A as well as Fig. 15BAs shown, after forming the source / drain region 110, the ESL 117 and the ILD layer 118 may be formed on the source / drain region 110. In some embodiments, after forming the source / drain region 110, an annealing process may be performed to densify the gate spacer 514. For example, the gate spacer 514 may be annealed at an annealing temperature. In some embodiments, the annealing temperature may be from about 200°C to about 1300°C (e.g., from about 1200°C to about 1250°C). The annealing process may remove contaminants in the gate spacer 514 and improve the atomic alignment of atoms in the gate spacer 514 to remove crystal defects, such as vacancy and dislocation. The annealing process may improve the quality of the gate spacer 514, which serves as an isolation structure between the polysilicon structure 312 and the source / drain region 110.

[0190] Reference Figure 2 In operation 225, the polysilicon structure may be replaced by a gate structure. Fig.16A as well as Fig. 16B As described above, the polysilicon structure 312 is replaced by the gate structure 112. Fig.16A as well as Fig. 16B As shown, replacing the polysilicon structure 312 with the gate structure 112 may include sequential operations: (i) removing the polysilicon structure 312, (ii) removing the exposed portion of the thermal oxide layer 322 to expose a portion of the fin structure 106, (iii) forming an interface oxide layer 121 on the exposed portion of the fin structure 106, (iv) depositing a gate oxide layer 124 on the interface oxide layer 121 and on the sidewalls of the gate spacer 514, (v) depositing a WFM layer 126 on the gate oxide layer 124, (vi) depositing a gate metal filling layer 128 on the WFM layer 126, (vii) etching the gate spacer 514 to form a gate spacer 114, (viii) forming a conductive cap layer 130 between the gate spacers 114 and on the gate oxide layer 124, on the WFM layer 126 and on the gate metal filling layer 128, and (ix) forming an insulating cap layer 132 on the conductive cap layer 130.

[0191] Reference Figure 2 In operation 230, a contact structure may be formed on the source / drain region and on the gate structure. Fig.16A as well as Fig. 16BAs described, the source / drain contact structure 120 is formed on the source / drain region 110, and the gate contact structure 139 is formed on the gate structure 112. In some embodiments, forming the source / drain contact structure 120 may include sequential operations: i) removing a portion of the ESL 117 and a portion of the ILD layer 118 to expose the source / drain region 110, ii) forming a silicide layer 134 on the source / drain region 110, iii) forming a contact plug 136 on the silicide layer 134, and iv) forming a nitride barrier layer 138 along the sidewall of the contact plug 136. In some embodiments, forming the gate contact structure 139 may include forming an opening through the insulating cap layer 132 and into the conductive cap layer 130, and filling the opening with a conductive material to form the gate contact structure 139.

[0192] According to some embodiments, Fig.17A An isometric view of CFET 1700 is shown. According to some embodiments, Fig. 17B A cross-sectional view of CFET 1700 along line AA is shown. Fig. 17B A view of CFET 1700 is shown with additional structure which is not shown in the figure for simplicity. Fig.17A Unless otherwise mentioned, the discussion of elements with the same reference numerals applies to each other.

[0193] Reference Fig.17A as well as Fig. 17B , CFET1700 may include (i) a substrate 1704 (ii) a fin base 1706 disposed on the substrate 1704, and (iii) an STI region 1716 disposed on the substrate 1704 and adjacent to the fin base 1706. In some embodiments, the substrate 1704 may be a semiconductor material, such as silicon, germanium, silicon germanium, SOI structure, and combinations thereof. In addition, the substrate 1704 may be doped with a p-type dopant (such as boron, indium, aluminum, or gallium) or an n-type dopant (such as phosphorus, arsenic, antimony, or bismuth). In some embodiments, the top surface of the substrate 1704 may be perpendicular to the crystal orientation

[100] or

[110] . In some embodiments, the fin base 1706 may include a material similar to the substrate 1704 and may have an extended side extending along the X-axis. In some embodiments, STI regions 1716 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide.

[0194] In some embodiments, CFET 1700 may further include (i) a GAA FET (all-around gate field effect transistor) 1702a disposed on the fin base 1706 and on the STI region 1716, (ii) a GAA FET 1702b disposed on the GAA FET 1702a, and (iii) a channel isolation layer 1746 disposed between the GAA FET 1702a and the GAA FET 1702b. The GAA FET 1702a may have a different conductivity type (e.g., n-type or p-type) than the GAA FET 1702b. In some embodiments, the GAA FET 1702a may be n-type and the GAA FET 1702b may be p-type, or vice versa.

[0195] Reference Fig.17A as well as Fig. 17B In some embodiments, the GAA FET 1702a may include (i) a stack of nanostructured layers 1742a disposed on the fin base 1706, (ii) a gate structure 1712a surrounding the nanostructured layer 1742a, (iii) a source / drain region 1710a disposed adjacent to the nanostructured layer 1742a, (iv) an ESL 1717a disposed on the source / drain region 1710a, (v) an ILD layer 1718a disposed on the ESL 1717a, and (vi) an internal spacer 1748 disposed adjacent to the gate structure 1712a. The nanostructured layer 1742a adjacent to and directly contacting the source / drain region 1710a may be used as a channel region. Fig. 17B As shown, the nanostructured layer 1742a disposed directly on the bottom surface of the channel isolation layer 1746 and not in contact with the source / drain region 1710a does not serve as a channel region. Fig. 17B A single row of channel regions is shown in FIG. 1 , but the GAA FET 1702 a may have one or more rows of channel regions.

[0196] In some embodiments, the GAA FET 1702 b may include (i) a stack of nanostructured layers 1742 b disposed on a channel isolation layer 1746, (ii) a gate structure 1712 b surrounding the nanostructured layer 1742 b, (iii) a source / drain region 1710 b disposed at a position adjacent to the nanostructured layer 1742 b, (iv) a source / drain contact structure 1720 b disposed at a front side of the source / drain region 1710 b, (v) an ESL 1717 b disposed on the source / drain region 1710 b, (vi) an ILD layer 1718 b disposed on the ESL 1717 b, (vii) a gate spacer 1714 disposed at a position adjacent to the gate structure 1712 b, and (viii) an inner spacer 1748 disposed at a position adjacent to the gate structure 1712 b. The nanostructured layer 1742b adjacent to and directly contacting the source / drain region 1710b may serve as a channel region. Fig. 17B As shown, the nanostructured layer 1742b disposed directly on the top surface of the channel isolation layer 1746 does not serve as a channel region. Fig. 17B Two rows of channel regions are shown in FIG. 1 , but GAAFET 1702a may have one or more rows of channel regions.

[0197] In some embodiments, the gate structures of CFET 1700 may have substantially equal gate lengths along the X-axis. Gate structure 1712a may be referred to as a "bottom gate structure" and gate structure 1712b may be referred to as a "top gate structure."

[0198] The term "nanostructured" as used in the present disclosure is defined as having a structure, film layer and / or region having a horizontal dimension (e.g., along the X-axis and / or Y-axis) less than about 100 nm and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, for example, about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. In some embodiments, the nanostructured layer 1742a and the nanostructured layer 1742b can be in the form of a nanosheet, a nanowire, a nanorod, a nanotube, or other nanostructured shapes.

[0199] In some embodiments, the ESL 1717a and ESL 1717b, the ILD layers 1718a and ILD layers 1718b, the inner spacer 1748, and the gate spacer 1714 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide.

[0200] The channel isolation layer 1746 can electrically isolate the channel region of the GAA FET 1702a from the channel region of the overlying GAA FET 1702b. In some embodiments, the channel isolation layer 1746 can include a dielectric material having a dielectric constant between 3 and 25. In some embodiments, the dielectric material can include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiO x N y ), silicon oxycarbonitride (SiO x C y N z ), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or a combination thereof. In some embodiments, the dielectric material may include a material having a dielectric constant lower than that of SiO2 (approximately 3.9), such as hydrogenated carbon doped silicon oxide (SiCOH) (dielectric constant between 2.7 and 3.3), fluorosilicate glass (FSG) (dielectric constant between 3.5 and 3.9), nanopore carbon doped oxide (CDO), black diamond (BD), benzocyclobutene (BCB) based polymer, aromatic (hydrocarbon) thermosetting polymer (ATP), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), poly-arylene ether (PAE), nitrogen-doped diamond-like carbon (DLC), and a combination thereof. In some embodiments, the thickness of the channel isolation layer 1746 may be between 10 nm and 30 nm to provide sufficient electrical isolation between the channel region of the GAA FET 1702 a and the channel region of the GAA FET 1702 b without affecting the size and manufacturing cost of the device. In some embodiments, the channel isolation layer 1746 may have a side surface with a linear side profile, a side surface with a facet side profile, or a side surface with a tapered side profile.

[0201] In some embodiments, the nanostructured layer 1742a and the nanostructured layer 1742b may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructured layer 1742a and the nanostructured layer 1742b may include silicon (Si), silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boride (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. Although the nanostructured layer 1742a and the nanostructured layer 1742b are shown with a rectangular cross-section, the nanostructured layer 1742a and the nanostructured layer 1742b may have a cross-section of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). In some embodiments, each layer of the nanostructured layer 1742a and the nanostructured layer 1742b may have a thickness of about 3nm to about 8nm. In some embodiments, each layer of the nanostructured layer 1742a and the nanostructured layer 1742b may have a width of about 5 nm to about 100 nm along the X-axis. In some embodiments, the distance between adjacent nanostructured layers 1742a and adjacent nanostructured layers 1742b along the Z-axis may be about 3 nm to about 12 nm. In some embodiments, the number of nanostructured layers 1742a and nanostructured layers 1742b in each stack may be 1, 2, 3, 4, 5, or 6.

[0202] In some embodiments, the gate structure 1712a and the gate structure 1712b may include (i) an interfacial oxide layer 1724 disposed on the gate structure 1712a and the gate structure 1712b, and (ii) a high-k (HK) gate dielectric layer 1726 disposed on the IL layer 1724. In some embodiments, the IL layer 1724 may include silicon oxide (SiO2), silicon germanium oxide (SiGeO x ) or germanium oxide (GeO x). In some embodiments, the HK gate dielectric layer 1726 may include a high dielectric constant dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2) and zirconium silicate (ZrSiO2). In some embodiments, the gate structure 1712a and the gate structure 1712b may also include a conductive layer 1728. The conductive layer 1728 may be a multi-layer structure. For simplicity, the different film layers of the conductive layer 1728 are not shown. Each conductive layer 1728 may include a WFM layer disposed on the HK gate dielectric layer 1726 and a gate metal filling layer located on the WFM layer. In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped tantalum nitride, or other aluminum-based materials suitable for n-type GAA FET 1702a or GAA FET 1702b. In some embodiments, the WFM layer may include titanium-based or tantalum-based nitrides or alloys that are substantially free of aluminum (e.g., no aluminum), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu) for p-type GAA FET 1702a or GAA FET 1702b. The gate metal filling layer may include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys and combinations thereof.

[0203] In some embodiments, the gate structure 1712a and the gate structure 1712b can be electrically isolated from the adjacent source / drain region 1710a and the source / drain region 1710b respectively by the internal spacer 1748. In some embodiments, the gate structure 1712b can be electrically isolated from the adjacent source / drain contact structure 1720b by the gate spacer 1714.

[0204] In some embodiments, the source / drain region 1710a may also be referred to as the bottom source / drain region 1710a. Fig.17AAs shown, the source / drain region 1710a may have a bottom surface in contact with the top surface of the fin base 1706. In some embodiments, the source / drain region 1710a may have a bottom surface coplanar with the bottom surface of the gate structure 1712a. In some embodiments, the source / drain region 1710a may have a side surface in contact with one or more nanostructured layers 1742a. ​​In some embodiments, the source / drain region 1710a may have a top surface in contact with the ESL 1717a. In some embodiments, the top surface of the source / drain region 1710a may be lower than the bottom surface of the nanostructured layer 1742a in contact with the channel isolation layer 1746. In some embodiments, the source / drain region 1710a may include an epitaxially grown p-type semiconductor material and may also be referred to as a p-type source / drain region 1710a. In some embodiments, the source / drain region 1710a may include silicon (Si), silicon boride (SiB), silicon aluminum (SiAl), silicon gallium (SiGa), silicon indium (SiIn), germanium (Ge), germanium boron (GeB), germanium aluminum (GeAl), germanium gallium (GeGa), germanium indium (GeIn), tin (Sn), tin boron (SnB), tin aluminum (SnAl), tin gallium (SnGa), tin indium (SnIn), silicon carbide (SiC), silicon carbon boride (SiCB), silicon carbon aluminum (SiCAl), silicon carbon gallium (SiCGa), silicon carbon indium (SiCIn), silicon germanium (SiGe), silicon germanium boride (SiGeB), silicon germanium aluminum (SiGeAl), silicon germanium gallium (SiGeGa), silicon germanium indium (SiGeIn) , silicon tin (SiSn), silicon tin boride (SiSnB), silicon tin aluminum (SiSnAl), silicon tin gallium (SiSnGa), silicon tin indium (SiSnIn), silicon germanium carbon (SiGeC), silicon germanium carbon boride (SiGeCB), silicon germanium carbon aluminum (SiGeCAl), silicon germanium carbon gallium (SiGeCGa), silicon germanium carbon indium (SiGeCIn), silicon germanium tin (SiGeSn), silicon germanium tin boron (SiGeSnB), silicon germanium tin aluminum (SiGeSnAl), silicon germanium tin gallium (SiGeSnGa), silicon germanium tin indium (SiGeSnIn), germanium tin (GeSn), germanium tin boron (GeSnB), germanium tin aluminum (GeSnAl), germanium tin gallium (GeSnGa), germanium tin indium (GeSnIn), or a combination thereof. In some embodiments, the source / drain region 1710a may have a height of about 10 nm to about 100 nm.

[0205] In some embodiments, the source / drain region 1710b may also be referred to as a top source / drain region 1710b. In some embodiments, the source / drain region 1710b may have a bottom surface that contacts the top surface of the ILD layer 1718a. In some embodiments, the source / drain region 1710b may have a top surface that is coplanar with the topmost surface of the nanostructured layer 1742b. In some embodiments, the source / drain region 1710b may have a side surface that contacts one or more nanostructured layers 1742b. In some embodiments, the bottom surface of the source / drain region 1710b may be higher than the top surface of the nanostructured layer 1742b that contacts the nanostructured layer 1946. In some embodiments, the source / drain region 1710b may include an epitaxially grown n-type semiconductor material and may also be referred to as an n-type source / drain region 1710b. In some embodiments, the source / drain region 1710 b may include silicon (Si), silicon phosphide (SiP), silicon arsenide (SiAs), silicon antimony (SiSb), silicon bismuth (SiBi), germanium (Ge), germanium phosphide (GeP), germanium arsenide (GeAs), germanium antimony (GeSb), germanium bismuth (GeBi), tin (Sn), tin phosphide (SnP), tin arsenide (SnAs), tin antimony (SnSb), tin bismuth (SnBi), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon carbon arsenide (SiCAs), silicon carbon antimony (SiCSb), silicon carbon bismuth (SiCBi), silicon germanium (SiGe), silicon germanium phosphide (SiGeP), silicon germanium arsenide (SiGeAs), silicon germanium antimony (SiGeSb), silicon germanium bismuth (SiGeBi), or the like. , silicon tin (SiSn), silicon tin phosphide (SiSnP), silicon tin arsenide (SiSnAs), silicon tin antimony (SiSnSb), silicon tin bismuth (SiSnBi), silicon germanium carbon (SiGeC), silicon germanium carbon phosphide (SiGeCP), silicon germanium carbon arsenide (SiGeCAs), silicon germanium carbon antimony (SiGeCSb), silicon germanium carbon bismuth (SiGeCBi), silicon germanium tin (SiGeSn), silicon germanium tin phosphide (SiGeSnP), silicon germanium tin arsenide (SiGeSnAs), silicon germanium tin antimony (SiGeSnSb), silicon germanium tin bismuth (SiGeSnBi), germanium tin (GeSn), germanium tin phosphide (GeSnP), germanium tin arsenide (GeSnAs), germanium tin antimony (GeSnSb), germanium tin bismuth (GeSnBi), or a combination thereof. In some embodiments, the source / drain region 1710b may have a height of about 10 nm to about 100 nm.

[0206] Reference Fig. 17B, the source / drain contact structure 1720b may be referred to as the front side source / drain contact structure 1720b. In some embodiments, the source / drain contact structure 1720b may include a silicide layer 1734b and a contact plug 1736b disposed on the silicide layer 1734b. In some embodiments, the silicide layer 1734b may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si), molybdenum silicide (Mo x Si y ), nickel silicide (WNi x Si y ), cobalt silicide (Co x Si y ), tungsten silicide (W x Si y ) or a combination thereof. In some embodiments, the contact plug 1736b may include a conductive material, such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and a combination thereof.

[0207] In some embodiments, the front side source / drain contact structure 1720 b may be electrically connected to a power source and / or other active components via a front side interconnect structure (not shown) formed on the GAA FET 1702 b .

[0208] According to some embodiments, Fig.18 For forming Fig.17A as well as Fig. 17B For illustrative purposes, reference will be made to the flow chart of an example method of CFET1700 shown in FIG. Figure 19-33 The exemplary process for manufacturing CFET 1700 shown in Fig.18 According to some embodiments, Fig.19 1 is an isometric view of CFET 1700 at various stages of fabrication. According to some embodiments, Figure 20-33 The CFET1700 at various stages of manufacture Fig.17A 1700. A cross-sectional view of line AA of FIG. 1700. Depending on the specific application, the operations may be performed in a different order or not performed. It should be noted that method 1800 may not produce a complete CFET 1700. Therefore, it should be understood that additional processes may be provided before, during, and after method 1800, and only some other processes may be briefly described in this disclosure. Figure 19-33 The components in the Fig.17A by Fig. 17BSame annotations as the components in .

[0209] Reference Fig.18 In operation 1805, a stack of superlattice structures including a nanostructured layer is formed on the fin base. Fig.19 As shown, a stack of superlattice structures 1940 is formed on the fin base 1706. In some embodiments, forming the stack of superlattice structures 1940 may include forming a first superlattice structure 1940a and a second superlattice structure 1940b and a nanostructured isolation layer 1946 disposed between the first superlattice structure 1940a and the second superlattice structure 1940b.

[0210] Forming each superlattice structure 1940a and the second superlattice structure 1940b may include alternately forming nanostructured layers 1942 and nanostructured layers 1944. In some embodiments, forming the nanostructured layers 1942 and the nanostructured layers 1944 may include forming the nanostructured layers 1942 and the nanostructured layers 1944 having the same crystal orientation as the fin base 1706. In some embodiments, forming each nanostructured layer 1942 may include depositing a silicon layer, and forming each nanostructured layer 1944 may include depositing a silicon germanium layer. The nanostructured layer 1942 may form the nanostructured layer 1742a and the nanostructured layer 1742b in a subsequent process. The nanostructured isolation layer 1946 may form the channel isolation layer 1746 in a subsequent process. In some embodiments, the formation of the stack of superlattice structure 1940 may include epitaxially growing materials of nanostructured layer 1942 and nanostructured layer 1944 and depositing materials of nanostructured isolation layer 1946 on substrate 1704, followed by optical lithography and etching processes.

[0211] Reference Fig.18 In operation 1810, an opening is formed in the stack of superlattice structures. Fig. 20 as well as Fig.21 As described above, the opening 2110 is formed in the stack of superlattice structures 1940. In some embodiments, forming the opening 2110 may include (i) Fig. 20 As shown, a polysilicon structure 2012 is formed on the stack of superlattice structures 1940, and (ii) as shown Fig.21As shown, a portion of the stack of superlattice structures 1940 not covered by the polysilicon structure 2012 is removed to form an opening 2110. In some embodiments, forming the polysilicon structure 2012 may include depositing a film layer of polysilicon on the stack of superlattice structures 1940 and patterning the film layer of polysilicon to form the polysilicon structure 2012. In some embodiments, gate spacers 1714 may be formed on side surfaces of the polysilicon structure 2012. In some embodiments, removing a portion of the stack of superlattice structures may include removing a portion of the nanostructured layer 1942 and a portion of the nanostructured layer 1944 not covered by the polysilicon structure 2021. In some embodiments, forming the opening 2110 may include etching back a portion of the fin base not covered by the polysilicon structure 2012. In some embodiments, as Fig.21 As shown, the opening 2110 may be formed to have a CD (width L) of about 5 nm to about 30 nm. Fig.21 As shown, the opening 2110 may be formed to have an AR (ratio between the depth D and the width L) greater than about 5.

[0212] Reference Fig.18 In operation 1820, p-type source / drain regions are epitaxially grown in the openings. Figure 22-27 As described above, the p-type semiconductor material may be epitaxially grown in the opening 2110. In some embodiments, the p-type semiconductor material may be epitaxially grown from the recessed fin base 1706 and / or the nanostructured layer 1742a exposed on the side surface of the opening 2110. In some embodiments, epitaxially growing the p-type semiconductor material may include epitaxially growing a p-type semiconductor material having the same crystallographic orientation as the fin base 1706 and / or the nanostructured layer 1742a. ​​In some embodiments, epitaxially growing the p-type semiconductor material may include epitaxially growing the p-type semiconductor material along the crystallographic orientation

[100] or

[110] . In some embodiments, the p-type semiconductor material may be epitaxially grown using a PECVD process at a temperature of approximately 500° C. or less. For example, as shown in reference Fig. 9B , Fig. 10B , Fig. 13B as well as Fig. 14B As described above, the p-type semiconductor material may be epitaxially grown using process 900B, process 1000B, process 1300B, or process 1400B.

[0213] Reference Fig. 9B as well as Fig. 27In some embodiments, process 900B may be used to epitaxially grow a p-type semiconductor material in the opening 2110 to form a p-type source / drain region 1710a. Unless otherwise noted, the discussion of epitaxially growing a p-type semiconductor material in the source / drain opening 710 using process 900B in operation 220 is applicable to epitaxially growing a p-type semiconductor material in the opening 2110 using process 900B in operation 1820. In some embodiments, forming the p-type source / drain region 1710a may include providing a plasma, a carrier gas, a precursor gas, an etching gas, and a dopant precursor gas in a PECVD chamber. In some embodiments, the dopant precursor gas may be a p-type dopant precursor gas. In some embodiments, as Fig. 9B As shown, the process of forming the p-type source / drain region 1710a can start at time T1 and end at time T2. In some embodiments, between time T1 and time T2, the plasma condition 908 can be "on", and the etching gas flow rate 904, the precursor gas flow rate 906, and the dopant precursor gas flow rate 910 can be maintained at a non-zero value E1, a non-zero value P1, and a non-zero value D1, respectively. In some embodiments, the carrier gas flow rate 902 can be maintained at a non-zero value, starting before time T1 and ending after time T2. In some embodiments, as Fig. 27 As shown, the process time T2-T1 can be controlled so that the p-type source / drain region 1710a can have a height P. In some embodiments, as Fig. 27 As shown, forming the p-type source / drain region 1710a may include forming a top surface of the p-type source / drain region 1710a to be lower than a bottom surface of the nanostructured layer 1742a , the bottom surface of the nanostructured layer 1742a being in contact with the nanostructured isolation layer 1946 .

[0214] Reference Fig. 10B as well as Fig. 27 In some embodiments, process 1000B may be used to epitaxially grow p-type semiconductor material in opening 2110 to form p-type source / drain region 1710a. Unless otherwise noted, the discussion of epitaxially growing p-type semiconductor material in source / drain opening 710 using process 1000B in operation 220 is applicable to epitaxially growing p-type semiconductor material in opening 2110 using process 1000B in operation 1820. Unless otherwise noted, the discussion of forming p-type source / drain 1710a using process 900B is applicable to forming p-type source / drain 1710a using process 1000B. In some embodiments, forming p-type source / drain 1710a using process 1000B may include varying both precursor gas flow rate 1006 and dopant precursor gas flow rate 1010 in a gas flow cycle. For example, if Fig. 10BAs shown, during the first phase of each gas flow cycle, the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at non-zero values ​​P1 and D1, respectively. During the second phase of each gas flow cycle, the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at zero.

[0215] Reference Fig. 13B as well as Fig. 27 In some embodiments, process 1300B may be used to epitaxially grow a p-type semiconductor material in the opening 2110 to form a p-type source / drain region 1710a. Unless otherwise noted, the discussion of epitaxially growing a p-type semiconductor material in the source / drain opening 710 using process 1300B in operation 220 is applicable to epitaxially growing a p-type semiconductor material in the opening 2110 using process 1300B in operation 1820. Unless otherwise noted, the discussion of forming a p-type source / drain 1710a using process 1000B is applicable to forming a p-type source / drain 1710a using process 1300B. In some embodiments, forming a p-type source / drain 1710a using process 1300B may include changing an etching gas flow rate 1304, a precursor gas flow rate 1006, and a dopant precursor gas flow rate 1010 in a gas flow cycle. For example, if Fig. 13B As shown, during the first phase of each gas flow cycle, the etching gas flow rate 1304 can be maintained at zero, while the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at a non-zero value P1 and a non-zero value D1. During the second phase of each gas flow cycle, the etching gas flow rate 1304 can be maintained at a non-zero value E1, while the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at zero.

[0216] Reference Fig. 14B as well as Fig. 27 In some embodiments, process 1400B may be used to epitaxially grow a p-type semiconductor material in the opening 2110 to form a p-type source / drain region 1710a. Unless otherwise noted, the discussion of epitaxially growing a p-type semiconductor material in the source / drain opening 710 using process 1400B in operation 220 is applicable to epitaxially growing a p-type semiconductor material in the opening 2110 using process 1400B in operation 1820. Unless otherwise noted, the discussion of forming a p-type source / drain region 1710a using process 1300B is applicable to forming a p-type source / drain region 1710a using process 1400B. In some embodiments, forming a p-type source / drain region 1710a using process 1400B may include changing plasma conditions 1408, etching gas flow rate 1304, precursor gas flow rate 1006, and dopant precursor gas flow rate 1010 in a gas flow cycle. For example, if Fig. 14BAs shown, during the first phase of each gas flow cycle, the plasma condition 1408 can be "off", the etching gas flow rate 1304 can be maintained at zero, and the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at a non-zero value P1 and a non-zero value D1. During the second phase of each gas flow cycle, the plasma condition 1408 can be "on", the etching gas flow rate 1304 can be maintained at a non-zero value E1, and the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at zero.

[0217] In some embodiments, forming the p-type source / drain region 1710a using the process 1000B, the process 1300B, or the process 1400B may include multiple gas flow cycles. Fig. 22 , Fig.23 , Fig.24 , Fig.25 as well as Fig.26 As shown, after the first, second, third, fourth, and fifth gas flow cycles of the process 1000B, the process 1300B, or the process 1400B, the p-type source / drain region 2210, the p-type source / drain region 2310, the p-type source / drain region 2410, the p-type source / drain region 2510, and the p-type source / drain region 2610 having a height PH1, a height PH2, a height PH3, a height PH4, and a height PH5 may be formed in the opening 2110. In some embodiments, as Fig. 27 As shown, after the plurality of gas flow cycles of process 1000B, process 1300B, or process 1400B are completed at time T2, a p-type source / drain region 1710a having a height P may be completely formed in opening 2110. According to some embodiments, although Figure 22-27 More than five gas flow cycles are shown to form the p-type source / drain regions 1710a, but any number of cycles may be used to form the p-type source / drain regions 1710a.

[0218] Reference Fig.18 In operation 1825, ESL and ILD layers are formed in the openings and on the P-type source / drain regions. Fig.28 As described above, the ESL 1717a may be formed on the p-type source / drain region 1710a and on the side surface of the opening 2110, and the ILD layer 1718 may be formed on the ESL 1717a. Fig.28As shown, forming the ESL 1717a and the ILD layer 1718 may include depositing one or more insulating materials in the opening 2110. In some embodiments, forming the ESL 1717a and the ILD layer 1718 may include etching back the portion of the ESL 1717a and the portion of the ILD layer 1718 located in the opening 2110. In some embodiments, as Fig.28 As shown, forming the ESL 1717 a and the ILD layer 1718 may include forming a top surface of the ILD layer 1718 that is higher than a top surface of the nanostructured layer 1742 b , the top surface of the nanostructured layer 1742 b being in contact with the nanostructured isolation layer 1946 .

[0219] Reference Fig.18 In operation 1830, n-type source / drain regions are epitaxially grown on the ILD layer. Figure 29-31 As described, the n-type semiconductor material may be epitaxially grown in the opening 2110. In some embodiments, the n-type semiconductor material may be epitaxially grown from the side surface of the nanostructured layer 1742b exposed on the side surface of the opening 2110. During the epitaxial growth of the n-type semiconductor material, the n-type semiconductor material may extend laterally and vertically to substantially fill the opening 2110. The n-type semiconductor material does not epitaxially grow on the non-semiconductor material of the inner spacer 1748 and the ILD layer 1718a. Therefore, in some embodiments, an air gap may be formed at the interface between the n-type semiconductor material and the inner spacer 1748 and between the n-type semiconductor material and the ILD layer 1718a. In some embodiments, epitaxially growing the n-type semiconductor material may include epitaxially growing the n-type semiconductor material having the same crystallographic orientation as the nanostructured layer 1742b. In some embodiments, epitaxially growing the n-type semiconductor material may include epitaxially growing the n-type semiconductor material along the crystallographic orientation

[100] or

[110] . In some embodiments, n-type semiconductor materials may be epitaxially grown using a PECVD process at a temperature of about 500° C. or less. Fig. 9B , Fig. 10B , Fig. 13B as well as Fig. 14B As described above, the n-type semiconductor material may be epitaxially grown using the process 900B, the process 1000B, the process 1300B, or the process 1400B.

[0220] Reference Fig. 9B as well as Fig.31In some embodiments, process 900B may be used to epitaxially grow n-type semiconductor material in the opening 2110 to form an n-type source / drain region 1710b. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in the source / drain opening 710 using process 900B in operation 220 is applicable to epitaxially growing n-type semiconductor material in the opening 2110 using process 900B in operation 1830. In some embodiments, forming the n-type source / drain region 1710b may include providing plasma, a carrier gas, a precursor gas, an etching gas, and a dopant precursor gas in a PECVD chamber. In some embodiments, the dopant precursor gas may be an n-type dopant precursor gas. In some embodiments, as Fig. 9B As shown, the process of forming the n-type source / drain region 1710b may start at time T1 and end at time T2. In some embodiments, between time T1 and time T2, the plasma condition 908 may be "on", and the etching gas flow rate 904, the precursor gas flow rate 906, and the dopant precursor gas flow rate 910 may be maintained at a non-zero value E1, a non-zero value P1, and a non-zero value D1, respectively. In some embodiments, the carrier gas flow rate 902 may be maintained at a non-zero value, starting before time T1 and ending after time T2. In some embodiments, as Fig.31 As shown, the process time T2-T1 can be controlled so that the p-type source / drain region 1710b can have a height N. In some embodiments, as Fig.31 As shown, forming the n-type source / drain region 1710b can include forming a top surface of the n-type source / drain region 1710b coplanar with a topmost surface of the nanostructured layer 1742b.

[0221] Reference Fig. 10B as well as Fig.31 In some embodiments, process 1000B may be used to epitaxially grow n-type semiconductor material in opening 2110 to form p-type source / drain region 1710b. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in source / drain opening 710 using process 1000B in operation 220 is applicable to epitaxially growing n-type semiconductor material in opening 2110 using process 1000B in operation 1830, unless otherwise noted. Unless otherwise noted, the discussion of forming n-type source / drain 1710b using process 900B is applicable to forming n-type source / drain 1710b using process 1000B. In some embodiments, forming n-type source / drain 1710b using process 1000B may include varying both precursor gas flow rate 1006 and dopant precursor gas flow rate 1010 in a gas flow cycle. For example, if Fig. 10BAs shown, during the first phase of each gas flow cycle, the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at non-zero values ​​P1 and D1, respectively. During the second phase of each gas flow cycle, the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at zero.

[0222] Reference Fig. 13B as well as Fig.31 In some embodiments, process 1300B may be used to epitaxially grow n-type semiconductor material in opening 2110 to form n-type source / drain region 1710b. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in source / drain opening 710 using process 1300B in operation 220 is applicable to epitaxially growing n-type semiconductor material in opening 2110 using process 1300B in operation 1830. Unless otherwise noted, the discussion of forming n-type source / drain 1710b using process 1000B is applicable to forming n-type source / drain 1710b using process 1300B. In some embodiments, forming n-type source / drain 1710b using process 1300B may include changing etching gas flow rate 1304, precursor gas flow rate 1006, and dopant precursor gas flow rate 1010 in a gas flow cycle. For example, if Fig. 13B As shown, during the first phase of each gas flow cycle, the etching gas flow rate 1304 can be maintained at zero, while the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at a non-zero value P1 and a non-zero value D1. During the second phase of each gas flow cycle, the etching gas flow rate 1304 can be maintained at a non-zero value E1, while the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at zero.

[0223] Reference Fig. 14B as well as Fig.31 In some embodiments, process 1400B may be used to epitaxially grow n-type semiconductor material in opening 2110 to form n-type source / drain region 1710b. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in source / drain opening 710 using process 1400B in operation 220 is applicable to epitaxially growing p-type semiconductor material in opening 2110 using process 1400B in operation 1830. Unless otherwise noted, the discussion of forming n-type source / drain region 1710b using process 1300B is applicable to forming n-type source / drain region 1710b using process 1400B. In some embodiments, forming n-type source / drain region 1710b using process 1400B may include changing plasma conditions 1408, etching gas flow rate 1304, precursor gas flow rate 1006, and dopant precursor gas flow rate 1010 in a gas flow cycle. For example, if Fig. 14BAs shown, during the first phase of each gas flow cycle, the plasma condition 1408 can be "off", the etching gas flow rate 1304 can be maintained at zero, and the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at a non-zero value P1 and a non-zero value D1. During the second phase of each gas flow cycle, the plasma condition 1408 can be "on", the etching gas flow rate 1304 can be maintained at a non-zero value E1, and the precursor gas flow rate 1006 and the dopant precursor gas flow rate 1010 can be maintained at zero.

[0224] In some embodiments, forming the n-type source / drain region 1710b using the process 1000B, the process 1300B, or the process 1400B may include multiple gas flow cycles. Fig.29 As shown, after the first gas flow cycle of process 1000B, process 1300B, or process 1400B is completed, n-type source / drain region 2910 may be formed in opening 2110. In some embodiments, as shown in FIG. Fig.30 As shown, after the second gas flow cycle of process 1000B, process 1300B, or process 1400B is completed, n-type source / drain region 3010 may be formed in opening 2110. In some embodiments, air gap 3011 may be formed between n-type source / drain region 3010 and ILD layer 1718a. Fig.31 As shown, after the multiple gas flow cycles of the process 1000B, the process 1300B, or the process 1400B are completed at time T2, the n-type source / drain region 1710 b having a height N may be completely formed in the opening 2110 .

[0225] Reference Fig.18 In operation 1835, a gate structure is formed to surround the nanostructured layer. Fig.32 As described above, the gate structure 1712a (referred to as a "bottom gate structure") is formed to surround the nanostructured layer 1742a, and the gate structure 1712b (referred to as a "top gate structure") is formed to surround the nanostructured layer 1742b.

[0226] like Fig.32 As shown, the formation of the gate structure 1712a and the gate structure 1712b may include sequential operations: (i) removing the nanostructured layer 1944 and the polysilicon structure 2012, (ii) forming the IL layer 1724 on the exposed areas of the nanostructured layer 1742a and the nanostructured layer 1742b, (iii) depositing the HK gate dielectric layer 1726 on the IL layer 1724, and (iv) depositing the conductive layer 1728 on the HK gate dielectric layer 1726. Fig.32As shown, after the gate structures 1712a and 1712b are formed, an ESL 1717b and an ILD layer 1718b may be formed in the opening.

[0227] Reference Fig.18 In operation 1840, a contact structure is formed on the n-type source / drain region. Fig.33 As described above, the front side source / drain contact structure 1720b is formed on the front side surface of the top n-type source / drain region 1710b. Fig.33 As shown, the formation of the front side source / drain contact structure 1720b may include sequential operations: (i) removing a portion of the ILD layer 1718b and a portion of the ESL 1717b to expose the front side surface of the top n-type source / drain region 1710b, (ii) forming a silicide layer 1734b on the front side surface of the top n-type source / drain region 1710b, and (iii) forming a contact plug 1736b on the silicide layer 1734b.

[0228] According to some embodiments, Fig.34A An isometric view of a semiconductor device 3400 is shown. According to some embodiments, Fig.34B A cross-sectional view of the semiconductor device 3400 along line AA is shown. Unless otherwise mentioned, the discussion of elements with the same reference numerals applies to each other.

[0229] Reference Fig.34A as well as Fig.34B , the semiconductor device 3400 may include (i) a substrate 3404, (ii) an STI region 3416 disposed on the substrate 3404, and (iii) a VFET 3402 disposed on the substrate 1704 and adjacent to the STI region 3416. In some embodiments, the substrate 3404 may be a semiconductor material, such as silicon, germanium, silicon germanium, an SOI structure, and combinations thereof. In addition, the substrate 3404 may be doped with a p-type dopant (such as boron, indium, aluminum, or gallium) or an n-type dopant (such as phosphorus, arsenic, antimony, or bismuth). In some embodiments, the top surface of the substrate 3404 may be perpendicular to the crystal orientation

[100] or

[110] . In some embodiments, the STI region 3416 may include an insulating material, such as silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide.

[0230] In some embodiments, the VFET 3402 may include (i) an ILD layer 3418 disposed at a position adjacent to the STI region 3416, (ii) a gate structure 3412 adjacent to the ILD layer 3418, (iii) a vertical channel layer 3442 surrounded by the gate structure 3412, (iv) a source / drain region 3410a and a source / drain region 3410b disposed at the top surface and the bottom surface of the vertical channel layer 3442, respectively, (v) a source / drain contact structure 3420a and a source / drain contact structure 3420b contacting the source / drain region 3410a and the source / drain region 3410b, respectively, (vi) a gate spacer 3414 disposed at a position adjacent to the gate structure 3412, and (vii) a gate contact structure 3439 disposed at a position passing through the STI region 3416 and contacting the gate structure 3412. In some embodiments, VFET 3402 may have p-type conductivity and may be referred to as p-type VFET 3402. In some embodiments, VFET 3402 may have n-type conductivity and may be referred to as n-type VFET 3402.

[0231] In some embodiments, the vertical channel layer 3442 may include a semiconductor material similar to or different from the substrate 3404. In some embodiments, the vertical channel layer 3442 may include silicon (Si), silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boride (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor material. Although a rectangular cross-section of the vertical channel layer 3442 is shown, the vertical channel layer 3442 may have a cross-section of other geometric shapes, such as a circular, elliptical, triangular, or polygonal shape.

[0232] In some embodiments, the gate structure 3412 may have substantially equal gate lengths along the Z axis. In some embodiments, the gate structure 3412 may include (i) an IL layer 3424 disposed on the vertical channel layer 3442, (ii) a HK gate dielectric layer 3426 disposed on the IL layer 3424, and (iii) a conductive layer 3428. The conductive layer 3428 may be a multi-layer structure. For simplicity, the different film layers of the conductive layer 3428 are not shown. The conductive layer 3428 may include a WFM layer disposed on the HK dielectric layer 3426 and a gate metal filling layer disposed on the WFM layer. In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped tantalum nitride, or other aluminum-based materials suitable for n-type VFET 3402. In some embodiments, the WFM layer may include a titanium-based or tantalum-based nitride or alloy that is substantially free of aluminum (e.g., without aluminum), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu) for p-type VFET 3402. The gate metal fill layer may include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. In some embodiments, the gate structure 3412 may be electrically isolated from the source / drain region 3410a and the source / drain region 3410b by a gate spacer 3414.

[0233] In some embodiments, the source / drain region 3410a and the source / drain region 3410b may also be referred to as the top source / drain region 3410a and the bottom source / drain region 3410b, respectively. In some embodiments, the source / drain region 3410a and the source / drain region 3410b may include epitaxially grown semiconductor materials. In some embodiments, the source / drain region 3410a and the source / drain region 3410b may include p-type semiconductor materials and may also be referred to as p-type source / drain region 3410a and p-type source / drain region 3410b. In some embodiments, the p-type source / drain regions 3410a and the p-type source / drain regions 3410b may include silicon (Si), silicon boride (SiB), silicon aluminum (SiAl), silicon gallium (SiGa), silicon indium (SiIn), germanium (Ge), germanium boron (GeB), germanium aluminum (GeAl), germanium gallium (GeGa), germanium indium (GeIn), tin (Sn), tin boron (SnB), tin aluminum (SnAl), tin gallium (SnGa), tin indium (SnIn), silicon carbide (SiC), silicon carbon boride (SiCB), silicon carbon aluminum (SiCAl), silicon carbon gallium (SiCGa), silicon carbon indium (SiCIn), silicon germanium (SiGe), silicon germanium boride (SiGeB), silicon germanium aluminum (SiGeAl), silicon germanium gallium (SiGeGa), silicon germanium indium (SiGeIn), silicon tin (SiSn), silicon tin boride (SiSnB), silicon tin aluminum (SiSnAl), silicon tin gallium (SiSnGa), silicon tin indium (SiSnIn), silicon germanium carbon (SiGeC), silicon germanium carbon boride (SiGeCB), silicon germanium carbon aluminum (SiGeCAl), silicon germanium carbon gallium (SiGeCGa), silicon germanium carbon indium (SiGeCIn), silicon germanium tin (SiGeSn), silicon germanium tin boron (SiGeSnB), silicon germanium tin aluminum (SiGeSnAl), silicon germanium tin gallium (SiGeSnGa), silicon germanium tin indium (SiGeSnIn), germanium tin (GeSn), germanium tin boron (GeSnB), germanium tin aluminum (GeSnAl), germanium tin gallium (GeSnGa), germanium tin indium (GeSnIn), germanium tin (GeSn), germanium tin boron (GeSnB), germanium tin aluminum (GeSnAl), germanium tin gallium (GeSnGa), germanium tin indium (GeSnIn), germanium tin (GeSn), germanium tin boron (GeSnB), germanium tin aluminum (GeSnAl), germanium tin gallium (GeSnGa), germanium tin indium (GeSnIn), or a combination thereof. In some embodiments, the source / drain region 3410 a and the source / drain region 3410 b may include an n-type semiconductor material and may also be referred to as the n-type source / drain region 3410 a and the n-type source / drain region 3410 b .In some embodiments, the n-type source / drain regions 3410a and the n-type source / drain regions 3410b may include silicon (Si), silicon phosphide (SiP), silicon arsenide (SiAs), silicon antimony (SiSb), silicon bismuth (SiBi), germanium (Ge), germanium phosphide (GeP), germanium arsenide (GeAs), germanium antimony (GeSb), germanium bismuth (GeBi), tin (Sn), tin phosphide (SnP), tin arsenide (SnAs), tin antimony (SnSb), tin bismuth (SnBi), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon carbon arsenide (SiCAs), silicon carbon antimony (SiCSb), silicon carbon bismuth (SiCBi), silicon germanium (SiGe), silicon germanium phosphide (SiGeP), silicon germanium arsenide (SiGeAs), silicon germanium antimony (SiGeSb), silicon germanium phosphide (SiGeSb), silicon germanium phosphide (SiGeP), silicon germanium arsenide (SiGeAs), silicon germanium antimony (SiGeSb), or silicon germanium phosphide (SiC). Bismuth (SiGeBi), silicon tin (SiSn), silicon tin phosphide (SiSnP), silicon tin arsenide (SiSnAs), silicon tin antimony (SiSnSb), silicon tin bismuth (SiSnBi), silicon germanium carbon (SiGeC), silicon germanium carbon phosphide (SiGeCP), silicon germanium carbon arsenide (SiGeCAs), silicon germanium carbon antimony (SiGeCSb), silicon germanium carbon bismuth (SiGeCBi), silicon germanium tin (SiGeSn), silicon germanium tin phosphide (SiGeSnP), silicon germanium tin arsenide (SiGeSnAs), silicon germanium tin antimony (SiGeSnSb), silicon germanium tin bismuth (SiGeSnBi), germanium tin (GeSn), germanium tin phosphide (GeSnP), germanium tin arsenide (GeSnAs), germanium tin antimony (GeSnSb), germanium tin bismuth (SiGeSnBi), germanium tin (GeSn), germanium tin phosphide (GeSnP), germanium tin arsenide (GeSnAs), germanium tin antimony (GeSnSb), germanium tin bismuth (GeSnBi), germanium tin (GeSn), germanium tin phosphide (GeSnP), germanium tin arsenide (GeSnAs), germanium tin antimony (GeSnSb), germanium tin bismuth (GeSnBi), germanium tin (GeSn),

[0234] The source / drain contact structure 3420a may be referred to as a front-side source / drain contact structure 3420a, and the source / drain contact structure 3420b may be referred to as a back-side source / drain contact structure 3420b. In some embodiments, the source / drain contact structure 3420b may include a silicide layer 3434a and a contact plug 3436a disposed on the silicide layer 3434a. In some embodiments, the source / drain contact structure 3420b may include a silicide layer 3434b and a contact plug 3436b disposed on the silicide layer 3434b. In some embodiments, the silicide layer 3434a and the silicide layer 3434b may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si), molybdenum silicide (Mo x Si y ), nickel silicide (WNi x Si y ), cobalt silicide (Co x Si y ), tungsten silicide (W x Si y) or a combination thereof. In some embodiments, the contact plug 3436a and the contact plug 3436b may include a conductive material, such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd) and a combination thereof.

[0235] In some embodiments, the front side source / drain contact structure 3420a can be electrically connected to a power source and / or other active components through a front side interconnect structure (not shown). In some embodiments, the back side source / drain contact structure 3420b can be electrically connected to a power source and / or other active components through a back side interconnect structure (not shown). In some embodiments, the source / drain contact structure 3420a and the source / drain 3420b can be electrically connected to each other.

[0236] According to some embodiments, Fig.35 For forming Fig.34A as well as Fig.34B 3400 of the semiconductor device shown in FIG. Figure 36-45 The exemplary process for manufacturing the semiconductor device 3400 shown in FIG. Fig.35 The operations shown in , according to some embodiments, Figure 36-45 3400 is a cross-sectional view along line AA of semiconductor device 3400 at various stages of manufacture. Depending on the specific application, operations may be performed in a different order or not performed. It should be noted that method 3500 may not produce a complete semiconductor device 3400. Therefore, it should be understood that additional processes may be provided before, during, and after method 3500, and only some other processes may be briefly described in this disclosure. Figure 36-45 The components in the Fig.34A by Fig.34B Same annotations as the components in .

[0237] In operation 3505, a vertical channel layer of a VFET is formed on a substrate. Fig.36As described, the vertical channel layer 3442 of the VFET 3402 is formed on the substrate 3404. The formation of the vertical channel layer 3442 may include sequential operations of (i) etching the substrate 3404 to form a vertical structure 3606, (ii) forming a silicon germanium layer 3608 on the vertical structure 3606, and (iii) forming the vertical channel layer 3442 on the silicon germanium layer 3608. In some embodiments, forming the vertical channel layer 3442 may include controlling the width D of the vertical channel layer to be between about 5 nm and about 30 nm. In some embodiments, forming the vertical channel layer 3442 may include epitaxially growing the vertical channel layer 3442 having the same crystal orientation as the substrate 3404. In some embodiments, the vertical channel layer 3442 may include epitaxially growing the vertical channel layer 3442 along the crystal orientation

[100] or

[110] .

[0238] After forming the vertical channel layer 3442 , a dielectric layer 3407 may be formed over the substrate 3404 and adjacent to the vertical structure 3606 , and an STI region 3416 may be formed over the substrate 3404 and adjacent to the dielectric layer 3407 .

[0239] Reference Fig.35 In operation 3510, a gate structure is formed to surround the vertical channel layer. For example, Fig.36 As shown, a gate structure 3412 is formed to surround the vertical channel layer 3442. After the gate structure 3412 is formed, an ILD layer 3418 may be deposited on the gate structure 3412 and on the side surfaces of the STI region 3416 to form an opening 3610. In some embodiments, as Fig.36 As shown, forming opening 3610 may include controlling a distance L between a top surface of vertical channel layer 3442 and a top surface of ILD layer 3418. In some embodiments, forming opening 3610 may include controlling AR (a ratio between distance L and depth D) to be greater than about 5.

[0240] Reference Fig.35 In operation 3515, a first source / drain region is formed on the front end of the vertical channel layer. Fig.37As described, the source / drain region 3410a is formed in the opening 3610 and on the vertical channel layer 3442. In some embodiments, forming the source / drain region 3410a may include epitaxially growing a p-type or n-type semiconductor material on the vertical channel layer 3442. In some embodiments, epitaxially growing the p-type or n-type semiconductor material may include epitaxially growing a p-type or n-type semiconductor material having the same crystallographic orientation as the vertical channel layer. In some embodiments, epitaxially growing the p-type or n-type semiconductor material on the source / drain may include epitaxially growing the p-type or n-type semiconductor material along the crystallographic orientation

[100] or

[110] . In some embodiments, the p-type or n-type semiconductor material may be epitaxially grown using a PECVD process at a temperature of approximately 500°C or less. For example, as shown in reference Fig. 9B , Fig. 10B , Fig. 13B as well as Fig. 14B As described above, the process 900B, the process 1000B, the process 1300B, or the process 1400B may be used to epitaxially grow a p-type or n-type semiconductor material.

[0241] Reference Fig. 9B as well as Fig.37 In some embodiments, process 900B may be used to epitaxially grow p-type or n-type semiconductor material in the opening 3610 and on the vertical channel layer 3442 to form the source / drain region 3410a. Unless otherwise noted, the discussion of epitaxially growing p-type semiconductor material in the source / drain opening 2110 using process 900B in operation 1820 is applicable to epitaxially growing p-type semiconductor material in the opening 3610 using process 900B in operation 3515. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in the source / drain opening 2110 using process 900B in operation 1830 is applicable to epitaxially growing n-type semiconductor material in the opening 3610 using process 900B in operation 3515.

[0242] Reference Fig. 10B as well as Fig.37 In some embodiments, process 1000B may be used to epitaxially grow p-type or n-type semiconductor material in the opening 3610 and on the vertical channel layer 3442 to form the source / drain region 3410a. Unless otherwise noted, the discussion of epitaxially growing p-type semiconductor material in the source / drain opening 2110 using process 1000B in operation 1820 is applicable to epitaxially growing p-type semiconductor material in the opening 3610 using process 1000B in operation 3515. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in the source / drain opening 2110 using process 1000B in operation 1830 is applicable to epitaxially growing n-type semiconductor material in the opening 3610 using process 1000B in operation 3515.

[0243] Reference Fig. 13B as well as Fig.37 In some embodiments, process 1300B may be used to epitaxially grow p-type or n-type semiconductor material in opening 3610 and on vertical channel layer 3442 to form source / drain region 3410a. Unless otherwise noted, the discussion of epitaxially growing p-type semiconductor material in source / drain opening 2110 using process 1300B in operation 1820 is applicable to epitaxially growing p-type semiconductor material in opening 3610 using process 1300B in operation 3515. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in source / drain opening 2110 using process 1300B in operation 1830 is applicable to epitaxially growing n-type semiconductor material in opening 3610 using process 1300B in operation 3515.

[0244] Reference Fig. 14B as well as Fig.37 In some embodiments, process 1400B may be used to epitaxially grow p-type or n-type semiconductor material in opening 3610 and on vertical channel layer 3442 to form source / drain region 3410a. Unless otherwise noted, the discussion of epitaxially growing p-type semiconductor material in source / drain opening 2110 using process 1400B in operation 1820 is applicable to epitaxially growing p-type semiconductor material in opening 3610 using process 1400B in operation 3515. Unless otherwise noted, the discussion of epitaxially growing n-type semiconductor material in source / drain opening 2110 using process 1400B in operation 1830 is applicable to epitaxially growing n-type semiconductor material in opening 3610 using process 1400B in operation 3515.

[0245] In some embodiments, forming source / drain region 3410a using process 1000B, process 1300B, or process 1400B may include multiple gas flow cycles. Fig.38 As shown, after the first stage of the first gas flow cycle of process 1000B, process 1300B, or process 1400B is completed, source / drain regions 3810 may be formed in opening 3610 and on vertical channel layer 3442, and amorphous layer 3811 may be formed on the dielectric surface of exposed gate spacer 3414, on the dielectric surface of exposed ILD layer 3418, and on the dielectric surface of exposed STI region 3416. In some embodiments, as Fig.39 As shown, after the second stage of the first gas flow cycle of process 1000B, process 1300B, or process 1400B is completed, amorphous layer 3811 may be removed. Fig.40As shown, after the second gas flow cycle of process 1000B, 1300B or 1400B is completed, a source / drain region 4010 having a larger volume than the source / drain region 3810 may be formed in the opening 3610. In some embodiments, as Fig.41 As shown, after the third gas flow cycle of process 1000B, 1300B or 1400B is completed, a source / drain region 4110 having a larger volume than the source / drain region 4010 may be formed in the opening 3610. In some embodiments, as Fig.37 As shown, after the plurality of gas flow cycles of process 1000B, 1300B, or 1400B are completed at time T2, source / drain region 3410 a may be completely formed in opening 3610 .

[0246] Reference Fig.35 In operation 3520, a first contact structure is formed on the first source / drain region. Fig.42 As described above, the front side source / drain region contact structure 3420a is formed on the front side surface of the source / drain region 3410a. Fig.42 As shown, the formation of the front side source / drain region contact structure 3420a may include sequential operations: (i) forming a silicide layer 3434a on the front side surface of the source / drain region 3410a, and (ii) forming a contact plug 3436a on the silicide layer 3434a.

[0247] Reference Fig.35 In operation 3525, a second source / drain region is formed on the rear end of the vertical channel layer. Fig.43 as well as Fig.44 As described above, the source / drain region 3410b is formed on the rear end of the vertical channel layer 3442. In some embodiments, as Fig.44 As shown, forming the source / drain region 3410 b may include sequential operations of: (i) forming an opening 4310 to expose the rear end of the vertical channel layer 3442 , and (ii) epitaxially growing a p-type or n-type semiconductor material in the opening 4310 and on the rear end of the vertical channel layer 3442 .

[0248] In some embodiments, Fig.43 As shown, forming the opening 4310 may include sequential operations: (i) removing a portion of the substrate 3404 from the back side to expose the dielectric layer 3407 and the vertical structure 3606, (ii) removing the dielectric layer 3407, the vertical structure 3606 and the silicon germanium layer 3608 to form the opening 4310, and (iii) forming an ILD layer 4318 on the side surface of the STI region 3416.

[0249] In some embodiments, epitaxial growth of p-type or n-type semiconductor material in the opening 4310 and on the rear end of the vertical channel layer 3442 may include the same as in reference Figure 37-41 The operation 3515 is the same as or similar to the operation described above, wherein Figure 37-41 This is an operation for forming a source / drain region 3410 a on the front end of the vertical channel layer 3442 .

[0250] Reference Fig.35 In operation 3530, a second contact structure is formed on the second source / drain region. Fig.45 As described above, the rear side source / drain region contact structure 3420b is formed on the rear side surface of the source / drain region 3410b. In some embodiments, forming the rear side source / drain region contact structure 3420b on the rear side surface of the source / drain region 3410b may include the same as in reference Fig.42 The operation 3515 is the same as or similar to the operation described above, wherein Fig.42 This is an operation for forming a front side source / drain region contact structure 3420a on the front side surface of the source / drain region 3410a.

[0251] The present disclosure provides exemplary methods (e.g., methods 200, 1800, and 3500) for forming source / drain regions or epitaxial regions in a field effect transistor (e.g., finFET 100, CFET 1700, or VFET 3402) using a PECVD process at a temperature of about 500° C. or less, wherein the etch selectivity of the etch process is greater than about 6. In some embodiments, the method may include a deposition process and an etching process performed in situ in a PECVD chamber. The method may be used to selectively grow semiconductor material in a single crystal form in an opening having a CD less than 30 nm and an AR greater than 5, while substantially preventing nodules and blockages from forming on a dielectric surface. In some embodiments, the method may include providing a plasma, an etching gas, and a precursor gas in a PECVD chamber to form an undoped source / drain region in the opening. In some embodiments, the method may also include providing a dopant precursor gas to form a p-type or n-type source / drain region in the opening. In some embodiments, the method may also include controlling plasma conditions, the flow rate of an etching gas (e.g., etching gas flow rate 1304), the flow rate of a precursor gas (e.g., precursor gas flow rate 1006), the rate of a dopant precursor gas (e.g., dopant precursor gas flow rate 1010), or a combination thereof.

[0252] In some embodiments, plasma may form free radicals of a precursor gas and / or free radicals of an etching gas during a deposition process and / or an etching process. Also, since free radicals are highly reactive, the use of plasma may increase the deposition rate and / or etching rate during a deposition process and / or an etching process at low temperatures (e.g., at a temperature of about 500° C. to about 20° C., at a temperature of about 400° C. or less, or at a temperature of about 400° C. to about 20° C.). Also, due to the highly reactive free radicals of the etching gas, an additional ex-situ etching process may be eliminated from the manufacturing process of the source / drain region or epitaxial region in a field effect transistor. Therefore, the use of plasma during a deposition process and / or an etching process may reduce the time and cost of manufacturing the source / drain region or epitaxial region in a field effect transistor.

[0253] In some embodiments, controlling the plasma conditions, the flow rate of the etching gas, the flow rate of the precursor gas and / or the flow rate of the dopant precursor gas can selectively grow a single crystalline form of semiconductor material in an opening having a CD less than about 30 nm and an AR greater than about 5, while substantially preventing defective amorphous semiconductor regions from being formed in the source / drain regions or the epitaxial regions and preventing nodules and blockages from being formed on the side surface of the dielectric layer adjacent to the source / drain regions or the epitaxial regions.

[0254] In some embodiments, a method for forming a semiconductor device includes: forming a fin structure on a substrate; forming a polysilicon structure on the fin structure; removing a portion of the fin structure adjacent to the polysilicon structure to form an opening; and forming a source / drain region in the opening. Forming the source / drain region includes exposing the fin structure in the opening to: a first flow rate of a precursor gas during a first stage of a gas flow cycle; a second flow rate of the precursor gas during a second stage of a gas flow cycle; an etching gas during the gas flow cycle; and a plasma during the gas flow cycle. The first flow rate is higher than the second flow rate. The step of exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process. In some embodiments, the step of exposing the fin structure in the opening to the etching gas includes exposing the fin structure in the opening to a flow rate of the etching gas that is higher than the first flow rate of the precursor gas. In some embodiments, the step of exposing the fin structure in the opening to the etching gas includes: maintaining a first flow rate of the etching gas during a first stage of the gas flow cycle; maintaining a second flow rate of the etching gas during a second stage of the gas flow cycle, wherein the first flow rate is lower than the second flow rate. In some embodiments, the step of exposing the fin structure in the opening to the etching gas includes: exposing the fin structure in the opening to the first flow rate of the etching gas during the first stage of the gas flow cycle, the first flow rate of the etching gas is lower than the first flow rate of the precursor gas. During the second stage of the gas flow cycle, exposing the fin structure in the opening to the second flow rate of the etching gas, the second flow rate of the etching gas is higher than the second flow rate of the precursor gas. In some embodiments, the step of forming the source / drain region further includes: exposing the fin structure in the opening to the first flow rate of the dopant precursor gas during the first stage of the gas flow cycle; and exposing the fin structure in the opening to the second flow rate of the dopant precursor gas during the second stage of the gas flow cycle, wherein the first flow rate of the dopant precursor gas is higher than the second flow rate of the dopant precursor gas. In some embodiments, the step of exposing the fin structure in the opening to plasma includes: generating plasma during the second stage of the gas flow cycle; and terminating the plasma during the first stage of the gas flow cycle. In some embodiments, the step of exposing the fin structure in the opening to plasma includes generating plasma during the first stage and the second stage of the gas flow cycle. In some embodiments, the step of exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed at a temperature of about 500°C or less. In some embodiments, the step of forming the source / drain region includes epitaxially growing a semiconductor material and removing an amorphous material from a dielectric side surface of the opening. In some embodiments, the step of forming the source / drain region also includes controlling the ratio of the first flow rate of the precursor gas and the flow rate of the etching gas to be about 50,000:1 to about 1:50,000.

[0255] In some embodiments, a method for forming a semiconductor device includes: forming a fin structure on a substrate; forming a dielectric layer on the fin structure; forming an opening in the fin structure and through the dielectric layer; and epitaxially growing a semiconductor material on the fin structure in the opening. Epitaxially growing the semiconductor layer includes: performing a deposition process using a first flow rate of a precursor gas during a first phase of a gas flow cycle and a second flow rate of the precursor gas during a second phase of the gas flow cycle; performing an etching process using a first flow rate of an etching gas during the first phase of the gas flow cycle and a second flow rate of the etching gas during the second phase of the gas flow cycle; and performing a plasma process during the gas flow cycle. The first flow rate of the precursor gas is higher than the first flow rate of the etching gas, and the second flow rate of the precursor gas is lower than the second flow rate of the etching gas. In some embodiments, the steps of performing the deposition process, the etching process, and the plasma process are in-situ processes. In some embodiments, the deposition process, the etching process, and the plasma process are performed at a temperature of about 500° C. or less. In some embodiments, the step of performing the plasma process includes: generating plasma during the second phase of the gas flow cycle; and terminating the plasma during the first phase of the gas flow cycle. In some embodiments, the step of epitaxially growing the semiconductor layer further includes: performing a doping process using a first flow rate of a dopant precursor gas during a first stage of a gas flow cycle and a second flow rate of a dopant precursor gas during a second stage of a gas flow cycle, and wherein the first flow rate of the dopant precursor gas is higher than the second flow rate of the dopant precursor gas.

[0256] In some embodiments, a method for forming a semiconductor device includes: forming a first superlattice structure on a substrate; forming an isolation layer on the first superlattice structure; forming a second superlattice structure on the isolation layer; forming an opening, the opening passing through the second superlattice structure, the isolation layer and the first superlattice structure; and forming a source / drain region in the opening and the source / drain region contacts the first superlattice structure. Forming the source / drain region includes performing a deposition process using a first flow rate of a precursor gas during a first phase of a gas flow cycle and a second flow rate of the precursor gas during a second phase of the gas flow cycle; performing a doping process using a first flow rate of a dopant precursor gas during the first phase of the gas flow cycle and a second flow rate of the dopant precursor gas during the second phase of the gas flow cycle; generating a plasma during the second phase of the gas flow cycle; and terminating the plasma during the first phase of the gas flow cycle. The first flow rate of the precursor gas is higher than the second flow rate of the precursor gas. The first flow rate of the dopant precursor gas is higher than the second flow rate of the dopant precursor gas. In some embodiments, the first flow rate of the precursor gas is non-zero and the second flow rate of the precursor gas is zero. In some embodiments, the step of forming the source / drain region further comprises: performing an etching process using a first flow rate of the etching gas during a first phase of the gas flow cycle and a second flow rate of the etching gas during a second phase of the gas flow cycle; and wherein the first flow rate of the etching gas is zero and the second flow rate of the etching gas is non-zero. In some embodiments, the step of forming the source / drain region further comprises forming a p-type epitaxial region in the opening. In some embodiments, the method of forming the semiconductor device further comprises forming an n-type source / drain region in the opening, above the source / drain region, and the n-type source / drain region is in contact with the second superlattice structure.

[0257] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the concept and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the concept and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a fin structure on a substrate; forming a polysilicon structure on the fin structure; removing a portion of the fin structure adjacent to the polysilicon structure to form an opening; and Forming a source / drain region in the opening includes exposing the fin structure in the opening to: a first flow rate of a precursor gas during a first phase of a gas flow cycle; a second flow rate of the precursor gas during a second phase of the gas flow cycle, wherein the first flow rate is higher than the second flow rate; an etching gas during the gas flow cycle; and a plasma during the gas flow cycle, The step of exposing the fin structure in the opening to the precursor gas, the etching gas and the plasma is performed in an in-situ process.

2. The method for forming a semiconductor device as described in claim 1, wherein the step of exposing the fin structure in the opening to the etching gas includes exposing the fin structure in the opening to a flow rate of the etching gas that is higher than the first flow rate of the precursor gas.

3. The method for forming a semiconductor device according to claim 1 , wherein the step of exposing the fin structure in the opening to the etching gas comprises: maintaining a first flow rate of the etching gas during the first phase of the gas flow cycle; A second flow rate of the etching gas is maintained during the second phase of the gas flow cycle, wherein the first flow rate is lower than the second flow rate.

4. The method for forming a semiconductor device according to claim 1, wherein the step of forming the source / drain region further comprises: During the first phase of the gas flow cycle, exposing the fin structure in the opening to a first flow rate of a dopant precursor gas; and During the second phase of the gas flow cycle, the fin structure in the opening is exposed to a second flow rate of the dopant precursor gas, wherein the first flow rate of the dopant precursor gas is higher than the second flow rate of the dopant precursor gas.

5. The method for forming a semiconductor device according to claim 1 , wherein the step of exposing the fin structure in the opening to the plasma comprises: generating the plasma during the second phase of the gas flow cycle; and The plasma is terminated during the first phase of the gas flow cycle. 6 . The method for forming a semiconductor device as claimed in claim 1 , wherein the step of exposing the fin structure in the opening to the precursor gas, the etching gas and the plasma is performed at a temperature of about 500° C. or less. 7 . The method for forming a semiconductor device as claimed in claim 1 , wherein the step of forming the source / drain region comprises epitaxially growing a semiconductor material and removing an amorphous material from the dielectric side surface of an opening.

8. A method for forming a semiconductor device, comprising: forming a fin structure on a substrate; forming a dielectric layer on the fin structure; forming an opening in the fin structure and through the dielectric layer; and Epitaxially growing a semiconductor layer on the fin structure in the opening, comprising: Performing a deposition process using a first flow rate of a precursor gas during a first phase of a gas flow cycle and a second flow rate of the precursor gas during a second phase of the gas flow cycle; performing an etching process using a first flow rate of an etching gas during the first phase of the gas flow cycle and a second flow rate of the etching gas during the second phase of the gas flow cycle, wherein the first flow rate of the precursor gas is higher than the first flow rate of the etching gas, and wherein the second flow rate of the precursor gas is lower than the second flow rate of the etching gas; and A plasma process is performed during the gas flow cycle.

9. A method for forming a semiconductor device, comprising: forming a first superlattice structure on a substrate; forming an isolation layer on the first superlattice structure; forming a second superlattice structure on the isolation layer; forming an opening passing through the second superlattice structure, the isolation layer, and the first superlattice structure; and Forming a source / drain region in the opening and the source / drain region is in contact with the first superlattice structure, comprising: performing a deposition process using a first flow rate of a precursor gas during a first phase of a gas flow cycle and a second flow rate of the precursor gas during a second phase of the gas flow cycle, wherein the first flow rate of the precursor gas is higher than the second flow rate of the precursor gas; performing a doping process using a first flow rate of a dopant precursor gas during the first phase of the gas flow cycle and a second flow rate of the dopant precursor gas during the second phase of the gas flow cycle, wherein the first flow rate of the dopant precursor gas is higher than the second flow rate of the dopant precursor gas; generating a plasma during the second phase of the gas flow cycle; and The plasma is terminated during the first phase of the gas flow cycle.

10. The method for forming a semiconductor device according to claim 9, wherein the step of forming the source / drain region further comprises: An etching process is performed using a first flow rate of an etching gas during the first phase of the gas flow cycle and a second flow rate of the etching gas during the second phase of the gas flow cycle; and wherein the first flow rate of the etching gas is zero and the second flow rate of the etching gas is a non-zero value.

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