High-heat-dissipation diamond substrate GaN transistor structure and preparation method thereof

Abstract

The invention discloses a high-heat-dissipation diamond substrate GaN transistor structure and a preparation method thereof. The transistor comprises a diamond substrate layer, a dielectric layer, an III-N barrier layer, a GaN channel layer and an III-N composite buffer layer. The source electrode, the drain electrode and the gate electrode are wrapped by the dielectric layer, the III-N composite buffer layer, the GaN channel layer and the III-N barrier layer are grown on the original substrate layer in sequence, the source electrode, the drain electrode and the gate electrode are prepared on the surface of the III-N barrier layer, the dielectric layer is deposited on the surface of the III-N barrier layer, the dielectric layer and the diamond are bonded, the original substrate layer is removed, and the device is inverted. And finally, etching an electrode connecting through hole on the surface, and leading the electrode to the surface of the device. The heat dissipation capability of the device can be improved, the self-heating effect of the device can be improved, high-frequency and high-power application is realized, and the stability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a high heat dissipation diamond substrate GaN transistor structure and a preparation method thereof. Background Art

[0002] The third generation of semiconductor materials represented by gallium nitride (GaN) have significant advantages such as large bandgap (3.4eV), high electron mobility, and high electron saturation rate. Therefore, they have a wider range of application scenarios in the fields of next-generation radio frequency devices and power electronic devices. The III-nitride semiconductor heterojunction has strong spontaneous polarization and piezoelectric polarization effects, which can form a high concentration (1×10 13 cm -2 ), large mobility (2000cm 2 / V·s) of high-density two-dimensional electron gas (2DEG), which makes GaN-based HEMT devices have the advantages of high breakdown voltage, low on-resistance, high switching frequency and small size, making them the preferred solution for the development of high-performance, low-power, low-cost microwave and millimeter-wave devices and their front-end circuits. In particular, they have important applications in the fields of wireless charging, laser radar, electric vehicles and intelligent transportation.

[0003] With the continuous development of GaN-based microwave power devices, higher output power and frequency are required. At the same time, for higher integration, the size of the device must also be reduced. However, with the miniaturization of size and the increase in power, the reliability and stability of the device are greatly challenged. This is because the self-heating effect of the active area of ​​the chip becomes serious with the increase in power density, resulting in deterioration of performance under high power. Therefore, the low heat dissipation capacity of GaN-based power devices has become an important factor restricting their performance improvement, and the heat dissipation capacity is mainly determined by the substrate material of the device. Diamond, as an ultra-wide bandgap semiconductor material, is currently the substrate with the highest thermal conductivity, with a thermal conductivity of up to 22W / cm·K, which is 44 times, 14.6 times and 5.5 times that of sapphire (0.5W / cm·K), silicon (1.5W / cm·K) and silicon carbide (4W / cm·K). Compared with the commonly used SiC and Si-based GaN microwave power devices, diamond-based GaN power devices have higher heat dissipation capabilities and are expected to achieve smaller size and higher power density power devices, thereby promoting the miniaturization, integration and high-power applications of future RF power devices and related systems. However, due to the large gap between diamond and GaN materials in crystal structure and lattice constant, it is currently difficult to directly epitaxially grow GaN materials on diamond substrates. Summary of the invention

[0004] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a high heat dissipation diamond substrate GaN transistor structure and a preparation method thereof, so as to improve the heat dissipation capacity of the device, solve the problem that the self-heating effect of the chip active area becomes serious due to the increase in power density of traditional devices, resulting in performance deterioration under high power, which is conducive to improving its self-heating effect, realizing high-frequency and high-power applications, and improving the stability of the device.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A high heat dissipation diamond substrate GaN transistor structure, comprising a diamond substrate layer, a dielectric layer, a III-N barrier layer, a GaN channel layer and a III-N composite buffer layer arranged in sequence from bottom to top; a source electrode, a drain electrode and a gate electrode are wrapped by the dielectric layer, and the source electrode and the drain electrode both form an ohmic contact with the III-N barrier layer, and the gate electrode forms a Schottky contact with the III-N barrier layer; a two-dimensional electron gas is generated near the heterojunction interface formed by the GaN channel layer and the III-N barrier layer as a conductive channel, and is regulated by the gate electrode;

[0007] An upper surface source electrode, an upper surface drain electrode and an upper surface gate electrode are arranged on the upper surface of the III-N composite buffer layer; three electrode connection through holes are arranged through the III-N barrier layer, the GaN channel layer and the III-N composite buffer layer, and the three electrode connection through holes respectively realize electrical connection between the source electrode and the upper surface source electrode, the drain electrode and the upper surface drain electrode, and the gate electrode and the upper surface gate electrode.

[0008] In one embodiment, the material of the dielectric layer is AlN or BN, the material of the III-N barrier layer is AlGaN, and the III-N composite buffer layer includes three layers, namely, a buffer layer, a transition layer and a nucleation layer from bottom to top. The material of the buffer layer is GaN or AlGaN, the material of the transition layer is AlGaN, and the material of the nucleation layer is AlN or GaN.

[0009] In one embodiment, the nucleation layer, transition layer and buffer layer are unintentionally doped

[0010] In one embodiment, the thickness of the diamond substrate layer is 50-1500 μm, the thickness of the dielectric layer is 80-1500 nm, the thickness of the III-N barrier layer is 10-30 nm, the thickness of the buffer layer is 100-5000 nm, the thickness of the transition layer is 200-1000 nm, and the thickness of the nucleation layer is 50-300 nm.

[0011] In one embodiment, the structures of the source electrode and the drain electrode are Ti / Al / Ni / Au, or Ta / Al / Ni / Au, or TiN / Al / Ni / Au from top to bottom, and the structures of the gate electrode are Ni and Au, or Ti and Au, or TiN and Au, or TaN and Au from top to bottom;

[0012] The material of the bottom layer of the upper surface source electrode, the upper surface drain electrode and the upper surface gate electrode is Ti, Cr, or TiN, and the material of the remaining layers is Au or Cu;

[0013] The material of the bottom layer of the upper surface gate electrode is Ti, Cr, or TiN; the material of the remaining layers is Au or Cu.

[0014] In one embodiment, the surfaces of the source electrode, the drain electrode and the gate electrode except the upper surface are wrapped by a dielectric layer, and the upper surface is connected to the lower surface of the III-N barrier layer and the bottom end of the electrode connection through hole.

[0015] In one embodiment, the electrode connection through hole is provided with an insulating material and a metal interconnection material, and the metal interconnection material is arranged along the length direction of the hole to realize the electrical connection between the source electrode and the upper surface source electrode, the drain electrode and the upper surface drain electrode, and the gate electrode and the upper surface gate electrode;

[0016] The insulating material is arranged between the inner wall of the electrode connection through hole and the metal interconnection material to realize the electrical isolation of the source electrode and the drain electrode as well as the gate electrode and the channel layer.

[0017] In one embodiment, the insulating material is SiO 2 , or SiN, or AlN, and its thickness, that is, the distance between the metal interconnection material and the inner wall of the electrode connection through hole, is 0.5-2μm; the metal interconnection material uses Ti and Cu or Ti and Au, wherein Ti is used as a metal barrier layer.

[0018] In one embodiment, the electrode connecting through hole is a circular hole or a square hole, and its diameter or diagonal length is 5-100 μm.

[0019] The present invention also provides a method for preparing a high heat dissipation diamond substrate GaN transistor, comprising the following steps:

[0020] Step 1: On the original substrate layer, a III-N composite buffer layer, a GaN channel layer, and a III-N barrier layer are grown in sequence, and then cleaned;

[0021] Step 2: preparing a source electrode and a drain electrode on the surface of the III-N barrier layer of the cleaned structure, wherein both the source electrode and the drain electrode simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer and the III-N barrier layer;

[0022] Step 3: On the surface of the structure obtained in step 2, a gate electrode is prepared, and the gate electrode forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer and the III-N barrier layer to prepare a conventional GaN HEMT device;

[0023] Step 4: Depositing a dielectric layer on top of the device obtained in step 3;

[0024] Step 5: Bonding the dielectric layer to the diamond substrate layer;

[0025] Step 6: Remove the original substrate layer and invert the device, using the diamond substrate layer as a new substrate layer;

[0026] Step 7: etching electrode connection holes on the surface of the inverted structure, and depositing insulating materials and metal interconnection materials in the electrode connection holes;

[0027] Step 8: Obtain the upper surface of the structure in step 7, make an upper surface source electrode, an upper surface drain electrode, and an upper surface gate electrode, and complete the production of the transistor.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The present invention does not change the traditional GaN HEMT manufacturing process, but uses a diamond substrate to improve the performance of the device: it can solve the problem that the self-heating effect of the chip active area becomes serious due to the increase in power density of traditional devices, resulting in performance deterioration under high power, which is conducive to improving its self-heating effect, realizing high-frequency and high-power applications, and improving the stability of the device

[0030] 2. The preparation method of the GaN transistor with a diamond substrate provided by the present invention is simple and relatively controllable, compatible with the original process, and can significantly improve the device performance.

[0031] 3. The diamond substrate GaN transistor provided by the present invention uses materials with lower cost and better performance, and is compatible with the original process. This preparation method can significantly improve device performance.

[0032] In summary, the present invention can solve the problem of serious self-heating effect in the active area of ​​the chip due to the increase in power density of traditional devices, resulting in performance deterioration under high power. It is beneficial to improve its self-heating effect and realize the miniaturization and high power of GaN-based power devices, thereby promoting its wide application in related fields of RF power devices and microwave power devices and improving the stability of the devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of a high heat dissipation diamond substrate GaN transistor structure of the present invention.

[0034] Figure 2 It is a schematic diagram of the process flow of a high heat dissipation diamond substrate GaN transistor structure of the present invention.

[0035] In the figure, 1. diamond substrate layer; 2. dielectric layer; 3. III-N barrier layer; 4. GaN channel layer; 5. III-N composite buffer layer; 6. source electrode; 7. drain electrode; 8. gate electrode; 9. upper surface source electrode; 10. upper surface drain electrode; 11. upper surface gate electrode; 12. electrode connection through hole; 13. insulating material; 14. metal interconnect material. DETAILED DESCRIPTION

[0036] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0037] See also Figure 1 The present invention discloses a high heat dissipation diamond substrate GaN transistor structure, comprising a diamond substrate layer 1, a dielectric layer 2, a III-N barrier layer 3, a GaN channel layer 4 and a III-N composite buffer layer 5 arranged in sequence from bottom to top, and the electrodes of the structure include a source electrode 6, a drain electrode 7, a gate electrode 8, an upper surface source electrode 9, an upper surface drain electrode 10 and an upper surface gate electrode 11. A two-dimensional electron gas is generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3 as a conductive channel, and is regulated by the gate electrode 8.

[0038] Among them, the source electrode 6, the drain electrode 7, and the gate electrode 8 are located at the interface between the dielectric layer 2 and the III-N barrier layer 3, and are wrapped by the dielectric layer 2. The upper surface source electrode 9, the upper surface drain electrode 10, and the upper surface gate electrode 11 are located on the upper surface of the III-N composite buffer layer 5. The source electrode 6 and the drain electrode 7 both form an ohmic contact with the III-N barrier layer 3, and the gate electrode 8 forms a Schottky contact with the III-N barrier layer 3.

[0039] Three electrode connection through holes 12 are provided through the III-N barrier layer 3, the GaN channel layer 4 and the III-N composite buffer layer 5, and the source electrode 6 and the upper surface source electrode 9, the drain electrode 7 and the upper surface drain electrode 10, and the gate electrode 8 and the upper surface gate electrode 11 are electrically connected through one electrode connection through hole 12 respectively.

[0040] The present invention uses diamond material as the diamond substrate layer 1, and its thickness can be 50-1500 μm. Diamond, as an ultra-wide bandgap semiconductor material, is the substrate with the highest thermal conductivity at present, and its thermal conductivity is as high as 22W / cm·K, which is 44 times, 14.6 times and 5.5 times that of sapphire (0.5W / cm·K), silicon (1.5W / cm·K) and silicon carbide (4W / cm·K). Compared with the currently commonly used SiC and Si-based GaN microwave power devices, diamond-based GaN power devices have higher heat dissipation capabilities.

[0041] The dielectric layer 2 of the present invention is made of AlN or BN with a thickness of 80-1500 nm. The dielectric layer 2 is compatible with the device process and has a certain thermal conductivity, thereby effectively utilizing the thermal conductivity of the diamond substrate layer 1 to reduce the junction temperature of the device.

[0042] The structures of the source electrode 6 and the drain electrode 7 of the present invention are Ti / Al and other metals, or Ta / Al and other metals, or TiN / Al and other metals from top to bottom; the gate electrode 8 is Ni and other metals, or Ti and other metals, or TiN and other metals, or TaN and other metals from top to bottom.

[0043] The material of the III-N barrier layer 3 of the present invention may be AlGaN with a thickness of 10-30 nm. AlGaN is a typical GaN material, but it is difficult for conventional GaN devices to use diamond substrates.

[0044] The III-N composite buffer layer 5 of the present invention includes three layers, namely, a buffer layer, a transition layer and a nucleation layer from bottom to top; the nucleation layer, the transition layer and the buffer layer are unintentionally doped. The material of the buffer layer is GaN or AlGaN, with a thickness of 100-5000nm; the material of the transition layer is AlGaN, with a thickness of 200-1000nm; the material of the nucleation layer is AlN or GaN, with a thickness of 50-300nm. The main function of the III-N composite buffer layer 5 is to reduce the lattice and thermal expansion coefficient mismatch between the GaN epitaxial layer and the underlying substrate, thereby reducing the defect density at the heterojunction interface and providing good electrical isolation. At the same time, due to the large difference in thermal expansion coefficient between GaN and common substrate materials such as Si and SiC, the III-N composite buffer layer 5 can alleviate the stress caused by the thermal expansion coefficient mismatch, prevent the device from cracking during high-temperature operation or thermal cycling, and the composite buffer layer can also play a role in defect filtering, reduce the propagation of defects from the substrate to the active layer, and improve the crystal quality of the GaN epitaxial layer.

[0045] The electrode connection through hole 12 of the present invention can be a circular hole or a square hole. When it is a circular hole, its diameter is 5-100 μm, and when it is a square hole, its diagonal length is 5-100 μm. The present invention constructs an electrical connection between the electrode in the dielectric layer 2 and the electrode on the upper surface of the III-N composite buffer layer 5, and an electrical isolation between the electrode in the dielectric layer 2 and the GaN channel layer 4 through the electrode connection through hole 12, and the electrode in the dielectric layer 2 can be led to the upper surface of the device.

[0046] In order to achieve the above electrical isolation and electrical connection, an insulating material 13 and a metal interconnection material 14 are provided in the electrode connection through hole 12. The insulating material 13 can be SiO 2 , or SiN, or AlN, with a thickness of 0.5-2μm; the metal interconnection material 14 can be Ti and Cu or Ti and Au, wherein Ti is used as a metal barrier layer. Specifically, the insulating material 13 can be designed between the inner wall of the electrode connection through hole 12 and the metal interconnection material 14, and the metal interconnection material 14 can be arranged at the center of the hole, arranged from top to bottom, or only arranged at the cross section of the GaN channel layer 4.

[0047] The bottom layer of the upper surface source electrode 9, the upper surface drain electrode 10 and the upper surface gate electrode 11 of the present invention is Ti, Cr, or TiN; the second layer and above materials include Au or Cu, with a thickness of 50-5000nm.

[0048] refer to Figure 2 The method for preparing a high heat dissipation diamond substrate GaN transistor structure of the present invention comprises the following steps:

[0049] Step 1: Clean the contaminants on the surface of the original substrate layer.

[0050] Specifically, hydrogen is introduced into the reaction chamber at a high temperature of 900-1100° C. to clean pollutants on the surface of the original substrate layer, where the original substrate layer is Si, SiC, or Sapphire.

[0051] Step 2: On the original substrate layer cleaned in step 1, a III-N composite buffer layer 5, a GaN channel layer 4, and a III-N barrier layer 3 are sequentially grown, and the implementation process may be, for example, a metal organic chemical vapor deposition MOCVD process.

[0052] Among them, the process conditions of metal organic chemical vapor deposition MOCVD are as follows:

[0053] TMGa was used as Ga precursor, TMAl was used as Al precursor, and H 2 and N 2 Mixed gas as carrier gas, NH 3 As a nitrogen source.

[0054] Deposition of GaN NH 3 The flow rate ratio of TMGa is 1500-2500, the temperature is maintained at 900-1100°C, and the growth pressure is maintained at 50-150 mbar.

[0055] Deposition of AlGaN NH 3 The flow rate ratio of TMGa to TMAl is 1500-2500, the flow rate ratio of TMGa to TMAl is 4-20, the temperature is maintained at 900-1100°C, and the growth pressure is maintained at 50-100 mbar.

[0056] Step 3: Clean the structure obtained in steps 1 and 2.

[0057] Specifically, the structure obtained in step 1 to step 2 is ultrasonically cleaned in acetone (MOS grade) for no less than 10 min, and finally cleaned with deionized water and blown dry with nitrogen.

[0058] Step 4: After cleaning in step 3, the source electrode 6 and the drain electrode 7 are prepared by vacuum evaporation or magnetron sputtering, and high-temperature annealing is performed. The source electrode 6 and the drain electrode 7 both form ohmic contacts with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3.

[0059] Among them, high temperature annealing is carried out at 750-900℃ N 2 Perform thermal annealing for 20s-90s in an atmosphere.

[0060] Step 5: In the middle of the top surface of the structure obtained in steps 1 to 4, a gate electrode 8 is prepared by vacuum evaporation or magnetron sputtering. The gate electrode 8 forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3 to prepare a traditional GaN HEMT device.

[0061] Step 6: On top of the device obtained in steps 1 to 5, a dielectric layer 2 is deposited by a process such as atomic layer deposition (ALD).

[0062] Step 7: Polishing the surface of the dielectric layer 2, for example, can be achieved by using a CMP chemical mechanical polishing process.

[0063] Step 8: Bond the processed top dielectric layer 2 of the structure to the diamond substrate layer 1 at low temperature.

[0064] Step 9: The original substrate layer is thinned by grinding and wet-etched or dry-etched to remove the original substrate layer, and the device is turned upside down, with the diamond substrate layer 1 serving as a new substrate layer.

[0065] Step 10: Etch electrode connection holes 12 on the surface of the inverted structure, deposit insulating material 13 in the electrode connection holes 12 by plasma enhanced chemical vapor deposition (PECVD) and other processes, sputter a metal barrier layer and a metal seed layer, and then electroplate a metal interconnection material 14 to completely fill the electrode connection holes 12.

[0066] Among them, the plasma enhanced chemical vapor deposition PECVD process conditions are as follows:

[0067] SiH 4 and N 2 O was used as the precursor gas, and the flow rates were maintained at 50-80 cm3 / min and 160-200 cm3 / min, respectively. 3 / min, the temperature is maintained at 250-300°C, the growth pressure is maintained at 80-100Pa, and the RF power is set to 60-100W.

[0068] Step 11: After obtaining the upper surface of the structure in steps 1 to 10, deposit the upper surface source electrode 9, the upper surface drain electrode 10 and the upper surface gate electrode 11 by vacuum evaporation or magnetron sputtering process, and lead the electrodes to the device surface to complete the manufacture of the transistor.

[0069] The following are several specific embodiments of the present invention.

[0070] Example 1

[0071] See also Figure 1 A high heat dissipation diamond substrate GaN transistor structure includes a diamond substrate layer 1, a dielectric layer 2, a source electrode 6 and a drain electrode 7 wrapped by the dielectric layer 2, and a gate electrode 8, a III-N barrier layer 3, a GaN channel layer 4, and a III-N composite buffer layer 5. Electrode connection through holes 12 are provided between the source electrode 6 and the drain electrode 7 and the gate electrode 8 and the upper surface of the III-N composite buffer layer 5. An upper surface source electrode 9, an upper surface drain electrode 10, and an upper surface gate electrode 11 are provided on the upper surface of the III-N composite buffer layer 5. The source electrode 6 and the drain electrode 7 both form an ohmic contact with the III-N barrier layer 3, the gate electrode 8 forms a Schottky contact with the III-N barrier layer 3, and a two-dimensional electron gas is generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3 as a conductive channel, and is regulated by the gate electrode 8.

[0072] The thickness of the diamond substrate layer 1 is 500μm, the dielectric layer 2 is made of AlN with a thickness of 1000nm, and the structures of the source electrode 6 and the drain electrode 7 are Ti / Al / Ni / Au from top to bottom, with thicknesses of 20 / 120 / 40 / 50nm. The gate electrode 8 is TiN / Au from top to bottom, with thicknesses of 50 / 300nm. The material of the III-N barrier layer 3 is AlGaN with a thickness of 10nm. In the three-layer structure of the III-N composite buffer layer 5, the material of the buffer layer is GaN with a thickness of 1000nm. The material of the transition layer is AlGaN with a gradient Al component, with a thickness of 800nm, and the Al component gradients from 1 to 0.1. The material of the nucleation layer is AlN with a thickness of 200nm.

[0073] The present invention utilizes the diamond substrate layer 1 to solve the problem of serious self-heating effect in the active area of ​​the chip due to the increase in power density of traditional devices, resulting in performance deterioration under high power. It is beneficial to improve its self-heating effect and realize the miniaturization and high power of GaN-based power devices, thereby promoting its wide application in related fields of radio frequency power devices and microwave power devices and improving the stability of the devices.

[0074] The electrode connection through hole 12 is a circular hole with a diameter of 20 μm. The insulating material 13 is made of SiO 2 The thickness is 1 μm, and the metal interconnection material 14 is made of Ti and Au, wherein Ti is used as a metal barrier layer. The structure of the upper surface source electrode 9, the upper surface drain electrode 10, and the upper surface gate electrode 11 is Au, with a thickness of 50 nm.

[0075] refer to Figure 2 The method for preparing the high heat dissipation diamond substrate GaN transistor structure comprises the following steps:

[0076] Step 1: At a high temperature of 1000°C, hydrogen is introduced into the reaction chamber to clean the pollutants on the surface of the original substrate layer Si and form a microscopic step structure on the substrate surface to facilitate the subsequent epitaxial process to grow various epitaxial layers.

[0077] Step 2: On the original substrate layer cleaned in step 1, a metal organic chemical vapor deposition (MOCVD) method is used to sequentially grow a III-N composite buffer layer 5, a GaN channel layer 4, and a III-N barrier layer 3.

[0078] First, a III-N composite buffer layer 5 is grown, and a nucleation layer, a transition layer and a buffer layer are grown in sequence from bottom to top by a metal organic chemical vapor deposition (MOCVD) method. That is, a 200 nm thick aluminum nitride nucleation layer is first grown on a substrate by a MOCVD method at a low temperature of 500°C, and then the temperature is raised to 1000°C, and a transition layer is grown on the nucleation layer by a MOCVD method. The transition layer is a gradient AlGaN with a thickness of 800 nm, and the Al component is gradually changed from 0.75 to 0.15, and then a GaN buffer layer with a thickness of 1000 nm is grown on the transition layer.

[0079] Then, a GaN channel layer 4 with a thickness of 300 nm is grown on the buffer layer at a temperature of 1000° C. by MOCVD, and an AlGaN barrier layer 3 with a thickness of 10 nm is epitaxially grown on the channel layer 4 , with an Al composition of 0.15.

[0080] Step 3: The structure obtained from step 1 to step 2 was ultrasonically cleaned in acetone (MOS grade) for 10 min, with the ultrasonic power set at 1 KW, and finally cleaned with deionized water and dried with nitrogen.

[0081] Step 4: After cleaning in step 3, the surface edge of the III-N barrier layer 3 of the structure is vacuum evaporation process, that is, multilayer metal Ti / Al / Ni / Au is grown in the area in the device by electron beam evaporation, from bottom to top, 20nm thick Ti, 120nm thick Al, 40nm thick Ni, 50nm thick Au, and the source electrode 6 and drain electrode 7 are formed after peeling, and then heated to 850℃ N 2 A high temperature annealing is performed for 30 seconds in an atmosphere, and both the source electrode 6 and the drain electrode 7 simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3 .

[0082] Step 5: After obtaining the top surface of the structure in steps 1 to 4, a gate electrode 8 of a TiN / Au combination is prepared again by electron beam evaporation, wherein the thickness of TiN is 50 nm and the thickness of Au is 300 nm. After peeling, a gate electrode 8 is formed. The gate electrode 8 forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3, thereby preparing a conventional GaN HEMT device.

[0083] Step 6: At the top of the device obtained in steps 1 to 5, a dielectric layer 2 is deposited by atomic layer deposition (ALD). Under process conditions of a reaction chamber temperature of 200°C and a pressure of 1.2 mbar, a dielectric layer 2 of AlN with a thickness of 1000 nm is epitaxially grown on the barrier layer 3 around the source 6, drain 7, and gate 8.

[0084] Step 7: Perform CMP chemical mechanical polishing on the surface of the dielectric layer 2 to improve the smoothness and flatness of the surface of the dielectric layer 2 .

[0085] Step 8: low-temperature bonding is performed on the processed top dielectric layer 2 of the structure and the substrate layer 1, with the bonding temperature being 100°C.

[0086] Step 9: The original substrate layer is thinned by grinding and wet-etched. The etching solution is a mixed solution of nitric acid, hydrofluoric acid and acetic acid. The original substrate layer Si is removed, and the device is turned upside down, and the substrate layer 1 is used as the new substrate layer.

[0087] Step 10: After the inverted structure is inverted, an electrode connection through hole 12 is etched, and an insulating material 13 is deposited in the electrode connection through hole by plasma enhanced chemical vapor deposition (PECVD), and then a metal barrier layer and a metal seed layer are sputtered, and then a metal interconnection material 14 is electroplated to completely fill the electrode connection through hole 12. Using inductively coupled plasma etching (ICP) technology, a circular upper electrode connection through hole 12 with a diameter of 20 μm is etched on the upper surface of the source electrode 6 and the drain electrode 7 as well as the gate electrode 8 and the III-N composite buffer layer 5. Using plasma enhanced chemical vapor deposition (PECVD) technology, on the SiH 4 and N 2 O is the precursor gas, and the flow rate is 60 cm 3 / min、200cm 3 Under the process conditions of 1 μm thick SiO2 is deposited on the inner wall of the upper electrode connecting through hole 12 at a temperature of 260°C, a growth pressure of 100 Pa, and a radio frequency power of 80 W. 2 Insulating material 13. Using sputtering technology, metal interconnect material 14 is deposited outside the insulating material 13, that is, a Ti barrier layer with a thickness of 0.3 μm and an Au seed layer with a thickness of 0.5 μm are first deposited outside the insulating material 13 in sequence, and then a periodic pulse reverse PPR electroplating technology is used to deposit metal Au outside the Au seed layer until the electrode connection through hole 12 is completely filled.

[0088] Step 11: At the upper surface electrode connection through hole 12 of the structure obtained in steps 1 to 10, a vacuum evaporation process is used, that is, metal Au with a thickness of 50 nm is grown in the device by electron beam evaporation in this area. After peeling, the upper surface source electrode 9, the upper surface drain electrode 10 and the upper surface gate electrode 11 are formed to complete the production of the transistor.

[0089] Example 2

[0090] See also Figure 1A high heat dissipation diamond substrate GaN transistor structure includes a diamond substrate layer 1, a dielectric layer 2, a source electrode 6 and a drain electrode 7 wrapped by the dielectric layer 2, and a gate electrode 8, a III-N barrier layer 3, a GaN channel layer 4, and a III-N composite buffer layer 5. Electrode connection through holes 12 are provided between the source electrode 6 and the drain electrode 7 and the gate electrode 8 and the upper surface of the III-N composite buffer layer 5. An upper surface source electrode 9, an upper surface drain electrode 10, and an upper surface gate electrode 11 are provided on the upper surface of the III-N composite buffer layer 5. The source electrode 6 and the drain electrode 7 both form an ohmic contact with the III-N barrier layer 3, the gate electrode 8 forms a Schottky contact with the III-N barrier layer 3, and a two-dimensional electron gas is generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3 as a conductive channel, and is regulated by the gate electrode 8.

[0091] The thickness of the diamond substrate layer 1 is 500μm, the dielectric layer 2 is made of BN with a thickness of 1000nm, and the structures of the source electrode 6 and the drain electrode 7 are TiN / Al / Ni / Au from top to bottom, with thicknesses of 30 / 120 / 20 / 50nm. The gate electrode 8 is Ni / Au from top to bottom, with thicknesses of 50 / 300nm. The material of the III-N barrier layer 3 is AlGaN with a thickness of 10nm. In the three-layer structure of the III-N composite buffer layer 5, the material of the buffer layer is AlGaN with a thickness of 400nm. The material of the transition layer is AlGaN with a gradient Al component, with a thickness of 900nm, and the Al component gradients from 1 to 0.1. The material of the nucleation layer is GaN with a thickness of 200nm.

[0092] The electrode connection through hole 12 is a circular hole with a diameter of 20 μm. The insulating material 13 is made of SiO 2 The metal interconnect material 14 is made of Ti and Cu, where Ti is used as a metal barrier layer. The structure of the upper surface source electrode 9, the upper surface drain electrode 10, and the upper surface gate electrode 11 is Cu, with a thickness of 50nm.

[0093] refer to Figure 2 The method for preparing the high heat dissipation diamond substrate GaN transistor structure comprises the following steps:

[0094] S1: At a high temperature of 1000°C, hydrogen is introduced into the reaction chamber to clean the pollutants on the surface of the original substrate layer Si and form a microscopic step structure on the substrate surface to facilitate the subsequent epitaxial process to grow various epitaxial layers.

[0095] S2: On the original substrate layer cleaned in step 1, a metal organic chemical vapor deposition (MOCVD) method is used to sequentially grow a III-N composite buffer layer 5, a GaN channel layer 4, and a III-N barrier layer 3.

[0096] A III-N composite buffer layer 5 is first grown, and a nucleation layer, a transition layer and a buffer layer are sequentially grown from bottom to top by a metal organic chemical vapor deposition (MOCVD) method. That is, a GaN nucleation layer with a thickness of 200 nm is first grown on a substrate by a MOCVD method at a low temperature of 500°C, and then the temperature is raised to 1000°C, and a transition layer with a thickness of 900 nm of gradient AlGaN is grown on the nucleation layer by a MOCVD method, in which the Al component gradually changes from 1 to 0.1, and then a 400 nm thick AlGaN buffer layer is grown on the transition layer.

[0097] Then, a GaN channel layer 4 with a thickness of 300 nm is grown on the buffer layer at a temperature of 1000° C. by MOCVD, and an AlGaN barrier layer 3 with a thickness of 10 nm is epitaxially grown on the channel layer 4 , with an Al composition of 0.15.

[0098] S3: The structure obtained in step 1 to step 2 is ultrasonically cleaned in acetone (MOS grade) for 10 minutes, with the ultrasonic power set at 1KW, and finally cleaned with deionized water and blown dry with nitrogen.

[0099] S4: After cleaning in step 3, the surface edge of the III-N barrier layer 3 of the structure is vacuum evaporated, i.e., a multilayer of metal TiN / Al / Ni / Au is grown in the device in the region by electron beam evaporation, which is 30nm thick TiN, 120nm thick Al, 20nm thick Ni, and 50nm thick Au from bottom to top. After stripping, the source electrode 6 and the drain electrode 7 are formed, and then heated to 850℃ N 2 A high temperature annealing is performed for 30 seconds in an atmosphere, and both the source electrode 6 and the drain electrode 7 simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3 .

[0100] S5: After obtaining the top surface of the structure in steps 1 to 4, a gate electrode 8 of a Ni / Au combination is prepared again by electron beam evaporation, wherein the thickness of Ni is 50 nm and the thickness of Au is 300 nm. After peeling, a gate electrode 8 is formed. The gate electrode 8 forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer 4 and the III-N barrier layer 3, thereby preparing a conventional GaN HEMT device.

[0101] S6: After obtaining the top of the device in steps 1 to 5, a dielectric layer 2 is deposited by atomic layer deposition (ALD). Under process conditions of a reaction chamber temperature of 200°C and a pressure of 1.2 mbar, a BN dielectric layer 2 with a thickness of 100 nm is epitaxially grown on the barrier layer 3 around the source 6, the drain 7, and the gate 8.

[0102] S7: performing CMP chemical mechanical polishing on the surface of the dielectric layer 2 to improve the smoothness and flatness of the surface of the dielectric layer 2 .

[0103] S8: low-temperature bonding the processed top dielectric layer 2 of the structure to the substrate layer 1, with the bonding temperature being 100°C.

[0104] S9: The original substrate layer is thinned by grinding and wet-etched. The etching solution is a mixed solution of nitric acid, hydrofluoric acid and acetic acid. The original substrate layer Si is removed, and the device is turned upside down. The substrate layer 1 is used as a new substrate layer.

[0105] S10: After the inverted structure is inverted, an electrode connection through hole 12 is etched, and an insulating material 13 is deposited in the electrode connection through hole by plasma enhanced chemical vapor deposition (PECVD), and then a metal barrier layer and a metal seed layer are sputtered, and then a metal interconnection material 14 is electroplated to completely fill the electrode connection through hole 12. Using inductively coupled plasma etching (ICP) technology, an upper electrode connection through hole 12 with a diameter of 20 μm and a circular through hole shape is etched on the upper surface of the source electrode 6 and the drain electrode 7 as well as the gate electrode 8 and the III-N composite buffer layer 5. Using plasma enhanced chemical vapor deposition (PECVD) technology, on the SiH 4 and N 2 O is the precursor gas, and the flow rate is 60 cm 3 / min、200cm 3 Under the process conditions of 1 μm thick SiO2 is deposited on the inner wall of the upper electrode connecting through hole 12 at a temperature of 260°C, a growth pressure of 100 Pa, and a radio frequency power of 80 W. 2 Insulating material 13. Using sputtering technology, metal interconnect material 14 is deposited outside the insulating material 13, that is, a Ti barrier layer with a thickness of 0.3 μm and a Cu seed layer with a thickness of 0.5 μm are first deposited in sequence outside the insulating material 13, and then a periodic pulse reverse PPR electroplating technology is used to deposit metal Cu outside the Cu seed layer until the electrode connection through hole 12 is completely filled.

[0106] S11: In steps 1 to 10, the upper surface electrode connection through hole 12 of the structure is obtained, and a vacuum evaporation process is used, that is, metal Cu with a thickness of 50nm is grown in the equipment by electron beam evaporation in this area. After peeling, the upper surface source electrode 9, the upper surface drain electrode 10 and the upper surface gate electrode 11 are formed to complete the production of the transistor.

[0107] In summary, compared with the prior art, the present invention is compatible with the original process and has a simple structure. By using diamond as the substrate of GaN HEMT through low-temperature bonding technology, the problem of serious self-heating effect in the active area of ​​the chip due to the increase in power density of traditional devices, resulting in performance deterioration under high power, is solved. It is beneficial to improve its self-heating effect and realize the miniaturization and high power of GaN-based power devices, thereby promoting its wide application in related fields of RF power devices and microwave power devices and improving the stability of the devices.

Claims

1. A high heat dissipation diamond substrate GaN transistor structure, characterized in that: The present invention comprises a diamond substrate layer (1), a dielectric layer (2), a III-N barrier layer (3), a GaN channel layer (4) and a III-N composite buffer layer (5) which are arranged in sequence from bottom to top; a source electrode (6), a drain electrode (7) and a gate electrode (8) are wrapped by the dielectric layer (2), and the source electrode (6) and the drain electrode (7) both form an ohmic contact with the III-N barrier layer (3), and the gate electrode (8) forms a Schottky contact with the III-N barrier layer (3); a two-dimensional electron gas is generated near the heterojunction interface formed by the GaN channel layer (4) and the III-N barrier layer (3) as a conductive channel, and is regulated by the gate electrode (8); The upper surface of the III-N composite buffer layer (5) is provided with an upper surface source electrode (9), an upper surface drain electrode (10) and an upper surface gate electrode (11); three electrode connection through holes (12) are provided through the III-N barrier layer (3), the GaN channel layer (4) and the III-N composite buffer layer (5); the three electrode connection through holes (12) respectively realize electrical connection between the source electrode (6) and the upper surface source electrode (9), the drain electrode (7) and the upper surface drain electrode (10), and the gate electrode (8) and the upper surface gate electrode (11).

2. The high heat dissipation diamond substrate GaN transistor structure and preparation method thereof according to claim 1, characterized in that: The material of the dielectric layer (2) is AlN or BN, the material of the III-N barrier layer (3) is AlGaN, and the III-N composite buffer layer (5) comprises three layers, namely, a buffer layer, a transition layer and a nucleation layer from bottom to top, the material of the buffer layer is GaN or AlGaN, the material of the transition layer is AlGaN, and the material of the nucleation layer is AlN or GaN.

3. The high heat dissipation diamond substrate GaN transistor structure and preparation method thereof according to claim 2, characterized in that: The nucleation layer, transition layer and buffer layer are unintentionally doped.

4. The high heat dissipation diamond substrate GaN transistor structure and the preparation method thereof according to claim 1, 2 or 3, characterized in that: The thickness of the diamond substrate layer (1) is 50-1500 μm, the thickness of the dielectric layer (2) is 80-1500 nm, the thickness of the III-N barrier layer (3) is 10-30 nm, the thickness of the buffer layer is 100-5000 nm, the thickness of the transition layer is 200-1000 nm, and the thickness of the nucleation layer is 50-300 nm.

5. The high heat dissipation diamond substrate GaN transistor structure and preparation method thereof according to claim 1, characterized in that: The structures of the source electrode (6) and the drain electrode (7) are Ti / Al / Ni / Au, or Ta / Al / Ni / Au, or TiN / Al / Ni / Au from top to bottom, and the structures of the gate electrode (8) are Ni and Au, or Ti and Au, or TiN and Au, or TaN and Au from top to bottom; The material of the bottom layer of the upper surface source electrode (9), the upper surface drain electrode (10) and the upper surface gate electrode (11) is Ti, Cr or TiN, and the material of the remaining layers is Au or Cu.

6. The high heat dissipation diamond substrate GaN transistor structure and the preparation method thereof according to claim 1, characterized in that: The surfaces of the source electrode (6), the drain electrode (7) and the gate electrode (8) except the upper surface are wrapped by the dielectric layer (2), and the upper surface is connected to the lower surface of the III-N barrier layer (3) and the bottom end of the electrode connection through hole (12).

7. The high heat dissipation diamond substrate GaN transistor structure and the preparation method thereof according to claim 1, characterized in that: The electrode connection through hole (12) is provided with an insulating material (13) and a metal interconnection material (14), and the metal interconnection material (14) is arranged along the length of the hole to realize electrical connection between the source electrode (6) and the upper surface source electrode (9), the drain electrode (7) and the upper surface drain electrode (10), and the gate electrode (8) and the upper surface gate electrode (11); The insulating material (13) is arranged between the inner wall of the electrode connection through hole (12) and the metal interconnection material (14) to achieve electrical isolation between the source electrode (6) and the drain electrode (7) as well as the gate electrode (8) and the channel layer (4).

8. The high heat dissipation diamond substrate GaN transistor structure and the preparation method thereof according to claim 7, characterized in that: The insulating material (13) is made of SiO2, SiN, or AlN, and its thickness, i.e., the distance between the metal interconnection material (14) and the inner wall of the electrode connection through hole (12), is 0.5-2 μm; the metal interconnection material (14) is made of Ti and Cu or Ti and Au, wherein Ti is used as a metal barrier layer.

9. The high heat dissipation diamond substrate GaN transistor structure and the preparation method thereof according to claim 1, characterized in that: The electrode connection through hole (12) is a circular hole or a square hole, and its diameter or diagonal length is 5-100 μm.

10. The method for preparing a high heat dissipation diamond substrate GaN transistor according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1: On the original substrate layer, a III-N composite buffer layer (5), a GaN channel layer (4), and a III-N barrier layer (3) are grown in sequence, and then cleaned; Step 2: preparing a source electrode (6) and a drain electrode (7) on the surface of the III-N barrier layer (3) of the cleaned structure, wherein the source electrode (6) and the drain electrode (7) simultaneously form an ohmic contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer (4) and the III-N barrier layer (3); Step 3: on the surface of the structure obtained in step 2, a gate electrode (8) is prepared, and the gate electrode (8) forms a Schottky contact with the two-dimensional electron gas generated near the heterojunction interface formed by the GaN channel layer (4) and the III-N barrier layer (3), thereby preparing a conventional GaN HEMT device; Step 4: depositing a dielectric layer (2) on top of the device obtained in step 3; Step 5: bonding the dielectric layer (2) to the diamond substrate layer (1); Step 6: Remove the original substrate layer, and invert the device, using the diamond substrate layer (1) as a new substrate layer; Step 7: etching electrode connection through holes (12) on the surface of the inverted structure, and depositing insulating material (13) and metal interconnection material (14) on the electrode connection through holes (12); Step 8: After obtaining the upper surface of the structure in step 7, a source electrode (9) and a drain electrode (10) are formed on the upper surface, as well as a gate electrode (11) on the upper surface, thereby completing the manufacture of the transistor.

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