Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a semiconductor substrate, forming a plurality of grooves in the semiconductor substrate, forming active regions between the grooves, and forming isolation structures in the grooves; etching back to remove a part of thickness of the active region, and forming a groove between adjacent isolation structures; a semiconductor channel layer is formed in the groove, the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used for improving the carrier mobility of the transistor; and oxidizing a part of the semiconductor channel layer, and forming a first gate oxide layer on the surface of the semiconductor channel layer. The method can prevent the edge region of the transistor from being conducted before the middle region.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing and are widely used in various integrated circuits. They are divided into NMOS transistors and PMOS transistors according to the main carriers and the doping type during manufacturing.

[0003] In the process of manufacturing PMOS transistors, in order to improve the mobility of carriers (holes), a silicon germanium layer is usually formed on the surface of the active area as a channel layer, and then a gate dielectric layer and a gate electrode are formed on the silicon germanium layer. However, the existing formation of PMOS transistors has the problem that the edge area is turned on before the middle area, which affects the performance of the device. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, comprising:

[0005] Providing a semiconductor substrate, wherein a plurality of trenches are formed in the semiconductor substrate, active regions are formed between the trenches, and isolation structures are formed in the trenches;

[0006] Etching back to remove a portion of the thickness of the active area to form a groove between adjacent isolation structures;

[0007] forming a semiconductor channel layer in the groove, wherein the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used to improve the carrier mobility of the transistor;

[0008] A portion of the semiconductor channel layer is oxidized to form a first gate oxide layer on a surface of the semiconductor channel layer.

[0009] In some embodiments, the material of the semiconductor substrate is silicon, and the material of the semiconductor channel layer is silicon germanium.

[0010] In some embodiments, the semiconductor substrate includes a first transistor region and a second transistor region; the active area of ​​the first transistor region is partially etched back to remove the thickness to form the groove; after forming the semiconductor channel layer, a protective layer is formed on the surface of the semiconductor channel layer and the isolation structure of the first transistor region; after forming the protective layer, a second gate oxide layer is formed on the surface of the active area of ​​the second transistor region; the protective layer is removed to form a first gate oxide layer on the surface of the semiconductor channel layer, and the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

[0011] In some embodiments, the first gate oxide layer and the second gate oxide layer are formed by an in-situ water vapor oxidation process. While the first gate oxide layer is being formed, the active area of ​​the second transistor region is continuously oxidized to increase the thickness of the second gate oxide layer.

[0012] In some embodiments, the depth of the groove is 5-10 nm, and the thickness of the semiconductor channel layer is 5-10 nm.

[0013] In some embodiments, the etching gas used when etching back to remove a portion of the thickness of the active area is HCl, the flow rate of the etching gas is 20-100 sccm, and the temperature of the chamber is 680-800 degrees Celsius.

[0014] In some embodiments, the semiconductor channel layer is formed by a selective epitaxial process.

[0015] In some embodiments, the selective epitaxial process uses SiH4 as the silicon source gas with a flow rate of 40-80 sccm, GeH4 as the germanium source gas with a flow rate of 20-50 sccm, and the chamber temperature of 550-700 degrees Celsius. It also includes selective gas HCl with a flow rate of 30-70 sccm.

[0016] In some embodiments, the material of the protective layer is silicon oxide; the protective layer is formed by an atomic layer deposition process; and the protective layer is removed by an isotropic wet etching process.

[0017] Some embodiments of the present disclosure further provide a semiconductor structure, including:

[0018] A semiconductor substrate, wherein the semiconductor substrate has a plurality of trenches, active regions are formed between the trenches, and the trenches have isolation structures;

[0019] The top surface of the active region is lower than the top surface of the isolation structure, so that there is a groove between adjacent isolation structures;

[0020] A semiconductor channel layer located on the top surface of the active region and in the groove, wherein the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used to improve the carrier mobility of the transistor;

[0021] A first gate oxide layer is located on the surface of the semiconductor channel layer.

[0022] In some of the aforementioned embodiments of the present disclosure, a semiconductor structure and a method for forming the same, the formation method comprises the following steps: providing a semiconductor substrate, wherein a plurality of grooves are formed in the semiconductor substrate, wherein the grooves are between active areas, and wherein isolation structures are formed in the grooves; etching back to remove a portion of the thickness of the active area, and forming grooves between adjacent isolation structures; forming a semiconductor channel layer in the grooves, wherein the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used to improve the carrier mobility of the transistor; and oxidizing a portion of the semiconductor channel layer, and forming a first gate oxide layer on the surface of the semiconductor channel layer. The active area of ​​the first transistor region is partially removed by back etching, and a groove is formed between adjacent isolation structures in the first transistor region, that is, the bottom surface of the groove (or the surface of the active area after back etching) is lower than the top surface of the isolation structure. A semiconductor channel layer is subsequently formed in the groove, and the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure. When gate dielectric layers of different thicknesses need to be formed in different regions later, a protective layer is first formed on the surface of the semiconductor channel layer formed in the first transistor region and on the surface of the isolation structure. After the corresponding gate dielectric layer is formed, the protective layer is removed. Since the top surfaces of the semiconductor channel layer and the isolation structure are flush when the protective layer is formed , the surface of the protective layer formed is flat, and there is no top corner area. When the protective layer is removed, the etching rate of each position of the protective layer is consistent, and there is no difference in etching rate due to the stress in the top corner area. Therefore, the semiconductor channel layer and the isolation structure near the junction of the semiconductor channel layer and the isolation structure will not be over-etched, so that the thickness of the edge area and the middle area of ​​the semiconductor channel layer can be kept consistent and no recess defect will be formed in the isolation structure. Therefore, after a gate dielectric layer and a gate electrode located on the gate dielectric layer are subsequently formed on the top surface of the semiconductor channel layer, when the semiconductor channel layer is used as the channel area of ​​the transistor, there will be no problem of the edge area being turned on earlier than the middle area, thereby improving the performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1-Figure 2 It is a partial structural schematic diagram of the formation process of the semiconductor structure in some embodiments of the present disclosure;

[0024] Figure 3-Figure 12 It is a structural schematic diagram of the formation process of the semiconductor structure of some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] As mentioned in the background art, the existing formation of PMOS transistors has the problem that the edge region is turned on before the middle region, which affects the performance of the device.

[0026] Research has found that in the actual process of manufacturing PMOS transistors, not only is it necessary to form a silicon germanium layer to improve the mobility of carriers (holes), but also the threshold voltage or turn-on voltage of the PMOS transistors formed in different regions is required to be different, that is, the thickness of the gate dielectric layer of the PMOS transistors formed in different regions is required to be different. Figure 1 , providing a semiconductor substrate 100, the semiconductor substrate 100 comprising a first region 21 and a second region (not shown in the figure), and subsequently performing PMOS transistors with gate dielectric layers of different thicknesses on the semiconductor substrates in the first region 21 and the second region, an isolation structure 102 is formed in the semiconductor substrate 100 in the first region 21, and an active region 101 is formed between the isolation structures 102, the isolation structure 102 comprising a first silicon oxide layer 103 located at the sidewall and bottom of a trench in the semiconductor substrate 100, a silicon nitride layer 104 located on the surface of the first silicon oxide layer 103, and a second silicon oxide layer 105 located on the surface of the silicon nitride layer 104 and filling the trench, the surface of the isolation structure 102 is flush with the surface of the active region 101, and a protrusion protruding from the active region is also formed on the surface of the active region 101 A silicon germanium layer 103 is formed on the surface of the semiconductor substrate 101, and the silicon germanium layer 103 is subsequently used as a channel layer of a PMOS transistor formed in the first region 21 to improve the carrier (hole) mobility of the PMOS transistor; after the silicon germanium layer 103 is formed, a protective layer 106 (the material of the protective layer 106 is generally silicon oxide) is formed on the surface of the isolation structure 102 and the silicon germanium layer 103, and the protective layer 106 forms a top corner region 22 at the junction of the isolation structure 102 and the silicon germanium layer 103 (or the active region). The purpose of forming the protective layer 106 is to protect the silicon germanium layer 103 and the isolation structure 102 from being damaged when a gate dielectric layer of different thickness (different from the thickness of the gate dielectric layer subsequently formed on the silicon germanium layer 103 in the first region 21) is formed on the surface of the active region of other regions (such as the second region) of the semiconductor substrate 100; Figure 2 After forming a gate dielectric layer of a first thickness (not shown in the figure) in other regions (such as the second region) of the semiconductor substrate 100, the protection layer 106 in the first region 21 is removed by wet etching (refer to Figure 1 ), and then a gate dielectric layer of a second thickness is formed on the silicon germanium layer 103 (not shown in the figure). Further research has found that because the protection layer 106 forms a top corner region 22 (refer to Figure 1 ), the stress at the top corner region 22 will be relatively large. When the protective layer 106 is wet-etched, the etching rate of the protective layer at the top corner region 22 will be greater than the etching rate of the protective layer on the top surface of the silicon germanium layer 103, so that the side of the silicon germanium layer 103 will be exposed in advance and over-etched, forming the edge region 23 of the silicon germanium layer 103 (refer to Figure 2 ) will become thinner, that is, the thickness of the edge region 23 of the silicon germanium layer 103 will be thinner than that of the middle region. After the gate dielectric layer covering the side and top surfaces of the silicon germanium layer 103 and the gate electrode (not shown in the figure) located on the gate dielectric layer are subsequently formed, when the silicon germanium layer 103 is used as the channel region of the PMOS transistor, the edge region of the silicon germanium layer 103 will be turned on earlier than the middle region, affecting the performance of the PMOS transistor. In addition, when etching the protective layer 106, a recess 24 is easily formed in the isolation structure 102 at the junction of the isolation structure 102 and the silicon germanium layer 103 (or active region) (refer to Figure 2 ), which also affects the performance of PMOS transistors.

[0027] To this end, the present disclosure provides a semiconductor structure and a method for forming the same, which prevents the problem that the edge region of the channel region of the formed transistor is turned on earlier than the middle region, thereby improving the performance of the transistor.

[0028] The specific implementation methods of the present disclosure are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present disclosure. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0029] Some embodiments of the present disclosure first provide a method for forming a semiconductor structure, which is described in detail below with reference to the accompanying drawings.

[0030] refer to Figure 3 , a semiconductor substrate 200 is provided, wherein a plurality of trenches are formed in the semiconductor substrate 200, active regions are formed between the trenches, and isolation structures are formed in the trenches.

[0031] The semiconductor substrate 200 serves as a platform for subsequent processes. The material of the semiconductor substrate 200 may be silicon (Si), germanium (Ge); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 200 is silicon. Certain impurity ions are doped into the semiconductor substrate 200 as needed. The impurity ions may be N-type impurity ions or P-type impurity ions. The P-type impurity ions may be one or more of boron, gallium, and indium. The N-type impurity ions may be one or more of phosphorus, arsenic, and antimony.

[0032] In some embodiments, the semiconductor substrate 200 may include a first transistor region 11 and a second transistor region 12, wherein the first transistor region 11 is subsequently formed into a first transistor, and the second transistor region 12 is subsequently formed into a second transistor. In a specific embodiment, the first transistor is a PMOS transistor, and the second transistor is a PMOS transistor or an NMOS transistor.

[0033] The number of the first transistor region 11 and the second transistor region 12 may be one or more, and the first transistor region 11 and the second transistor region 12 may be adjacent to each other or not.

[0034] The semiconductor substrate 200 of the first transistor region 11 has a plurality of trenches, between which are active regions 201, and in which isolation structures 206 are formed, and the isolation structures 206 of the first transistor region 11 are used for electrical isolation between adjacent active regions 201. The semiconductor substrate 200 of the second transistor region 12 also has a plurality of trenches, between which are active regions 202, and in which isolation structures 216 are formed, and the isolation structures 216 of the second transistor region 12 are used for electrical isolation between adjacent active regions 202.

[0035] In some embodiments, the trench depths in the first transistor region 11 and the second transistor region 12 are the same, the trenches are formed in the semiconductor substrate 200 of the first transistor region 11 and the second transistor region 12 simultaneously, and the isolation structures (206, 216) in the trenches are formed simultaneously. In other embodiments, the trench depths in the first transistor region 11 and the second transistor region 12 may be different.

[0036] The isolation structures (206, 216) formed in the trenches in the first transistor region 11 and the second transistor region 12 have the same structure, and the top surface of the isolation structures (206, 216) is flush with the top surface of the active regions (201, 202). In some embodiments, the isolation structures 206 and 216 both include: a first silicon oxide layer 203 located on the sidewall and bottom surface of the trench, a silicon nitride layer 204 located on the surface of the first silicon oxide layer 203, and a second silicon oxide layer 205 located on the surface of the silicon nitride layer 204.

[0037] In a specific embodiment, the formation process of the isolation structure 206 and the isolation structure 216 includes: forming a plurality of grooves in the semiconductor substrate 200 of the first transistor region 11 and the second transistor region 12; forming a first silicon oxide film on the sidewall and bottom wall surfaces of the grooves and on the surface of the semiconductor substrate 200; forming a silicon nitride film on the surface of the first silicon oxide film; forming a second silicon oxide film on the surface of the silicon nitride film, and the second silicon oxide film fills the grooves; using a chemical mechanical polishing process to remove the first silicon oxide film, the silicon nitride film and the second silicon oxide film on the surface of the semiconductor substrate 200, and forming a first silicon oxide layer 203, a silicon nitride layer 204 located on the surface of the first silicon oxide layer 203, and a second silicon oxide layer 205 located on the surface of the silicon nitride layer 204 in the grooves.

[0038] refer to Figure 4 and Figure 5 , a partial thickness of the active region 201 (of the first transistor region 11 ) is removed by etching back, and a groove 209 is formed between adjacent isolation structures 206 (of the first transistor region 11 ).

[0039] In some embodiments, before etching back to remove a portion of the thickness of the active area 201 (of the first transistor region 11), a first mask layer 207 is formed on the active area 202 and the surface of the isolation structure 216 of the second transistor region 12 and the surface of the isolation structure 206 of the first transistor region 11, and the first mask layer 207 has an opening 208 exposing the surface of the active area 201 of the first transistor region 11. The material of the first mask layer 207 can be photoresist, and the opening 208 is formed in the first mask layer 207 through exposure and development processes; using the first mask layer 207 as a mask, the active area 201 of the first transistor region 11 is etched back to remove a portion of the thickness, and a groove 209 is formed between adjacent isolation structures 206 of the first transistor region 11.

[0040] The active area 201 of the first transistor region 11 is partially removed by etching back, and a groove 209 is formed between adjacent isolation structures 206 of the first transistor region 11, that is, the bottom surface of the groove 209 (or the surface of the active area 201 after etching back) is lower than the top surface of the isolation structure 206, and a semiconductor channel layer 210 is subsequently formed in the groove 209 (refer to Figure 8 ), the top surface of the semiconductor channel layer 210 is flush with the top surface of the isolation structure 206. When gate dielectric layers of different thicknesses need to be formed in different regions later, a protective layer 211 is first formed on the surface of the semiconductor channel layer 210 formed in the first transistor region 11 and on the surface of the isolation structure 206 (refer to Figure 8), after forming the corresponding gate dielectric layer, the protective layer will be removed. Since the top surfaces of the semiconductor channel layer 210 and the isolation structure 206 are flush when the protective layer 211 is formed, the surface of the formed protective layer 211 is flat, and there will be no top corner area. When removing the protective layer 211, the etching rate of each position of the protective layer 211 is consistent, and there will be no difference in etching rate due to the stress in the top corner area. Therefore, the semiconductor channel layer 210 and the isolation structure 206 near the junction will not be over-etched, so that the thickness of the edge area and the middle area of ​​the semiconductor channel layer 210 can be kept consistent and no recess defect will be formed in the isolation structure 206. Therefore, after subsequently forming a gate dielectric layer and a gate electrode located on the gate dielectric layer on the top surface of the semiconductor channel layer 210, when the semiconductor channel layer 210 is used as the channel area of ​​the transistor, there will be no problem that the edge area is turned on earlier than the middle area, thereby improving the performance of the transistor.

[0041] In some embodiments, the depth of the groove 209 is 5-10 nm.

[0042] In some embodiments, the etching gas used when etching back to remove a portion of the thickness of the active area 201 is HCl, the flow rate of the etching gas is 20-100 sccm, and the temperature of the chamber is 680-800 degrees Celsius. In some embodiments, when etching, the etching gas is HCl, which can be ionized to form plasma to etch the active area 201.

[0043] refer to Figure 6 A semiconductor channel layer 210 is formed in the groove 209 , and a top surface of the semiconductor channel layer 210 is flush with a top surface of the isolation structure 206 .

[0044] The semiconductor channel layer 210 serves as a channel region of a transistor to be formed subsequently. The semiconductor channel layer 210 is used to improve the mobility of carriers of the transistor to be formed subsequently.

[0045] The first transistor region 11 is subsequently used to form a PMOS transistor. The material of the semiconductor channel layer 210 may be silicon germanium. The semiconductor channel layer 210 is used to improve the mobility of hole carriers of the subsequently formed PMOS transistor.

[0046] The semiconductor channel layer 210 is formed by a selective epitaxial process.

[0047] In some embodiments, the selective epitaxial process uses SiH4 as the silicon source gas with a flow rate of 40-80 sccm, GeH4 as the germanium source gas with a flow rate of 20-50 sccm, and the chamber temperature of 550-700 degrees Celsius. It also includes selective gas HCl with a flow rate of 30-70 sccm.

[0048] In some embodiments, the semiconductor channel layer 210 has a thickness of 5-10 nm.

[0049] Since HCl gas is used in both the step of etching back to remove a portion of the thickness of the active area 201 and the step of forming the semiconductor channel layer 210, in some embodiments, etching back to remove a portion of the thickness of the active area 201 and forming the semiconductor channel layer 210 can be performed in the same chamber, for example, both are performed in a selective epitaxial deposition chamber. After the step of etching back to remove a portion of the thickness of the active area 201 is performed in the selective epitaxial deposition chamber, the step of forming the semiconductor channel layer 210 is performed in the same selective epitaxial deposition chamber to save process time, improve process efficiency, prevent the sidewalls and bottom of the groove 208 from leaving the cavity after the groove 209 is formed, and be contaminated or oxidized, thereby improving the quality of the formed semiconductor channel layer 210.

[0050] In other embodiments, the step of etching back to remove a portion of the thickness of the active area 201 and the step of forming the semiconductor channel layer 210 are performed in different process chambers.

[0051] In some embodiments, reference Figure 7 , remove the first mask layer 207 (refer to Figure 6 ).

[0052] The first mask layer 207 may be removed by an etching process or an ashing process.

[0053] In some embodiments, reference Figure 8 , further comprising: after forming the semiconductor channel layer 210 , forming a protection layer 211 on surfaces of the semiconductor channel layer 210 and the isolation structure 206 of the first transistor region 11 .

[0054] The protective layer 211 covers the surface of the semiconductor channel layer 210 and the isolation structure 206 of the first transistor region 11 to form the protective layer 211, and exposes the surface of the active area 202 (and the isolation structure 216) of the second transistor region 12. When the corresponding process (such as forming a gate dielectric layer (or a second gate oxide layer)) is subsequently performed in the second transistor region 12, the protective layer 211 protects the semiconductor channel layer 210 and the isolation structure 206 of the first transistor region 11 from being damaged.

[0055] The protective layer 211 may be a single layer or a multi-layer stacked structure, and the material of the protective layer 211 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0056] The protective layer 211 is formed by a deposition process, and the protective layer formed by the second transistor region 12 is removed by an etching process. The deposition process includes an atomic layer deposition process, atmospheric pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (ThermalCVD), and high density plasma chemical vapor deposition (HDPCVD).

[0057] In some embodiments, reference Fig. 9 , further comprising: after forming the protection layer 211 , forming a gate dielectric layer (a second gate oxide layer 212 ) on the surface of the active area 202 of the second transistor region 12 .

[0058] The material of the second gate oxide layer 212 may be silicon oxide. In one embodiment, the second gate oxide layer 212 is formed by an in-situ water vapor oxidation process. The second gate oxide layer 212 serves as a gate dielectric layer of the transistor formed in the second transistor region 12. The transistor formed in the second transistor region 12 may be a PMOS transistor or an NMOS transistor.

[0059] In some embodiments, reference Fig.10 , further comprising: forming a second gate oxide layer 212 covering the second transistor region 12 and a second mask layer 213 of the isolation structure 216 , wherein the second mask layer 213 exposes the protection layer 211 of the first transistor region 11 .

[0060] The second mask layer 213 is used to protect the second gate oxide layer 212 and the isolation structure 216 of the second transistor region 12 when the protection layer 211 is removed.

[0061] The material of the second mask layer 213 is different from the material of the protection layer 211. In one embodiment, the material of the second mask layer 213 is photoresist.

[0062] In some embodiments, reference Fig.11 , further comprising: removing the protective layer 211 (reference Fig.10 ).

[0063] The protective layer 211 may be removed by using an isotropic wet etching process or an isotropic dry etching process.

[0064] In the present disclosure, since the top surface of the semiconductor channel layer 210 formed in the groove 209 is flush with the top surface of the isolation structure 206, when it is necessary to form a gate dielectric layer (second gate oxide layer 212) of different thicknesses in the second transistor region 12, a protective layer 211 is first formed on the surface of the semiconductor channel layer 210 formed in the first transistor region 11 and on the surface of the isolation structure 206. After the corresponding gate dielectric layer (second gate oxide layer 212) is formed, the protective layer 211 is removed. Since the top surfaces of the semiconductor channel layer 210 and the isolation structure 206 are flush when the protective layer 211 is formed, the surface of the formed protective layer 211 is flat and there is no top corner area. When the protective layer 211 is removed, the protective layer 211 is not The etching rate of each position of the layer 211 is consistent, and there will be no difference in etching rate due to stress in the top corner area. Therefore, the semiconductor channel layer 210 and the isolation structure 206 near the junction of the semiconductor channel layer 210 and the isolation structure 206 in the first transistor area 11 will not be over-etched, so that the thickness of the edge area and the middle area of ​​the semiconductor channel layer 210 can be kept consistent and no recess defect will be formed in the isolation structure 206. Therefore, after a gate dielectric layer and a gate electrode located on the gate dielectric layer are subsequently formed on the top surface of the semiconductor channel layer 210, when the semiconductor channel layer 210 is used as the channel area of ​​the transistor, there will be no problem of the edge area being turned on earlier than the middle area, thereby improving the performance of the transistor formed in the first transistor area 11.

[0065] refer to Fig.12 , remove the second mask layer 213 (refer to Fig.11 ) ; partially oxidizing the semiconductor channel layer 210 to form a first gate oxide layer 215 on the surface of the semiconductor channel layer 210.

[0066] The second mask layer 213 may be formed by a wet etching process or an ashing process.

[0067] The semiconductor channel layer 210 is partially oxidized by an in-situ water vapor oxidation process. While the semiconductor channel layer 210 is partially oxidized (or while the first gate oxide layer is formed), the active area 202 of the second transistor region 12 is continuously oxidized to increase the thickness of the second gate oxide layer 212, that is, the thickness of the formed second gate oxide layer 212 is greater than the thickness of the first gate oxide layer 215 (or the thickness of the first gate oxide layer 215 is less than the thickness of the second gate oxide layer 212) to meet the performance requirements of transistors formed in different regions (such as different threshold voltages or turn-on voltages).

[0068] In some embodiments, the method further includes: forming a first gate electrode (not shown in the figure) on the surface of the first gate oxide layer 215 ; and forming a second gate electrode (not shown in the figure) on the surface of the second gate oxide layer 212 .

[0069] The material of the first gate electrode and the second gate electrode is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0070] In some embodiments, before forming the first gate electrode and the second gate electrode, a first work function layer may be formed on the surface of the first gate oxide layer 215 ; and a second work function layer may be formed on the surface of the second gate oxide layer 212 .

[0071] The first work function layer is used to adjust the work function of the transistor formed in the first transistor region 11 . The second work function layer is used to adjust the work function of the transistor formed in the second transistor region 12 .

[0072] The materials of the first work function layer and the second work function layer may be the same or different.

[0073] In some embodiments, the material of the first work function layer or the second work function layer includes titanium, tantalum, titanium nitride, tantalum nitride, cobalt, titanium aluminum nitride, titanium aluminum cobalt, ruthenium, copper manganese, titanium aluminum nitride, titanium aluminum or lanthanum.

[0074] Some embodiments of the present disclosure further provide a semiconductor structure, referring to Fig.12 ,include:

[0075] A semiconductor substrate 200, wherein the semiconductor substrate 200 has a plurality of trenches, an active area 201 is formed between the trenches, and an isolation structure 206 is formed in the trenches;

[0076] The top surface of the active region 201 is lower than the top surface of the isolation structure 206 , so that a groove 209 is provided between adjacent isolation structures 206 ;

[0077] A semiconductor channel layer 210 located on the top surface of the active area 201 and in the groove 209, wherein the top surface of the semiconductor channel layer 210 is flush with the top surface of the isolation structure 206, and the semiconductor channel layer 210 is used to improve the carrier mobility of the transistor;

[0078] A first gate oxide layer 215 is located on the surface of the semiconductor channel layer 210 .

[0079] In some embodiments, the semiconductor substrate 200 includes a first transistor region 11 and a second transistor region 12; the top surface of the active area 201 of the first transistor region 11 is lower than the top surface of the active area 202 of the second transistor region 12; the top surface of the active area 202 of the second transistor region 12 has a second gate oxide layer 212, and the thickness of the first gate oxide layer 215 is less than the thickness of the second gate oxide layer 212.

[0080] In some embodiments, the semiconductor substrate 200 is made of silicon, and the semiconductor channel layer 210 is made of silicon germanium.

[0081] In some embodiments, the depth of the groove 209 is 5-10 nm, and the thickness of the semiconductor channel layer 210 is 5-10 nm.

[0082] In some embodiments, the present invention further includes: a first gate electrode (not shown in the figure) located on the surface of the first gate oxide layer 215 ; and a second gate electrode (not shown in the figure) located on the surface of the second gate oxide layer 212 .

[0083] The material of the first gate electrode and the second gate electrode is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0084] In some embodiments, the invention further includes: a first work function layer located between the first gate oxide layer 215 and the first gate electrode; and a second work function layer located between the second gate oxide layer 212 and the second gate electrode.

[0085] The first work function layer is used to adjust the work function of the transistor formed in the first transistor region 11 . The second work function layer is used to adjust the work function of the transistor formed in the second transistor region 12 .

[0086] The materials of the first work function layer and the second work function layer may be the same or different.

[0087] In some embodiments, the material of the first work function layer or the second work function layer includes titanium, tantalum, titanium nitride, tantalum nitride, cobalt, titanium aluminum nitride, titanium aluminum cobalt, ruthenium, copper manganese, titanium aluminum nitride, titanium aluminum or lanthanum.

[0088] It should be noted that the terms "including" and "having" and their variations involved in the present disclosure are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present disclosure. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to (or referenced) with each other.

[0089] Although the present disclosure has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present disclosure. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present disclosure by using the methods and technical contents disclosed above without departing from the spirit and scope of the present disclosure. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure shall fall within the protection scope of the technical solution of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein a plurality of trenches are formed in the semiconductor substrate, active regions are formed between the trenches, and isolation structures are formed in the trenches; Etching back to remove a portion of the thickness of the active area to form a groove between adjacent isolation structures; forming a semiconductor channel layer in the groove, wherein the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used to improve the carrier mobility of the transistor; A portion of the semiconductor channel layer is oxidized to form a first gate oxide layer on a surface of the semiconductor channel layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the semiconductor substrate is silicon, and the material of the semiconductor channel layer is silicon germanium.

3. The method for forming a semiconductor structure according to claim 1 or 2, wherein: The semiconductor substrate includes a first transistor region and a second transistor region; The active area of ​​the first transistor region is partially etched back to remove the active area to form the groove; after forming the semiconductor channel layer, a protective layer is formed on the surface of the semiconductor channel layer and the isolation structure of the first transistor region; after forming the protective layer, a second gate oxide layer is formed on the surface of the active area of ​​the second transistor region; the protective layer is removed to form a first gate oxide layer on the surface of the semiconductor channel layer, wherein the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The first gate oxide layer and the second gate oxide layer are formed by an in-situ water vapor oxidation process. While the first gate oxide layer is formed, the active area of ​​the second transistor region is continuously oxidized to increase the thickness of the second gate oxide layer.

5. The method for forming a semiconductor structure according to claim 3, wherein: The depth of the groove is 5-10 nm, and the thickness of the semiconductor channel layer is 5-10 nm.

6. The method for forming a semiconductor structure according to claim 3, wherein: When etching back to remove a portion of the thickness of the active area, the etching gas used is HCl, the flow rate of the etching gas is 20-100 sccm, and the temperature of the chamber is 680-800 degrees Celsius.

7. The method for forming a semiconductor structure according to claim 6, wherein: The semiconductor channel layer is formed by a selective epitaxial process.

8. The method for forming a semiconductor structure according to claim 7, wherein: The selective epitaxial process uses SiH4 as the silicon source gas with a flow rate of 40-80sccm, GeH4 as the germanium source gas with a flow rate of 20-50sccm, and a chamber temperature of 550-700 degrees Celsius. It also includes HCl as the selective gas with a flow rate of 30-70sccm.

9. The method for forming a semiconductor structure according to claim 3, wherein: The material of the protective layer is silicon oxide; the protective layer is formed by an atomic layer deposition process; and the protective layer is removed by an isotropic wet etching process.

10. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a plurality of trenches, active regions are formed between the trenches, and the trenches have isolation structures; The top surface of the active region is lower than the top surface of the isolation structure, so that there is a groove between adjacent isolation structures; A semiconductor channel layer located on the top surface of the active region and in the groove, wherein the top surface of the semiconductor channel layer is flush with the top surface of the isolation structure, and the semiconductor channel layer is used to improve the carrier mobility of the transistor; A first gate oxide layer is located on the surface of the semiconductor channel layer.

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