Semiconductor device

Abstract

The invention relates to a semiconductor device. This semiconductor device is provided with a stacked structure in which channel formation region layers CH1, CH2 and gate electrode layers G1, G2, G3 are alternately stacked on a substrate 50. The lowest layer of the stacked structure is occupied by the first gate electrode layer G1. The uppermost layer of the stacked structure is occupied by the Nth (N > = 3) gate electrode layer G3. Each gate electrode layer includes a first end face 11, a second end face 12, a third end face 13, and a fourth end face 14. The first end face 11 and the third end face 13 face each other. The second end face 12 and the fourth end face 14 face each other. First end surfaces 11 of the odd-numbered gate electrode layers G1, G3 are connected to a first contact part 41. A third end surface 13 of the even gate electrode layer G2 is connected to the second contact portion 42.

Description

[0001] This application is a divisional application with application date of December 26, 2018, application number 201880087237.4, and invention name “Semiconductor Device”, all contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to semiconductor devices, and more particularly, to field effect transistors having nanowire or nanosheet structures. Background Art

[0003] The scaling trend of advanced MOS transistors since 2012 is described. In the 20-nm technology era, the use of bulk planar MOSFETs is dominant. In the 14-nm technology era and beyond, the trend will be toward FETs that fully utilize a fin structure (referred to as "Fin-FET" for convenience of description) or FETs with a fully depleted silicon-on-insulator (FD-SOI) structure (referred to as "FD-SOI-FET" for convenience of description). Although the thickness of the silicon layer (i.e., the thickness of the fin structure in Fin-FET or the thickness of the silicon layer in FD-SOI-FET) that is closely related to the gate length scale is an important factor in the miniaturization of FETs, it is considered that the silicon layer has a technical limit of 5-nm thickness.

[0004] FET having a nanowire structure (referred to as "nanowire FET" for convenience of description) can be considered as a technology for breaking through the limitation on the thickness of the silicon layer forming the channel formation region of the FET as described above (for example, see Japanese Patent Application Publication No. 2015-195405).

[0005] Incidentally, applying a reverse bias voltage to the channel formation region enables the performance to be improved according to the operation of the transistor, thereby reducing the leakage current. Specifically, in one example, +V dd is applied to one of the gate electrodes sandwiching the channel formation region, and +V dd The transistor driving capability can be improved by applying 0 volts to the other of the gate electrodes sandwiching the channel formation region. In addition, in one example, 0 volts is applied to one of the gate electrodes sandwiching the channel formation region, and -V is applied to the other of the gate electrodes sandwiching the channel formation region. dd , so that the leakage current can be reduced in the off state of the transistor.

[0006] Reference List

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2015-195405 Summary of the invention

[0009] Problems to be solved by the present invention

[0010] However, because the gate electrode surrounds the periphery of the channel formation region of the nanowire structure, the nanowire FET disclosed in the above-mentioned patent document 1 fails to apply a reverse bias to the channel formation region. In other words, the nanowire FET disclosed in the above-mentioned patent document 1 cannot reduce leakage current while improving performance according to the operation of the transistor.

[0011] Therefore, the present disclosure is directed to providing a semiconductor device capable of reducing leakage current while improving performance according to an operation of a transistor.

[0012] Solution to the problem

[0013] The semiconductor device of the present disclosure for achieving the above-mentioned object includes:

[0014] a stacked structure having channel formation region layers and gate electrode layers alternately arranged on top of each other on a substrate,

[0015] The lowest layer of the stacked structure is formed with a first layer of a gate electrode layer,

[0016] The top layer of the stacked structure is formed with an Nth (N≥3) layer of a gate electrode layer,

[0017] Each gate electrode layer has a first end surface, a second end surface, a third end surface opposite to the first end surface, and a fourth end surface opposite to the second end surface,

[0018] The first end surfaces of the odd-numbered layers of the gate electrode layer are connected to the first contact portion, and

[0019] The third end surfaces of the even-numbered layers of the gate electrode layer are connected to the second contact portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A , Figure 1B and Figure 1C They are respectively a diagram when the semiconductor device of the first embodiment is viewed from above, a diagram along Figure 1A A schematic cross-sectional view taken along arrow BB in FIG. Figure 1A Schematic cross-sectional view taken along arrow CC in FIG.

[0021] Figure 2A , Figure 2B and Figure 2C are schematic partial plan views of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0022] Figure 3A , Figure 3B and Figure 3C They are Figure 2A , Figure 2B and Figure 2C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0023] Figure 4A , Figure 4B and Figure 4C They are Figure 3A , Figure 3B and Figure 3C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0024] Figure 5A , Figure 5B and Figure 5C They are Figure 4A , Figure 4B and Figure 4C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0025] Fig. 6A , Figure 6B and Figure 6C They are Figure 5A , Figure 5B and Figure 5C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0026] Fig. 7A , Figure 7B and Figure 7C They are Fig. 6A , Figure 6B and Figure 6C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0027] Fig. 8A , Figure 8B and Figure 8C They are Fig. 7A , Figure 7B and Figure 7C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0028] Fig.9A , Fig. 9B and Fig. 9C They are Fig. 8A , Figure 8B and Figure 8C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0029] Fig. 10A , Fig. 10B and Fig. 10C They are Fig.9A , Fig. 9B and Fig. 9C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0030] Fig.11A , Fig. 11B and Fig. 11C They are Fig. 10A , Fig. 10B and Fig. 10C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1AA similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0031] Fig. 12A , Fig. 12B and Fig. 12C They are Fig.11A , Fig. 11B and Fig. 11C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0032] Fig.13A , Fig. 13B and Fig. 13C They are Fig. 12A , Fig. 12B and Fig. 12C Next, for describing the method of manufacturing the semiconductor device according to the first embodiment, a schematic partial plan view of a substrate, etc., along the Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0033] Fig.14A , Fig. 14B and Fig. 14C is a schematic partial end view of a substrate and the like for describing a method of manufacturing the semiconductor device of the second embodiment.

[0034] Fig.15A , Fig. 15B and Fig. 15C yes Fig.14A , Fig. 14B and Fig. 14C Next, there are schematic partial end views of a substrate, etc., each for describing a method of manufacturing the semiconductor device according to the second embodiment.

[0035] Fig.16A , Fig. 16B and Fig. 16C yes Fig.15A , Fig. 15B and Fig. 15C Next, there are schematic partial end views of a substrate, etc., each for describing a method of manufacturing the semiconductor device according to the second embodiment.

[0036] Fig.17A , Fig. 17B and Fig. 17C yes Fig.16A , Fig. 16B and Fig. 16C Next, there are schematic partial end views of a substrate, etc., each for describing a method of manufacturing the semiconductor device according to the second embodiment.

[0037] Fig.18A , Fig.18B and Fig.18C yes Fig.17A , Fig. 17B and Fig. 17C Next, there are schematic partial end views of a substrate, etc., respectively for describing the method of manufacturing the semiconductor device according to the second embodiment.

[0038] Fig.19A , Fig.19B and Fig.19C yes Fig.18A , Fig.18B and Fig.18C Next, there are schematic partial end views of a substrate, etc., each for describing a method of manufacturing the semiconductor device according to the second embodiment.

[0039] Fig. 20 1 is a diagram explaining that by applying a reverse bias voltage to a channel formation region, a reduction in leakage current can be achieved while improving performance according to the operation of a semiconductor device. DETAILED DESCRIPTION

[0040] Hereinafter, the present disclosure will be described based on embodiments with reference to the drawings, but the present disclosure is not limited to the embodiments, and various numerical values ​​and materials in the embodiments are for illustrative purposes. Note that the present description will be made in the following order.

[0041] 1. General Description of the Semiconductor Device of the Present Disclosure

[0042] 2. First Embodiment (Semiconductor Device of the Present Disclosure)

[0043] 3. Second Embodiment (Variation of the First Embodiment)

[0044] 4. Others

[0045] <General Description of Semiconductor Device of the Present Disclosure>

[0046] In the semiconductor device disclosed herein, the channel formation region layer can include a channel structure portion having a nanowire or nanosheet structure. Specifically, the channel structure portion forming a channel formation region layer includes one or more nanowire structures or nanosheet structures. The peripheral portion of the nanowire structure (specifically, the first end face and the third end face described below of each channel formation region layer having a nanowire structure) is covered with an insulating layer. The space between the nanosheet structures is filled with an insulating layer. One or more nanowire structures or nanosheet structures are arranged side by side along the width direction of a channel formation region layer.

[0047] The semiconductor device of the present disclosure includes:

[0048] Each channel formation region layer has a first end face adjacent to the first end face of the gate electrode layer; a second end face adjacent to the second end face of the gate electrode layer; a third end face adjacent to the third end face of the gate electrode layer; and a fourth end face adjacent to the fourth end face of the gate electrode layer,

[0049] The second end surface of each channel formation region layer has a channel structure portion connected to one source / drain region common to the channel formation region layers, and

[0050] The fourth end surface of each channel formation region layer has a channel structure portion connected to another source / drain region shared by the channel formation region layers. Then, in this case,

[0051] The second end surface of each gate electrode layer may be opposite to one of the source / drain regions via the insulating material layer, and

[0052] The fourth end surface of each gate electrode layer may be opposite to the other of the source / drain regions via the insulating material layer.

[0053] In addition, in the semiconductor device of the present disclosure including the above-mentioned various preferred modes, the third end surface of the odd-numbered layers of the gate electrode layer and the first end surface of the even-numbered layers of the gate electrode layer can be covered with an insulating material layer. In addition, the second end surface and the fourth end surface of the gate electrode layer can also be covered with an insulating material layer.

[0054] Furthermore, the semiconductor device of the present disclosure includes:

[0055] In the above-mentioned various preferred modes, the first end surface of the odd-numbered layer of the gate electrode layer may protrude from the first end surface of the channel formation region layer, and

[0056] The third end surface of the even-numbered layers of the gate electrode layer may protrude from the third end surface of the channel formation region layer.

[0057] Furthermore, in the semiconductor device of the present disclosure including the above-described various preferred modes, one of the first contact portion and the second contact portion may be connected to a first wiring (specifically, for example, the wiring is used as a signal line; the same applies to the following description). The other may be connected to a second wiring (specifically, for example, the wiring is used as a power supply line for applying a reverse bias potential such as a reverse reverse bias voltage or a forward reverse bias voltage, or alternatively, the wiring is used as a power supply line V dd or power line V ss The same applies to the following description).

[0058] In the semiconductor device of the present disclosure including the above-mentioned various preferred embodiments (hereinafter, referred to as "the semiconductor device of the present disclosure, etc."), examples of the substrate may include a silicon semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SGOI) substrate. Examples of materials forming the channel structure portion may include Si, SiGe, Ge, and InGaAs. The semiconductor device of the present disclosure, etc. may be an n-channel type or a p-channel type. In the case of adopting the n-channel type, the channel structure may include Si, and in the case of adopting the p-channel type, the channel structure portion may include SiGe. From the viewpoint of obtaining the best work function of each, the determination as to whether the semiconductor device of the present disclosure, etc. is an n-channel type or a p-channel type is performed only by selecting the material forming the gate electrode layer. In the case of using a Si channel structure portion and an n-channel semiconductor device, examples of materials for forming the gate electrode layer may include TiN, TaN, Al, TiAl, and W. On the other hand, in the case of using a SiGe channel structure portion and a p-channel semiconductor device, examples of materials for forming the gate electrode layer may include TiN and W. Examples of a material forming the gate insulating film may include SiO 2 , SiN, and SiON, or may include a high dielectric constant material (so-called high-k material) such as HfO 2 , HfAlON, and Y 2 O 3 ).

[0059] In the nanowire structure, the two ends of the wiring, which in one example has a diameter of 5nm to 10nm and in one example is composed of Si or SiGe, are connected by one and the other of the source / drain regions, or supported by one and the other of the source / drain regions. In addition, in the nanosheet structure, in one example, the two ends of a material having a substantially rectangular cross-sectional shape, which is composed of Si or SiGe and has a width × thickness of (10nm to 50nm) × (5nm to 10nm), are connected by one and the other of the source / drain regions, or supported by one and the other of the source / drain regions. In addition, depending on the thickness and width of the material forming the above structure, it is determined whether to use a nanowire structure or a nanosheet structure. Examples of materials forming the source / drain region may include silicon (Si), SiGe, and Ge. In addition, examples of materials forming the first contact portion and the second contact portion may include silicon (Si), aluminum or aluminum-based alloys (e.g., pure aluminum, Al-Si, Al-Cu, Al-Si-Cu, Al-Ge, Al-Si-Ge), polysilicon, copper, copper alloys, tungsten, tungsten alloys, titanium, titanium alloys (including TiW, TiNW, TiN, and TiAl), WSi2, MoSi2, and TaN. In addition, examples of materials forming the insulating material layer may include SiO-based XMaterials (materials forming silicon-based oxide films); SiN-based materials, including SiON-based materials such as SiN and SiON; SiOC; SiOF and SiCN. X Examples of materials forming the insulating material layer include SiO2, undoped silicate glass (NSG), borophosphosilicate glass (BPSG), PSG, BSG, AsSG, SbSG, PbSG, spin-on glass (SOG), low temperature oxide (LTO, low temperature CVD-SiO2), low melting point glass and glass paste. Alternatively, examples of materials forming the insulating material layer may include inorganic insulating materials such as titanium oxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), magnesium oxide (MgO), chromium oxide (CrO x ), zirconium oxide (ZrO2), niobium oxide (Nb2O5), tin oxide (SnO2) and vanadium oxide (VO x ). Alternatively, examples of materials forming the insulating material layer may include various resins, such as polyimide-based resins, epoxy-based resins or acrylic resins, and low dielectric constant insulating materials, such as SiOCH, organic SOG or fluorine-based resins (for example, materials having a dielectric constant k (=ε / ε0) of, for example, 3.5 or less, specifically, for example, fluorocarbons, cycloperfluorocarbon polymers, benzocyclobutene, cyclic fluororesins, polytetrafluoroethylene, amorphous tetrafluoroethylene, polyarylether, fluorinated arylether, fluorinated polyimide, amorphous carbon, polyparaxylene (polyparaxylene) or fluorinated fullerene). Alternatively, examples of materials forming the insulating material layer may include Silk (a trademark of Dow Chemical Co., a coated low dielectric constant interlayer insulating film material) and Flare (a trademark of Honeywell Electronic Materials Co., a polyallyl ether (PAE)-based material). In addition, these materials may be used alone or in appropriate combinations thereof. The above materials may also be used to form the insulating layer and interlayer insulating layer described later. The insulating material layer, the insulating layer and the interlayer insulating layer may be formed using known methods including various CVD methods, various coating methods, various PVD methods (such as sputtering and vacuum evaporation methods), various printing methods (such as screen printing methods), plating methods, electrodeposition methods, immersion methods and sol-gel methods.

[0060] Note that the SiGe layer can also be obtained by a process of placing a SiGe layer in an upper layer and a Si layer in a lower layer, and performing oxidation so that the upper SiGe layer is SiO 2 and the lower Si layer is a SiGe layer.

[0061] First embodiment

[0062] The first embodiment relates to the semiconductor device (field effect transistor, specifically nanowire FET) of the present disclosure. Figure 1A is a diagram (schematic partial plan view) of the semiconductor device of the first embodiment when the semiconductor device is viewed from above, Figure 1B It is along Figure 1A A schematic cross-sectional view taken along arrow BB in FIG. Figure 1C is along Figure 1A Schematic cross-sectional view taken along arrow CC in FIG.

[0063] The semiconductor device of the first embodiment or the second embodiment described later includes:

[0064] A stacked structure having channel formation region layers CH1 and CH2 and gate electrode layers G1, G2, and G3 alternately arranged on top of each other on a substrate 50,

[0065] The lowest layer of the stacked structure is formed with a first gate electrode layer G1.

[0066] The top layer of the stacked structure is formed with an Nth (N≥3) gate electrode layer G3.

[0067] The gate electrode layers G1, G2 and G3 respectively have a first end face 11, a second end face 12, a third end face 13 opposite to the first end face 11, and a fourth end face 14 opposite to the second end face 12.

[0068] The first end surfaces 11 of the odd-numbered layers G1 and G3 of the gate electrode layer are connected to the first contact portion 41, and

[0069] The third end surface 13 of the even-numbered layer G2 of the gate electrode layer is connected to the second contact portion 42 .

[0070] Then, in the semiconductor device according to the first embodiment or the second embodiment described later, each of the channel formation region layers CH1 and CH2 includes a channel structure portion 25 having a nanowire structure or a nanosheet structure (a nanosheet structure in the first embodiment). Specifically, in the first embodiment, the channel structure portion 25 forming one channel formation region layer includes a plurality of (specifically, two) nanosheet structures. The peripheral portion of the nanosheet structure (specifically, the first end face 21 and the third end face 23 of each channel formation region layer CH1 and CH2 described below) is covered with insulating layers 27 and 28. The space between the nanosheet structures is filled with insulating layers 27 and 28.

[0071] In addition, the semiconductor device of the first embodiment or the second embodiment described later includes channel formation region layers CH1 and CH2, each having a first end face 21 adjacent to the first end face 11 of the gate electrode layers G1, G2, and G3; and a second end face 22 adjacent to the second end face 12 of the gate electrode layers G1, G2, and G3; a third end face 23 adjacent to the third end face 13 of the gate electrode layers G1, G2, and G3; and a fourth end face 24 adjacent to the fourth end face 14 of the gate electrode layers G1, G2, and G3. The second end face 22 of each of the channel formation region layers CH1 and CH2 has a channel structure portion 25, which is connected to (specifically, via an extension portion 20 of the channel structure portion 25) 11 and 20 12 ) and the channel formation region layers CH1 and CH2 share one source / drain region 31, and the fourth end face 24 of each of the channel formation region layers CH1 and CH2 has a channel structure portion 25 connected to (specifically, connected to) the extension portion 20 of the channel structure portion 25. 21 and 20 22 ) another source / drain region 32 shared with the channel formation region layers CH1 and CH2. In addition, the second end face 12 of each of the gate electrode layers G1, G2 and G3 is opposite to the one source / drain region 31 via the insulating material layers 61, 62 and 63 corresponding to one gate sidewall, and the fourth end face 14 of each of the gate electrode layers G1, G2 and G3 is opposite to the other source / drain region 32 via the insulating material layers 61, 62 and 63 corresponding to one gate sidewall.

[0072] In addition, the third end faces 13 of the odd-numbered gate electrode layers G1 and G3, the first end face 11 of the even-numbered gate electrode layer G2, and the first end faces 21 and the third end faces 23 of the channel formation region layers CH1 and CH2 are covered with the insulating material layers 61, 62 and 63 and the insulating layers 27 and 28. In addition, the second end faces 12 and the fourth end faces 14 of the gate electrode layers G1, G2 and G3 are also covered with the insulating material layers 61, 62 and 63.

[0073] Here, the first end faces 11 of the odd-numbered gate electrode layers G1 and G3 protrude from the first end faces 21 of the channel formation region layers CH1 and CH2 (this portion is indicated by the protrusion 15). The third end face 13 of the even-numbered gate electrode layer G2 protrudes from the third end faces 23 of the channel formation region layers CH1 and CH2 (this portion is indicated by the protrusion 16). One 41 of the first contact portion 41 and the second contact portion 42 is connected to a first wiring (specifically, for example, a wiring used as a signal line). The other 42 is connected to a second wiring (specifically, for example, a wiring used as a reverse bias potential power supply line).

[0074] The substrate 50 includes a silicon semiconductor substrate, and the channel structure portion 25 includes silicon (Si). The semiconductor device according to the first embodiment or the semiconductor device according to the second embodiment described later is an n-channel type. Examples of materials forming the gate electrode layers G1, G2 and G3 may include TiN, TaN, Al, TiAl and W. The gate insulating film 26 includes SiO2; SiN; SiON; a high dielectric constant material (so-called high-k material) such as HfO2, HfAlON, Y2O3. The source / drain regions 31 and 32 include silicon. The first contact portion 41 and the second contact portion 42 include, for example, TiN, TaN, Al, TiAl and W. The insulating layers 27, 28 and the insulating material layers 61, 62, 63 include SiO2, SiN, or SiON.

[0075] In the following, reference will be made to Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig.9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B and Fig. 13C A method of manufacturing the semiconductor device according to the first embodiment will be explained. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A and Fig.13A is a schematic partial plan view of a substrate, etc., Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B and Fig. 13B It is along Figure 1A A similar schematic partial cross-sectional view taken along arrow BB in FIG. Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C and Fig. 13C It is along Figure 1A A similar schematic partial cross-sectional view taken along arrow CC in FIG.

[0076] [Craftsmanship - 100]

[0077] On the substrate 50 including the silicon semiconductor substrate, an element isolation region (not shown) is first formed. Then, a gate electrode layer G1 is formed in the region of the substrate 50 where the active region is to be formed using sputtering, photolithography, and etching techniques. Subsequently, an insulating material layer 61 is formed on the region of the substrate 50 where the gate electrode layer G1 is removed using a CVD method, and the insulating material layer 61 is planarized. Thus, it is possible to obtain Figure 2A , Figure 2B , Figure 2C The structure shown.

[0078] In addition, in the following description of the method for manufacturing the semiconductor device according to the first embodiment, the terms of gate electrode layers G1, G2, and G3 are used. However, in [Process-100] to [Process-180], in fact, a conductive material layer is formed before being used as the gate electrode layers G1, G2, and G3, and these conductive material layers are also preferably referred to as "gate electrode forming layers", but the terms of gate electrode layers G1, G2, and G3 are used for simplification of description.

[0079] [Craft-110]

[0080] Then, a silicon layer 201 having a lower gate insulating film 26 formed thereon is provided on the gate electrode layer G1 and the insulating material layer 61 using a smart cut method. Figure 3A , Figure 3B , Figure 3C The structure shown.

[0081] [Craft-120]

[0082] Subsequently, a channel structure 25 and an insulating layer 27 are formed in the silicon layer 201 to obtain a channel formation region layer CH1. Specifically, unnecessary regions of the silicon layer 201 are removed using photolithography and etching techniques, an insulating layer 27 is formed on the exposed surface using a CVD method, and the insulating layer 27 is planarized. Thus, a channel formation region layer CH1 can be obtained. Figure 4A , Figure 4B and Figure 4C In addition, the silicon layer 201 located between the nanosheet structures is also removed, and the insulating layer 27 is filled in the region where the silicon layer 201 is removed. The silicon layer 201 located on both sides of the region filled with the insulating layer 27 corresponds to the channel formation region layer CH1 (channel structure portion 25).

[0083] [Craft-130]

[0084] Subsequently, an upper gate insulating film 26 (see FIG. 1 ) is formed on the entire surface including the upper surface of the channel formation region layer CH1 using sputtering, photolithography, and etching techniques. Figure 5A , Figure 5B , Figure 5C ), and further a gate electrode layer G2 is formed thereon. Subsequently, an insulating material layer 62 is formed on the region where the gate electrode layer G2 is removed by a CVD method, and the insulating material layer 62 is planarized. Thus, it is possible to obtain Fig. 6A , Figure 6B , Figure 6C The structure shown.

[0085] [Craft-140]

[0086] Then, a silicon layer 202 having a lower gate insulating film 26 formed in advance is provided on the gate electrode layer G2 and the insulating material layer 62 using a smart cut method. Fig. 7A , Figure 7B , Figure 7C The structure shown.

[0087] [Crafts-150]

[0088] Subsequently, a channel structure 25 and an insulating layer 28 are formed in the silicon layer 202 to obtain a channel formation region layer CH2. Specifically, unnecessary regions of the silicon layer 202 are removed using photolithography and etching techniques, an insulating layer 28 is formed on the exposed surface using a CVD method, and the insulating layer 28 is planarized. Thus, it is possible to obtain Fig. 8A , Figure 8B , Figure 8CIn addition, the silicon layer 202 located between the nanosheet structures is also removed, and the insulating layer 28 is filled in the region where the silicon layer 202 is removed. The silicon layer 202 located on both sides of the region filled with the insulating layer 28 corresponds to the channel formation region layer CH2 (channel structure portion 25).

[0089] [Craft-160]

[0090] Subsequently, an upper gate insulating film 26 (see FIG. 1 ) is formed on the entire surface including the upper surface of the channel formation region layer CH2 using sputtering, photolithography, and etching techniques. Fig.9A , Fig. 9B and Fig. 9C ), and further a gate electrode layer G3 is formed thereon. Subsequently, an insulating material layer 63 is formed on the region where the gate electrode layer G3 is removed by a CVD method, and the insulating material layer 63 is planarized. Thus, it is possible to obtain Fig. 10A , Fig. 10B , Fig. 10C The structure shown.

[0091] [Craft-170]

[0092] Subsequently, source / drain regions 31 and 32 are formed. Specifically, a resist layer is formed on the gate electrode layer G3 and the like to cover the desired region. Then, the insulating material layer 63, the silicon layer 202, the insulating material layer 62, the silicon layer 201, and the insulating material layer 61 are etched using the resist layer as an etching mask, and then the resist layer is removed. Thus, it is possible to obtain Fig.11A , Fig. 11B , Fig. 11C The extension portion 20 of the channel structure portion 25 11 and 20 12 The extension portion 20 of the channel structure portion 25 remains on the second end surface 22 of the corresponding channel formation region layers CH1 and CH2. 21 and 20 22 The fourth end faces 24 of the corresponding channel formation region layers CH1 and CH2 are left. Then, a mask layer 71 is formed to surround the region of the substrate 50 where the source / drain regions 31 and 32 are to be formed, and the source / drain regions 31 and 32 containing silicon are formed on the exposed substrate 50 using an epitaxial growth method. Thus, it is possible to obtain Fig. 12A , Fig. 12B , Fig. 12C The structure shown.

[0093] [Craft-180]

[0094] Then, the mask layer 71 is removed. Using a known method, a first contact portion 41 connected to the first end surface 11 of the odd-numbered gate electrode layers G1 and G3 and a second contact portion 42 connected to the third end surface 13 of the even-numbered gate electrode layer G2 are formed. Fig.13A, Fig. 13B , Fig. 13C as well as Figure 1A , Figure 1B , Figure 1C The structure shown.

[0095] [Craft-190]

[0096] Subsequently, an interlayer insulating layer (not shown) is formed on the entire surface. An opening is formed in the interlayer insulating layer located above the first contact portion 41, the second contact portion 42, and the source / drain regions 31 and 32. The connection holes and wirings connected to the source / drain regions 31 and 32, and the connection holes, first wirings, and second wirings connected to the first contact portion 41 and the second contact portion 42 only need to be formed on the interlayer insulating layer from the inside of the opening.

[0097] The semiconductor device according to the first embodiment has a stacked structure in which channel formation region layers and gate electrode layers are alternately stacked. The first end surface of the odd-numbered gate electrode layer is connected to the first contact portion, and the third end surface of the even-numbered gate electrode layer is connected to the second contact portion. Thus, different voltages can be applied to the odd-numbered gate electrode layer and the even-numbered gate electrode layer, that is, a reverse bias voltage different from the gate potential can be applied. This makes it possible to reduce leakage current while improving performance according to the operation of the semiconductor device. Specifically, it can be expected that the standby current is reduced by 50% and the maximum frequency is increased by 30%.

[0098] Fig. 20 Schematically shows the potential V applied to the gate electrode layer gs The current I flowing through the channel formation region ds In one example, the first contact portion 41 is connected to a first wiring (specifically, for example, a wiring used as a signal line), and the second contact portion 42 is connected to a second wiring (specifically, a wiring used as a reverse bias potential power line). In one example, when 0V to V dd V is applied to the first wiring and V dd V (or, for example, fixed at 2V dd ) is fixedly applied to the second wiring. gs -I ds The curve, denoted as "A", shows that the performance of the semiconductor device can be improved according to the operation. On the other hand, when 0V to V dd V is applied to the first wiring and -V dd (Or, for example, fixed at -2V dd ) is fixedly applied to the second wiring. gs -I ds curve, indicated as "B". In addition, in the semiconductor device of the present technology having a structure in which a reverse bias is not applied, the potential V gsand current I ds The relationship between is schematically represented as "C".

[0099] In the case where the wiring length of the signal line of the logic circuit is short and a gate electrode layer connected to the signal line is formed above and below the channel formation region layer, the transmission destination of the heat generated in the channel formation region layer is generally limited. Therefore, the desired heat dissipation effect cannot be achieved. On the other hand, in the semiconductor device according to the first embodiment, one of the gate electrode layers formed above and below the channel formation region layer is connected to a wiring having a very long wiring length and used to apply a reverse bias (second wiring). Therefore, the heat generated in the channel formation region layer can be effectively dissipated, so that the self-heating effect is weakened and the performance degradation is minimized. The degree of degradation caused by the self-heating effect depends on many factors and is therefore difficult to determine unconditionally. However, in the case of the semiconductor device of the present technology, it is fully conceivable that about 20% of performance degradation occurs. In other words, in the semiconductor device according to the first embodiment, it is believed that the effect of reduced performance degradation of about 20% due to the self-heating effect can be obtained.

[0100] Second embodiment

[0101] The second embodiment is a modification of the first embodiment, and the channel formation region layers CH1 and CH2 include a channel structure portion 25 having a nanowire structure. In the second embodiment, the channel structure portion 25 forming one channel formation region layer includes a plurality of (specifically, three) nanowire structures.

[0102] Except that the channel structure portion 25 has a nanowire structure, the configuration and structure of the semiconductor device according to the second embodiment can be substantially similar to the configuration and structure of the semiconductor device according to the first embodiment, so a detailed description thereof is omitted. In addition, in the semiconductor device according to the second embodiment, it is not necessary to form the insulating layers 27 and 28.

[0103] In the following, reference will be made to Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B and Fig.19C 1 is a schematic partial end view to explain a method of manufacturing a semiconductor device according to a second embodiment. Note that Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A It is along Fig. 14C A schematic partial end view taken along arrow AA in FIG. Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B It is along Fig. 14C A schematic partial end view taken along arrow BB in FIG. Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C It is along Fig.14A The arrows CC and Fig. 14B Schematic partial end view taken along arrow CC in FIG.

[0104] [Craftsmanship - 200]

[0105] First, processes similar to [Process- 100 ] and [Process- 110 ] of the first embodiment are performed.

[0106] [Craft-210]

[0107] Subsequently, a resist layer 81 is provided which covers both ends of the channel formation region layer CH1 and covers a portion of the silicon layer 201 where a nanowire structure is to be formed in the channel formation region layer CH1 to obtain a channel formation region layer CH1 (see Fig.14A , Fig. 14B and Fig. 14C Then, after etching the silicon layer 201 using the resist layer 81 as an etching mask (see Fig.15A , Fig. 15B and Fig. 15C ), remove the resist layer 81 (see Fig.16A , Fig. 16B and Fig. 16C ). Therefore, a silicon layer 201 located in a region where source / drain regions are to be formed may be provided on the insulating material layer 61, and a silicon layer 201 for forming a nanowire structure may be formed on the gate electrode layer G1.

[0108] [Craft-220]

[0109] Subsequently, a portion 26A (including SiON) of a gate insulating film is formed by performing thermal oxidation on the silicon layer 201 having the nanowire structure (see Fig.17A , Fig. 17B , Fig. 17C ). Thermal oxidation allows the cross-sectional shape of the silicon layer 201 having the nanowire structure to be substantially semicircular. Then, the remaining portion 26B of the gate insulating film including HfO2 is formed on the portion 26A of the gate insulating film including SiON using atomic layer deposition (ALD) (see Fig.18A , Fig.18B , Fig. 18C ). Thus, a layer of nanowire structure can be obtained.

[0110] [Craft-230]

[0111] Subsequently, a gate electrode layer G2 is formed in the region of the substrate 50 where the active region is to be formed using sputtering, photolithography, and etching techniques. Then, an insulating material layer 62 is formed on the region where the gate electrode layer G2 is removed using CVD technology, and the insulating material layer 62 is planarized. Thus, it is possible to obtain Fig.19A , Fig.19B , Fig.19C In addition, the description of the following [Process-240] to [Process-260] is omitted.

[0112] [Craft-240]

[0113] Then, the silicon layer 202 having the lower gate insulating film 26 formed in advance is disposed on the gate electrode layer G2 and the insulating material layer 62 using a smart cut method. Then, the second layer of the nanowire structure is obtained by performing [Process-210] to [Process-230].

[0114] [Crafts-250]

[0115] Subsequently, a gate electrode layer G3 is formed in a region of the substrate 50 where an active region is to be formed using sputtering, photolithography, and etching techniques. Then, an insulating material layer 63 is formed on the region where the gate electrode layer G3 is removed using CVD techniques and is planarized.

[0116] [Craft-260]

[0117] Then, the semiconductor device of the second embodiment can be obtained by performing processes similar to [process- 170 ] to [process- 190 ] of the first embodiment.

[0118] Although the present disclosure is described above based on the preferred embodiment, the configuration and structure of the semiconductor device described in the embodiment, the material forming the semiconductor device, and the method for manufacturing the semiconductor device are merely examples and can be appropriately modified. In addition, the process sequence in the method for manufacturing a semiconductor device according to the embodiment can be appropriately modified as needed. In the embodiment, only the channel structure portion having a nanosheet structure is described, but the channel structure portion can be a nanowire structure. In addition, in the first embodiment, an n-channel semiconductor device can be used, and a p-channel semiconductor device can also be used. In this case, it is only necessary to appropriately modify the material forming the semiconductor device. An SOI substrate can be used instead of a silicon semiconductor substrate as a substrate. In the embodiment, although a stacking structure in which two channel formation region layers and three gate electrode layers are alternately stacked is described, the stacking structure is not limited to such a structure. Such a structure can be adopted in which a channel formation region layer having (N-1) layers (where N=3, 4, 5, ...) and an N-layer gate electrode layer are alternately stacked. A second wiring can be provided for each semiconductor device, or a second wiring can be provided for each of a plurality of semiconductor devices. In other words, the second wiring can be shared by a plurality of semiconductor devices. Such a structure makes it possible to further increase the heat dissipation area and thus further increase the heat dissipation through the second wiring, thereby reducing the self-heating effect.

[0119] The embodiment describes that the odd-numbered gate electrode layer (first gate electrode layer) is connected to the first wiring, and the even-numbered gate electrode layer (second gate electrode layer) is connected to the second wiring. On the other hand, a configuration can be formed in which the odd-numbered gate electrode layer (first gate electrode layer) is connected to the second wiring, and the even-numbered gate electrode layer (second gate electrode layer) is connected to the first wiring.

[0120] In addition, in [Craft-170], after obtaining Fig.11A , Fig. 11B and Fig. 11C After the structure shown in the figure, the insulating material layer 63 and the extension portion 20 of the channel structure portion 25 can be 21 and 20 22 , the insulating material layer 62 and the extension portion 20 of the channel structure portion 25 11 and 20 12 Then, the through hole can be filled with a conductive material. Thus, the source / drain regions 31 and 32 can be formed.

[0121] Note that the present disclosure may also include the following configurations.

[0122] [A01] <<Semiconductor Device>>

[0123] A semiconductor device comprising:

[0124] A stacked structure having channel formation region layers and gate electrode layers alternately arranged on top of each other on a substrate,

[0125] The lowest layer of the stacked structure forms the first gate electrode layer.

[0126] The top layer of the stacked structure forms the Nth (N≥3) gate electrode layer.

[0127] Each gate electrode layer has a first end surface, a second end surface, a third end surface opposite to the first end surface, and a fourth end surface opposite to the second end surface,

[0128] The first end surfaces of the odd-numbered layers of the gate electrode layer are connected to the first contact portion, and

[0129] The third end surfaces of the even-numbered layers of the gate electrode layer are connected to the second contact portion.

[0130] [A02] The semiconductor device according to [A01], wherein the channel formation region layer includes a channel structure portion having a nanosheet structure or a nanowire structure.

[0131] [A03] The semiconductor device according to [A01] or [A02], wherein each channel formation region layer has a first end face adjacent to the first end face of the gate electrode layer, a second end face adjacent to the second end face of the gate electrode layer, a third end face adjacent to the third end face of the gate electrode layer, and a fourth end face adjacent to the fourth end face of the gate electrode layer,

[0132] The second end surface of each channel formation region layer has a channel structure portion connected to one of the source / drain regions common to the channel formation region layers, and

[0133] The fourth end surface of each channel formation region layer has a channel structure portion connected to the other of the source / drain regions common to the channel formation region layers.

[0134] [A04] The semiconductor device according to [A03], wherein the second end face of each gate electrode layer is opposed to one of the source / drain regions via the first insulating film, and

[0135] The fourth end face of each gate electrode layer is opposed to the other of the source / drain regions via the second insulating film.

[0136] [A05] A semiconductor device according to any one of [A01] to [A04], wherein the third end faces of the odd-numbered layers of the gate electrode layer, the first end faces of the even-numbered layers of the gate electrode layer, and the first end faces and the third end faces of each channel formation region layer are covered with an insulating material layer.

[0137] [A06] The semiconductor device according to any one of [A01] to [A05], wherein a first end surface of the odd-numbered layer of the gate electrode layer protrudes from a first end surface of the channel formation region layer, and

[0138] The third end faces of the even-numbered layers of the gate electrode layer protrude from the third end face of the channel formation region layer.

[0139] [A07] The semiconductor device according to any one of [A01] to [A06], wherein one of the first contact portion and the second contact portion is connected to the first wiring, and the other is connected to the second wiring.

[0140] Reference Symbols List

[0141] 11, 12, 13, 14 End surface of gate electrode layer

[0142] 15, 16 The protrusion from the end surface of the gate electrode layer

[0143] 201, 202 Silicon layer

[0144] 20 11 , 20 12 , 20 21 , 20 22 Extension portion of channel formation region layer

[0145] 21, 22, 23, 24 End surface of the channel formation region layer

[0146] 25 Channel structure

[0147] 26 Gate insulating film

[0148] 26A Gate insulating film portion

[0149] 27, 28 insulation layer

[0150] 31, 32 source / drain region

[0151] 41 First contact part

[0152] 42 Second contact part

[0153] 50 substrates

[0154] 61, 62, 63 insulation material layer

[0155] 71 Mask layer

[0156] 81 Resist layer

[0157] 82 Anti-corrosion layer

[0158] CH1, CH2 channel formation layer

[0159] G1, G2, G3 gate electrode layers.

Claims

1. A semiconductor device comprising: A stacked structure having a channel formation region layer and a gate electrode layer alternately arranged on top of each other on a substrate, Wherein, the lowest layer of the stacked structure forms the first gate electrode layer, The top layer of the stacked structure forms the Nth gate electrode layer, where N≥3. Each of the gate electrode layers has a first end face, a second end face, a third end face opposite to the first end face, and a fourth end face opposite to the second end face, The second end surface and the fourth end surface of each gate electrode layer are opposite to one of the source / drain regions shared by the stacked structure via an insulating material layer. The first end surfaces of the gate electrode layers of the odd-numbered layers are connected to the first contact portion, and the third end surfaces of the gate electrode layers of the even-numbered layers are connected to the second contact portion; Each of the channel formation region layers includes a channel structure portion, and each of the channel structure portions includes an extension portion, which is connected to one of the source / drain regions, and the extension portion is arranged on each end of the channel structure portion so that the extension portion is positioned between the insulating material layers.

2. The semiconductor device according to claim 1, wherein The channel structure portion has a nanosheet structure or a nanowire structure.

3. The semiconductor device according to claim 1, wherein Each of the channel formation region layers has a first end face adjacent to the first end face of the gate electrode layer, a second end face adjacent to the second end face of the gate electrode layer, a third end face adjacent to the third end face of the gate electrode layer, and a fourth end face adjacent to the fourth end face of the gate electrode layer, The second end surface of each of the channel formation region layers has a channel structure portion connected to one of the source / drain regions common to the channel formation region layers, and The fourth end surface of each of the channel formation region layers has a channel structure portion connected to the other of the source / drain regions common to the channel formation region layers.

4. The semiconductor device according to claim 3, wherein: A second end face of each of the gate electrode layers opposes one of the source / drain regions via a first insulating film, and a fourth end face of each of the gate electrode layers opposes the other of the source / drain regions via a second insulating film.

5. The semiconductor device according to claim 1, wherein The third end faces of the gate electrode layers of the odd-numbered layers, the first end faces of the gate electrode layers of the even-numbered layers, and the first end face and the third end face in each of the channel formation region layers are covered with an insulating material layer.

6. The semiconductor device according to claim 1, wherein The first end surface of the gate electrode layer of the odd-numbered layer protrudes from the first end surface of the channel formation region layer, and The third end faces of the gate electrode layers of the even-numbered layers protrude from the third end faces of the channel formation region layers.

7. The semiconductor device according to claim 1, wherein One of the first contact portion and the second contact portion is connected to a first wiring, and the other of the first contact portion and the second contact portion is connected to a second wiring.

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