Semiconductor device structure and manufacturing method thereof

Abstract

One embodiment of the present disclosure provides a method of manufacturing a semiconductor device structure. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer, and performing an oxide backfill process to form a seamless dielectric material between the second semiconductor layer and the third semiconductor layer. The oxide backfill process includes exposing the second conductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a single layer, and exposing the single layer to an oxygen-containing precursor for a second duration to form a seamless dielectric material, the oxygen-containing precursor having a second flow rate, the second flow rate is about 2 to about 20 times the first flow rate, and the second duration is about 2 to about 20 times the first duration.

Description

Technical Field

[0001] The disclosed embodiments relate to semiconductor technology, and more particularly to a semiconductor device structure with seamless dielectric material and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have led to generations of integrated circuits, each with smaller and more complex circuits than the previous one. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. This miniaturization is also accompanied by more complex designs and processes for incorporating integrated circuits into devices.

[0003] Therefore, there is a need to improve the processing and manufacture of integrated circuits. Summary of the invention

[0004] One embodiment is a method for manufacturing a semiconductor device structure. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer, and performing an oxide refill process to form a seamless dielectric material between the second semiconductor layer and the third semiconductor layer. The oxide refill process includes: exposing the second conductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a monolayer, the silicon-containing precursor having a first flow rate bottom and a chemical structure:

[0005]

[0006] Each R group contains at least two carbons. The oxide backfill process also includes exposing the monolayer to an oxygen-containing precursor for a second duration to form a seamless dielectric material, the oxygen-containing precursor having a second flow rate, the second flow rate being about 2 times to about 20 times the first flow rate, and the second duration being about 2 times to about 20 times the first duration.

[0007] Another embodiment is a method for manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack, the semiconductor layer stack including a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method also includes forming a sacrificial gate stack on a first portion of the fin structure, recessing a second portion of the fin structure, removing a second semiconductor layer disposed below the sacrificial gate stack to form a plurality of openings between vertically adjacent first semiconductor layers, and performing an atomic layer deposition process to form a seamless dielectric material in the openings. The atomic layer deposition process includes performing a plurality of first cycles, each of the first cycles including flowing a first silicon-containing precursor into a process chamber at a first flow rate for a first duration, and flowing a first oxygen-containing precursor into the process chamber at a second flow rate for a second duration, and then performing a plurality of second cycles, each of the second cycles including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the process chamber at a third flow rate for a third duration, and flowing a second oxygen-containing precursor into the process chamber at a fourth flow rate for a fourth duration.

[0008] Another embodiment is a method for manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack, the semiconductor layer stack includes a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method also includes recessing a portion of the fin structure to expose a well portion of the fin structure, removing the second semiconductor layer to form a plurality of openings between vertically adjacent first semiconductor layers, and performing a hybrid atomic layer deposition process to form a seamless dielectric material in the opening. The hybrid atomic layer deposition process includes performing a plasma enhanced atomic layer deposition process at a first temperature, and then performing a thermal atomic layer deposition process at a second temperature, the second temperature being substantially greater than the first temperature. The method also includes forming a source / drain region from the well portion, removing the seamless dielectric material, and forming a gate electrode layer surrounding a plurality of exposed portions of the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following will be described in detail with reference to the accompanying drawings of the specification. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure.

[0010] Figures 1 to 10 is a perspective view illustrating a semiconductor device structure at various manufacturing stages according to some embodiments.

[0011] FIG. 10-1 shows, according to some embodiments, Fig.10 A cross-sectional side view of a portion of a semiconductor device structure.

[0012] FIG. 11A to FIG. 11D According to some embodiments, Fig.10 A cross-sectional side view of a portion of a semiconductor device structure at various stages of a thermal atomic deposition process.

[0013] Fig.12 FIG. 2 shows the chemical structure of a silicon-containing precursor used in a thermal atomic deposition process according to some embodiments.

[0014] Fig.13 2 is a diagram illustrating various states of a compound formed by a thermal atomic deposition process, according to some embodiments.

[0015] Figures 14 to 20 is a perspective view illustrating a semiconductor device structure at various manufacturing stages according to some embodiments.

[0016] FIG. 15-1 shows, according to some embodiments, Fig.15 A cross-sectional side view of a portion of a semiconductor device structure.

[0017] FIG. 15-2 shows, according to some embodiments, Fig.15 A cross-sectional side view of a portion of a semiconductor device structure.

[0018] Description of reference numerals:

[0019] 100: Semiconductor device structure

[0020] 101: Base

[0021] 104: Semiconductor layer stacking

[0022] 106: First semiconductor layer

[0023] 108: Second semiconductor layer

[0024] 110: Oxide layer

[0025] 111: Nitride layer

[0026] 112: Fin structure

[0027] 114: Groove

[0028] 116: Ibe

[0029] 116t: Top surface

[0030] 118: Insulation material

[0031] 120: Quarantine

[0032] 120t: Top surface

[0033] 130: Sacrificial gate structure

[0034] 132: Sacrificial gate dielectric layer

[0035] 134: Sacrificial gate electrode layer

[0036] 135: Oxide layer

[0037] 136: Mask layer

[0038] 137: Nitride layer

[0039] 138: Gate spacer layer

[0040] 140: Gate spacer

[0041] 140a: Part I

[0042] 140b: Part 2

[0043] 141: Opening

[0044] 143: Dielectric Materials

[0045] 143s: Side surface

[0046] 144: Dielectric spacer

[0047] 146: Source / drain region

[0048] 162: Contact Etch Stop Layer

[0049] 163: Interlayer dielectric layer

[0050] 168: Interface layer

[0051] 170: Gate dielectric layer

[0052] 172: Gate electrode layer

[0053] 174: Gate structure

[0054] 200 / 300: Partial

[0055] 202: Single layer

[0056] A / B / C / D / E / F: Status DETAILED DESCRIPTION

[0057] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0058] Furthermore, spatially relative terms such as "below", "beneath", "lower", "above", "above", "upper", "top", "higher" and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0059] Embodiments of the present disclosure provide semiconductor device structures and methods for manufacturing the same. In some embodiments, an oxide refill process such as a thermal horizontal oxide refill (THOR) process is performed to form a seamless dielectric material between vertically adjacent semiconductor layers.

[0060] Although some embodiments described herein are described in the context of nanosheet channel field-effect transistors (FETs), embodiments of some embodiments of the present disclosure may be used in other processes and / or other devices, such as horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. Those skilled in the art will readily appreciate other modifications that may be made within the scope of the present disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the structure, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes to create, for example, a pattern with a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

[0061] Figures 1 to 20 1 is an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that additional embodiments of the method may be Figures 1 to 20 Additional operations are provided before, during, and after the steps shown, and some of the steps described below may be replaced or deleted in additional embodiments of the method. The order of the steps / processes is not limited and may be interchanged.

[0062] Figures 1 to 10 1 is a perspective view of a semiconductor device structure 100 at various stages of fabrication according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed above the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimony (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0063] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, boron for n-type field effect transistors (NFETs) and phosphorus for p-type field effect transistors (PFETs).

[0064] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices such as nanosheet channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon (Si), and the second semiconductor layer 108 may be made of silicon germanium (SiGe). In some examples, the first semiconductor layer 106 may be made of silicon germanium (SiGe), and the second semiconductor layer 108 may be made of silicon (Si). Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or may include other materials, such as germanium (Ge), silicon carbon (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or any combination of the foregoing.

[0065] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the film layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0066] The first semiconductor layer 106 or a portion of the first semiconductor layer 106 may form (multiple) nanosheet channels of the semiconductor device structure 100 at a subsequent manufacturing stage. The term nanostructure is used herein to refer to any material portion having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, this term refers to elongated material portions of circular and substantially circular cross-sections, as well as beam or strip material portions, including, for example, cylindrical or substantially rectangular cross-sections. The (multiple) nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0067] Each first semiconductor layer 106 may have a thickness in a range of about 5 nanometers (nm) to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range of about 2 nm to about 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are alternately arranged, such as Figure 1 This is for illustrative purposes and is not intended to be limiting beyond what is specifically set forth in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of film layers depends on the number of channels of the semiconductor device structure 100. Figure 1As shown, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 may be silicon oxide, and may have a different etching selectivity than the nitride layer 111. The nitride layer 111 may include any appropriate nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 may be a mask structure.

[0068] exist Figure 2 In the embodiment of the present invention, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108, and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (such as an oxide layer 110 and a nitride layer 111) formed on the semiconductor layer stack 104 using multiple patterning operations including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) above the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in the unprotected area through the hard mask layer, the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0069] exist Figure 3In the embodiment, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride carbon (SiOCN), silicon carbon nitride (SiCN), fluorine-doped silicate glass (FSG), a low dielectric constant (K) dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or flowable CVD (FCVD).

[0070] exist Figure 4 In the embodiment of the present invention, the insulating material 118 is recessed to form an isolation region 120. The recessing of the insulating material 118 exposes multiple portions of the fin structure 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 causes a trench 114 to be formed between adjacent fin structures 112. The isolation region 120 can be formed using a suitable dry etching process, a wet etching process, or a combination of the foregoing. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108, which is in contact with the well 116 formed by the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation (STI). In some embodiments, the oxide layer 110 and the nitride layer 111 are also removed during the recessing of the insulating material 118.

[0071] exist Figure 5In the embodiment of the present invention, one or more sacrificial gate structures 130 are formed above the semiconductor device structure 100. The sacrificial gate structure 130 is formed above the first portion of the fin structure 112 and the first portion of the isolation region 120, while exposing the second portion of the fin structure 112 and the second portion of the isolation region 120. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multi-layer structure. For example, the mask layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these film layers into the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a material based on silicon oxide. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor device structure 100.

[0072] exist Figure 6 In the embodiment of the present invention, a gate spacer layer 138 is formed to cover the sacrificial gate structure 130, the second portion of the fin structure 112, and the second portion of the isolation region 120. The gate spacer layer 138 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride (SiCN), silicon oxycarbide, silicon oxycarbon nitride (SiOCN), and / or combinations thereof. In some embodiments, the gate spacer layer 138 is formed by a compliant process, such as an atomic layer deposition (ALD) process. In some embodiments, the thickness of the gate spacer layer 138 is in a range of about 2 nm to about 10 nm.

[0073] exist Figure 7 In the embodiment, an anisotropic etching process is performed to remove the horizontal portion of the gate spacer layer 138. The anisotropic etching process may be a selective etching process that does not substantially affect the nitride layer 137, the first semiconductor layer 106, and the isolation region 120. In this way, the second portion of the fin structure 112 is exposed.

[0074] exist Figure 8In the embodiment of the present invention, one or more etching processes are performed to recess the exposed second portion of the fin structure 112 that is not covered by the sacrificial gate structure 130 (and the portion of the gate spacer layer 138 formed on the sidewall of the sacrificial gate structure 130), and remove the portion of the gate spacer layer 138. The portion of the gate spacer layer 138 formed on the sidewall of the mask layer 136 may also be recessed. The one or more etching processes may include dry etching (such as reactive ion etching (RIE), neutron beam etching (NBE), etc.) and / or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH)). One or more etching processes form a gate spacer 140, the gate spacer 140 including a first portion 140a formed on the sidewall of the sacrificial gate electrode layer 134 and a second portion 140b formed on the second portion of the isolation region 120. In some embodiments, as Figure 8 As shown, the one or more etching processes also remove a portion of the second portion of the isolation region 120. As a result, the top surface 120t of the second portion of the isolation region 120 is located at a level substantially lower than the top surface 116t of the well 116.

[0075] exist Fig. 9 In some embodiments, the second semiconductor layer 108 includes germanium (Ge), and the subsequently formed source / drain (S / D) regions include phosphorus-doped silicon for n-type FETs. The Ge in the second semiconductor layer 108 and the phosphorus in the S / D regions can inter-diffuse, which can cause a high interfacial state density (Dit) on the first semiconductor layer 106. As a result, the mobility of n-type devices may be reduced. Therefore, in some embodiments, such as Fig. 9 As shown, the second semiconductor layer 108 is removed before forming the S / D region. In some embodiments, the second semiconductor layer 108 is completely removed, and an opening 141 is formed between vertically adjacent first semiconductor layers 106. The second semiconductor layer 108 may be removed by a selective etching process (such as a selective dry etching process, a selective wet etching process, or a combination of the foregoing). The selective etching process does not substantially affect the gate spacer 140, the first semiconductor layer 106, the isolation region 120, and the nitride layer 137.

[0076] exist Fig.10In the embodiment of the present invention, a dielectric material 143 is formed in the opening 141 and on the exposed surface of the semiconductor device structure 100. In some embodiments, the dielectric material 143 is an oxide such as silicon dioxide formed by a thermal horizontal oxide refill (THOR) process. In some embodiments, the THOR process is a thermal atomic layer deposition (thermal ALD) process.

[0077] FIG. 10-1 shows, according to some embodiments, Fig.10 10-1, the dielectric material 143 is not only formed in the opening 141, but also formed on the sidewalls of the sacrificial gate structure 130. In some embodiments, the gate spacer 140 includes two dielectric layers.

[0078] FIG. 11A to FIG. 11D According to some embodiments, Fig.10 1 is a cross-sectional side view of a portion 200 of the semiconductor device structure 100 at various stages of a thermal atomic deposition process for forming a dielectric material 143. The portion 200 includes a vertically adjacent first semiconductor layer 106, and Fig.11A FIG. 11D to FIG. 11D illustrate an ALD process for seamlessly forming a dielectric material 143 between vertically adjacent first semiconductor layers 106. For clarity, FIG. 11A to FIG. 11D The dielectric material 143 formed on the side surface of the first semiconductor layer 106 is omitted. Fig.11A As shown, a single layer 202 is formed on the exposed surface of the first semiconductor layer 106. In some embodiments, the single layer 202 is formed by exposing the first semiconductor layer 106 to a silicon-containing precursor at a process temperature ranging from about 200 degrees Celsius to about 500 degrees Celsius (such as 250 degrees Celsius to about 400 degrees Celsius). The silicon-containing precursor may include any suitable silicon-containing material. In some embodiments, the silicon-containing precursor includes a Fig.12 Materials with the chemical structures shown. Fig.12 As shown, the silicon-containing precursor includes two R groups and two hydrogen atoms connected to the silicon atom. In some embodiments, each R group contains at least two carbons. The silicon-containing precursor can have a symmetrical chemical structure. For example, Fig.12 The appearance of the molecule shown does not change by rotating the molecule about line AA (the axis of symmetry passing through the silicon atoms). Fig.12 The silicon-containing precursor shown may also form a peroxy linkage (POL) in the dielectric material 143 . A peroxy linkage is a bond between two oxygen atoms.

[0079] Return to reference Fig.11A , a silicon-containing precursor may flow into a processing chamber in which the semiconductor device structure 100 is disposed, the silicon-containing precursor having a first flow rate and a first duration. Next, the flow of the silicon-containing precursor is stopped and a pumping process is performed to pump out any silicon-containing precursor in the processing chamber. After the pumping process, an oxygen-containing precursor flows into the processing chamber, and the oxygen-containing precursor reacts with the monolayer 202 to form the dielectric material 143, as shown in FIG. Fig. 11B As shown. The process temperature during the flow of the oxygen-containing precursor may be the same as the process temperature during the flow of the silicon-containing precursor. In some embodiments, the process temperature is in the range of about 200 degrees Celsius to about 500 degrees Celsius, such as about 250 degrees Celsius to about 400 degrees Celsius. The oxygen-containing precursor may include any suitable oxygen-containing material. In some embodiments, the oxygen-containing precursor includes ozone. The oxygen-containing precursor may flow into the process chamber at a second flow rate, and the second flow rate is substantially greater than the first flow rate of the silicon-containing precursor. In some embodiments, the second flow rate may be 2 to 20 times the first flow rate, such as about 5 times to about 10 times, or about 10 times to about 20 times. The oxygen-containing precursor may flow into the process chamber for a second duration, and the second duration is substantially longer than the first duration of the silicon-containing precursor. In some embodiments, the second duration may be 2 to 20 times the first duration, such as about 5 times to about 10 times, or about 10 times to about 20 times. In some embodiments, the second flow rate is about 5 to about 10 times greater than the first flow rate, and the second duration is about 5 to about 10 times greater than the first duration.

[0080] Fig.13 1 is a diagram showing various states of a compound formed by a thermal atomic deposition process according to some embodiments. Fig.13 As shown, through Fig.11A as well as Fig. 11B The dielectric material 143 formed by the process described in the above has states A, B, C, D, and E. In state A, a peroxy linkage (POL) is formed. Fig.1210. The POL is formed in state A by a silicon-containing precursor of the chemical structure shown and ozone as an oxygen-containing precursor. If the process temperature of the thermal ALD process is greater than about 500 degrees Celsius, or if the deposition process is a plasma ALD process, reduction may occur, which changes the dielectric material 143 from state A to state C. As described above, in some embodiments, the flow rate of the oxygen-containing precursor is about 2 times to about 20 times, such as about 10 times to about 20 times, the flow rate of the silicon-containing precursor. In some embodiments, the duration of exposure of the semiconductor device structure 100 to the oxygen-containing precursor is about 2 times to about 20 times, such as about 10 times to about 20 times, the duration of exposure of the semiconductor device structure 100 to the silicon-containing precursor. In some embodiments, the flow rate of the oxygen-containing precursor is about 5 times to about 10 times the flow rate of the silicon-containing precursor, and the duration of exposure of the semiconductor device structure 100 to the oxygen-containing precursor is about 5 times to about 10 times the duration of exposure of the semiconductor device structure 100 to the silicon-containing precursor. These process conditions favor activation of dielectric material 143 in state A, which results in state E, such as Fig.13 The dielectric material 143 in state E is unstable and is more susceptible to network reorganization, resulting in the dielectric material 143 being in state F, as shown in FIG. Fig.13 The state change from state A to state E and then to state F can produce a seamless dielectric material 143, which is Fig.11D Described in detail in.

[0081] If the flow rate of the oxygen-containing precursor is less than 10 times the flow rate of the silicon-containing precursor, the duration of exposure to the oxygen-containing precursor is less than 10 times the duration of exposure to the silicon-containing precursor, or the combination of the flow rate of the oxygen-containing precursor is less than 5 times the flow rate of the silicon-containing precursor and the duration of exposure to the oxygen-containing precursor is less than 5 times the duration of exposure to the silicon-containing precursor, it is more conducive to the reduction and / or oxygen vacancy recovery of the dielectric material 143 in state A. In this way, the dielectric material 143 can change from state A to state B and / or state D. On the other hand, if the flow rate of the oxygen-containing precursor is greater than 20 times the flow rate of the silicon-containing precursor, the duration of exposure to the oxygen-containing precursor is greater than 20 times the duration of exposure to the silicon-containing precursor, or the combination of the flow rate of the oxygen-containing precursor is greater than 10 times the flow rate of the silicon-containing precursor and the duration of exposure to the oxygen-containing precursor is greater than 10 times the duration of exposure to the silicon-containing precursor, the manufacturing cost increases without obvious advantages. In other words, using Fig.12 The illustrated thermal ALD process with a silicon-containing precursor, ozone as an oxygen-containing precursor, a faster flow rate of the oxygen-containing precursor, and / or a longer duration of exposure to the oxygen-containing precursor, forms a dielectric material 143 having improved horizontal gapfill capability.

[0082] After exposing the semiconductor device structure 100 to the oxygen-containing precursor, the process chamber is again evacuated. The flow of the silicon-containing precursor into the process chamber and the flow of the oxygen-containing precursor into the process chamber (with evacuating the process chamber between the two steps) is considered a cycle of the thermal ALD process. After multiple cycles, the dielectric material 143 fills the openings 141 between the vertically adjacent first semiconductor layers 106, such as Fig. 11C as well as Fig.11D As shown. Fig. 11C As shown, a monolayer 202 is formed on the dielectric material 143, and a gap is formed between the portion of the monolayer 202 formed above the bottom first semiconductor layer 106 and the portion of the monolayer 202 formed below the top first semiconductor layer 106. The gap is very small. In some embodiments, the gap is in a range of about 0.1 nm to about 0.3 nm. In some embodiments, the gap is smaller than the bond length of Si-OO-Si. Next, an oxygen-containing precursor flows into the process chamber and reacts with the monolayer 202 to form the dielectric layer 143. As described above, the process conditions are favorable for the dielectric material 143 to change from state A to state E to state F. Fig.13 As shown, the Si-OO-Si in state A breaks into dangling Si bonds and peroxy radicals, as shown in state E. Since the gaps between the portions of the monolayer 202 are small, the peroxy radicals of the portion of the monolayer 202 formed above the bottom first semiconductor layer 106 can be bonded to the dangling Si bonds of the portion of the monolayer 202 formed below the top first semiconductor layer 106, which changes the dielectric material 143 from state E to state F. In this way, the gaps are filled and the dielectric material 143 seamlessly fills the opening 141. In addition, by FIG. 11A to FIG. 11D The dielectric material 143 formed by the process described in has a wet etch rate greater than about 100 angstroms per minute (using a 1:100 diluted hydrofluoric acid (HF) solution).

[0083] In some embodiments, the thermal ALD process includes a plurality of cycles to form the dielectric material 143. A first number of cycles are performed under a first process condition, and a second number of cycles are performed under a second process condition different from the first process condition. The second process condition may be FIG. 11A to FIG. 11D, and the first process condition may result in rapid deposition and / or use less precursor. For example, the first process condition may include causing the silicon-containing precursor and the oxygen-containing precursor to flow at substantially the same flow rate and / or for the same duration. In some embodiments, the flow rate of the silicon-containing precursor under the first process condition is the same as the flow rate of the silicon-containing precursor under the second process condition, and the flow rate of the oxygen-containing precursor under the second process condition is about 2 times to about 20 times the flow rate of the oxygen-containing precursor under the first process condition. In some embodiments, the duration of exposure to the silicon-containing precursor under the first process condition is the same as the duration of exposure to the silicon-containing precursor under the second process condition, and the duration of exposure to the oxygen-containing precursor under the second process condition is about 2 times to about 20 times the duration of exposure to the oxygen-containing precursor under the first process condition. The process temperature under the first process condition may be greater than 500 degrees Celsius. The silicon-containing precursor in the first process condition may be any suitable silicon-containing material, such as silane, disilane, dichlorosilane, trichlorosilane, and the oxygen-containing precursor may be any suitable oxygen-containing material, such as oxygen, nitrogen dioxide (NO 2 ), carbon dioxide (CO 2 ). In some embodiments, about 60% to about 90% of the plurality of cycles are performed under the first process condition, and about 10% to about 40% of the plurality of cycles are performed under the second process condition. After the cycles performed under the first process condition, the cycles performed with the second process condition are performed. In other words, the thermal ALD process includes performing a plurality of first cycles under the first process condition to form a dielectric material 143 between vertically adjacent first semiconductor layers 106, and to form a gap between portions of the dielectric material 143 formed on the top first semiconductor layer 106 and the bottom first semiconductor layer 106. The thermal ALD process further includes performing a plurality of second cycles under the second process condition to fill the gap with the dielectric material 143, and the resulting dielectric material 143 formed between the vertically adjacent first semiconductor layers 106 is seamless. In some embodiments, the plurality of first cycles includes a first number of cycles, the plurality of second cycles includes a second number of cycles, and the first number of cycles is about 1.5 times to about 9 times the second number of cycles.

[0084] In some embodiments, a low temperature thermal ALD process is performed to form the dielectric material 143. The deposited dielectric material 143 includes SiO 2, wherein the ratio of silicon to oxygen is less than about 2. The deposition temperature is in the range of about 200 degrees Celsius to about 500 degrees Celsius, and the deposition rate in growth per cycle (GPC) is in the range of about 0.01 angstroms / cycle to about 10 angstroms / cycle or from about 0.1 angstroms / minute to about 20 angstroms / minute. The low temperature thermal ALD process can be a single chamber ALD or a batch type ALD. In some embodiments, an organic silicon-containing precursor and an oxygen-containing precursor are used in the low temperature thermal ALD process. The oxygen-containing precursor may include O 2 Free radicals and / or O 3 If the process temperature is properly controlled, a self-limiting effect can be achieved. The dielectric material 143 deposited by the low temperature thermal ALD process can be diluted 1:100 and has a density range of about 1.5 g / cm 3 (g / cm 3 ) to about 2.3 g / cm 3 The dielectric material 143 may have a wet etch rate (WER) greater than 100 angstroms / minute (such as from about 100 angstroms / minute to about 800 angstroms / minute) in hydrofluoric acid. Using Fourier-transform infrared spectroscopy (FTIR), the dielectric material 143 may have an -OH peak characteristic at 3400±100. The dielectric material 143 may have a dielectric constant greater than about 1×10 -6 Ampere / cm 2 (A / cm 2 During the deposition of dielectric material 143, silicon consumption of first semiconductor layer 106 may be in the range of about 2 angstroms to about 10 angstroms due to oxidation. Dielectric material 143 may include a dielectric having a thickness of less than 1×10 4 Atomic concentrations of carbon and nitrogen and greater than 1x10 4 Atomic concentration of hydrogen and hydroxide. The roughness of the dielectric material 143 may be less than 0.5 angstroms (root mean square (RMS)) or less than 5 angstroms (maximum value (Rmax)).

[0085] In some embodiments, a hybrid ALD process is performed to form a seamless dielectric material 143 between vertically adjacent first semiconductor layers 106. The hybrid ALD process includes a plasma phase and a thermal phase. For example, the plasma phase includes a plurality of first cycles performed as a plasma enhanced atomic layer deposition (PEALD) process, and the thermal phase includes a plurality of second cycles performed as a thermal ALD process. The thermal ALD process may be FIG. 11A to FIG. 11D The thermal ALD process described. The PEALD process can be performed at a substantially lower process temperature, such as from about 50 degrees Celsius to about 100 degrees Celsius. The silicon-containing precursor and the oxygen-containing precursor in the PEALD can be the same as the silicon-containing precursor and the oxygen-containing precursor of the first process condition described above, and the silicon-containing precursor and the oxygen-containing precursor can be activated by a plasma, such as capacitively coupled plasma (CCP), inductively coupled plasma (ICP), transformer coupled plasma (TCP). Similar to the first process condition, the plasma stage of the hybrid ALD uses less precursors and is faster than the second process condition of the thermal ALD (or the thermal stage of the hybrid ALD).

[0086] Figures 14 to 20 1 is a perspective view of a semiconductor device structure 100 at various stages of fabrication according to some embodiments. Fig.14 As shown, an etch-back process is performed to remove portions of dielectric material 143 except for portions of dielectric material 143 formed in opening 141. In some embodiments, the etch-back process is an anisotropic etching process. Fig.14 As shown, the end of the dielectric material 143 and the end of the first semiconductor layer 106 have substantially flat surfaces, which may be flush with the corresponding first portion 140a of the gate spacer 140. Fig.15 As shown, the ends of dielectric material 143 are horizontally removed along the X direction. In other words, dielectric material 143 is recessed along the X direction. The removal of the ends of dielectric material 143 forms cavities. In some embodiments, the dielectric material 143 is removed by using an etchant such as hydrofluoric acid (HF) and ammonia (NH 3 ), diluted hydrofluoric acid (DHF) solution, or deionized water with ozone and DHF solution) to remove the end of the dielectric material 143.

[0087] FIG. 15-1 shows, according to some embodiments, Fig.15FIG. 15-1 is a cross-sectional side view of a portion 300 of a semiconductor device structure. As shown in FIG. 15-2 , the end of the dielectric material 143 is removed and a cavity is formed between vertically adjacent first semiconductor layers 106. FIG. 15-3 is a diagram showing, according to some embodiments, Fig.15 15-2, the dielectric material 143 includes a side surface 143s after being horizontally recessed. Because the dielectric material 143 is seamlessly formed between the adjacent first semiconductor layers 106, the side surface 143s is substantially linear. If a seam is formed in the dielectric material 143, the side surface 143s may be concave, which may cause the gate electrode layer 172 ( Fig. 20 ) and S / D region 146( Fig. 20 ) between them.

[0088] like Fig.16 As shown in FIG. 16 , after removing the end of the dielectric material 143, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a dielectric material such as silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or silicon nitride (SiN). The dielectric spacer 144 may be formed by first forming a compliant dielectric layer using a compliant deposition process such as ALD, and then performing anisotropic etching to remove the portion of the compliant dielectric layer other than the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. As shown in FIG. 16 , the dielectric material 143 covers between the dielectric spacers 144 along the X direction. In some embodiments, the dielectric spacer 144 and the dielectric material 143 include different materials with different etching selectivities.

[0089] like Fig.17As shown, source / drain (S / D) regions 146 are formed by the well 116. In some embodiments, the S / D regions 146 may be grown vertically and horizontally to form facets that may correspond to crystalline planes of the material used for the well 116. In the present disclosure, source regions and drain regions may be used interchangeably and their structures are substantially the same. In addition, the source / drain regions may refer to the source or drain individually or collectively depending on the context. In some embodiments, the S / D regions 146 are n-type S / D epitaxial components and may be made of one or more layers of silicon (Si), silicon phosphide (SiP), silicon carbon (SiC), and silicon carbon phosphide (SiCP) for n-type channel FETs. In some embodiments, the S / D regions 146 are p-type epitaxial components and may be made of one or more layers of silicon (Si), silicon germanium (SiGe), and germanium (Ge) for p-type channel FETs. For p-type channel FETs, p-type dopants such as boron (B) may also be included in the S / D regions 146. The S / D region 146 may be formed by using CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE) epitaxial growth method. Figure 8 ) is removed during the formation of the S / D region 146. In this way, the germanium (Ge) source is removed before the S / D region 146 is formed and the high interface state density (Dit) is improved.

[0090] like Fig.17As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the first portion 140a of the gate spacer 140 and is disposed on the second portion 140b of the gate spacer 140 and the S / D region 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on the CESL 162. The material of the ILD layer 163 may include a compound containing silicon (Si), oxygen (O), carbon (C), and / or hydrogen (H), such as silicon oxide, silicon hydroxide carbon (SiCOH), or silicon oxycarbide (SiOC). Organic materials such as polymers may also be used for the ILD layer 163. The ILD layer 163 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 163 , the semiconductor device structure 100 may be thermally treated to anneal the ILD layer 163 .

[0091] A planarization process is performed to expose the sacrificial gate electrode layer 134, such as Fig.17 The planarization process may be any suitable process, such as a chemical mechanical polish (CMP) process. The planarization process removes a portion of the ILD layer 163 disposed on the sacrificial gate stack 130 and a portion of the CESL 162. The planarization process may also remove the mask structure 136.

[0092] like Fig.18 As shown, the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed, exposing a portion of the top surface of the topmost first semiconductor layer 106. A first portion of the isolation region 120 is also exposed. The sacrificial gate electrode layer 134 can be first removed by any suitable process, such as dry etching, wet etching, or a combination of the foregoing, followed by the removal of the sacrificial gate dielectric layer 132, which can be performed by any suitable process, such as dry etching, wet etching, or a combination of the foregoing. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the spacers 140, the ILD layer 163, and the CESL 162.

[0093] like Fig.19As shown, the dielectric material 143 is removed. The dielectric material 143 can be removed by any suitable process. In some embodiments, the dielectric material 143 is removed by a selective etching process. The selective etching process can remove the dielectric material 143 between the first semiconductor layers 106, but does not remove the first semiconductor layers 106, the ILD layer 163, the CESL 162, and the gate spacer 140. After removing the dielectric material 143, the portion of each first semiconductor layer 106 not covered by the dielectric spacer 144 can be exposed. Each first semiconductor layer 106 can be a nanostructure channel.

[0094] like Fig. 20 As shown, after forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The IL 168 may include an oxide, such as silicon oxide, and may be formed due to a cleaning process. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-K dielectric materials, other suitable dielectric materials, and / or combinations of the foregoing. Examples of high-K dielectric materials include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium oxysilicide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al 2 O 3 ), hafnium oxide-aluminum oxide (HfO 2 -Al2O 3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate dielectric layer 170 and the gate electrode layer 172 may also be deposited over the ILD layer 163. The gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 163 are then removed by using, for example, CMP until the top surface of the ILD layer 163 is exposed.

[0095] Embodiments of the present disclosure provide a method for forming a semiconductor device structure 100. In some embodiments, the method is a THOR process. The THOR process can be a thermal ALD process, a thermal ALD process for different process conditions for different number of cycles, or a hybrid ALD process. Some embodiments can achieve advantages. For example, the dielectric material 143 formed between vertically adjacent first semiconductor layers 106 by the THOR process is seamless.

[0096] One embodiment is a method for manufacturing a semiconductor device structure. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer, and performing an oxide refill process to form a seamless dielectric material between the second semiconductor layer and the third semiconductor layer. The oxide refill process includes: exposing the second conductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a monolayer, the silicon-containing precursor having a first flow rate bottom and a chemical structure:

[0097]

[0098] Each R group contains at least two carbons. The oxide backfill process also includes exposing the monolayer to an oxygen-containing precursor for a second duration to form a seamless dielectric material, the oxygen-containing precursor having a second flow rate, the second flow rate being about 2 times to about 20 times the first flow rate, and the second duration being about 2 times to about 20 times the first duration.

[0099] Another embodiment is a method for manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack, the semiconductor layer stack including a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method also includes forming a sacrificial gate stack on a first portion of the fin structure, recessing a second portion of the fin structure, removing a second semiconductor layer disposed below the sacrificial gate stack to form a plurality of openings between vertically adjacent first semiconductor layers, and performing an atomic layer deposition process to form a seamless dielectric material in the openings. The atomic layer deposition process includes performing a plurality of first cycles, each of the first cycles including flowing a first silicon-containing precursor into a process chamber at a first flow rate for a first duration, and flowing a first oxygen-containing precursor into the process chamber at a second flow rate for a second duration, and then performing a plurality of second cycles, each of the second cycles including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the process chamber at a third flow rate for a third duration, and flowing a second oxygen-containing precursor into the process chamber at a fourth flow rate for a fourth duration.

[0100] Another embodiment is a method for manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack, the semiconductor layer stack includes a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method also includes recessing a portion of the fin structure to expose a well portion of the fin structure, removing the second semiconductor layer to form a plurality of openings between vertically adjacent first semiconductor layers, and performing a hybrid atomic layer deposition process to form a seamless dielectric material in the opening. The hybrid atomic layer deposition process includes performing a plasma enhanced atomic layer deposition process at a first temperature, and then performing a thermal atomic layer deposition process at a second temperature, the second temperature being substantially greater than the first temperature. The method also includes forming a source / drain region from the well portion, removing the seamless dielectric material, and forming a gate electrode layer surrounding a plurality of exposed portions of the first semiconductor layer.

[0101] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the concept and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the concept and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device structure, comprising: removing a first semiconductor layer, wherein the first semiconductor layer is disposed between a second semiconductor layer and a third semiconductor layer; as well as Performing an oxide backfill process to form a seamless dielectric material between the second semiconductor layer and the third semiconductor layer, comprising: The second semiconductor layer and the third semiconductor layer are exposed to a silicon-containing precursor for a first duration to form a single layer, wherein the silicon-containing precursor has a first flow rate and a chemical structure: ， wherein each R group contains at least two carbons; The single layer is exposed to an oxygen-containing precursor for a second duration to form the seamless dielectric material, wherein the oxygen-containing precursor has a second flow rate, the second flow rate is about 2 times to about 20 times the first flow rate, and the second duration is about 2 times to about 20 times the first duration. 2 . The method for manufacturing a semiconductor device structure as claimed in claim 1 , wherein the second flow rate is about 5 times to about 10 times the first flow rate, and the second duration is about 5 times to about 10 times the first duration.

3. The method for fabricating a semiconductor device structure as claimed in claim 1, wherein the oxygen-containing precursor comprises ozone.

4. A method for manufacturing a semiconductor device structure, comprising: forming a fin structure from a substrate, wherein the fin structure comprises a semiconductor layer stack, the semiconductor layer stack comprising a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers; forming a sacrificial gate stack on a first portion of the fin structure; recessing a second portion of the fin structure; removing the second semiconductor layers disposed below the sacrificial gate stack to form a plurality of openings between the vertically adjacent first semiconductor layers; as well as Performing an atomic layer deposition process to form a seamless dielectric material in the openings includes: performing a plurality of first cycles, each of the first cycles comprising flowing a first silicon-containing precursor into a process chamber at a first flow rate for a first duration, and flowing a first oxygen-containing precursor into the process chamber at a second flow rate for a second duration; And then A plurality of second cycles are performed, each of the second cycles comprising flowing a second silicon-containing precursor different from the first silicon-containing precursor into the process chamber at a third flow rate for a third duration and flowing a second oxygen-containing precursor into the process chamber at a fourth flow rate for a fourth duration. 5 . The method for manufacturing a semiconductor device structure as claimed in claim 4 , wherein the first flow rate is substantially the same as the second flow rate. 6 . The method for manufacturing a semiconductor device structure as claimed in claim 4 , wherein the first duration is substantially the same as the second duration. 7 . The method for manufacturing a semiconductor device structure as claimed in claim 4 , further comprising removing a plurality of ends of the seamless dielectric material to form a plurality of cavities.

8. A method for manufacturing a semiconductor device structure, comprising: forming a fin structure from a substrate, wherein the fin structure comprises a semiconductor layer stack, the semiconductor layer stack comprising a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers; recessing a portion of the fin structure to expose a well portion of the fin structure; removing the second semiconductor layers to form a plurality of openings between the vertically adjacent first semiconductor layers; Performing a hybrid atomic layer deposition process to form a seamless dielectric material in the openings includes: performing a plasma enhanced atomic layer deposition process at a first temperature; and then performing a thermal atomic layer deposition process at a second temperature, the second temperature being substantially greater than the first temperature; forming a source / drain region from the well; removing the seamless dielectric material; and A gate electrode layer is formed around the exposed portions of the first semiconductor layers. 9 . The method for fabricating a semiconductor device structure as claimed in claim 8 , wherein the first temperature is in a range of about 50 degrees Celsius to about 100 degrees Celsius, and the second temperature is in a range of about 200 degrees Celsius to about 500 degrees Celsius.

10. The method for manufacturing a semiconductor device structure as claimed in claim 8, wherein the plasma enhanced atomic layer deposition process includes a first number of cycles, and the thermal atomic layer deposition process includes a second number of cycles, and the second number of cycles is less than the first number of cycles.

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