A GaN vertical complementary field effect transistor and inverter

Abstract

The application discloses a GaN vertical complementary field effect transistor (VCFET) and an inverter, the VCFET comprising a substrate, a first transistor, a second transistor and a common gate electrode, the first transistor and the second transistor being vertically stacked on the substrate in sequence; the first transistor is an n-type transistor, and the second transistor is a p-type transistor, and an overall structure of a GaN buffer layer, an n-type transistor GaN channel layer, an AlGaN barrier layer, a p-type transistor GaN channel layer and a p-type transistor GaN doping layer is formed; the n-type channel and the p-type channel are simultaneously controlled through the common gate electrode. On the basis of the structure, the source electrode of the p-type transistor is connected to a high level, the source electrode of the n-type transistor is connected to a low level, the drain electrodes of the two transistors are connected together and simultaneously used as an output end, and the gate electrode is used as an input end, so that the inverter is realized. The VCFET realizes the electronic transmission characteristics of high efficiency and low power consumption, has a smaller footprint while maintaining high performance, and improves the integration degree.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a GaN vertical complementary field-effect transistor (VCFET) and its inverter. Background Technology

[0002] GaN-based materials, namely group III nitride materials, possess a series of excellent physical properties, including a large bandgap, high critical breakdown electric field, high mobility, and high electron saturation velocity. In addition, group III nitride materials have relatively high polarizability, resulting in a high two-dimensional electron gas concentration at the interface of group III nitride heterojunctions. These excellent material properties enable GaN high electron mobility transistors (HEMTs) to have excellent performance such as high breakdown voltage, low on-resistance, low gate charge, high switching speed, and high energy conversion efficiency, making them core devices for applications in electric vehicles, power grids, high-speed rail, and consumer electronics power modules.

[0003] The trend towards miniaturization in radio frequency (RF) and power electronic systems has created an urgent need for GaN chips that monolithically integrate digital and analog integrated circuits. However, traditional methods require discrete Si CMOS driver circuit modules, increasing system size and design complexity. Therefore, monolithically integrating GaN digital and analog circuits with GaN HEMT RF and power electronic devices is of great significance. GaN field-effect transistors (FETs) and inverters are core components of GaN digital and analog circuits; however, mature technologies for GaN complementary field-effect transistors (CFETs) and inverters are still lacking. Literature has reported the implementation of PMOS using p-GaN gate materials in normally-off GaN HEMTs and NMOS using HEMT structures. However, p-GaN has a high ionization energy of p-type impurities, a low hole concentration, and a relatively low hole mobility, resulting in low PMOS output current. Furthermore, the horizontal arrangement of NMOS and PMOS chips leads to a large chip area. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the present invention aims to provide a GaN vertical complementary field-effect transistor and inverter, so that the complementary field-effect transistor and inverter have higher performance and smaller footprint.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a GaN vertical complementary field-effect transistor, comprising a substrate, a first transistor, a second transistor, and a common gate electrode, wherein the first transistor and the second transistor are stacked vertically on the substrate in sequence.

[0007] The first transistor is an n-type transistor, including a GaN buffer layer, an n-type GaN channel layer and a common AlGaN barrier layer arranged sequentially along the direction away from the substrate. The GaN buffer layer is directly disposed on the substrate. A two-dimensional electron gas is formed at the heterojunction interface between the GaN channel layer and the AlGaN barrier layer. The two-dimensional electron gas region serves as the n-type channel, i.e. the conductive channel of the first transistor.

[0008] The second transistor is a p-type transistor, comprising the AlGaN barrier layer, the p-type GaN channel layer and the p-type GaN doped layer arranged sequentially in a direction away from the substrate. At the heterojunction interface between the p-type GaN channel layer and the AlGaN barrier layer, holes accumulate to form a two-dimensional hole gas. The two-dimensional hole gas region will serve as the p-type channel, i.e., the conductive channel of the second transistor.

[0009] The n-type channel and p-type channel are stacked vertically; the first source electrode and the first drain electrode of the first transistor are arranged in the n-type GaN channel layer, and the second source electrode and the second drain electrode of the second transistor are arranged in the p-type GaN channel layer. The first transistor and the second transistor share the gate electrode to achieve simultaneous control of the n-type channel and the p-type channel.

[0010] In one embodiment, the first source electrode and the first drain electrode of the first transistor are arranged horizontally at both ends of the n-transistor GaN channel layer; the second source electrode and the second drain electrode of the second transistor are arranged horizontally at both ends of the p-transistor GaN channel layer; and the gate electrode is arranged horizontally on both sides of the structure of the GaN vertical complementary field-effect transistor.

[0011] In one embodiment, the horizontal direction in which the first source electrode and the first drain electrode are arranged, and the horizontal direction in which the second source electrode and the second drain electrode of the second transistor are arranged, are both perpendicular to the horizontal direction in which the gate electrode is arranged.

[0012] In one embodiment, the substrate is Si, SiC, sapphire, or diamond, and is further selected to be Si.

[0013] In one embodiment, the bottom metal of the gate electrode is one of Ni, Ti, Mo, and Ta, and the other metals are different materials from the bottom metal, and are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti, and are further selected to be Ni / Au from bottom to top.

[0014] In one embodiment, the bottom metal of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode is one of Ti, Mo, and Ta. The other metals are different materials from the bottom metal and are composed of one or more of Au, Ni, Al, Mo, Ta, and Ti. Furthermore, they are selected to be Ti / Al / Ni / Au from bottom to top.

[0015] In one embodiment, the AlGaN barrier layer is unintentionally doped, with an aluminum molar composition of 5-100% and a thickness between 3-30 nm, and further selected with an aluminum composition of 25% and a thickness of 20 nm to provide sufficient barrier height to prevent leakage current.

[0016] In one embodiment, the thickness of the n-tube GaN channel layer is 50-500 nm, which is unintentionally doped or n-type doped, and further selected to be 200 nm thick, which is unintentionally doped.

[0017] In one embodiment, the thickness of the p-tube GaN channel layer is 10-30 nm, which is unintentionally doped or p-type doped, and further selected to be 20 nm thick, which is unintentionally doped.

[0018] In one embodiment, the thickness of the p-tube GaN doped layer is 10-150 nm, and it is either unintentionally doped or heavily p-type doped. The dopant in the p-tube GaN doped layer is Mg or Zn, and the impurity concentration of the p-tube GaN doped layer is 1 × 10⁻⁶. 18 -1×10 21 cm -3 Furthermore, a thickness of 80 nm was selected, with Mg as the dopant and an impurity concentration of 1 × 10⁻⁶. 20 cm -3 .

[0019] In one embodiment, a gate dielectric layer is provided between the gate electrode and the n-channel GaN channel layer and the p-channel GaN channel layer, the gate dielectric layer being used to insulate between the n-channel GaN channel layer and the gate electrode, and between the p-channel GaN channel layer and the gate electrode.

[0020] In one embodiment, the material of the gate dielectric layer is SiO2, SiN, Al2O3, HfO2, ZrO2, or AlN.

[0021] In a second aspect, the present invention also provides a GaN vertical complementary field-effect transistor inverter, based on the GaN vertical complementary field-effect transistor described in the first aspect, wherein the gate electrode is the input terminal, the first drain electrode and the second drain electrode are connected together and serve as the output terminal, the first source electrode is connected to a low level, and the second source electrode is connected to a high level, thereby realizing the logic inversion between the output terminal and the input terminal.

[0022] A third aspect of the present invention also provides a method for fabricating a GaN vertical complementary field-effect transistor as described in the first aspect, comprising the following steps:

[0023] Step 1: Epitaxially grow a GaN buffer layer on the substrate;

[0024] Step 2: Grow an n-channel GaN layer on the GaN buffer layer;

[0025] Step 3: Fabricate the first source electrode and the first drain electrode at the end of the GaN channel layer of the n-tube;

[0026] Step 4: Epitaxially grow an AlGaN barrier layer on the n-tube GaN channel layer;

[0027] Step 5: Grow p-tube GaN channel layers on the AlGaN barrier layer;

[0028] Step 6: Fabricate the second source electrode and the second drain electrode at the end of the GaN channel layer of the p-tube;

[0029] Step 7: Grow a p-tube GaN doped layer on the p-tube GaN channel layer;

[0030] Step 8: Fabricate gate electrodes on both sides of the transistor.

[0031] In one embodiment, the GaN buffer layer, n-tube GaN channel layer, p-tube GaN channel layer and p-tube GaN doped layer are all manufactured using MOCVD process at a temperature of 1000°C.

[0032] The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are all made using photolithography. A photoresist mask is made to expose the electrode to be made, and then multiple layers of metal are grown in the exposed area by electron beam evaporation. After being peeled off, the corresponding electrodes are formed.

[0033] Compared with the prior art, the beneficial effects of the present invention are:

[0034] (1) Because the CFET structure stacks the first transistor (N-type transistor) and the second transistor (P-type transistor) vertically on the substrate layer in sequence, it greatly reduces the area occupied by the two transistors on the horizontal plane, enabling higher transistor density to be achieved on a smaller chip area. That is, the CFET structure simultaneously achieves miniaturization of the device volume in both the horizontal and vertical directions.

[0035] (2) The gate electrode design on both sides of the CFET structure can provide better gate electrode control, reduce leakage current, and improve switching speed.

[0036] (3) The vertical stacking structure of the CFET helps to reduce parasitic capacitance and resistance and improve the overall performance of the device.

[0037] (4) In this CFET structure, by using a double heterojunction structure of p-GaN layer-AlGaN barrier layer-n-GaN layer, it is possible to simultaneously fabricate conductive channels of N-type transistors and P-type transistors, and to reduce the thickness of the conductive channels to a certain extent, thereby further miniaturizing the size and thickness of the device.

[0038] (5) Due to the close arrangement of n-type and p-type transistors, faster switching speeds can be provided, which is a significant advantage for CMOS inverters, especially in high-speed digital logic applications. Because of the low leakage current of the CFET structure, the power consumption of CMOS inverters is also reduced in both static and dynamic operations.

[0039] (6) Because the vertical stacking structure of the transistors facilitates vertical heat conduction rather than horizontal conduction in a planar structure, this helps improve the thermal management of the CMOS inverter, reduce thermal resistance, and improve the long-term stability of the device. The vertical stacking structure also helps reduce parasitic capacitance and resistance, improving the overall electrical performance of the CMOS inverter.

[0040] (7) In addition, the technology proposed in this invention is compatible with the original process, and the manufacturing process is relatively simple.

[0041] The overview of the technical solution of this invention only provides a preliminary outline. For a deeper understanding of the technical details and implementation methods of this invention, please refer to the detailed content of this specification for practical operation. Furthermore, to more clearly demonstrate the features and advantages of each item of this invention, a specific embodiment of this invention will be described in detail below. Attached Figure Description

[0042] By carefully reading the detailed description of the following specific embodiments, those skilled in the art will be able to clearly recognize the numerous additional advantages and benefits of the present invention. The accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention in any way. Furthermore, in all the drawings, the same parts are indicated by consistent reference numerals to maintain consistency and clarity of description. In the drawings:

[0043] Figure 1 This is a three-dimensional structural diagram of the GaN vertical complementary field-effect transistor (VCFET) of the present invention.

[0044] Figure 2 This is a schematic diagram of the three-dimensional structure and cross-sectional position of the GaN vertical complementary field-effect transistor (VCFET) of the present invention.

[0045] Figure 3 The present invention relates to the GaN vertical complementary field-effect transistor (VCFET) in... Figure 2 Cross-sectional view along direction A.

[0046] Figure 4 The present invention relates to the GaN vertical complementary field-effect transistor (VCFET) in... Figure 2 Cross-sectional view along direction B.

[0047] Figure 5 The gate (50) in the GaN vertical complementary field-effect transistor (VCFET) of this invention is in Figure 2 Cross-sectional view along direction C.

[0048] Figures 6-14 This is a partial schematic diagram of the formation process of a GaN vertical complementary field-effect transistor (VCFET) provided in an embodiment of the present invention.

[0049] In the picture:

[0050] 10-Substrate; 21-n-GaN doped layer; 22-n-GaN channel layer; 23-First source electrode; 24-First drain electrode; 30-AlGaN barrier layer; 41-p-GaN doped layer; 42-p-GaN channel layer; 43-Second source electrode; 44-Second drain electrode; 50-Gate electrode; 51-Gate dielectric layer. Detailed Implementation

[0051] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings and examples.

[0052] It should be noted that the accompanying drawings are schematic diagrams of various structures drawn according to embodiments of the present invention, and are not made to scale. Some details have been enlarged for clearer expression, while some details may have been omitted for simplification. The shapes of the regions and layers shown in the drawings, as well as their relative dimensions and positional relationships, are exemplary and may differ in actual production due to manufacturing tolerances or technical constraints. Furthermore, those skilled in the art can design regions or layers with different shapes, sizes, and relative layouts according to actual needs.

[0053] In this discussion, when it is mentioned that a layer / component is "above" another layer / component, this means that the layer / component may directly cover the other layer / component, or there may be other layers / components in between. Similarly, if a layer / component is "above" another layer / component in a particular direction, then it is "below" that layer / component in the opposite direction. Similar or identical parts may be identified using consistent or similar numbering throughout this description.

[0054] To gain a deeper understanding of the aforementioned technical solutions, a detailed description will be provided below in conjunction with specific implementation schemes. It should be understood that the embodiments and specific features of this disclosure are specific descriptions of the technical solutions of this application and do not constitute a limitation on the technical solutions of this application. Without violating the principles, the embodiments of this application and the technical elements they contain can be combined with each other.

[0055] Example 1

[0056] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the present invention is a GaN vertical complementary field-effect transistor (VCFET), including a substrate 10, a first transistor, a second transistor, and a common gate electrode 50. The first transistor and the second transistor are stacked vertically on the substrate 10 in sequence.

[0057] For ease of description, this invention can define an XYZ coordinate system, where the Z-axis is defined as the thickness direction of the transistor, i.e., the stacking direction. Figure 1 The vertical direction is represented by the center line, and the Y direction is defined as the length direction of the layer. Figure 1 The left and right directions are represented by the 'm' direction, and the 'X' direction is defined as the width direction of the layer. Figure 1 The middle represents the front and back directions.

[0058] The first transistor of the present invention is an n-type transistor, comprising a GaN buffer layer 21, an n-type GaN channel layer 22, a first source electrode 23, a first drain electrode 24, and a common AlGaN barrier layer 30. The GaN buffer layer 21 is directly disposed on the substrate 10. The GaN buffer layer 21, the n-type GaN channel layer 22, and the AlGaN barrier layer 30 are arranged sequentially in a direction away from the substrate 10. The first source electrode 23 and the first drain electrode 24 of the first transistor are disposed on the n-type GaN channel layer 22. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface between the GaN channel layer 22 and the AlGaN barrier layer 30. The 2DEG region serves as the n-type channel, i.e., the conductive channel of the first transistor.

[0059] The second transistor of the present invention is a p-type transistor, comprising an AlGaN barrier layer 30, a p-type GaN channel layer 42, a p-type GaN doped layer 41, a second source electrode 43, and a second drain electrode 44. The p-type GaN channel layer 42 is directly disposed on the AlGaN barrier layer 30, and is vertically opposite to the GaN channel layer 22. The AlGaN barrier layer 30, the p-type GaN channel layer 42, and the p-type GaN doped layer 41 are arranged sequentially in a direction away from the substrate 10. The second source electrode 43 and the second drain electrode 44 of the second transistor are disposed on the p-type GaN channel layer 42. At the heterojunction interface between the p-type GaN channel layer 42 and the AlGaN barrier layer 30, holes accumulate to form a two-dimensional hole gas (2DHG). The 2DHG region will serve as the p-type channel, i.e., the conductive channel of the second transistor.

[0060] In this invention, n-type and p-type channels are vertically stacked, wherein the common AlGaN barrier layer 30 refers to the AlGaN barrier layer 30 being a shared layer for the first transistor and the second transistor. The common gate electrode 50 refers to the gate electrode 50 being a shared gate for the first transistor and the second transistor. The first transistor and the second transistor share the gate electrode 50, enabling simultaneous control of both the n-type and p-type channels.

[0061] The complementary field-effect transistor provided in this embodiment of the invention reduces the area occupied by the two transistors on the horizontal plane by vertically stacking the first and second transistors on the substrate, thereby achieving a higher transistor density in a smaller chip area. Simultaneously, this vertical stacking structure also helps reduce parasitic capacitance and resistance.

[0062] By using a shared AlGaN barrier layer, this invention forms a double heterojunction structure of p-GaN layer-AlGaN barrier layer-n-GaN layer, which can not only simultaneously fabricate conductive channels for n-type and P-type transistors, but also reduce the thickness of the conductive channel to a certain extent, thereby further reducing the transistor thickness.

[0063] Overall, the VCFET of this invention achieves efficient and low-power electronic transport characteristics, while maintaining high performance and having a smaller footprint, thus improving integration.

[0064] For example, the first source electrode 23 and the first drain electrode 24 of the first transistor of the present invention are arranged horizontally at the left and right ends of the n-channel GaN channel layer 22, i.e., at the two ends in the Y direction. The first source electrode 23 and the first drain electrode 24 have the same thickness as the n-channel GaN channel layer 22. The second source electrode 43 and the second drain electrode 44 of the second transistor are arranged horizontally at the left and right ends of the p-channel GaN channel layer 42, i.e., at the two ends in the Y direction. The second source electrode 43 and the second drain electrode 44 have the same thickness as the p-channel GaN channel layer 42. The gate electrode 50 is arranged horizontally on both sides of the structure of the GaN vertical complementary field-effect transistor, i.e., on both sides in the X direction. The gate electrode 50 can be directly disposed on the substrate 10 and has the same total thickness as the GaN buffer layer 21, the n-channel GaN channel layer 22, the AlGaN barrier layer 30, the p-channel GaN channel layer 42, and the p-channel GaN doped layer 41. The structure with the gate electrode 50 on both sides can provide better gate electrode control, reduce leakage current, and improve switching speed.

[0065] Example 2

[0066] Based on Embodiment 1, the present invention provides a GaN vertical complementary field-effect transistor inverter, which uses the gate electrode 50 as the input terminal, connects the first drain electrode 24 and the second drain electrode 44 as the output terminal, connects the first source electrode 23 to the low level and the second source electrode 43 to the high level, thereby realizing the logic inversion between the output terminal and the input terminal.

[0067] Because this invention employs a structure in which n-type and p-type transistors are closely packed, it can provide a faster switching speed. At the same time, because the leakage current of the CFET structure in this invention is low, the power consumption of the inverter in both static and dynamic operation can be reduced accordingly.

[0068] Meanwhile, because the transistors of this invention employ a vertical stacking structure, vertical heat conduction is more conducive to heat dissipation, resulting in better stability of the inverter. Furthermore, the transistors have smaller parasitic capacitance and resistance, which also improves the overall electrical performance of the inverter.

[0069] Example 3

[0070] Based on Example 1, a gate dielectric layer 51 is provided between the gate electrode 50 and the n-channel GaN channel layer 22, and between the p-channel GaN channel layer 42. The material of the gate dielectric layer 51 can be SiO2, SiN, Al2O3, HfO2, ZrO2, or AlN; in this example, HfO2 is selected. The gate dielectric layer 51 provides insulation between the n-channel GaN channel layer 22 and the gate electrode 50, and between the p-channel GaN channel layer 42 and the gate electrode 50.

[0071] Example 4

[0072] The present invention provides a fabrication process for a vertically stacked complementary field-effect transistor as follows:

[0073] Step one: A silicon oxide thin film is formed on the side of substrate 10 used for stacking the first and second transistors. This is followed by cleaning, as shown below. Figure 5 As shown, hydrogen gas is introduced into the reaction chamber at a high temperature of 1000℃ to remove contaminants from the surface of substrate 10 and form a microscopic stepped structure on the substrate surface to facilitate the subsequent epitaxial growth of various epitaxial layers. The substrate 10 is made of silicon and has a thickness of 800 μm.

[0074] Step two, epitaxially grow a GaN buffer layer 21 on substrate 10, such as... Figure 6 As shown.

[0075] The temperature was raised to 1000℃, and a GaN buffer layer 21 with a thickness of 1000 nm was grown on the substrate 10 using MOCVD. The GaN buffer layer 21 was n-type doped, specifically using silicon (Si) doping, with a doping concentration of 1×10⁻⁶. 18 cm -3 .

[0076] Step 3, fabricate the n-tube GaN channel layer 22, as follows: Figure 7 As shown.

[0077] Using MOCVD, a 300 nm thick n-type GaN channel layer 22 was grown on the GaN buffer layer 21 at a temperature of 1000 °C. The n-type GaN channel layer 22 was n-type doped, specifically using silicon (Si) doping with a doping concentration of 1 × 10⁻⁶. 18 cm -3 .

[0078] Step four: Fabricate the first source electrode 23 and the first drain electrode 24 on both sides of the horizontal direction of the GaN channel layer 22 of the n-tube, as follows: Figure 8 , Figure 9 As shown.

[0079] A photoresist mask is fabricated using photolithography to expose the first source electrode 23 and the first drain electrode 24 of the first transistor to be fabricated. Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this area by electron beam evaporation, that is, from bottom to top, Ti is 50nm thick, Al is 150nm thick, Ni is 50nm thick, and Au is 50nm thick. After peeling, the first source electrode 23 and the first drain electrode 24 of the first transistor are formed.

[0080] Step 5, continue fabricating the AlGaN barrier layer 30, as follows: Figure 10 As shown.

[0081] A 30 nm thick AlGaN barrier layer 30 is epitaxially formed on the n-tube GaN channel layer 22. The AlGaN barrier layer 30 is undoped and has an aluminum composition of 0.3.

[0082] Step 6, fabricate the p-tube GaN channel layer 42, as shown. Figure 11 As shown.

[0083] Using MOCVD, a 300 nm thick p-tube GaN channel layer 42 was grown on the AlGaN barrier layer 30 at a temperature of 1000 °C. The p-tube GaN channel layer 42 was p-type doped, specifically with magnesium (Mg) doping at a concentration of 1 × 10⁻⁶. 18 cm -3 .

[0084] Step 7: Fabricate a second source electrode 43 and a second drain electrode 44 on both sides of the horizontal direction of the p-tube GaN channel layer 42, as follows: Figure 12 , Figure 13 As shown.

[0085] A photoresist mask is fabricated using photolithography to expose the second source electrode 43 and the first drain electrode 44 of the second transistor to be fabricated. Then, a multilayer metal Ti / Al / Ni / Au layer is grown in this region by electron beam evaporation, namely, Ti with a thickness of 50 nm, Al with a thickness of 150 nm, Ni with a thickness of 50 nm, and Au with a thickness of 50 nm from bottom to top. After peeling, the second source electrode 43 and the second drain electrode 44 of the second transistor are formed.

[0086] Step 8: Fabricate the GaN doped layer 41 for the p-tube, as shown below. Figure 13 As shown.

[0087] The temperature was raised to 1000℃, and a 1000 nm thick p-tube GaN doped layer 41 was grown on the p-tube GaN channel layer 42 using MOCVD. The p-tube GaN doped layer 41 is p-type doped, specifically with magnesium (Mg) doping at a concentration of 1 × 10⁻⁶. 18 cm -3 .

[0088] Step nine, fabricate gate electrodes 50 on both sides of the transistor, such as... Figure 4 As shown, the gate electrode 50 is made of Ti / Au, and hafnium oxide can be set as the gate dielectric layer 51.

[0089] The VCFET of the present invention can be prepared by following the above steps, and its process is compatible with the existing process.

[0090] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention, as long as they meet the scope of the technical solutions in the specification. However, these modifications and changes based on the ideas of the present invention are still within the protection scope of the present invention.

Claims

1. A GaN vertical complementary field-effect transistor, characterized in that, It includes a substrate (10), a first transistor, a second transistor, and a common gate electrode (50), wherein the first transistor and the second transistor are stacked vertically on the substrate (10) in sequence; The first transistor is an n-type transistor, including a GaN buffer layer (21), an n-type GaN channel layer (22) and a common AlGaN barrier layer (30) arranged sequentially along the direction away from the substrate (10). The GaN buffer layer (21) is directly arranged on the substrate (10). A two-dimensional electron gas is formed at the heterojunction interface between the GaN channel layer (22) and the AlGaN barrier layer (30). The two-dimensional electron gas region serves as the n-type channel, i.e., the conductive channel of the first transistor. The second transistor is a p-type transistor, including the AlGaN barrier layer (30), the p-type GaN channel layer (42) and the p-type GaN doped layer (41) arranged sequentially along the direction away from the substrate (10). At the heterojunction interface between the p-type GaN channel layer (42) and the AlGaN barrier layer (30), holes accumulate to form a two-dimensional hole gas. The two-dimensional hole gas region will serve as the p-type channel, that is, the conductive channel of the second transistor. The n-type channel and the p-type channel are stacked vertically; the first source electrode (23) and the first drain electrode (24) of the first transistor are arranged on the n-type GaN channel layer (22), and the second source electrode (43) and the second drain electrode (44) of the second transistor are arranged on the p-type GaN channel layer (42). The first transistor and the second transistor share the gate electrode (50) to achieve simultaneous control of the n-type channel and the p-type channel.

2. The GaN vertical complementary field-effect transistor according to claim 1, characterized in that, The first source electrode (23) and the first drain electrode (24) of the first transistor are arranged horizontally at both ends of the n-transistor GaN channel layer (22); the second source electrode (43) and the second drain electrode (44) of the second transistor are arranged horizontally at both ends of the p-transistor GaN channel layer (42); the gate electrode (50) is arranged horizontally on both sides of the structure of the GaN vertical complementary field-effect transistor.

3. A GaN vertical complementary field-effect transistor according to claim 2, characterized in that, The horizontal direction in which the first source electrode (23) and the first drain electrode (24) are arranged, and the horizontal direction in which the second source electrode (43) and the second drain electrode (44) of the second transistor are arranged, are both perpendicular to the horizontal direction in which the gate electrode (50) is arranged.

4. A GaN vertical complementary field-effect transistor according to claim 2 or 3, characterized in that, The substrate (10) is Si, SiC, sapphire or diamond, and the bottom metal of the gate electrode (50) is one of Ni, Ti, Mo or Ta. Other metals besides the bottom metal are different materials from the bottom metal and are composed of one or more of Au, Ni, Al, Mo, Ta or Ti. The bottom metals of the first source electrode (23), the first drain electrode (24), the second source electrode (43) and the second drain electrode (44) are one of Ti, Mo or Ta. Other metals besides the bottom metal are different materials from the bottom metal and are composed of one or more of Au, Ni, Al, Mo, Ta or Ti.

5. A GaN vertical complementary field-effect transistor according to claim 1, characterized in that, The AlGaN barrier layer (30) is unintentionally doped, with an aluminum molar composition of 5-100% and a thickness of 3-30 nm to provide sufficient barrier height to prevent leakage current; the n-tube GaN channel layer (22) has a thickness of 50-500 nm and is unintentionally doped or n-type doped; the p-tube GaN channel layer (42) has a thickness of 10-30 nm and is unintentionally doped or p-type doped; the p-tube GaN doped layer (41) has a thickness of 10-150 nm and is unintentionally doped or heavily p-type doped. The dopant in the p-tube GaN doped layer (41) is Mg or Zn, and the impurity concentration of the p-tube GaN doped layer (41) is 1×10⁻⁶. 18 -1×10 21 -3 cm.

6. A GaN vertical complementary field-effect transistor according to claim 1, characterized in that, A gate dielectric layer (51) is provided between the gate electrode (50) and the n-channel GaN channel layer (22) and the p-channel GaN channel layer (42). The gate dielectric layer (51) is used to insulate the n-channel GaN channel layer (22) from the gate electrode (50) and the p-channel GaN channel layer (42) from the gate electrode (50).

7. A GaN vertical complementary field-effect transistor according to claim 6, characterized in that, The material of the gate dielectric layer (51) is SiO2, SiN, Al2O3, HfO2, ZrO2 or AlN.

8. A GaN vertical complementary field-effect transistor inverter, characterized in that, Based on any one of claims 1 to 7, a GaN vertical complementary field-effect transistor is provided, wherein the gate electrode (50) is the input terminal, the first drain electrode (24) and the second drain electrode (44) are connected and serve as the output terminal, the first source electrode (23) is connected to a low level, and the second source electrode (43) is connected to a high level, thereby realizing the logic inversion between the output terminal and the input terminal.

9. A method for fabricating a GaN vertical complementary field-effect transistor according to any one of claims 1 to 7, comprising the following steps: Step 1: Epitaxially grow a GaN buffer layer (21) on the substrate (10); Step 2: Grow an n-tube GaN channel layer (22) on the GaN buffer layer (21); Step 3: Fabricate the first source electrode (23) and the first drain electrode (24) at the end of the GaN channel layer (22) of the n-tube; Step 4: Epitaxially grow an AlGaN barrier layer (30) on the n-tube GaN channel layer (22); Step 5: Grow p-tube GaN channel layer (42) on AlGaN barrier layer (30); Step 6: Fabricate a second source electrode (43) and a second drain electrode (44) at the end of the GaN channel layer (42) of the p-tube; Step 7: Grow a p-tube GaN doped layer (41) on the p-tube GaN channel layer (42); Step 8: Fabricate gate electrodes (50) on both sides of the transistor.

10. The method for fabricating a GaN vertical complementary field-effect transistor according to claim 9, characterized in that, The GaN buffer layer (21), n-tube GaN channel layer (22), p-tube GaN channel layer (42) and p-tube GaN doped layer (41) are all manufactured using MOCVD process at a temperature of 1000℃. The first source electrode (23), the first drain electrode (24), the second source electrode (43), and the second drain electrode (44) are all made by photolithography to create a photoresist mask, exposing the electrode to be made, and then growing multiple layers of metal in the exposed area by electron beam evaporation. After being peeled off, the corresponding electrodes are formed.

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