CDM protection structure of SOC chip and SOC chip

Abstract

A CDM protection structure of a SOC chip and a SOC chip, comprising: a wafer and a substrate, a digital ground PAD-DVSS and an analog ground PAD-AVSS on the wafer are connected to digital and analog circuits respectively, a radio frequency signal pin PIN-RF is located on the substrate and connected to the analog circuit, independent pins lead the digital ground and the analog ground to the substrate, an inductor connects the digital ground PAD-DVSS and the radio frequency signal pin PIN-RF, controls the CDM discharge path, slows down the charge release speed, and thus protects the CMOS tube connected to the PIN-RF. The formed ESD protection path provides discharge protection for the analog circuit, ensuring that the charge in the analog circuit is discharged through the path, while the charge in the digital circuit is discharged through the inductor. The CDM protection structure design improves the CDM protection capability of the chip at the expense of a relatively small receiver sensitivity, meets the effectiveness and reliability requirements of the JEDEC standard, and reduces the risk of yield reduction due to CDM failure. In addition to digital-analog hybrid SOC chips, the present invention is also applicable to single analog SOC chips.

Description

Technical Field

[0001] The invention relates to a SOC integrated circuit, and in particular to a CDM (Charged Device Model) protection structure of a SOC chip. Background Art

[0002] As the integration of SOC chips becomes higher and higher and CMOS technology becomes more and more advanced, how to improve CDM capabilities has become a very important issue.

[0003] In the semiconductor manufacturing and assembly process, it is relatively easy to control potential ESD problems of machines and personnel. Semiconductor devices include ESD protection circuits. To ensure the effectiveness and reliability requirements of the JEDEC standard, ESD testing must be performed to qualify the parts. There are three main test models for ESD testing: human body model (HBM), charging device model (CDM) and machine model (MM). Among them, the human body model and machine model are easier to simulate and control because of the external excitation drive signal and the long discharge time, which is farther than the working frequency band (>1GHz). CDM refers to the chip / bare die that has accumulated a large amount of charge inside itself due to external electric fields, frictional charging and other factors. When it comes into contact with the grounded conductor (the grounding here is a relative probability, as long as the potential is relatively low enough, it can be considered as grounding, such as ground potential or metal casing, tools, etc.), a large amount of charge escapes from the system, and an electrostatic pulse will be generated in a very short time. This pulse is the CDM discharge. The discharge characteristics of CDM are short time, high current pulse, and uncertain waveform. Its discharge time is shorter and the discharge phenomenon is more difficult to simulate.

[0004] With the advancement of CMOS technology, the operating voltage of transistors is developing towards low voltage, and the voltage and current capacity that transistors can withstand are also getting lower and lower. The CDM protection capability of chips is also receiving more and more attention from the industry. With the improvement of chip integration, especially the development of SOC chips, the chip area is getting larger and larger. The larger the area, the higher the charging energy, which makes the final discharge current larger and more likely to damage the device. The 22nm CMOS process, in the 10mm 2 Up to 100mm 2 The CDM capability of integrated circuit chips is between 150V and 250V, while the CDM capability that can be controlled by the chip assembly factory during the packaging factory and chip system integration assembly process can only reach 200V. In order to ensure that the chip does not have a reduced yield due to CDM failure, it is necessary to improve the CDM protection capability of the integrated circuit.

[0005] One method of protecting against CDM electrostatic discharge is to add parallel ESD clamp components to the chip's input port. This design includes adding series resistors and additional PMOS and NMOS transistors between the input port and the core device to enhance the protection effect. When charge accumulates inside the chip and the port is grounded, the ESD clamp component responds quickly, directing most of the current to the clamp component and limiting the voltage at the input port to a lower level (e.g. 5V). This clamping action reduces the voltage shock to the core device. Once the voltage drops to the point where the ESD clamp component is no longer effective, another ESD protection circuit is activated, allowing the remaining current to discharge through the transistor and series resistor to further protect the core device. This protection method is particularly effective for digital circuits because the input end of digital circuits usually processes 0V and full-amplitude signals, the signal is transmitted in the form of voltage, and the input impedance of the core component is large and the current is small. Even if a series resistor is added, the effect on the signal voltage is minimal. However, for analog circuits, especially those used in receiver systems such as low-noise amplifiers, such additional protection components may increase front-end losses and reduce receiver sensitivity.

[0006] Existing technologies are mainly used for CDM protection of digital circuits, and the industry has also done a lot of research on CDM protection of individual analog circuits. For chips with operating frequencies exceeding 5GHz, there are a variety of ESD (Electrostatic Discharge) protection design schemes to choose from. Among them, parallel LC resonators, impedance matching, T-coils, and harmonic distribution ESD protection schemes have shown good results in CDM protection. However, these schemes are achieved at the cost of occupying chip area and increasing design complexity. When the chip area remains unchanged, the accumulated charge inside the chip will eventually discharge through the pins. Although the frequency of discharge will be changed through the matching of the external circuit, this adjustment has limited effect on improving CDM protection capabilities.

[0007] It should be noted that the information disclosed in the above background technology section is only used for understanding the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0008] The main purpose of the present invention is to overcome the defects existing in the above-mentioned background technology and provide a CDM protection structure of a SOC chip and a SOC chip.

[0009] To achieve the above object, the present invention adopts the following technical solutions:

[0010] In a first aspect of the present invention, a CDM protection structure of a SOC chip includes:

[0011] A wafer and a substrate for packaging the wafer;

[0012] A digital ground PAD-DVSS and an analog ground PAD-AVSS are respectively connected to a digital circuit and an analog circuit on the wafer;

[0013] A radio frequency signal pin PIN-RF is provided on the substrate and connected to the analog circuit on the wafer;

[0014] Independent pins, used to lead the digital ground PAD-DVSS and the analog ground PAD-AVSS to the substrate respectively;

[0015] an inductor, arranged on the substrate, connecting the digital ground PAD-DVSS and the radio frequency signal pin PIN-RF, and used to control the CDM discharge path; the radio frequency signal pin PIN-RF cooperates with the digital ground PAD-DVSS through the inductor to transmit electrical signals and reduce the influence of CDM discharge on signal transmission, wherein the inductor slows down the release speed of the charge during the CDM discharge to protect the CMOS transistor connected to the radio frequency signal pin PIN-RF;

[0016] An ESD protection path, used for CDM discharge protection of the analog circuit, connected to the analog ground PAD-AVSS;

[0017] The charge of the analog circuit is discharged through the ESD protection path, while the charge of the digital circuit is discharged through the inductor and finally reaches the PIN-RF.

[0018] In a second aspect of the present invention, a CDM protection structure of a SOC chip includes:

[0019] A wafer and a substrate for packaging the wafer;

[0020] A first analog ground PAD-AVSS1 and a second analog ground PAD-AVSS2 are respectively connected to the first and second analog circuits on the wafer;

[0021] A radio frequency signal pin PIN-RF is provided on the substrate and connected to the first analog circuit on the wafer;

[0022] Independent pins, used to lead the first analog ground PAD-AVSS1 and the second analog ground PAD-AVSS2 to the substrate respectively;

[0023] an inductor, arranged on the substrate, connecting the second analog ground PAD-AVSS2 and the RF signal pin PIN-RF, and used to control the CDM discharge path; the RF signal pin PIN-RF cooperates with the second analog ground PAD-AVSS2 through the inductor to transmit electrical signals and reduce the influence of CDM discharge on signal transmission, wherein the inductor slows down the release speed of the charge during the CDM discharge to protect the CMOS transistor connected to the RF signal pin PIN-RF;

[0024] An ESD protection path, used for CDM discharge protection of an analog circuit, connected to the first analog ground PAD-AVSS1;

[0025] The charge of the first analog circuit is discharged through the ESD protection path, while the charge of the second analog circuit is discharged through the inductor and finally reaches the PIN-RF.

[0026] In a third aspect of the present invention, a SOC chip includes the CDM protection structure of the SOC chip.

[0027] The present invention has the following beneficial effects:

[0028] The present invention provides a CDM protection structure for a SOC chip, which can effectively improve the CDM protection capability of the chip while minimizing the loss of front-end devices. In particular, in a mixed digital-analog SOC integrated circuit, by introducing an inductor on the substrate and connecting the digital ground PAD-DVSS and the radio frequency signal pin PIN-RF, the present invention can control the CDM discharge path and slow down the charge release speed, thereby protecting the radio frequency signal pin from damage by electrostatic discharge. This design not only enhances the chip's protection against CDM events, but also has minimal impact on the quality of the radio frequency signal, ensuring the sensitivity of the receiver and the integrity of the signal transmission.

[0029] The digital ground and analog ground are led out to the substrate through independent pins, and the ESD protection path is used to discharge the analog circuit. The design of the present invention allows the charge to choose the path through the inductor when the CDM discharges, rather than directly through the sensitive device, thereby reducing the impact on the internal circuit of the chip. Through simulation modeling and actual testing, the present invention demonstrates the effective control of CDM discharge at different operating frequencies and the minimal impact on the quality of the RF signal, which is particularly important in high-frequency applications.

[0030] In addition, the CDM protection structure of the present invention also has good compatibility and can be applied to a single analog chip. By properly separating the ground of sensitive and non-sensitive devices on the wafer and connecting them through inductance on the package side, the CDM protection capability is further enhanced. This design achieves comprehensive protection of the SOC chip without significantly increasing the chip area and design complexity, improves the chip reliability and yield, and meets the effectiveness and reliability requirements of the JEDEC standard.

[0031] Other beneficial effects of the embodiments of the present invention will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the CDM protection structure of the digital-analog hybrid SOC chip according to an embodiment of the present invention.

[0033] Figure 2 This is the CDM discharge path diagram when no inductance is added.

[0034] Figure 3 This is a CDM discharge path diagram after adding inductance according to an embodiment of the present invention.

[0035] Figure 4 This is a simulation modeling diagram of an embodiment of the present invention.

[0036] FIG. 5A to FIG. 5C The figure shows the CDM simulation results when no inductance is added, which respectively shows the current at the PAD end, the current on the ESD, and the current on the LNA during CDM discharge.

[0037] FIG. 6A to FIG. 6D The results of CDM simulation of the embodiment of the present invention are shown respectively, showing the current at the PAD end, the current on the ESD, the current on the LNA, and the current on the newly added inductor branch during CDM discharge.

[0038] Figure 7 The figure is an analysis diagram of the impact on the quality of radio frequency signals after the chip containing the embodiment of the present invention is attached to the PCB.

[0039] Figure 8 The figure is a diagram of the CDM protection structure of a single analog chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following is a detailed description of the embodiments of the present invention. It should be emphasized that the following description is only exemplary and is not intended to limit the scope and application of the present invention.

[0041] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, connection can be used for fixing as well as for coupling or communication.

[0042] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0044] The present invention aims to reduce the loss of front-end devices in SOC integrated circuits as much as possible while effectively improving the CDM protection capability of the system, especially the CDM protection capability of SOC containing digital circuits and analog circuits. The present invention is also applicable to the CDM protection of a single analog SOC chip.

[0045] See also Figure 1 and Figure 3The embodiment of the present invention provides a CDM protection structure of a digital-analog hybrid SOC chip, including: a wafer 2 and a substrate 1 for packaging the wafer 2; a digital ground PAD-DVSS and an analog ground PAD-AVSS, respectively connected to a digital circuit and an analog circuit on the wafer 2; a radio frequency signal pin PIN-RF, arranged on the substrate 1, connected to the analog circuit on the wafer 2 through a radio frequency signal interface PAD-RF; independent pins PIN-DVSS and PIN-AVSS, used to lead the digital ground PAD-DVSS and the analog ground PAD-AVSS to the substrate 1 respectively; an inductor 3, arranged on the substrate 1, connecting the digital ground PAD-DVSS and the radio frequency signal pin PIN- RF, used to control the CDM discharge path; the RF signal pin PIN-RF cooperates with the digital ground PAD-DVSS through the inductor 3 to transmit electrical signals and reduce the impact of CDM discharge on signal transmission, wherein the inductor 3 slows down the release speed of the charge during the CDM discharge to protect the CMOS transistor connected to the RF signal pin PIN-RF, so that the internal core CMOS transistor device is protected from the risk of breakdown; the ESD protection path is used for the CDM discharge protection of the analog circuit, and is connected to the analog ground PAD-AVSS; wherein the charge of the analog circuit is discharged through the ESD protection path, and the charge of the digital circuit passes through the inductor 3 and finally reaches the PIN-RF for discharge. This CDM protection structure can improve the CDM protection capability of the chip without substantially affecting the receiver sensitivity, or with very little impact.

[0046] In some embodiments, the independent pins on the substrate may be connected to the digital ground PAD-DVSS and the analog ground PAD-AVSS on the wafer through wire bonding or flip-chip technology.

[0047] In a preferred embodiment, the digital ground PAD-DVSS and the analog ground PAD-AVSS are connected on the wafer in the form of a guard ring to reduce interference between different circuit parts.

[0048] See also Figure 1 and Figure 3 In a preferred embodiment, the inductor is connected between the independent pin PIN-DVSS of the digital ground PAD-DVSS and the radio frequency signal pin PIN-RF.

[0049] See also Figure 8The embodiment of the present invention also provides a CDM protection structure of a SOC chip (single analog chip) containing only analog circuits, including: a wafer 2 and a substrate 1 encapsulating the wafer 2; a first analog ground PAD-AVSS1 and a second analog ground PAD-AVSS2, respectively connected to a first analog circuit ("analog circuit 1") and a second analog circuit ("analog circuit 2") on the wafer 2; a radio frequency signal pin PIN-RF, arranged on the substrate 1, connected to the first analog circuit on the wafer 2 through a radio frequency signal interface PAD-RF; independent pins PIN-AVSS1 and PIN-AVSS2, used to lead the first analog ground PAD-AVSS1 and the second analog ground PAD-AVSS2 to the substrate 1 respectively; an inductor 3, arranged on the substrate 1, connecting the second analog ground PAD-AVSS2 and the radio frequency signal pin PIN-RF, The inductor 3 can be connected between the pin PIN-AVSS2 of the second analog ground PAD-AVSS2 and the RF signal pin PIN-RF to control the CDM discharge path; the RF signal pin PIN-RF and the second analog ground PAD-AVSS2 cooperate through the inductor 3 to transmit electrical signals and reduce the impact of CDM discharge on signal transmission, wherein the inductor 3 slows down the release speed of the charge during the CDM discharge to protect the transistor connected to the RF signal pin PIN-RF, so that the internal core CMOS transistor device is protected from the risk of breakdown; the ESD protection path is used for CDM discharge protection of the analog circuit and is connected to the first analog ground PAD-AVSS1; wherein the charge of the first analog circuit is discharged through the ESD protection path, and the charge of the second analog circuit passes through the inductor 3 and finally reaches PIN-RF for discharge.

[0050] An embodiment of the present invention further provides a SOC chip, comprising the CDM protection structure of the SOC chip of any of the aforementioned embodiments.

[0051] The SOC chip CDM protection structure of the present invention significantly improves the chip's protection capability against electrostatic discharge through carefully designed inductors and ESD protection paths. The structure controls the CDM discharge path by adding an inductor path, slows down the charge release speed, and reduces the current flowing through the core transistor to protect the transistor connected to the PIN-RF from damage. The present invention utilizes the inductive reactance characteristics of the inductor to hinder the high-frequency discharge current, thereby protecting the sensitive RF CMOS active transistor. This design not only improves the CDM protection capability of the chip, but also has minimal impact on the quality of the RF signal, ensuring the sensitivity of the receiver and the integrity of the signal transmission. In addition, through simulation modeling and testing, the present invention demonstrates effective control of CDM discharge at different operating frequencies and minimal impact on the quality of the RF signal. The present invention can provide comprehensive CDM protection for the SOC chip without significantly increasing the chip area and design complexity. This protection structure is particularly suitable for high-frequency applications, and can improve the CDM protection capability of the chip without affecting the sensitivity of the receiver, meet the effectiveness and reliability requirements of the JEDEC standard, and thus reduce the risk of yield reduction due to CDM failure.

[0052] The specific embodiments and experimental verification of the present invention are further described below.

[0053] A CDM protection structure for a SOC chip is designed based on a digital-analog hybrid SOC system, in which a bare wafer is packaged on a substrate. The digital ground and analog ground on the bare wafer are led out to the substrate through independent pins, and the radio frequency signal pin PIN-RF on the substrate is connected to the digital ground pin through an inductor.

[0054] like Figure 1 and Figure 3 As shown, the CDM protection structure of the embodiment of the present invention is particularly suitable for SOC system chips containing digital and analog circuits. On the wafer, the ground PAD-AVSS of the analog chip and the ground PAD-DVSS of the digital chip are connected in the form of a guard ring to reduce interference between different circuit parts. PAD-AVSS and PAD-DVSS can be separately led out to the substrate through leads or flip-chip. On the package side, the RF signal pin PIN-RF is connected to PIN-DVSS through an inductor to form an ESD3 path for discharge.

[0055] When the CDM is charged, the digital circuit and the analog circuit are charged at the same time. Figure 2 As shown in the figure, when the substrate does not add inductance, the charge of the analog circuit is discharged through the ESD1 path, while the charge of the digital circuit is discharged through the ESD2 path, passing through the sensitive device and finally reaching the PIN-RF. Figure 3As shown in the figure, after increasing the inductance between PIN-RF and PIN-DVSS, the charge of the analog circuit is still discharged through the ESD1 path. Since PAD-AVSS and PAD-DVSS inside the wafer have certain resistance characteristics, the charge of the digital circuit will pass through the newly formed ESD3 path, pass through the inductor on the substrate, and finally reach PIN-RF for discharge.

[0056] The design of the present invention significantly improves the CDM protection capability of the chip, especially for digital circuits with a larger area, the performance improvement is more obvious. Figure 4 The simulation modeling results of the present invention are shown, in which the charging equivalent capacitance of the packaged chip is simulated as 2pF, the substrate resistance is 15ohm, and the interconnection resistance of the digital ground and the analog ground is also 15ohm. The inductance added to the substrate is 3nH, the inductor resistance is between 0.5ohm and 5ohm, and the simulated CDM voltage is 250V.

[0057] FIG. 5A to FIG. 5C The results of CDM simulation without adding inductance are shown in Figure 5A is the current at the PAD end, Figure 5B is the current on the ESD, Figure 5C is the current in the low noise amplifier LNA. FIG. 6A to FIG. 6C The results of CDM simulation after adding inductance according to the solution of the present invention are shown, wherein Fig. 6A is the current at the PAD end, Figure 6B is the current on the ESD, Figure 6C is the current on the LNA. Compared with the case where the inductance is not added, the current flowing through the LNA is reduced from 0.149mA to 0.094mA. Assuming that the original LNA can withstand a voltage of 250V, the voltage that the present invention can withstand is 250V*0.149 / 0.094=396V.

[0058] Analysis of the impact on RF signal quality: After the chip containing the present invention is attached to the PCB, PIN-DVSS and PIN-AVSS are connected on the PCB. From the perspective of board-level RF, a large inductor and a long trace are connected in parallel to the ground at the RF connection port. The Q value of the inductor on the substrate can be very high. For example, the Q value of a 4nH inductor can reach more than 30. In addition, a high-resistance line of a certain length (width 6mil, length 4mm) is added to the substrate. Figure 7 As shown, assuming an RF system with 50 ohms input and output, its impact on the main frequency band 2.4 GHz is 0.296 dB, and 5.8 GHz and 8 GHz are less than 0.1 dB.

[0059] The present invention can also be used on a single analog chip, such as Figure 8As shown in the figure, the ground of the core components sensitive to CDM and the ground of the non-sensitive devices (but with a larger area and a larger amount of electricity when CDM is charged) are separated on the wafer (not completely separated, they will still be connected through psub, but with a larger resistance value), and then the grounds PAD-AVSS1 and PAD-AVSS2 of the core components sensitive to CDM are brought out separately, and on the package side, the protected pins PIN-RF and PIN-AVSS2 are connected through inductance, thereby achieving the purpose of increasing the CDM protection capability.

[0060] The above content is a further detailed description of the present invention in combination with specific / preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, without departing from the concept of the present invention, it can also make several substitutions or modifications to these described embodiments, and these substitutions or modifications should be regarded as belonging to the protection scope of the present invention. In the description of this specification, the description of reference terms "an embodiment", "some embodiments", "preferred embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in combination with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In the absence of mutual contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the scope of protection of the patent application.

Claims

1. A CDM protection structure of a SOC chip, characterized in that: include: A wafer and a substrate for packaging the wafer; A digital ground PAD-DVSS and an analog ground PAD-AVSS are respectively connected to a digital circuit and an analog circuit on the wafer; A radio frequency signal pin PIN-RF is provided on the substrate and connected to the analog circuit on the wafer; Independent pins, used to lead the digital ground PAD-DVSS and the analog ground PAD-AVSS to the substrate respectively; An inductor, arranged on the substrate, connected to the digital ground PAD-DVSS and the radio frequency signal pin PIN-RF, and used for controlling the CDM discharge path; The RF signal pin PIN-RF cooperates with the digital ground PAD-DVSS through the inductor to transmit an electrical signal and reduce the impact of CDM discharge on signal transmission, wherein the inductor slows down the release speed of the charge during the CDM discharge to protect the CMOS transistor connected to the RF signal pin PIN-RF; An ESD protection path, used for CDM discharge protection of the analog circuit, connected to the analog ground PAD-AVSS; The charge of the analog circuit is discharged through the ESD protection path, while the charge of the digital circuit is discharged through the inductor and finally reaches the PIN-RF.

2. The CDM protection structure of the SOC chip according to claim 1, characterized in that: The independent pins on the substrate are connected to the digital ground PAD-DVSS and the analog ground PAD-AVSS on the wafer through wire connection or flip-chip technology.

3. The CDM protection structure of the SOC chip according to claim 1 or 2, characterized in that: The digital ground PAD-DVSS and the analog ground PAD-AVSS are connected on the wafer in the form of a guard ring to reduce interference between different circuit parts.

4. The CDM protection structure of the SOC chip according to claim 1 or 2, characterized in that: The inductor is connected between an independent pin of the digital ground PAD-DVSS and the radio frequency signal pin PIN-RF.

5. A CDM protection structure of a SOC chip, characterized in that: include: A wafer and a substrate for packaging the wafer; A first analog ground PAD-AVSS1 and a second analog ground PAD-AVSS2 are respectively connected to the first and second analog circuits on the wafer; A radio frequency signal pin PIN-RF is provided on the substrate and connected to the first analog circuit on the wafer; Independent pins, used to lead the first analog ground PAD-AVSS1 and the second analog ground PAD-AVSS2 to the substrate respectively; an inductor, arranged on the substrate, connected to the second analog ground PAD-AVSS2 and the radio frequency signal pin PIN-RF, and used for controlling the CDM discharge path; The RF signal pin PIN-RF cooperates with the second analog ground PAD-AVSS2 through the inductor to transmit an electrical signal and reduce the impact of CDM discharge on signal transmission, wherein the inductor slows down the release speed of the charge during the CDM discharge to protect the CMOS transistor connected to the RF signal pin PIN-RF; An ESD protection path, used for CDM discharge protection of an analog circuit, connected to the first analog ground PAD-AVSS1; The charge of the first analog circuit is discharged through the ESD protection path, while the charge of the second analog circuit is discharged through the inductor and finally reaches the PIN-RF.

6. The CDM protection structure of the SOC chip as claimed in claim 5, characterized in that: The independent pins on the substrate are connected to the first analog ground PAD-AVSS1 and the second analog ground PAD-AVSS2 on the wafer through wire connection or flip-chip technology.

7. The CDM protection structure of the SOC chip according to claim 5 or 6, characterized in that: The first analog ground PAD-AVSS1 and the second analog ground PAD-AVSS2 are connected on the wafer in the form of a guard ring to reduce interference between different circuit parts.

8. The CDM protection structure of the SOC chip according to claim 5 or 6, characterized in that: The inductor is connected between an independent pin of the second analog ground PAD-AVSS2 and the radio frequency signal pin PIN-RF.

9. A SOC chip, characterized in that: A CDM protection structure comprising a SOC chip as claimed in any one of claims 1 to 8.

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