Semiconductor device

Abstract

The semiconductor device includes an electronic component and a substrate disposed facing each other in a first direction, and a solder connecting the electronic component and the substrate, the electronic component having a first electrode on a surface facing the substrate, and the substrate having a second electrode on a surface facing the electronic component. The solder has a bonding portion, which is an intermetallic compound, at the interface with the electronic component and the substrate, the solder has Sn as the main component, and the variation in the thickness of the bonding portion in the first direction is less than 2 [mu] m.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In recent years, with the purpose of miniaturization, high density and high functionality of electronic devices, semiconductor devices have been required to be miniaturized and high-densified, and area array packaged semiconductor devices such as BGA (Ball Grid Array) and CSP (Chip Size Package) have been widely used. In area array packaged semiconductor devices, uniform electrodes and solder balls are formed on the back with a fixed size, fixed area and fixed pitch. The electrodes of the wiring substrate are also formed with a fixed size, fixed area and fixed pitch to correspond to these electrodes and solder balls.

[0003] In an area array type packaged semiconductor device, electrodes and solder balls are pre-formed by the package manufacturer, and the composition of the solder balls is generally Sn-3.0Ag-0.5Cu. By using solder balls, solder is formed on the electrodes of the wiring substrate, and by mounting the packaged semiconductor device and heating it, solder bumps are formed to join the corresponding electrodes to each other. Solder bumps can be arranged in large quantities in a fixed area by reducing the size and spacing, which is conducive to miniaturization and high density. The wiring length of the solder bump is shorter than that of the structure connected via a lead, so it is conducive to high-speed transmission and can achieve high performance. It can be considered that with the increasing requirements for the electrification, EV, and mechatronics of automobiles, there will be more opportunities for the installation of on-board electronic control devices in high-temperature parts such as the engine periphery and the motor periphery.

[0004] Patent document 1 discloses a mounting structure, characterized in that it includes a BGA having a BGA electrode, a circuit substrate having a circuit substrate electrode, and a solder joint portion arranged on the circuit substrate electrode and connected to the BGA electrode, wherein the solder joint portion includes: Cu having a Cu content of not less than 0.6 mass% and not more than 1.2 mass%; Ag having a Ag content of not less than 3.0 mass% and not more than 4.0 mass%; and Bi having a Bi content of not less than 0 mass% and not more than 1.0 mass%, and the mounting structure satisfies any one of the following (1) to (3): (1) within the range of a Cu content of not less than 0.6 mass% and not more than 0.91 mass%, an In content of not less than 5 mass% and not more than 1.0 mass%; .3+(6-(1.55×Cu content+4.428))mass% to 6.8+(6-(1.57×Cu content+4.564))mass%, and the remainder is composed of Sn; (2) in the range of Cu content greater than 0.91mass% and less than 1.0mass%, the In content is greater than 5.3+(6-(1.55×Cu content+4.428))mass% to 6.8mass%, and the remainder is composed of Sn; (3) in the range of Cu content greater than 1.0mass% and less than 1.2mass%, the In content is greater than 5.3mass% to 6.8mass%, and the remainder is composed of Sn. Prior art literature Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-111072 Summary of the invention Technical problem to be solved by the invention

[0006] In the invention described in Patent Document 1, a countermeasure against void destruction is unknown. Technical solutions to technical problems

[0007] The semiconductor device of the first embodiment of the present invention includes an electronic component and a substrate arranged relative to each other in a first direction, and a solder connecting the electronic component and the substrate, wherein the electronic component has a first electrode on a surface opposite to the substrate, and the substrate has a second electrode on a surface opposite to the electronic component, and the solder has a joint portion as an intermetallic compound at the interface with each of the first electrode and the second electrode, the solder has Sn as a main component, and the deviation of the thickness of the joint portion in the first direction is less than 2 microns. Effects of the Invention

[0008] According to the present invention, void destruction of solder can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is an external view of a semiconductor device. Figure 2 is a detailed picture of the solder bump. Figure 3 This is a diagram showing the presence or absence of void destruction due to the difference in the shape of the lower intermetallic compound. Figure 4 The diagram shows the manufacturing process of a semiconductor device. Figure 5 This is a diagram showing the results of the temperature cycle test in the second embodiment. Figure 6 This is a diagram showing the results of the first temperature cycle test in the third embodiment. Figure 7 This is a diagram showing the results of the second temperature cycle test in the third embodiment. DETAILED DESCRIPTION

[0010] —Implementation Method 1— Below, refer to Figure 1 to Figure 4 Embodiment 1 of the semiconductor device will be described.

[0011] Reference Figure 1 to Figure 4 Implementation method 1 will be described. Figure 1 1 is an external view of the semiconductor device 100. In order to clarify the correlation between the drawings, mutually orthogonal XYZ axes are defined. Hereinafter, the Z-axis direction is also referred to as the "first direction". Figure 1 In the middle, the inner side is the Y axis. Figure 1 As shown, the semiconductor device 100 has a wiring substrate 1 and a semiconductor package 2 as an electronic component. The semiconductor package 2 is an area array type package. The wiring substrate 1 has a plurality of lower electrodes 4 on the upper surface. The semiconductor package 2 has a plurality of upper electrodes 3 on the lower surface, and is mounted opposite to the plurality of lower electrodes 4 and the wiring substrate 1 via solder balls 5 provided on the upper electrodes 3, forming solder bumps 7. Hereinafter, the upper electrode 3 is also referred to as the "first electrode", and the lower electrode 4 is also referred to as the "second electrode".

[0012] Figure 2 yes Figure 1 Detailed view of the solder bump 7 shown. When the solder ball 5 and the solder paste 6 described later are heated and melted to form the solder bump 7, a lower intermetallic compound 8a is formed at the interface between the lower electrode 4 and the solder bump 7. Similarly, an upper intermetallic compound 8b is also formed at the interface between the upper electrode 3 and the solder bump 7. In the case of BGA packaging, the upper intermetallic compound 8b is formed when the package manufacturer mounts the solder ball 5, and can also grow by heating and melting when connected to the wiring substrate 1. Hereinafter, the lower intermetallic compound 8a and the upper intermetallic compound 8b are also referred to as the "joining portion" 8.

[0013] Figure 3 This is a diagram showing whether or not void destruction occurs due to the difference in shape of the lower intermetallic compound 8a. Figure 3 The left side of shows the case where the thickness deviation of the lower intermetallic compound 8a is 2 μm or more. Figure 3 The right side of shows the case where the deviation of the thickness of the lower intermetallic compound 8a is less than 2 μm. Figure 3 The upper part is a schematic diagram. Figure 3 The middle part is an enlarged picture. Figure 3 The lower section is a wide area view. The enlarged view and the wide area view are the actual observation results, and the scales on the left and right are consistent. The details of the middle section and the lower section will be described later. The thickness deviation of the lower intermetallic compound 8a is the difference between the maximum and minimum thickness of the lower intermetallic compound 8a, which is Figure 3 The length L1 or the length L2 in the embodiment. The length L1 is greater than 2 μm, and the length L2 is less than 2 μm.

[0014] When the deviation of the thickness of the lower intermetallic compound 8a in the Z direction is more than 2μm, it is believed that stress concentration is easily caused and microvoids are easily generated. In contrast, if the deviation of the thickness of the intermetallic compound in the Z direction is small, stress concentration is not easily caused, and the generation of microvoids can be suppressed. The cross-sectional observation results of the BGA joints of the solder ball with a diameter of 0.8mm and the solder paste 6 printed on the corresponding electrode are all Sn-3.0Ag-0.5Cu in the middle section. In this regard, a temperature cycle test was carried out for 500 cycles in which the ambient temperature was alternately changed between -40°C and 125°C. The cross-sectional observation results after 500 cycles are shown in the lower section.

[0015] In the case where the deviation of the thickness of the lower intermetallic compound 8a in the Z direction is large, microvoids are generated at the interface between the joint 8 and the lower intermetallic compound 8a after 500 cycles. On the other hand, in the case where the deviation of the thickness of the lower intermetallic compound 8a in the Z direction is small, no microvoids are generated at the interface between the joint 8 and the lower intermetallic compound 8a after 500 cycles. In detail, the dimension ratio of the width direction to the Z direction of the lower intermetallic compound 8a is less than 1:1, the Z direction is smaller, and the particle size in the Z direction is less than 2μm. In this case, void destruction can be suppressed. Among them, the width direction of the lower intermetallic compound 8a is the dimension of the root of the lower intermetallic compound 8a, such as W1 or W2 in the upper section. The Z direction of the lower intermetallic compound 8a is the dimension from the root to the vertex.

[0016] Figure 4 1 is a diagram showing a manufacturing process of a semiconductor device 100. The semiconductor device 100 includes a wiring substrate 1 and a semiconductor package 2. Figure 4As shown in (a), the wiring substrate 1 has a plurality of lower electrodes 4 on the upper surface, that is, the surface on the positive side of the Z axis. Figure 4 As shown in (b), solder paste 6 is formed on each lower electrode 4. The solder paste 6 may be formed by printing or applied by a dispenser, but the forming method is not limited thereto.

[0017] like Figure 4 As shown in (c), a semiconductor package 2 having a plurality of upper electrodes 3 on its lower surface and solder balls 5 on its lower surface is arranged on solder paste 6. The semiconductor package 2 is arranged using, for example, a mounting machine. When heated using a reflow furnace or the like, Figure 4 (c) is the structure shown in Figure 4 (d) shows the semiconductor device 100. Figure 4 The solder bump 7 shown in (d) is formed by melting the solder ball 5 and the solder paste 6 and then cooling them.

[0018] In order to reduce the particle size of the intermetallic compound, a series of efforts are required, such as the optimization of the joint profile, the temperature control after the joint, the optimization of the metallization of the components, and the optimization of the solder composition used in the welding. As an effort for the metallization of the components, a method of joining with a Ni-plated electrode on either the surface or the base can be cited. In addition, as an effort for the solder composition used in the welding, the intermetallic compound can be a Ni-Sn compound alone, a Cu-Sn compound and a Ni-Sn compound can be contained in any proportion, etc.

[0019] According to the above-described first embodiment, the following effects can be obtained. (1) The semiconductor device 100 has a semiconductor package 2 and a wiring substrate 1 arranged relative to each other in a first direction, i.e., the Z-axis direction, and a solder bump 7 connecting the semiconductor package 2 and the wiring substrate 1. The semiconductor package 2 has a first electrode, i.e., an upper electrode 3, on a surface opposite to the wiring substrate 1. The wiring substrate 1 has a second electrode, i.e., a lower electrode 4, on a surface opposite to the semiconductor package 2. The solder bump 7 has a joint 8 as an intermetallic compound at the interface with the upper electrode 3 and the lower electrode 4, respectively. The solder contains Sn as a main component. The deviation of the thickness of the joint 8 in the Z-axis direction is less than 2 microns. Therefore, if Figure 3 As shown on the right side of , void destruction in solder bump 7 can be suppressed.

[0020] In the past, the following problem has been known, namely, in a high temperature environment, tiny gaps (micro voids) are generated between the solder and the intermetallic compound, and when they are connected, cracks progress at the electrode interface, resulting in a reduction in life. In addition, it is known that due to the difference in linear expansion coefficients of the components on the solder bump, it is deformed under temperature load, and stress is applied to the solder bump at the outermost periphery of the BGA package, causing cracks to progress in the solder. If these also occur at the same time as the crack progresses at the electrode interface, the life until the solder bump breaks is shortened, and reliability is further impaired. However, in the semiconductor device 100 of the present embodiment, by suppressing the deviation in the thickness of the joint 8 in the Z-axis direction to less than 2 microns, it is possible to suppress such problems. Figure 3 The void in solder bump 7 shown on the right side is destroyed.

[0021] (2) The semiconductor package 2 and the solder form a ball grid array package. Therefore, the upper electrode 3 and the solder bump 7 are bonded in advance, and void destruction in the upper intermetallic compound 8b is less likely to occur.

[0022] —Implementation Method 2— Reference Figure 5 Embodiment 2 of the semiconductor device is described. In the following description, the same reference numerals are given to the same components as those in Embodiment 1, and the differences are mainly described. The points not specifically described are the same as those in Embodiment 1. In this embodiment, the composition of the solder is mainly different from that in Embodiment 1. In the above-mentioned Embodiment 1, the content of Bi (bismuth) in the solder is not particularly limited. In this embodiment, the content of Bi contained in the bonding portion 8 is specified.

[0023] Figure 5 The figure shows the results of the temperature cycle test when the content of Bi contained in the bonding portion 8 is 3.0 wt% and 2.6 wt%. The temperature cycle test is a test in which the ambient temperature is alternately changed between -40°C and 125°C for 500 cycles. Figure 5 When the Bi content shown in the upper part is 3.0 wt%, micro voids are generated after the temperature cycle test, and they are connected and develop into cracks. Figure 5 In the case where the Bi content shown in the lower part is 2.6 wt%, no micro voids are generated even after the temperature cycle test. In addition, in any case, the deviation of the thickness in the Z direction of the lower intermetallic compound 8a formed at the interface between the joint 8 and the lower electrode 4 is 2 μm or more. Therefore, even if the deviation of the thickness in the Z direction of the joint 8 is 2 μm or more, when the Bi content of the joint 8 is less than 3.0 wt%, void destruction can be suppressed.

[0024] According to the above-mentioned second embodiment, the following effects can be obtained. (3) The semiconductor device 100 has a semiconductor package 2 and a wiring substrate 1 arranged relative to each other in a first direction, and solder connecting the semiconductor package 2 and the wiring substrate 1. The semiconductor package 2 has a first electrode, namely, an upper electrode 3, on a surface opposite to the wiring substrate 1. The wiring substrate 1 has a second electrode, namely, a lower electrode 4, on a surface opposite to the semiconductor package 2. The solder bump 7 has a joint 8 as an intermetallic compound at the interface with the upper electrode 3 and the lower electrode 4, respectively. The solder bump 7 contains Sn as a main component. The deviation of the thickness of the joint 8 in the Z-axis direction is more than 2 microns, and the Bi content of the joint 8 is less than 3.0% by weight. Therefore, as Figure 5 As shown in the lower part of , even if the thickness of the bonding portion 8 in the Z-axis direction has a deviation of 2 micrometers or more, void destruction can be suppressed by modifying the composition of the solder.

[0025] —Implementation Method 3— Reference Figure 6-7 , Embodiment 3 of the semiconductor device is described. In the following description, the same reference numerals are given to the same components as those in Embodiment 1, and the differences are mainly described. Points not specifically described are the same as those in Embodiment 1. In this embodiment, the composition of the solder is mainly different from that in Embodiment 1 and Embodiment 2.

[0026] Figure 6 Graph showing the cycle test results when the composition of the bonding portion 8 is Sn-3.9Ag-0.5Cu-3.0Sb. Figure 6 In the figure, the left side shows the case where the deviation of the thickness in the Z direction of the lower intermetallic compound 8a formed on the interface between the joint 8 and the lower electrode 4 is less than 2μm, and similarly the right side shows the case where it is greater than 2μm. In this temperature cycle test, the ambient temperature is varied between -40°C and 125°C as in other embodiments. However, in this embodiment, observations were made after 500 cycles and 2000 cycles, respectively. In the observation results after 500 cycles shown in the upper section, no microvoids were generated regardless of the deviation of the thickness in the Z direction of the lower intermetallic compound 8a. In the observation results after 2000 cycles shown in the lower section, cracks that progressed in the joint 8 due to thermal fatigue damage were confirmed, but no microvoids were generated on the joint interface.

[0027] Figure 7 : is a graph showing the cycle test results when the composition of the bonding portion 8 is Sn-4.0Ag-0.5Cu. That is, Figure 7The bonding portion 8 shown does not contain Bi. In this case, the particle size of the lower intermetallic compound 8a formed at the interface between the bonding portion 8 and the lower electrode 4 in the Z direction is 2 μm or more. In this temperature cycle test, the ambient temperature was changed between -40°C and 125°C as in the previous test, and observations were made after 500 cycles and 1000 cycles, respectively.

[0028] like Figure 7 As shown in FIG. 1 , no microvoids were generated after 500 cycles, but microvoids were generated after 1000 cycles. Figure 3 .like Figure 3 As shown on the left side of , the composition of the bonding portion 8 is Sn-3.0Ag-0.5Cu, the deviation of the thickness of the lower intermetallic compound 8a in the Z direction is 2 μm or more, and micro voids are generated by the temperature cycle test.

[0029] According to the present embodiment Figure 6 and Figure 7 , Implementation Method 1 Figure 3 The observation results shown on the left side of show the following. That is, by including more Ag in the solder, the Ag3Sn network increases, and the generation area of ​​microvoids is dispersed, so there is a tendency to suppress void damage. However, it can be considered that due to the solid solution strengthening of Sb, the deformation performance becomes larger, the stress acting on the grain boundary is relaxed, and the effect of suppressing microvoids at the joint interface is greater. It can be seen that when the joint 8 does not contain Bi and the Sb content is 3.0 weight% or more, void damage can be best suppressed.

[0030] According to the third embodiment described above, the following effects can be obtained. (4) In the bonding portion 8, the content of Bi is less than 3.0 wt. %, and the content of Sb is 3.0 wt. % or more. Figure 6 As shown, the generation of micro voids can be suppressed regardless of the variation in the thickness of the bonding portion 8 in the Z direction.

[0031] (5) The thickness deviation of the bonding portion 8 in the Z-axis direction is 2 micrometers or more, the bonding portion 8 does not contain Bi and the Sb content is 3.0 wt% or more. Figure 7 As shown, void destruction can be suppressed.

[0032] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various changes can be made within the scope of the gist thereof. In addition, in order to explain the present invention in an easy-to-understand manner, the above embodiments have been described in detail, but are not limited to all structures that must be provided with the description.

[0033] The electronic control device involved in the present invention has a built-in structure that connects the area array type package to the wiring substrate 1 via the solder bump 7. If the particle size of the intermetallic compound formed on the interface between the joint 8 and the electrode in the Z direction is less than 2μm, void destruction can be suppressed. Even if the particle size of the intermetallic compound in the Z direction is greater than 2μm, as long as the components of the joint 8 do not contain Bi and the Sb content is greater than 3.0 weight %, the respective sizes and their ratios and shapes are not limited to the structure of the figure, and the structural components such as the area array type package or wiring substrate used are arbitrary.

[0034] The above-mentioned embodiments and modifications can be combined respectively. Although various embodiments and modifications are described above, the present invention is not limited to these contents. Other modes that can be considered within the scope of the technical concept of the present invention are also included in the scope of the present invention. Description of symbols

[0035] 1: Wiring substrate 2: Semiconductor packaging 3: Upper electrode 4: Lower electrode 5: Solder ball 6: Solder paste 7: Solder Bumps 8: Joint 8a: Lower intermetallic compound 8b: Upper intermetallic compound 100: Semiconductor device.

Claims

1. A semiconductor device comprising an electronic component and a substrate arranged opposite to each other in a first direction, and solder connecting the electronic component and the substrate, wherein: The electronic component has a first electrode on a surface facing the substrate. The substrate has a second electrode on a surface facing the electronic component. The solder has a bonding portion as an intermetallic compound at the interface with each of the first electrode and the second electrode. The solder contains Sn as a main component. The thickness of the bonding portion in the first direction has a deviation of less than 2 micrometers.

2. The semiconductor device according to claim 1, wherein The electronic component and the solder form a ball grid array package.

3. A semiconductor device comprising an electronic component and a substrate arranged opposite to each other in a first direction, and solder connecting the electronic component and the substrate, wherein: The electronic component has a first electrode on a surface facing the substrate. The substrate has a second electrode on a surface facing the electronic component. The solder has a bonding portion as an intermetallic compound at the interface with each of the first electrode and the second electrode. The solder contains Sn as a main component. The thickness deviation of the bonding portion in the first direction is 2 micrometers or more, The Bi content of the bonding portion is less than 3.0% by weight.

4. The semiconductor device according to claim 3, wherein: In the bonding portion, the content of Bi is less than 3.0% by weight, and the content of Sb is 3.0% by weight or more.

5. A semiconductor device comprising an electronic component and a substrate arranged opposite to each other in a first direction, and solder connecting the electronic component and the substrate, wherein: The electronic component has a first electrode on a surface facing the substrate. The substrate has a second electrode on a surface facing the electronic component. The solder has a bonding portion as an intermetallic compound at the interface with each of the first electrode and the second electrode. The solder contains Sn as a main component. The thickness deviation of the bonding portion in the first direction is 2 micrometers or more, The bonding portion does not contain Bi, and the Sb content of the bonding portion is 3.0 wt % or more.

Images