Imaging device and electronic apparatus

Abstract

The invention provides an imaging device and an electronic apparatus capable of suppressing deterioration of device characteristics. The imaging device includes: a sensor substrate including a pixel region in which a plurality of pixels performing photoelectric conversion are arranged side by side; a circuit substrate bonded to one surface side of the sensor substrate, the circuit substrate including a circuit that processes a signal input to the sensor substrate or a signal output from the sensor substrate; and a voltage supply terminal that is provided on the opposite side of the surface of the circuit board facing the sensor board and supplies a power supply voltage or a reference voltage to the circuit. At least a portion of the voltage supply terminal is disposed at a position overlapping the pixel region in a thickness direction of a laminated substrate including the sensor substrate and the circuit substrate.

Description

Technical Field

[0001] The present technology relates to an imaging device and an electronic device. Background Art

[0002] A configuration in which a plurality of semiconductor substrates are stacked on one another has been proposed for an imaging device such as a CMOS image sensor (for example, see Patent Document 1).

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-72294 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] The imaging device includes a pixel area in which pixels are regularly arranged in a two-dimensional array and a peripheral area located around the pixel area. The electrode pads arranged in the peripheral area and the logic circuit arranged at a position overlapping with the pixel area are connected to each other by wiring, and the power supply voltage, etc. are supplied to the logic circuit via the wiring. When the number of stacking layers of the wiring or the number of stacking layers of the semiconductor substrate increases, the wiring length from the electrode pad to the logic circuit increases, and IR drop (voltage drop) is likely to occur. IR drop may cause degradation of device characteristics. In particular, in the case of using the most advanced devices that require high-speed operation, the degradation of device characteristics caused by IR drop is often obvious.

[0008] The present disclosure has been made in view of such circumstances, and an object thereof is to provide an imaging apparatus and an electronic device capable of suppressing degradation of device characteristics.

[0009] Solution to the problem

[0010] An imaging device according to one aspect of the present disclosure includes: a sensor substrate including a pixel area in which a plurality of pixels performing photoelectric conversion are arranged side by side; a circuit substrate bonded to one surface side of the sensor substrate, the circuit substrate including a circuit for processing a signal input to the sensor substrate or a signal output from the sensor substrate; and a voltage supply terminal, which is arranged on the opposite side of the surface of the circuit substrate facing the sensor substrate and supplies a power supply voltage or a reference voltage to the circuit, wherein at least a portion of the voltage supply terminal is arranged at a position overlapping with the pixel area in the thickness direction of a stacked substrate including the sensor substrate and the circuit substrate.

[0011] According to this, the power supply voltage or the reference voltage is supplied to the circuit of the circuit substrate from the opposite side of the surface of the circuit substrate facing the sensor substrate (for example, the back side of the circuit substrate). For example, compared with the case where the power supply voltage or the reference voltage is supplied to the circuit of the circuit substrate from the peripheral area side of the sensor substrate, the imaging device can shorten the path for supplying the power supply voltage or the reference voltage (hereinafter also referred to as the voltage supply path) and the length of the wiring to which the voltage is applied. As a result, the imaging device can suppress IR drop and can suppress the degradation of device characteristics.

[0012] An electronic device according to another aspect of the present disclosure includes an imaging device and an optical system, which enables the imaging device to form an image of image light from a subject, wherein the imaging device includes: a sensor substrate, which includes a pixel area in which a plurality of pixels performing photoelectric conversion are arranged side by side; a circuit substrate, which is bonded to one surface side of the sensor substrate, the circuit substrate including a circuit for processing a signal input to the sensor substrate or a signal output from the sensor substrate; and a voltage supply terminal, which is arranged on the opposite side of the surface of the circuit substrate facing the sensor substrate and supplies a power supply voltage or a reference voltage to the circuit, wherein at least a portion of the voltage supply terminal is arranged at a position overlapping with the pixel area in the thickness direction of a stacked substrate including the sensor substrate and the circuit substrate.

[0013] According to this, since the electronic device includes the imaging device capable of suppressing the degradation of device characteristics due to IR drop, performance degradation can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 : is a diagram showing a configuration example of an imaging device according to a first embodiment of the present disclosure.

[0015] Figure 2 is a circuit diagram showing a configuration example of a pixel.

[0016] Figure 3 FIG. 1 is a plan view schematically showing an example of arrangement of a pixel region and a peripheral region in a sensor substrate.

[0017] Figure 4 is a cross-sectional view illustrating a configuration example of an imaging device according to a first embodiment of the present disclosure.

[0018] Figure 5 : is a plan view showing a configuration example of bump electrodes according to the first embodiment of the present disclosure.

[0019] Figure 6 is a cross-sectional view showing a configuration example of a via hole according to the first embodiment of the present disclosure.

[0020] Figure 7: is a diagram schematically showing a path (voltage supply path) for supplying a power supply voltage or a reference voltage from a bump electrode for voltage supply to a logic circuit in the imaging device according to the first embodiment of the present disclosure.

[0021] Fig. 8A 2 is a cross-sectional view showing a method of manufacturing an imaging device according to a first embodiment of the present disclosure in order of steps.

[0022] Figure 8B is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0023] Figure 8C is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0024] Fig.8D is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0025] Fig. 8E is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0026] Figure 8F is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0027] Figure 8G is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0028] Figure 8H is another cross-sectional view showing the method of manufacturing the imaging device according to the first embodiment of the present disclosure in order of steps.

[0029] Fig. 9 is a cross-sectional view showing the configuration of an imaging device according to Comparative Example 1 of the present disclosure.

[0030] Fig.10 is a cross-sectional view showing the configuration of an imaging device according to Comparative Example 2 of the present disclosure.

[0031] Fig.11 is a cross-sectional view illustrating a configuration of an imaging device according to a first modification example of the first embodiment of the present disclosure.

[0032] Fig.12 is a cross-sectional view illustrating a minute via hole of an imaging device according to a first modification example of the first embodiment of the present disclosure.

[0033] Fig.13is a cross-sectional view illustrating a configuration example of an imaging device according to a second embodiment of the present disclosure.

[0034] Fig.14 is a cross-sectional view showing a configuration example of a via hole according to a second embodiment of the present disclosure.

[0035] Fig.15 is a diagram schematically showing a voltage supply path of an imaging device according to a second embodiment of the present disclosure.

[0036] Fig.16 is a cross-sectional view illustrating a configuration of an imaging device according to a first modification example of the second embodiment of the present disclosure.

[0037] Fig.17 : is a diagram schematically showing a voltage supply path of an imaging device according to a first modification example of the second embodiment of the present disclosure.

[0038] Fig.18 is a cross-sectional view illustrating a configuration of an imaging device according to a second modification example of the second embodiment of the present disclosure.

[0039] Fig.19 : is a diagram schematically showing a voltage supply path of an imaging device according to a second modification example of the second embodiment of the present disclosure.

[0040] Fig. 20 The diagram shows a configuration example of an electronic device to which the technology according to the present disclosure (the present technology) is applied.

[0041] Fig.21 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) is applied.

[0042] Fig. 22 It is shown Fig.21 A block diagram of an example of the functional configuration of a camera and a camera control unit (CCU) is shown.

[0043] Fig.23 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applied.

[0044] Fig.24 : is a diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the illustrations of the accompanying drawings referred to in the following description, the same or similar parts are represented by the same or similar figure marks. Note that the accompanying drawings are only schematic diagrams, and the relationship between thickness and plane size, the ratio of each layer in thickness, etc. may not be consistent with what actually occurs. Therefore, the specific thickness and size should be determined in consideration of the following description. In addition, it goes without saying that the dimensional relationship or ratio between the drawings is partially different.

[0046] The definitions of directions such as upward and downward in the following description are only for convenience of explanation and do not limit the technical concept of the present disclosure. For example, it goes without saying that when the object is rotated 90° and observed, upward and downward are converted to right and left, and when the object is rotated 180° and observed, up and down are reversed.

[0047] In the following description, there will be cases where terms such as the X-axis direction, the Y-axis direction, and the Z-axis direction are used to explain directions. For example, the X-axis direction and the Y-axis direction are directions parallel to the back side 1b of the sensor substrate 1 described later. The back side 1b of the sensor substrate 1 is also the back side 111b of the stacked substrate 111 including the sensor substrate 1 and the logic substrate 2 described later. The X-axis direction and the Y-axis direction are also referred to as horizontal directions. The Z-axis direction is the normal direction of the back side 11b of the sensor substrate 11 (i.e., the back side 111b of the stacked substrate 111). The Z-axis direction is also the thickness direction of the stacked substrate 111. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0048] In the following description, a “plan view” refers to, for example, a view viewed from the thickness direction (for example, the Z-axis direction) of the laminated substrate 111 .

[0049] <First embodiment>

[0050] (Overall structure example)

[0051] Figure 1 is a diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present disclosure. For example, Figure 1 The imaging device 100 shown is a complementary metal oxide semiconductor field effect transistor (CMOS) image sensor. Figure 1 As shown, the imaging device 100 includes a pixel region (so-called imaging region) R1, in which a plurality of pixels 102 that perform photoelectric conversion are regularly arranged two-dimensionally, and a logic circuit 113 (an example of a “circuit” in the present disclosure). The pixel 102 includes a photodiode and a pixel transistor as a photoelectric conversion element. Figure 2 An example configuration of each pixel 102 will be described.

[0052] The logic circuit 113 includes, for example, the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, the output circuit 107, and the control circuit 108. The logic circuit 113 is, for example, a CMOS circuit. The CMOS circuit is a circuit including n-channel MOSFET and p-channel MOSFET.

[0053] The control circuit 108 receives data such as an input clock and a designated operation mode, and outputs data such as internal information about the imaging device. That is, the control circuit 108 generates a clock signal and a control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock, and the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, etc. operate based on these signals. Then, the control circuit 108 inputs these signals to the vertical drive circuit 104, the column signal processing circuit 105, and the horizontal drive circuit 106.

[0054] The vertical drive circuit 104 is, for example, a shift register, selects a pixel drive line, supplies a pulse for driving a pixel to the selected pixel drive line, and drives the pixel in a row unit. That is, the vertical drive circuit 104 sequentially selects and scans each pixel 102 in the pixel region R1 in a vertical direction in a row unit, and supplies a pixel signal based on a signal charge generated by a photoelectric conversion element of each pixel 102 according to the amount of received light to a corresponding column signal processing circuit 105 through a corresponding vertical signal line 109.

[0055] The column signal processing circuit 105 is provided, for example, for each column of the pixel 102, and performs signal processing such as noise removal on the signal output from the pixel 102 of one row for each pixel column. That is, the column signal processing circuit 105 performs signal processing such as CDS for removing fixed pattern noise inherent to the pixel 102, signal amplification, and analog-to-digital conversion (ADC). A horizontal selection switch (not shown) is provided and connected between the output stage of the column signal processing circuit 105 and the horizontal signal line 110.

[0056] The horizontal driving circuit 106 is, for example, a shift register, and sequentially selects each column signal processing circuit 105 by sequentially outputting horizontal scanning pulses, and causes each column signal processing circuit 105 to output a pixel signal to a horizontal signal line 110 .

[0057] The output circuit 107 performs signal processing on the signals sequentially supplied from the respective column signal processing circuits 105 through the horizontal signal line 110, and outputs the processed signals. For example, the output circuit 107 may perform only buffering, or may perform black level adjustment, column variation correction, various types of digital signal processing, etc. The input / output terminal 112 communicates signals with the outside.

[0058] Figure 21 is a circuit diagram showing a configuration example of each pixel 102. The pixel 102 includes a photodiode PD, a transfer transistor TR, a floating diffusion FD, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. The transfer transistor TR, the floating diffusion FD, the amplifier transistor AMP, the selection transistor SEL, and the reset transistor RSP constitute a readout circuit 115 that reads out a charge (pixel signal) obtained as a result of photoelectric conversion performed by the photodiode PD.

[0059] The photodiode PD is a photoelectric conversion unit that converts incident light into electric charge by photoelectric conversion and accumulates the electric charge, and its anode terminal is grounded and its cathode terminal is connected to the transfer transistor TR. A transmission signal is supplied from the vertical drive circuit 104 to the gate electrode (hereinafter also referred to as the transfer gate) of the transfer transistor TR. The transfer transistor TR is driven according to the transmission signal supplied to the transfer gate. When the transfer transistor TR is turned on, the electric charge accumulated in the photodiode PD is transferred to the floating diffusion FD. The floating diffusion FD is a floating diffusion region having a predetermined accumulation capacity connected to the gate electrode of the amplifier transistor AMP, and temporarily accumulates the electric charge transferred from the photodiode PD.

[0060] The amplifier transistor AMP outputs a pixel signal of a level corresponding to the charge accumulated in the floating diffusion FD (i.e., the potential of the floating diffusion FD) to the vertical signal line 109 via the selection transistor SEL. That is, with the configuration in which the floating diffusion FD is connected to the gate electrode of the amplifier transistor AMP, the floating diffusion FD and the amplifier transistor AMP function as a conversion unit that amplifies the charge generated in the photodiode PD and converts the charge into a pixel signal of a level corresponding to the charge.

[0061] The selection transistor SEL is driven according to the selection signal supplied from the vertical drive circuit 104, and when the selection transistor SEL is turned on, the pixel signal output from the amplifier transistor AMP can be output to the vertical signal line 109. The reset transistor RST is driven according to the reset signal supplied from the vertical drive circuit 104, and when the reset transistor RST is turned on, the charge accumulated in the floating diffusion FD is discharged to the power supply line Vdd, and the floating diffusion FD is reset.

[0062] Note that the pixel 102 may have a shared pixel structure. The shared pixel structure includes a plurality of photodiodes PD, a plurality of transfer transistors TR, a shared floating diffusion FD, and each of other shared pixel transistors (e.g., an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST). That is, in the shared pixel structure, the photodiodes PD and transfer transistors TR constituting a plurality of unit pixels are configured to share each pixel transistor other than the transfer transistor TR.

[0063] (Configuration Example of Pixel Region and Peripheral Region)

[0064] Figure 3 1 is a plan view schematically showing an example of the arrangement of the pixel region and the peripheral region in the sensor substrate 1. Figure 3 As shown in FIG. 1 , the sensor substrate 1 includes a pixel region R1 and a peripheral region R2 arranged around the pixel region R1. The pixel region R1 is a region receiving light emitted by an on-chip lens OCL (see FIG. 2 ). Figure 4 ) is a light receiving area for collecting light, and includes a plurality of pixels 102. The peripheral area R2 is, for example, an area where the pixels 102 and the on-chip lens OCL are not configured. In the imaging device 100, the area of ​​the pixel area R1 is larger than the area of ​​the peripheral area R2. Note that a light shielding film may be provided in the peripheral area R2 via an insulating film. In this case, the peripheral area R2 may be referred to as an optical black area.

[0065] Figure 4 : is a cross-sectional view showing a configuration example of an imaging device 100 according to a first embodiment of the present disclosure. Figure 4 The image taken along the line X1-X1' parallel to the X-axis direction is shown. Figure 3 The cross section of the plan view shown. Figure 4 As shown, the imaging device 100 is a device in which light is emitted from the back side 1b of the sensor substrate 1 (at Figure 4 The imaging device 100 includes a sensor substrate 1 having a pixel region R1 and a peripheral region R2 and a logic substrate 2 (an example of a “circuit substrate” in the present disclosure) having a logic circuit 113. The logic substrate 2 is bonded to the front surface 1a of the sensor substrate 1 (at Figure 4 The lower side is formed on the surface of the substrate 3.

[0066] The sensor substrate 1 includes a semiconductor substrate 11 (an example of a "second semiconductor layer" of the present disclosure) provided with a plurality of pixels 102. The semiconductor substrate 11 is, for example, a thin silicon film. The semiconductor substrate 11 is provided with a photodiode PD as a photoelectric conversion unit configured in each pixel 102, a separation unit 12 that separates adjacent pixels 102, and a pixel transistor Tr1. The separation unit 12 has, for example, a shallow trench isolation (STI) structure.

[0067] like Figure 2 As shown, each pixel 102 includes a transfer transistor TR, a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. Figure 4 The pixel transistor Tr1 shown includes these various transistors.

[0068] The wiring layer 13 (an example of the “third wiring layer” of the present disclosure) is provided on the front face 11a side of the semiconductor substrate 11. The wiring layer 13 is a multilayer wiring layer, and includes an interlayer insulating film 14, wiring 15 configured in multiple layers (with the interlayer insulating film 14 interposed therebetween), a connecting pad 16 (an example of “a portion of the conductor included in the third wiring layer” of the present disclosure), and a via 17. The via 17 connects the semiconductor substrate 11 to the wiring 15, connects a portion of the wiring 15 to another portion, or connects the wiring 15 to one of the connecting pads 16 in the thickness direction of the laminated substrate 111 (for example, in the Z-axis direction). The connecting pad 16 faces the bonding surface between the sensor substrate 1 and the logic substrate 2. The surface of the connecting pad 16 (in the Figure 4 The bottom side is exposed from the interlayer insulating film 14.

[0069] Figure 4 The case where the wiring 15 and the connection pad 16 are five layers of metal M1 to M5 is shown. The wiring 15, the connection pad 16, and the via 17 contain, for example, copper (Cu) or a Cu alloy. The wiring 15, the connection pad 16, and the via 17 can be formed by a single damascene method or a dual damascene method. In addition, at least a portion of the wiring 15 and at least a portion of the via 17 can contain aluminum (Al), an Al alloy, a conductive polysilicon film doped with impurities, etc.

[0070] On the back side of the semiconductor substrate 11 (at Figure 4 On the side of the semiconductor substrate 11b (the upper side in the figure), an on-chip lens OCL (an example of a "lens" in the present disclosure) is provided. In addition, a color filter CF is provided between each on-chip lens OCL and the back side 11b of the semiconductor substrate 11. Note that Figure 4 The color filter CF and the on-chip lens OCL are arranged in the pixel region R1 but not in the peripheral region R2, but the present embodiment is not limited thereto. In the present embodiment, the color filter CF and the on-chip lens OCL may be arranged not only in the pixel region R1 but also in the peripheral region R2.

[0071] The logic substrate 2 includes a semiconductor substrate 21 (an example of a “first semiconductor layer” of the present disclosure). The semiconductor substrate 21 has a front surface 21a (an example of a “first surface” of the present disclosure) facing the sensor substrate 1 and a back surface 21b (an example of a “second surface” of the present disclosure) located on the opposite side of the front surface 21a. The semiconductor substrate 21 contains silicon. A plurality of MOS transistors constituting the logic circuit 113 are provided on the front surface 21a of the semiconductor substrate 21 (on the Figure 4 The middle is the upper side. Figure 4 As some of the plurality of MOS transistors constituting the logic circuit 113 , n-channel or p-channel MOS transistors Tr2 to Tr7 are shown.

[0072] The area of ​​the pixel region R1 is larger than that of the peripheral region R2. Therefore, more logic circuits 113 are arranged at positions overlapping with the pixel region R1 in the Z-axis direction than at positions overlapping with the peripheral region R2 in the Z-axis direction. That is, more logic circuits 113 are arranged at positions overlapping with the pixel region R1 in a plan view than at positions overlapping with the peripheral region R2 in a plan view.

[0073] The wiring layer 23 (an example of the “first wiring layer” of the present disclosure) is provided on the front face 21a side of the semiconductor substrate 21. The wiring layer 23 is a multilayer wiring layer, and includes an interlayer insulating film 24, wiring 25 configured in multiple layers (with the interlayer insulating film 24 interposed therebetween), a connecting pad 26 (an example of “a portion of the conductor included in the first wiring layer” of the present disclosure), and a via 27. The via 27 connects the semiconductor substrate 21 to the wiring 25, connects a portion of the wiring 25 to another portion, or connects the wiring 25 to one of the connecting pads 26 in the thickness direction of the stacked substrate 111 (for example, in the Z-axis direction). The connecting pad 26 faces the bonding surface between the sensor substrate 1 and the logic substrate 2. The surface of the connecting pad 26 (in the Z-axis direction) Figure 4 The upper side is shown in the figure) and is exposed from the interlayer insulating film 24. The connection pad 26 is bonded to the connection pad 16 in the wiring layer 13 described above.

[0074] Figure 4 The wiring 25 and the connection pad 26 are shown as a case where the metal M11 to M25 of fifteen layers. The wiring 25, the connection pad 26, and the via 27 contain, for example, copper (Cu) or a Cu alloy. The wiring 25, the connection pad 26, and the via 27 can be formed by a single damascene method or a dual damascene method. In addition, at least a portion of the wiring 25 and at least a portion of the via 27 can contain aluminum (Al), an Al alloy, a conductive polysilicon film doped with impurities, etc.

[0075] On the back side of the semiconductor substrate 21 (at Figure 4 On the side of the semiconductor substrate 21b (hereinafter referred to as the bottom), a wiring layer 33 (an example of a "second wiring layer" of the present disclosure) is provided. The wiring layer 33 is a multilayer wiring layer, and includes an interlayer insulating film 34, wirings 35 configured in multiple layers (with the interlayer insulating film 34 interposed therebetween), electrode pads 36, and vias 37. The vias 37 connect the semiconductor substrate 21 to the wirings 35 in the Z-axis direction, connect a part of the wirings 35 to another part, or connect the wirings 35 to one of the electrode pads 36. The surface of the electrode pad 36 (in the Z-axis direction) is Figure 4 The bottom side is exposed from the interlayer insulating film 34.

[0076] Figure 4The wiring 35 and the electrode pad 36 are shown as a case where the metal M31 to M33 of three layers. The wiring 35, the electrode pad 36 and the via 37 contain, for example, copper (Cu) or a Cu alloy. The wiring 35, the electrode pad 36 and the via 37 can be formed by a single damascene method or a dual damascene method. In addition, at least a portion of the wiring 35 and at least a portion of the via 37 can contain aluminum (Al), an Al alloy, a conductive polysilicon film doped with impurities, etc.

[0077] The bump electrodes 41 and 42 are provided on the opposite side of the surface of the logic substrate 2 facing the sensor substrate 1, that is, the back surface 2b of the logic substrate 2 (at Figure 4 For example, the bump electrodes 41 and 42 are arranged on the surface of the electrode pad 36 (at Figure 4 The bump electrode 41 is a voltage supply terminal for supplying a power supply voltage (e.g., Vdd) or a reference voltage (e.g., ground potential (0 V)) to the logic circuit 113. The bump electrode 42 is a signal terminal for inputting a signal to the logic circuit 113 or outputting a signal from the logic circuit 113. The bump electrodes 41 and 42 are made of, for example, gold (Au) or solder.

[0078] like Figure 4 As shown, the semiconductor substrate 21 is provided with a front surface 21a (at Figure 4 The via 51 (an example of a “first via” in the present disclosure) and the via 52 (an example of a “second via” in the present disclosure) between the back surface 21b located on the opposite side of the front surface 21a are shown. In addition, a contact 53 connecting the via 51 and the wiring 25 is provided on the via 51. A contact 54 connecting the via 52 and the wiring 25 is provided on the via 52.

[0079] The bump 41 for voltage supply is connected to the via 51 via the wiring 35 in the wiring layer 33, and is also connected to the wiring 25 via the via 51 and the contact 53. The bump electrode 42 for inputting or outputting a signal is connected to the via 52 via the wiring 35 in the wiring layer 33, and is also connected to the wiring 25 via the via 52 and the contact 54.

[0080] Figure 5 : is a plan view showing a configuration example of bump electrodes 41 and 42 according to the first embodiment of the present disclosure. Figure 5 FIG. 1 shows the front face 111a side of the laminated substrate 111. Figure 4 and Figure 5As shown, the bump electrode 41 and the via hole 51 are arranged at a position overlapping with the pixel region R1 in the Z-axis direction. The bump electrode 41 and the via hole 51 are arranged side by side in the X-axis direction (an example of the "first direction" of the present disclosure) and the Y-axis direction (an example of the "second direction" of the present disclosure) in a plan view observed from the Z-axis direction. In addition, the bump electrode 42 and the via hole 52 are arranged at a position overlapping with the peripheral region R2 in the Z-axis direction.

[0081] Note that Figure 5 In the embodiment, the wiring 25n extending in the X-axis direction and the wiring 25m extending in the Y-axis direction are connected via the via hole 51 (see Figure 4 ) etc. are connected to the bump electrode 41 for voltage supply (refer to Figure 4 ) is a part of the wiring 25 and is an example of a wiring including any layer of metals M11 to M25. The wiring 25n and the wiring 25m are metals of different layers.

[0082] Figure 6 2 is a cross-sectional view showing a configuration example of the via hole 51 according to the first embodiment of the present disclosure. Figure 6 As shown in FIG. 2 , the semiconductor substrate 21 is provided with a through hole H that passes through the front surface 21 a and the back surface 21 b. The insulating film 55 is provided on the inner side surface of the through hole H. Figure 6 As shown, the via 51 is provided in the through hole H via the insulating film 55 . One end 51 a of the via 51 is connected to the wiring 35 , and the other end 51 b of the via 51 is connected to the corresponding contact 53 .

[0083] The through hole H1 is, for example, formed from the interlayer insulating film 34 side (at Figure 6 Therefore, the diameter of the through hole H1 is larger on the interlayer insulating film 34 side (on the Figure 6 The diameter d1b of the end 51a is defined as the diameter of the via hole 51. The diameter d1b of the via hole 51 is, for example, greater than or equal to the minimum gate length of the transistor included in the logic circuit 113 and less than or equal to 1000 nm, and its size is, for example, several hundred nanometers.

[0084] Since the diameter of the via hole 51 is smaller than the usual size, the via hole 51 is also referred to as a micro via hole in this specification. In addition, in the first embodiment, the via hole 52 arranged at a position overlapping with the peripheral region R2 in the Z-axis direction also has the same structure and the same diameter as the via hole 51. Therefore, the via hole 52 is also referred to as a micro via hole.

[0085] Note that since the vias 51 and 52 penetrate the semiconductor substrate 21 (e.g., silicon substrate), the vias 51 and 52 may be referred to as through silicon vias (TSVs). In addition, since the vias 51 and 52 have small diameters and are TSVs, the vias 51 and 52 may be referred to as micro TSVs. Alternatively, since the vias 51 and 52 have nanometer-scale diameters and are TSVs, the vias 51 and 52 may be referred to as nTSVs.

[0086] The insulating film 55 is, for example, a silicon oxide film (SiO2). The conductive film constituting the micro vias 51 and 52 includes, for example, tungsten (W). The insulating film 55 is provided on the inner side surface of the through hole H1 to insulate the material of the semiconductor substrate 21 (for example, silicon) from the material of the micro via (for example, W).

[0087] Note that since the through hole H1 in which the micro vias 51 and 52 are arranged has a high aspect ratio, it is desirable to deposit the insulating film 55 by a film forming method having high coverage such as atomic layer deposition (ALD). The insulating film 55 is deposited with a film thickness of, for example, about 20 nm. In addition, the conductive film constituting the micro vias 51 and 52 is deposited by chemical vapor deposition (CVD). For example, tungsten (W) has good embedding properties and therefore has good embedding properties in the through hole H1 having a high aspect ratio.

[0088] (Voltage supply path)

[0089] Figure 7 1 is a diagram schematically showing a path (voltage supply path) for supplying a power supply voltage or a reference voltage from a bump electrode 41 for voltage supply to a logic circuit 113 in the imaging device 100 according to the first embodiment of the present disclosure. Figure 7 As shown in FIG. 1 , in the imaging device 100, the bump electrode 41 for supplying voltage is arranged at a position overlapping with the pixel region R1 in the Z-axis direction. The power supply voltage or the reference voltage is supplied from the bump electrode 41 to the logic circuit 113B via the wiring 35, the micro via 51 and the contact 53. In the imaging device 100, the power supply voltage or the reference voltage is supplied from the bump electrode 41 for supplying voltage to the logic circuit 113 located directly above it. As a result, compared with the comparative examples 1 and 2 described later (refer to Fig. 9 and Fig.10 ) can be shortened compared to the conventional method.

[0090] (Manufacturing method)

[0091] Next, we will explain Figure 4The manufacturing method of the imaging device 100 shown in FIG. 1 is shown. Note that the imaging device 100 is manufactured using various devices such as a film forming device (including a CVD device and a sputtering device), an ion implantation device, a heat treatment device, an etching device, a chemical mechanical polishing (CMP) device, and a bonding device. These devices are collectively referred to as a manufacturing device.

[0092] Figures 8A to 8H 1 is a cross-sectional view showing a method for manufacturing the imaging device 100 according to the first embodiment of the present disclosure in order of steps. Fig. 8A As shown, the manufacturing device forms a sensor substrate 1 ′ and a logic substrate 2 ′ by a CMOS process. Fig. 8A The sensor substrate 1 ′ shown on the right side of FIG. 1 is in a state after the surface of the interlayer insulating film 14 is planarized by CMP to expose the surface of the connection pad 16 . Fig. 8A The logic substrate 2 ′ shown on the right side of FIG. 1 is in a state where the surface of the interlayer insulating film 24 is planarized by CMP to expose the surface of the connection pad 26 .

[0093] Next, if Figure 8B As shown, the manufacturing apparatus makes the surface 1a' side of the sensor substrate 1' and the surface 2a' side of the logic substrate 2' face each other. Figure 8C As shown, the manufacturing device then bonds the sensor substrate 1' and the logic substrate 2' together. In this bonding step, the manufacturing device brings the interlayer insulating film 14 of the sensor substrate 1 and the interlayer isolation film 24 of the logic substrate 2 into close contact with each other, brings the connection pads 16 of the sensor substrate 1 and the connection pads 26 of the logic substrate 2 into close contact with each other, and performs heat treatment. As a result, the interlayer insulating films 14 and 24 are bonded to each other, and the connection pads 16 and 26 are bonded to each other, so that the sensor substrate 1' and the logic substrate 2' are integrated.

[0094] Next, the manufacturing apparatus grinds the back surface 21 b side of the semiconductor substrate 21 to thin (ie, reduce the thickness of) the semiconductor substrate 21. The semiconductor substrate 21 is polished (Foiling) by CMP.

[0095] Next, if Fig.8D As shown, the manufacturing apparatus sequentially forms minute via holes 51 and 52 and the wiring layer 33 connected to the minute via holes 51 and 52 on the back surface 21b side of the polished semiconductor substrate 21. As a result, the Figure 4 The logic substrate 2 is shown.

[0096] exist Fig.8D In the step of, the sensor substrate 1' is used as a supporting substrate for supporting the logic substrate 2'. Since the back side 1b' of the sensor substrate 1' used as a supporting substrate is ground and removed in a subsequent step, there is no problem even if the back side 1b' comes into contact with a manufacturing device or the like and some scratches occur in this step.

[0097] In addition, Figure 8C During the bonding process, the sensor substrate 1' and the logic substrate 2' are integrated. As a result, the logic substrate 2' can be more firmly fixed, for example, compared with the case where the logic substrate 2' is processed in a state where the logic substrate 2' is bonded to the support substrate via a resin adhesive sheet or the like. Since the through hole H1 (refer to FIG. 8) can be formed in the semiconductor substrate 21 in a state where the logic substrate 2' is firmly fixed, and the formation and patterning of a conductive film such as tungsten (W) can be performed, the micro vias 51 and 52 can be formed with high processing accuracy.

[0098] Furthermore, since the logic substrate 2' is not fixed using a resin adhesive sheet or the like, a process having a maximum temperature of about 400°C can be used when forming the minute via holes 51 and 52 and the wiring layer 33. The range of process selection can be expanded.

[0099] Next, if Fig. 8E As shown, the manufacturing apparatus attaches (temporarily bonds) the support substrate 57 to the back surface 2b of the logic substrate 2 (at Fig. 8E Next, the manufacturing apparatus grinds the back side 11b of the semiconductor substrate 11 (at Fig. 8E The semiconductor substrate 11 is polished by CMP. As a result, the Figure 4 The sensor substrate 1 is shown.

[0100] Next, if Figure 8F As shown, the manufacturing device is on the back side 11b of the polished semiconductor substrate 11 (that is, on the back side 1b of the sensor substrate 1 ( Figure 8F A color filter CF is formed on the semiconductor substrate 11 (shown above). Next, the manufacturing device forms an on-chip lens OCL on the color filter CF. Although not shown, a protective film may be formed between the semiconductor substrate 11 and the color filter CF and between the color filter CF and the on-chip lens OCL. After forming the on-chip lens OCL, the manufacturing device peels off the adhesive sheet 56 and the support substrate 57 from the back side 2b of the logic substrate 2.

[0101] Next, if Figure 8G As shown, the manufacturing apparatus forms bump electrodes 41 for voltage supply and bump electrodes 42 for inputting and outputting signals on the back surface 2 b side of the logic substrate 2 .

[0102] Next, if Figure 8HAs shown in FIG. 1 , the manufacturing device attaches the protective sheet 58 to the back side 2b of the logic substrate 2. Then, the manufacturing device dices (divides into pieces) the stacked substrate 111 including the sensor substrate 1 and the logic substrate 2 along the cutting line DL. After cutting, the stacked substrate 111 (chip) obtained as a result of the cutting is peeled off from the protective sheet 58. Through these steps, the stacked substrate 111 (chip) is completed. Figure 4 The imaging device 100 is shown.

[0103] (Effects of the First Embodiment)

[0104] As described above, the imaging device 100 according to the first embodiment of the present disclosure includes the sensor substrate 1 including the pixel region R1 in which the plurality of pixels 102 performing photoelectric conversion are arranged side by side, the logic substrate 2 is bonded to one face side of the sensor substrate 1 and includes the logic circuit 113 that processes a signal input to the sensor substrate 2 or a signal output from the sensor substrate 1, and the bump electrode 41 is provided on the opposite side of the face of the logic substrate 2 facing the sensor substrate 1 (for example, the back surface 2b side of the logic substrate 2) and supplies a power supply voltage or a reference voltage to the logic circuit 113. At least a portion of the bump electrode 41 is arranged at a position overlapping with the pixel region R1 in the thickness direction (for example, in the Z-axis direction) of the stacked substrate 111 including the sensor substrate 1 and the logic substrate 2.

[0105] According to this, at the position overlapped in the Z-axis direction, the power supply voltage or the reference voltage is supplied from the back surface 2b side of the logic substrate 2 to the logic circuit 113 located directly above it. As in Comparative Examples 1 and 2 described later, the imaging device 100 can shorten the length of the voltage supply path and the wiring to which the voltage is applied, compared with the case where the power supply voltage or the reference voltage is supplied from the peripheral area of ​​the sensor substrate. As a result, the imaging device 100 can suppress IR drop (voltage drop), and, for example, can easily keep the voltage applied to the elements (for example, MOS transistors Tr2 to Tr4) included in the logic circuit 113 constant. As a result, the imaging device 100 can suppress the degradation of device characteristics due to IR drop.

[0106] (Comparative Example)

[0107] (1) Comparative Example 1

[0108] Fig. 9 4 is a cross-sectional view showing the configuration of an imaging device 400 according to Comparative Example 1 of the present disclosure. Fig. 9 As shown, the imaging device 400 according to Comparative Example 1 includes a sensor substrate 301 including a photodiode PD and a logic substrate 302 bonded to one surface of the sensor substrate 301 (at Fig. 9In the imaging device 400 according to Comparative Example 1, a bonding pad 341 for power supply is provided on the uppermost surface of the sensor substrate 301. Although not shown, a gold wire or the like is wire-bonded to the bonding pad 341.

[0109] In the imaging device 400, as Fig. 9 As shown by the arrow in , the power supply voltage is supplied from the pad 341 to the logic circuit 413 provided on the semiconductor substrate 321 via a large number of wirings in the sensor substrate 301 and the logic substrate 302. In addition, since the bonding pad 341 is arranged in the peripheral region R2, the power supply voltage is supplied from the peripheral region R2 to the logic circuit 413 arranged at a position overlapping with the pixel region R1 in the Z-axis direction. As a result, in Comparative Example 1, the path (voltage supply path) for supplying the power supply voltage or the reference voltage is long, and IR drop is likely to occur.

[0110] In addition, the wire bonded to the bonding pad 341 has a small diameter and a loop height. The smaller the diameter of the wire, the longer the length of the wire, the higher the resistance value of the wire, and thus the more likely IR drop occurs.

[0111] (2) Comparative Example 2

[0112] Fig.10 is a cross-sectional view showing the configuration of an imaging device 500 according to Comparative Example 2 of the present disclosure. Fig.10 As shown, in the imaging device 500 according to Comparative Example 2, a pad 341 for power supply is provided on the uppermost surface of the logic substrate 302. Although not shown, in Comparative Example 2, as in Comparative Example 1, a gold wire or the like is wire-bonded to the bonding pad 341.

[0113] In the imaging device 500, as Fig.10 As shown by the arrow in , the power supply voltage is supplied from the bonding pad 341 to the logic circuit 413 provided on the semiconductor substrate 321 via a large number of wirings in the logic substrate 302. In addition, since the bonding pad 341 is arranged in the peripheral region R2, the power supply voltage is supplied from the peripheral region R2 to the logic circuit 413 arranged at a position overlapping with the pixel region R1 in the Z-axis direction. As a result, in Comparative Example 2, the voltage supply path is also long, and IR drop is likely to occur. In addition, since the bonding pad 341 is wire-bonded, IR drop is more likely to occur as the diameter of the wire becomes smaller and the length of the wire becomes longer.

[0114] (Variation of the first embodiment)

[0115] (1) First Modification

[0116] In the above-described embodiment, it has been described that the minute vias 51 and 52 are connected to the wiring 25 via the contacts 53 and 54. However, in the embodiment of the present disclosure, the minute vias 51 and 52 may be directly connected to the wiring 25.

[0117] Fig.11 : is a cross-sectional view showing the configuration of an imaging device 100A according to a first modification example of the first embodiment of the present disclosure. Fig.12 1 is a cross-sectional view showing a minute via 51 of an imaging device 100A according to a first modification of the first embodiment of the present disclosure. In the imaging device 100A according to the first modification of the first embodiment, the minute via 51 connected to the bump electrode 41 for voltage supply and the minute via 52 connected to the bump electrode 42 for input and output signals are directly connected to the wiring 25 without passing through the contacts 53 and 54. Even with such a configuration, the same effects as those produced by the imaging device 100 according to the first embodiment described above are produced.

[0118] Furthermore, although the through hole H1 is formed from the interlayer insulating film 34 side in the first embodiment, the first embodiment is not limited thereto. Fig.12 In the embodiment, the through hole H1 can be formed from the interlayer insulating film 24 side (at Fig.12 The through hole H1 is formed on the interlayer insulating film 24 side, and the diameter of the through hole H1 can be formed in a manner larger on the interlayer insulating film 24 side.

[0119] The diameter of the minute via hole 51 provided in the through hole H1 via the insulating film 55 may also be formed in a manner that is larger on the end portion 51a side connected to the wiring 25. In this case, the diameter d1a of the end portion 51a may be the diameter of the minute via hole 51. The diameter d1a of the minute via hole 51 is, for example, greater than or equal to the minimum gate length of the transistor included in the logic circuit 113 and less than or equal to 1000 nm, and its size is, for example, several hundred nanometers. Note that although Fig.12 Although not shown, the micro via 52 arranged at a position overlapping with the peripheral region R2 in the Z-axis direction may also have the configuration according to the first modification example like the micro via 51 .

[0120] In the imaging device 100A, as Fig.12 As shown, the power supply voltage or the reference voltage is also supplied to the logic circuit 113 from the back surface 2b side of the logic substrate 2 at a position overlapping with the pixel region R1 in the Z-axis direction. As a result, since the imaging device 100A can shorten the voltage supply path compared with Comparative Examples 1 and 2, the same effects as those produced by the imaging device 100 according to the first embodiment described above can be produced.

[0121] (2) Second Modification

[0122] In the above-mentioned first embodiment, it has been explained that in the thickness direction of the laminated substrate 111 (for example, in the Z-axis direction), the bump electrode 41 for voltage supply is configured at a position overlapping with the pixel region R1, and the bump electrode 42 for inputting and outputting signals is configured at a position overlapping with the peripheral region R2. However, in the first embodiment of the present disclosure, the bump electrodes 41 and 42 are not limited to this. In the embodiment of the present disclosure, for example, depending on the configuration of the logic circuit, a portion of the bump electrode 41 for voltage supply may be configured at a position overlapping with the peripheral region R2, and a portion of the bump electrode 42 for transmitting and receiving signals may be configured at a position overlapping with the pixel region R1.

[0123] Even with such a configuration, the power supply voltage or the reference voltage is supplied to the logic circuit 113 from the back surface 2b side of the logic substrate 2. As a result, the voltage supply path to the logic circuit 113 can be shortened, and IR drop can be suppressed.

[0124] (3) Third Modification

[0125] Although it has been described in the first embodiment that a plurality of pixel transistors are provided on the sensor substrate 1, the embodiments of the present disclosure are not limited thereto. In the embodiments of the present disclosure, a portion of the pixel transistors may be provided on the logic substrate 2. For example, among the pixel transistors, the amplification transistor AMP may be provided on the logic substrate 2, and the other transistors may be provided on the sensor substrate 1. Alternatively, among the pixel transistors, the transmission transistor TR may be provided on the sensor substrate 1, and the other transistors may be provided on the logic substrate 2.

[0126] <Second Implementation Method>

[0127] In the above-described first embodiment, the case where the logic substrate 2 is one semiconductor substrate 21 has been described. However, in the embodiment of the present disclosure, the number of semiconductor substrates constituting the logic substrate 2 is not limited to one. The logic substrate 2 may include a plurality of semiconductor substrates.

[0128] (Configuration example)

[0129] Fig.13 1 is a cross-sectional view showing a configuration example of an imaging device 100B according to a second embodiment of the present disclosure. Fig.13 As shown, in the imaging device 100B according to the second embodiment, the logic substrate 2 includes a semiconductor substrate 21 provided with a logic circuit 113A and a semiconductor substrate 61 (an example of a “third semiconductor layer” of the present disclosure) provided with a logic circuit 113B. Figure 1 The illustrated logic circuit 113 includes a logic circuit 113A and a logic circuit 113B.

[0130] Fig.13 As some of the plurality of MOS transistors constituting the logic circuit 113A, n-channel or p-channel MOS transistors Tr2 to Tr7 are shown. Fig.13 As some of the plurality of MOS transistors constituting the logic circuit 113B, n-channel or p-channel MOS transistors Tr2 to Tr7 are shown.

[0131] The semiconductor substrate 61 has a front surface 61a (an example of the “third surface” of the present disclosure) facing the sensor substrate 1 and a back surface 61b (an example of the “fourth surface” of the present disclosure) located on the opposite side of the front surface 61a. The wiring layer 63 (an example of the “fourth wiring layer” of the present disclosure) is arranged on the front surface 61a side of the semiconductor substrate 61, and the wiring layer 73 (an example of the “fifth wiring layer” of the present disclosure) is arranged on the back surface 61b side of the semiconductor substrate 61.

[0132] The wiring layer 63 on the front face 61a side is a multilayer wiring layer and includes an interlayer insulating film 64, wiring 65 in a multilayer configuration (with the interlayer insulating film 64 interposed therebetween), a connecting pad 66 (an example of "a portion of a conductor included in the fourth wiring layer" of the present disclosure), and a via 67. The via 67 connects the semiconductor substrate 61 to the wiring 65 in the thickness direction of the laminated substrate 111 (for example, in the Z-axis direction), connects a portion of the wiring 65 to another portion, or connects the wiring 65 to one of the connecting pads 66. The connecting pad 66 faces the bonding surface between the sensor substrate 1 and the logic substrate 2. The surface of the connecting pad 66 (in the Z-axis direction) is Fig.13 The upper side is shown in the middle) and is exposed from the interlayer insulating film 64.

[0133] The wiring 65, the connection pad 66, and the via 67 include, for example, copper (Cu) or a Cu alloy. The wiring 65, the connection pad 66, and the via 67 may be formed by a single damascene method or a dual damascene method. In addition, at least a portion of the wiring 65 and at least a portion of the via 67 may include aluminum (Al), an Al alloy, a conductive polysilicon film doped with impurities, and the like.

[0134] The wiring layer 73 on the back surface 61b side is a single-layer or multi-layer wiring layer, and includes an interlayer insulating film 74, wiring 75, a connection pad 76 (an example of "a part of the conductor included in the fifth wiring layer" of the present disclosure), and a via 77. The via 77 connects a part of the wiring 75 to another part in the Z-axis direction, or connects the wiring 75 to one of the connection pads 76. The surface of the connection pad 76 (in the Z-axis direction) is Fig.13 The bottom side is exposed from the interlayer insulating film 74.

[0135] The wiring 75, the connection pad 76, and the via 77 include, for example, copper (Cu) or a Cu alloy. The wiring 75, the connection pad 76, and the via 77 may be formed by a single damascene method or a dual damascene method. In addition, at least a portion of the wiring 75 and at least a portion of the via 77 may include aluminum (Al), an Al alloy, a conductive polysilicon film doped with impurities, or the like.

[0136] In the imaging device 100B, the interlayer insulating films 24 and 74 are bonded to each other, and the connection pads 26 and 76 are bonded to each other. As a result, in the logic substrate 2, the lower substrate including the semiconductor substrate 21 and the upper substrate including the semiconductor substrate 61 are integrated. In addition, the interlayer insulating films 64 and 14 are bonded to each other, and the connection pads 66 and 16 are bonded to each other, so that the sensor substrate 1 and the logic substrate 2 are integrated.

[0137] In addition, the semiconductor substrate 61 is provided with a via 78 (an example of the "fourth via" of the present disclosure) that passes through between the front face 61a and the back face 61b of the semiconductor substrate 61 and connects the wiring 65 on the front face 61a side and the wiring 75 on the back face 61b side to each other. The via 78 is arranged at a position overlapping with the peripheral region R2 in the Z-axis direction.

[0138] Fig.14 2 is a cross-sectional view showing a configuration example of a via hole 78 according to a second embodiment of the present disclosure. Fig.14 As shown in FIG. 1 , the semiconductor substrate 61 is provided with a through hole H2 that passes through the front surface 61a and the back surface 61b. The insulating film 68 is provided on the inner side surface of the through hole H2. Fig.14 As shown, the via 78 is provided in the through hole H2 via the insulating film 68 . One end 78 a of the minute via 51 is connected to the wiring 65 , and the other end 78 b of the via 78 is connected to the wiring 75 .

[0139] The through hole H2 is, for example, formed from the interlayer insulating film 74 side (at Fig.14 Therefore, the diameter of the through hole H2 is greater on the interlayer insulating film 74 side (at Fig.14 The diameter d2 of the end 78b is defined as the diameter of the via hole 78. The diameter d2 of the via hole 78 is sufficiently larger than the diameter d2 of the end 78b. Figure 6 The diameter d1b of the micro via hole 51 is shown as Fig.12 The diameter d1a of the micro via 51 shown in FIG. 5 is, for example, several micrometers in size.

[0140] Note that since the via 78 penetrates the semiconductor substrate 61 (eg, silicon substrate), the via 78 may be referred to as a through silicon via (TSV).

[0141] (Voltage supply path)

[0142] Fig.15 Schematic diagram of a voltage supply path of an imaging device 100B according to a second embodiment of the present disclosure. Fig.15 As shown, in the imaging device 100B, in addition to the bump electrode 42 for transmitting and receiving signals, a bump electrode 41 for voltage supply is arranged at a position overlapping with the peripheral region R2 in the Z-axis direction. Similarly, in addition to the micro via 52 for transmitting and receiving signals, a micro via 51 for voltage supply is arranged at a position overlapping with the peripheral region R2 in the Z-axis direction. The via 78 is connected to the bump electrode 41 for voltage supply and the micro via 51 arranged at the position overlapping with the peripheral region R2 in the Z-axis direction via wirings 25 and 75, etc.

[0143] like Fig.15 As shown, a path (hereinafter referred to as "voltage supply path A to 113B") is provided for supplying a power supply voltage or a reference voltage from the bump electrode 41 arranged at a position overlapping with the peripheral region R2 in the Z-axis direction to the logic circuit 113B via the wirings 25 and 75 and the via 78. In the imaging device 100B, the power supply voltage or the reference voltage can be supplied to the logic circuit 113B via the "voltage supply path A to 113B".

[0144] (Effects of the Second Embodiment)

[0145] As described above, the imaging device 100B according to the second embodiment of the present disclosure includes the following Figure 1 The logic circuit 113 shown, the logic circuit 113A provided on the semiconductor substrate 21, and the logic circuit 113B provided on the semiconductor substrate 61. The power supply voltage or the reference voltage is supplied to the logic circuit 113A from the back surface 2b side of the logic substrate 2 at a position overlapping with the pixel region R1 in the Z-axis direction. As a result, the imaging device 100B can shorten the voltage supply path to the logic circuit 113A and suppress IR drop.

[0146] In addition, the power supply voltage or the reference voltage is supplied to the logic circuit 113B from the back surface 2b side of the logic substrate 2 at a position overlapping with the peripheral region R2 in the Z-axis direction. Therefore, the voltage supply path to the logic circuit 113B tends to be longer than that in the case of the logic circuit 113A. However, similar to the logic circuit 113A, the voltage is supplied to the logic circuit 113B not through a lead such as a gold wire but via the bump electrode 41. As a result, compared with the case where the voltage is supplied via an electric wire in Comparative Examples 1 and 2, the resistance value of the voltage supply path to the logic circuit 113B can be reduced, so that the IR drop can be suppressed.

[0147] As described above, the imaging device 100B can suppress IR drop, and for example, can easily keep the voltage applied to the elements (e.g., MOS transistors Tr2 to Tr4) included in the logic circuit 113A and the voltage applied to the elements (e.g., MOS transistors Tr8 to Tr13) included in the logic circuit 113B constant. As a result, the imaging device 100B can suppress the degradation of device characteristics due to IR drop.

[0148] (Variation of the Second Embodiment)

[0149] (1) First Modification

[0150] In the embodiment of the present disclosure, minute via holes for voltage supply may be provided not only in the semiconductor substrate 21 but also in the semiconductor substrate 61 . Fig.16 1 is a cross-sectional view showing a configuration of an imaging device 100C according to a first modification example of the second embodiment of the present disclosure. Fig.16 As shown, in the imaging device 100C according to the first modified example of the second embodiment, a minute via hole 81 for voltage supply (an example of a "third via hole" of the present disclosure) is provided in the semiconductor substrate 61. The minute via hole 81 passes through between the front surface 61a and the back surface 10b of the semiconductor substrate 61. The minute via hole 81 is connected to a contact 83, and the wiring 65 on the front surface 61a side and the wiring 75 on the back surface 61b side are connected via the contact 83.

[0151] The configuration and diameter of minute via 81 and contact 83 are the same as those of minute via 51 and contact 53. The diameter of minute via 81 is greater than or equal to the minimum gate length of a transistor included in logic circuit 113B and less than or equal to 1000 nm, for example, its size is several hundred nanometers.

[0152] The minute via 81 is a TSV like the minute via 51 , and may be referred to as a minute TSV, or may be referred to as an nTSV because its diameter is at the nanometer level.

[0153] The micro via 81 is arranged at a position overlapping with the pixel region R1 in the thickness direction (for example, in the Z-axis direction) of the laminated substrate 111. When the diameter of the via 78 arranged at a position overlapping with the peripheral region R2 in the Z-axis direction is compared with the diameter of the micro via 81, the diameter of the via 78 is larger than the diameter of the micro via 82.

[0154] Fig.17 Schematic diagram of a voltage supply path of an imaging device 100C according to a first modification of the second embodiment of the present disclosure. Fig.17As shown, in the imaging device 100C, a path (hereinafter referred to as "voltage supply path B to 113B") is provided for supplying a power supply voltage or a reference voltage from the bump electrode 41 arranged at a position overlapping with the pixel region R1 in the Z-axis direction to the logic circuit 113B via the wiring 75, the micro via 81, and the contact 83. In the imaging device 100C, the power supply voltage or the reference voltage is supplied to the logic circuit 113B via the "voltage supply path B to 113B".

[0155] According to this, the power supply voltage or the reference voltage is supplied not only to the logic circuit 113A but also to the logic circuit 113B from the position overlapping with the pixel region R1 in the Z-axis direction on the back surface 2b side of the logic substrate 2. Since the imaging device 100C can shorten the voltage supply path to the logic circuit 113B, the IR drop can be further suppressed.

[0156] Note that in the imaging device 100C, it is also possible to set Fig.15 The imaging device 100C can further reduce the resistance value of the voltage supply path to the logic circuit 113B by including both the “voltage supply path A to 113B” and the “voltage supply path B to 113B”.

[0157] (2) Second Modification

[0158] In the embodiment of the present disclosure, the diameter of the via hole arranged at the position overlapping with the peripheral region R2 in the Z-axis direction may be larger than the diameter of the micro via hole 51 arranged at the position overlapping with the pixel region R1 in the Z-axis direction.

[0159] Fig.18 1 is a cross-sectional view showing a configuration of an imaging device 100D according to a second modification example of the second embodiment of the present disclosure. Fig.18 As shown, in the imaging device 100D according to the second modified example of the second embodiment, the via hole 91 that penetrates between the front surface 21a and the back surface 21b of the semiconductor substrate 21 is arranged at a position overlapping with the peripheral region R2 in the Z-axis direction. One end of the via hole 91 is connected to the bump electrode 41 for voltage supply arranged in the peripheral region. The other end of the via hole 91 is connected to the wiring 25 on the front surface 12a side of the semiconductor substrate 21. In addition, one end of another via hole 91 can be connected to the bump electrode 42 for transmitting and receiving signals arranged in the peripheral region R2, and the other end can be connected to the wiring 25 on the front surface 12a side of the semiconductor substrate 21.

[0160] The via hole 91 is formed from the back surface 21b side to the front surface 21a side of the semiconductor substrate 21. Therefore, the diameter of the via hole 91 is formed to be Fig.18When the diameter d3 of the end of the via hole 91 on the back side 21b is defined as the diameter of the via hole 91, the diameter d3 of the via hole 91 is sufficiently larger than the diameter of the micro via hole 51 (for example, Figure 6 The d1b and Fig.12 d1a) shown in FIG. 1 , and its size is, for example, several micrometers. As a result, the resistance of the via hole 91 arranged in the peripheral region R2 can be suppressed to be lower than the resistance of the minute via hole S1 arranged in the pixel region R1.

[0161] Note that since the via hole 91 penetrates the semiconductor substrate 21 (eg, silicon substrate), the via hole 91 may be referred to as a through silicon via (TSV).

[0162] Fig.19 1 is a diagram schematically showing a voltage supply path of logic circuits 113A and 113B in an imaging device 100C according to a second modification example of the second embodiment of the present disclosure. Fig.19 As shown, in the imaging device 100C, a path (hereinafter referred to as "voltage supply path C to 113B") is provided for supplying a power supply voltage or a reference voltage from the bump electrode 41 arranged at a position overlapping with the peripheral region R2 in the Z-axis direction to the logic circuit 113B via the large-diameter via 91, the wiring 75, the micro via 81, and the contact 83. In the imaging device 100D, the power supply voltage or the reference voltage is supplied to the logic circuit 113B via the "voltage supply path C to 113B".

[0163] With the imaging device 100D, since the resistance of the voltage supply path to the logic circuit 113B can be further reduced by configuring the via hole 91 with a large diameter, the IR drop can be further suppressed.

[0164] Note that in the imaging device 100C, at least Fig.17 The “voltage supply path A to 113B” or “voltage supply path B to 113B” is shown. Since the imaging device 100D includes at least the “voltage supply path A to 113B” or “voltage supply path B to 113B” in addition to the “voltage supply path C to 113B”, the resistance value of the voltage supply path to the logic circuit 113B can be further reduced.

[0165] <Other Implementation Options>

[0166] As described above, the present disclosure is described according to its embodiments and variations, but it should not be understood that the description and drawings constituting a part of the present disclosure limit the present disclosure. Through the present disclosure, various alternative embodiments, examples and operating techniques will be clear to those skilled in the art. For example, the logic substrate 2 is not limited to the case where it includes one or two semiconductor substrates. The logic substrate 2 can be obtained by bonding three or more semiconductor substrates with wiring layers inserted therebetween. In addition, a MOS transistor or the like constituting a part of the logic circuit 113 can be arranged on the semiconductor substrate 11 included in the sensor substrate 1.

[0167] In addition, any type of circuit may be provided on each of the stacked substrates (sensor substrate 1 and logic substrate 2). For example, in the case where the imaging device according to the embodiment of the present disclosure includes a two-layer stacked structure of an upper substrate (e.g., sensor substrate 1) and a lower substrate (e.g., logic substrate 2), as Figure 4 The imaging device 100 shown or Fig.11 As shown in the imaging device 100A, Figure 2 A portion of the pixel circuit shown (eg, readout circuit 115 ), other signal processing circuits, drive circuits, etc. may be configured on the lower substrate. Figure 2 All pixel circuits (eg, pixel 102 ) shown in FIG. 1 may be configured on an upper substrate, and other signal processing circuits and driving circuits may be configured on a lower substrate.

[0168] Even in the case where the imaging device according to the embodiment of the present disclosure has a three-layer stacked structure of an upper substrate (e.g., sensor substrate 1), an intermediate substrate (a part of logic substrate 2), and a lower substrate (another part of logic substrate 2), as Fig.13 The imaging device 100B shown, Fig.16 The imaging device 100C shown or Fig.18 As shown in the imaging device 100D, Figure 2 A portion or all of the pixel circuit shown or a signal processing circuit such as an ADC (for example, Figure 1 The column signal processing circuit 105 shown in the figure can also be appropriately arranged on each substrate.

[0169] In addition, Figure 4 The imaging device 100 shown or Fig.11 In the imaging device 100A shown, the circuits mounted on the lower substrate (e.g., logic substrate 2) are not limited to the logic circuit 113 and the pixel circuit. The circuits mounted on the lower substrate may be any of various circuits such as a signal processing circuit, a drive circuit, and a control circuit, including an analog circuit and / or a logic circuit.

[0170] Similarly, installed in Fig.13 The imaging device 100B shown, Fig.16 The imaging device 100C shown or Fig.18 The circuits on the intermediate substrate (a part of the logic substrate 2) and the lower substrate (another part of the logic substrate 2) of the illustrated imaging device 100D are not limited to the logic circuit 113 and the pixel circuit. The circuits mounted on the intermediate substrate and the lower substrate may be any of various circuits such as a signal processing circuit, a drive circuit, and a control circuit, including an analog circuit and / or a logic circuit.

[0171] As described above, the present disclosure certainly includes various embodiments and the like not described herein. Without departing from the gist of the above embodiments and variations, at least one of various omissions, substitutions or changes may be made to the constituent elements. In addition, the effects described in this specification are merely illustrative; however, the effects are not limited thereto, and other effects may also exist. The technical scope of the present disclosure is limited only by the invention of the specified matters of the reasonable claim scope according to the above description.

[0172] <Application examples of electronic equipment>

[0173] The technology according to the present disclosure (the present technology) can be applied to electronic devices. Fig. 20 is a diagram showing a configuration example of an electronic device 600 to which the present technology is applied. Fig. 20 As shown, the electronic device 600 includes a solid-state imaging device 601, an optical lens 602 (an example of the "optical system" of the present disclosure), a shutter device 603, a drive circuit 604, and a signal processing circuit 605. The electronic device 600 may be an electronic device such as a camera, but is not limited thereto. In addition, the electronic device 600 includes the above Figure 4 , Fig.11 , Fig.13 , Fig.16 , Fig.18 Any one or more of the imaging devices 100 , 100A, 100B, 100C, and 100D shown in the figure above serve as the solid-state imaging device 601 .

[0174] The optical lens 602 forms an image of the image light (incident light 606) from the subject on the imaging surface of the solid-state imaging device 601. As a result, the signal charge is accumulated in the solid-state imaging device 601 for a certain period of time. The shutter device 603 controls the light irradiation period and the light shielding period of the solid-state imaging device 601. The drive circuit 604 supplies a drive signal to control the transmission operation of the solid-state imaging device 601 and the shutter operation of the shutter device 603. According to the drive signal (timing signal) supplied from the drive circuit 604, the solid-state imaging device 601 performs signal transmission. The signal processing circuit 605 performs various types of signal processing on the signal (pixel signal) output from the solid-state imaging device 601. The video signal after signal processing is stored in a storage medium such as a memory, or is output to a monitor.

[0175] By such a configuration, since the electronic device 600 includes any one or more of the imaging devices 100 , 100A, 100B, 100C, and 100D capable of suppressing degradation of device characteristics due to IR drop as the solid-state imaging device 601 , performance degradation can be suppressed.

[0176] Note that the electronic device 600 is not limited to a camera and may be other electronic devices. For example, the electronic device 600 may be an imaging device such as a camera module for a mobile device such as a mobile phone.

[0177] <Application examples of endoscopic surgery systems>

[0178] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0179] Fig.21 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0180] exist Fig.21 , a state is shown in which an operator (doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 on which the endoscope 11100 is supported, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0181] The endoscope 11100 includes a lens barrel 11101 having an area of ​​a predetermined length from its distal end to be inserted into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of the lens barrel 11101. In the example shown in the drawings, the endoscope 11100 including a hard scope having a hard lens barrel 11101 is shown. However, the endoscope 11100 may also include a soft scope having a soft lens barrel 11101.

[0182] The lens barrel 11101 has an opening at its distal end into which the objective lens is fitted. The light source device 11203 is connected to the endoscope 11100 so that the light generated by the light source device 11203 is guided to the distal end of the lens barrel through a light guide extending inside the lens barrel 11101, and the light is irradiated toward the observation object in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 may be a straight-view mirror, or may be an oblique mirror or a side-view mirror.

[0183] An optical system and an imaging element are provided inside the camera head 11102, so that the reflected light (observation light) from the observation object is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the camera control unit (CCU) 11201 as RAW data.

[0184] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, for example, the CCU 11201 receives an image signal from the camera 11102, and performs various types of image processing such as development processing (demosaic processing) to display an image based on the image signal.

[0185] The display device 11202 displays thereon an image based on an image signal on which image processing has been performed by the CCU 11201 under the control of the CCU 11201 .

[0186] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light used when photographing a surgical area to the endoscope 11100 .

[0187] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information or instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0188] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for cauterization or incision of tissues, sealing of blood vessels, etc. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space of the operator. The recorder 11207 is a device capable of recording various types of information related to the operation. The printer 11208 is a device capable of printing various types of information related to the operation in various forms such as text, images, graphics, etc.

[0189] Note that, for example, the irradiation light supplied to the light source device 11203 of the endoscope 11100 when photographing the surgical area may include a white light source of an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance adjustment of the captured image can be performed by the light source device 11203. In addition, in this case, if the lasers from each RGB laser light source are emitted to the observed object in a time-division manner and the driving of the imaging element of the camera 11102 is controlled synchronously with the emission timing. Then, images corresponding to RGB colors can be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0190] In addition, the light source device 11203 can be controlled so that the intensity of the light to be output is changed between each predetermined timing. By controlling the drive of the imaging element of the camera 11102 synchronously with the timing of the change in light intensity to acquire images in time division and synthesize the images, a high dynamic range image without underexposed occlusion shadows and overexposed highlights can be generated.

[0191] In addition, the light source device 11203 can supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by using the wavelength dependence of light absorption in body tissue to emit light having a narrowband domain compared to the irradiation light (i.e., white light) during ordinary observation, narrowband domain observation (narrowband domain imaging) is performed to photograph predetermined tissues such as blood vessels on the surface of the mucosa with high contrast. In addition, in special light observation, fluorescence observation is performed to obtain an image by fluorescence generated by emitting excitation light. In fluorescence observation, for example, excitation light can be irradiated to body tissue to observe fluorescence from body tissue (autofluorescence observation), or reagents such as indocyanine green (ICG) can be locally injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is emitted to obtain a fluorescent image. The light source device 11203 can supply narrowband domain light and / or excitation light suitable for the above-mentioned special light observation.

[0192] Fig. 22 It is shown Fig.21 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0193] The camera 11102 includes a lens unit 11401, an imaging section 11402, a driving section 11403, a communication section 11404, and a camera control section 11405. The CCU 11201 includes a communication section 11411, an image processing section 11412, and a control section 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 for communicating with each other.

[0194] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light received from the distal end of the lens barrel 11101 is guided to the camera head 11102 and is incident on the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0195] The imaging unit 11402 includes an imaging element. The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). When the imaging unit 11402 is constructed as a multi-board type, for example, image signals corresponding to each RGB are generated by the imaging element, and a color image can be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 can also be constructed to have a pair of imaging elements for acquiring image signals for the right eye and the left eye for three-dimensional (3D) display. If a 3D display is performed, the operator 11131 can more accurately grasp the depth of the body tissue in the surgical site. Note that when the imaging unit 11402 is constructed as a multi-board type, a plurality of lens units 11401 are provided corresponding to the respective imaging elements.

[0196] In addition, the imaging portion 11402 does not necessarily have to be provided on the camera head 11102. For example, the imaging portion 11402 may be provided just behind the objective lens inside the lens barrel 11101.

[0197] The driving section 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control section 11405. Therefore, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0198] The communication section 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication section 11404 transmits the image signal acquired from the imaging section 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0199] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, for example, information specifying a frame rate of a captured image, information specifying an exposure value at the time of imaging, and / or information specifying a magnification and focus of a captured image, etc.

[0200] Note that imaging conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control section 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated in the endoscope 11100.

[0201] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received via the communication unit 11404 .

[0202] The communication section 11411 includes a communication device for transmitting and receiving various types of information to and from the camera 11102. The communication section 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0203] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted by electrical communication, optical communication, or the like.

[0204] The image processing unit 11412 performs various types of image processing on the image signal in the form of RAW data transmitted from the camera 11102 .

[0205] The control unit 11413 performs various types of control related to imaging of the operation area, etc., by the endoscope 11100 and display of a captured image obtained by imaging the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0206] In addition, the control unit 11413 controls the display device 11202 to display the captured image of the surgical area, etc. based on the image signal that has been image-processed by the image processing unit 11412. In this case, the control unit 11413 can recognize various objects within the captured image by using various image recognition technologies. For example, the control unit 11413 detects the edge shape and / or color of the object contained in the captured image to recognize surgical instruments such as forceps, specific living body parts, bleeding, fog when the energy treatment instrument 11112 is used, etc. When controlling the display device 11202 to display the captured image, the control unit 11413 can cause the display device 11202 to display various types of surgical support information with the image of the surgical area in an overlapping manner by using the recognition result. When the surgical support information is displayed in an overlapping manner and presented to the operator 11131, the burden on the operator 11131 can be reduced, and the operator 11131 can reliably perform the operation.

[0207] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable for both electrical signals and optical communication.

[0208] Here, in the example shown in the drawing, communication is performed by wired communication using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0209] Examples of endoscopic surgical systems to which the technology of the present disclosure can be applied have been described above. For example, the technology of the present disclosure can be applied to the endoscope 11100, the imaging unit 11402 of the camera 11102, the image processing unit 11412 of the CCU 11201, etc. in the above-mentioned configuration. Specifically, Figure 4 , Fig.11 , Fig.13 , Fig.16 , Fig.18 The imaging devices 100, 100A, 100B, 100C, and 100D shown in the figures can be applied to the imaging unit 10402. By applying the technology according to the present disclosure to the endoscope 11100, the imaging unit 11402 of the camera 11102, the image processing unit 11412 of the CCU 11201, etc., a clearer image of the surgical area can be obtained, and the operator can reliably confirm the surgical area. In addition, by applying the technology according to the present disclosure to the endoscope 11100, the imaging unit 11402 of the camera 11102, the image processing unit 11412 of the CCU 11201, etc., the surgical area image can be obtained with a lower delay, so that treatment with a feeling similar to the case where the operator tactilely observes the surgical area can be performed.

[0210] Note that although the description is given here by taking an endoscopic surgery system as an example, the technology according to the present disclosure can be applied to a microscope surgery system or the like, for example.

[0211] <Application example of mobile object>

[0212] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is implemented as a device to be installed on any type of mobile body such as an automobile, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, or a robot.

[0213] Fig.23 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0214] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.23 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0215] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a drive force generating device for generating a drive force of the vehicle such as an internal combustion engine, a drive motor, etc., a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0216] The main system control unit 12020 controls the operation of various devices provided in the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, a fog light, etc. In this case, a radio wave or a signal of various switches transmitted from a portable device instead of a key may be input to the main system control unit 12020. The main system control unit 12020 receives the input of the radio wave or the signal, and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0217] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 can detect objects such as people, cars, obstacles, signs, text on the road, etc., or detect the distance thereto based on the received image.

[0218] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information related to the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays.

[0219] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the state of the driver. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver falls asleep in a sitting position.

[0220] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device based on the information related to the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of the vehicle, following driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0221] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so as to achieve automatic driving in which the vehicle drives autonomously without relying on the driver's operation.

[0222] In addition, the microcomputer 12051 can output a control instruction to the main system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the positions of the front vehicle or the oncoming vehicle detected by the exterior information detection unit 12030 to perform coordinated control to achieve glare prevention such as switching the high beam to the low beam.

[0223] The sound / image output unit 12052 transmits at least one of a sound and an image output signal to an output device capable of visually or auditorily notifying a vehicle occupant or information outside the vehicle. Fig.23 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0224] Fig.24 The figure is an example of the installation position of the imaging unit 12031.

[0225] exist Fig.24In the figure, as the imaging unit 12031, the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0226] The imaging units 12101, 12102, 12103, 12104 and 12105 are arranged at positions such as the front of the vehicle 12100, the side mirrors, the rear bumper and the rear door, and the upper side of the windshield in the vehicle. The imaging unit 12101 arranged in the front of the vehicle and the imaging unit 12105 arranged on the upper side of the windshield in the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged in the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 arranged in the rear bumper or the rear door mainly obtains images on the rear of the vehicle 12100. The images in front obtained by the imaging units 12101 and 12105 are mainly used to detect vehicles in front, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0227] Notice, Fig.24 An example of the shooting range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front of the vehicle. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104 on each other, a bird's-eye view image of the vehicle 12100 as seen from above is obtained.

[0228] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0229] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each solid object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed to the vehicle 12100), thereby extracting a solid object located on the driving route of the vehicle 12100, especially the closest solid object, and traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 as the front vehicle. In addition, the microcomputer 12051 can set the distance between the vehicles that is previously ensured in front of the front vehicle, and can perform automatic braking control (including tracking travel stop control), automatic acceleration control (including tracking travel start control), etc. Therefore, coordinated control such as automatic driving that aims at autonomous driving of the vehicle without relying on the operation of the driver can be performed.

[0230] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles and other three-dimensional objects, extract the classified three-dimensional object data, and automatically avoid obstacles using the extracted three-dimensional object data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk indicating the degree of danger of collision with each obstacle. When the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 and the display unit 12062 or performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can assist driving to avoid collisions.

[0231] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian exists in the captured images of the imaging units 12101 to 12104. For example, the identification of the pedestrian is performed by extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points indicating the outline of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that the pedestrian exists in the captured images of the imaging units 12101 to 12104 and thereby identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a quadrilateral contour line for emphasis in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon indicating the pedestrian is displayed at a desired position.

[0232] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. For example, the technology of the present disclosure can be applied to the imaging unit 12031 and the like in the above-mentioned configuration. Specifically, Figure 4 , Fig.11 , Fig.13 , Fig.16 , Fig.18 The imaging devices 100, 100A, 100B, 100C, and 100D shown in FIG. 100 and FIG. 100B can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, a captured image that is easier to view can be obtained, so that driver fatigue can be reduced.

[0233] Note that the present disclosure may also have the following configurations.

[0234] (1) An imaging device comprising:

[0235] a sensor substrate including a pixel region in which a plurality of pixels performing photoelectric conversion are arranged side by side;

[0236] a circuit substrate bonded to one surface side of the sensor substrate, the circuit substrate including a circuit for processing a signal input to or output from the sensor substrate; and

[0237] a voltage supply terminal which is provided on the opposite side of the surface of the circuit substrate facing the sensor substrate and supplies a power supply voltage or a reference voltage to the circuit, wherein

[0238] At least a portion of the voltage supply terminal is arranged at a position overlapping with the pixel region in a thickness direction of a laminate substrate including the sensor substrate and the circuit substrate.

[0239] (2) The imaging device according to (1), wherein

[0240] The circuit substrate comprises:

[0241] a first semiconductor layer having a first surface facing the sensor substrate and a second surface located on an opposite side of the first surface,

[0242] a first wiring layer disposed on the first surface side of the first semiconductor layer, and

[0243] A first via hole passes through the first surface and the second surface of the first semiconductor layer, wherein

[0244] The first via hole is arranged at a position overlapping with the pixel area in the thickness direction of the laminated substrate, and

[0245] At least a part of the voltage supply terminal is connected to the first wiring layer through a first via hole.

[0246] (3) The imaging device according to (2), wherein

[0247] A diameter of the first via hole is greater than or equal to a minimum gate length of a transistor included in the circuit and less than or equal to 1000 nm.

[0248] (4) The imaging device according to (2) or (3), wherein

[0249] The circuit substrate comprises:

[0250] a second wiring layer disposed on the second surface side of the first semiconductor layer, and

[0251] The voltage supply terminal is connected to the first via via the second wiring layer.

[0252] (5) The imaging device according to any one of (1) to (4), further comprising:

[0253] a signal terminal which is provided on the opposite side of the surface of the circuit substrate facing the sensor substrate and inputs a signal to the circuit or outputs a signal from the circuit, wherein

[0254] The sensor substrate has a peripheral region located around the pixel region, and

[0255] At least a portion of the signal terminal is disposed at a position overlapping with the peripheral region in the thickness direction of the laminated substrate.

[0256] (6) The imaging device according to (5), wherein

[0257] The circuit substrate comprises:

[0258] a first semiconductor layer having a first surface facing the sensor substrate and a second surface located on an opposite side of the first surface,

[0259] a first wiring layer disposed on the first surface side of the first semiconductor layer, and

[0260] A second via hole passes through the first surface and the second surface of the first semiconductor layer, wherein

[0261] The second via hole is arranged at a position overlapping with the peripheral area in the thickness direction of the laminated substrate, and

[0262] At least a part of the signal terminal is connected to the first wiring layer through the second via hole.

[0263] (7) The imaging device according to (6), wherein

[0264] The circuit substrate includes a first via hole penetrating between the first surface and the second surface of the first semiconductor layer.

[0265] The first via hole is arranged at a position overlapping with the pixel area in the thickness direction of the stacked substrate,

[0266] At least a part of the voltage supply terminal is connected to the first wiring layer via a first via hole, and

[0267] The diameter of the second via hole is greater than the diameter of the first via hole.

[0268] (8) The imaging device according to any one of (2) to (4), (6) and (7), wherein

[0269] The sensor substrate comprises:

[0270] a second semiconductor layer provided with the plurality of pixels, and

[0271] The third wiring layer is arranged between the second semiconductor layer and the circuit substrate, wherein

[0272] A portion of the conductor included in the first wiring layer and a portion of the conductor included in the third wiring layer are joined to each other.

[0273] (9) The imaging device according to any one of (1) to (7), wherein

[0274] The sensor substrate comprises:

[0275] a second semiconductor layer provided with the plurality of pixels, and

[0276] a third wiring layer disposed between the second semiconductor layer and the circuit substrate,

[0277] The circuit substrate comprises:

[0278] a third semiconductor layer having a third face facing the sensor substrate and a fourth face located on an opposite side of the third face, and

[0279] a fourth wiring layer disposed on the third surface side of the third semiconductor layer, and

[0280] A portion of the conductor included in the fourth wiring layer and a portion of the conductor included in the third wiring layer are joined to each other.

[0281] (10) The imaging device according to (9), wherein

[0282] The circuit substrate includes a fifth wiring layer disposed on the fourth surface side of the third semiconductor layer, and

[0283] A portion of the conductor included in the fifth wiring layer and a portion of the conductor included in the first wiring layer are joined to each other.

[0284] (11) The imaging device according to (10), wherein

[0285] The circuit substrate includes a third via hole that penetrates between the third surface and the fourth surface of the third semiconductor layer and connects the fourth wiring layer and the fifth wiring layer to each other, and

[0286] The third via hole is arranged at a position overlapping with the pixel area in the thickness direction of the laminate substrate.

[0287] (12) The imaging device according to (11), wherein

[0288] A diameter of the third via hole is greater than or equal to a minimum gate length of a transistor included in the circuit and less than or equal to 1000 nm.

[0289] (13) The imaging device according to (11) or (12), wherein

[0290] The circuit substrate includes a fourth via hole that penetrates between the third surface and the fourth surface of the third semiconductor layer and connects the fourth wiring layer and the fifth wiring layer to each other.

[0291] The sensor substrate has a peripheral region located around the pixel region, and

[0292] The fourth via hole is arranged at a position overlapping with the peripheral region in the thickness direction of the laminate substrate.

[0293] (14) The imaging device according to (13), wherein

[0294] A diameter of the fourth via hole is greater than a diameter of the third via hole.

[0295] (15) The imaging device according to any one of (1) to (14), further comprising:

[0296] A plurality of voltage supply terminals, wherein

[0297] The plurality of voltage supply terminals are arranged side by side in a first direction and a second direction intersecting the first direction in a plan view viewed in the thickness direction of the laminated substrate.

[0298] (16) The imaging device according to any one of (1) to (15), further comprising:

[0299] a lens disposed on an opposite side of the one face of the sensor substrate; and

[0300] A color filter is provided between the lens and the sensor substrate.

[0301] (17) An electronic device comprising:

[0302] imaging device; and

[0303] an optical system that causes the imaging device to form an image of image light from a subject, wherein

[0304] The imaging device comprises:

[0305] a sensor substrate including a pixel region in which a plurality of pixels performing photoelectric conversion are arranged side by side;

[0306] a circuit substrate bonded to one surface side of the sensor substrate, the circuit substrate including a circuit for processing a signal input to or output from the sensor substrate; and

[0307] a voltage supply terminal which is provided on the opposite side of the surface of the circuit substrate facing the sensor substrate and supplies a power supply voltage or a reference voltage to the circuit, wherein

[0308] At least a portion of the voltage supply terminal is arranged at a position overlapping with the pixel region in a thickness direction of a laminate substrate including the sensor substrate and the circuit substrate.

[0309] Reference numerals list

[0310] 1,1',301 Sensor substrate

[0311] 1a,2a,11a,12a,21a,61a,111a front

[0312] 1b,2b,10b,11b,21b,61b,111b Back

[0313] 2,2',302 Logic substrate

[0314] 3. Laminated substrate

[0315] 11,21,61,71,321 Semiconductor substrate

[0316] 12 Separation unit

[0317] 13,23,33,63,73 Wiring layer

[0318] 14,24,34,64,74 Interlayer insulation film

[0319] 15,25,25m,25n,35,65,75 wiring

[0320] 16,26,66,76 connection pads

[0321] 17,27,37,67,77,78,91 vias

[0322] 41 Bump electrode (for voltage supply)

[0323] 42 Bump electrodes (for transmitting and receiving signals)

[0324] 51,52,81 Micro vias

[0325] 51a,51b,78a,78b End

[0326] 53,54,83 contacts

[0327] 55,68 Insulation film

[0328] 56 Adhesive sheet

[0329] 57 Support substrate

[0330] 58 Protective film

[0331] 100,100A,100B,100C,100D,400,500 Imaging Device

[0332] 102 pixels

[0333] 104 Vertical drive circuit

[0334] 105 columns signal processing circuit

[0335] 106 Horizontal drive circuit

[0336] 107 Output Circuit

[0337] 108 Control Circuit

[0338] 109 vertical signal line

[0339] 110 horizontal signal line

[0340] 111 Laminated substrate

[0341] 112 Input / output terminals

[0342] 113,113A,113B,413 Logic Circuits

[0343] 115 Readout Circuit

[0344] 600 Electronic equipment

[0345] 601 Solid-state imaging device

[0346] 602 Optical lens

[0347] 603 Shutter Device

[0348] 604 drive circuit

[0349] 605 Signal Processing Circuit

[0350] 606 Incident Light

[0351] 10402 Imaging Department

[0352] 11000 Endoscopic Surgery System

[0353] 11100 Endoscope

[0354] 11101 Lens tube

[0355] 11102 Camera

[0356] 11110 Surgical instruments

[0357] 11111 Insufflable tube

[0358] 11112 Energy management equipment

[0359] 11120 Support arm device

[0360] 11131 Surgeon (Doctor)

[0361] 11132 patients

[0362] 11133 beds

[0363] 11200 Cart

[0364] 11201 Camera Control Unit (CCU)

[0365] 11202 Display device

[0366] 11203 Light source device

[0367] 11204 Input Device

[0368] 11205 Disposal equipment control device

[0369] 11206 Pneumoperitoneum device

[0370] 11207 Recorder

[0371] 11208 Printer

[0372] 11400 Transmission Cable

[0373] 11401 Lens unit

[0374] 11402 Imaging Department

[0375] 11403 Drive unit

[0376] 11404 Ministry of Communications

[0377] 11405 Camera Control Unit

[0378] 11411 Ministry of Communications

[0379] 11412 Image Processing Department

[0380] 11413 Control Department

[0381] 12000 Vehicle Control Systems

[0382] 12001 Communication Network

[0383] 12010 Drive system control unit

[0384] 12020 Main system control unit

[0385] 12030 External vehicle information detection unit

[0386] 12031 Imaging Department

[0387] 12040 In-vehicle information detection unit

[0388] 12041 Driver status detection unit

[0389] 12050 Integrated control unit

[0390] 12051 Microcomputer

[0391] 12052 Sound / image output unit

[0392] 12061 Audio Speaker

[0393] 12062 Display unit

[0394] 12063 Dashboard

[0395] 12100 Vehicles

[0396] 12101,12102,12103,12104,12105 Imaging Department

[0397] 12111,12112,12113,12114 Imaging range

[0398] A, B, C voltage supply path

[0399] AMP Amplifier Transistor

[0400] CF Color Filter

[0401] d1a,d1b,d2,d3 diameter

[0402] DL cutting line

[0403] FD Floating Diffusion

[0404] H,H1,H2 through hole

[0405] I In-vehicle Network

[0406] M1~M5,M11~M25,M31~M33 Metal

[0407] OCL On-Chip Lens

[0408] PD Photodiode

[0409] R1 pixel area

[0410] R2 Surrounding Area

[0411] RST Reset transistor

[0412] SEL select transistor

[0413] TR Pass Transistor

[0414] Tr1~Tr13 pixel transistor

Claims

1. An imaging device, comprising: a sensor substrate including a pixel region in which a plurality of pixels performing photoelectric conversion are arranged side by side; a circuit substrate bonded to one surface side of the sensor substrate, the circuit substrate including a circuit for processing a signal input to the sensor substrate or a signal output from the sensor substrate; and a voltage supply terminal which is provided on the opposite side of the surface of the circuit substrate facing the sensor substrate and supplies a power supply voltage or a reference voltage to the circuit, wherein At least a portion of the voltage supply terminal is arranged at a position overlapping with the pixel region in a thickness direction of a laminate substrate including the sensor substrate and the circuit substrate.

2. The imaging device according to claim 1, wherein The circuit substrate comprises: a first semiconductor layer having a first surface facing the sensor substrate and a second surface located on an opposite side of the first surface, a first wiring layer disposed on the first surface side of the first semiconductor layer, and A first via hole passes through the first surface and the second surface of the first semiconductor layer, wherein The first via hole is arranged at a position overlapping with the pixel area in the thickness direction of the laminated substrate, and At least a part of the voltage supply terminal is connected to the first wiring layer through a first via hole.

3. The imaging device according to claim 2, wherein A diameter of the first via hole is greater than or equal to a minimum gate length of a transistor included in the circuit and less than or equal to 1000 nm.

4. The imaging device according to claim 2, wherein The circuit substrate comprises: a second wiring layer disposed on the second surface side of the first semiconductor layer, and The voltage supply terminal is connected to the first via via the second wiring layer.

5. The imaging device according to claim 1, further comprising: a signal terminal which is provided on the opposite side of the surface of the circuit substrate facing the sensor substrate and inputs a signal to the circuit or outputs a signal from the circuit, wherein The sensor substrate has a peripheral region located around the pixel region, and At least a portion of the signal terminal is disposed at a position overlapping with the peripheral region in the thickness direction of the laminated substrate.

6. The imaging device according to claim 5, wherein The circuit substrate comprises: a first semiconductor layer having a first surface facing the sensor substrate and a second surface located on an opposite side of the first surface, a first wiring layer disposed on the first surface side of the first semiconductor layer, and A second via hole passes through the first surface and the second surface of the first semiconductor layer, wherein The second via hole is arranged at a position overlapping with the peripheral area in the thickness direction of the laminated substrate, and At least a part of the signal terminal is connected to the first wiring layer through the second via hole.

7. The imaging device according to claim 6, wherein The circuit substrate includes a first via hole penetrating between the first surface and the second surface of the first semiconductor layer. The first via hole is arranged at a position overlapping with the pixel area in the thickness direction of the stacked substrate, At least a part of the voltage supply terminal is connected to the first wiring layer via a first via hole, and The diameter of the second via hole is greater than the diameter of the first via hole.

8. The imaging device according to claim 2, wherein The sensor substrate comprises: a second semiconductor layer provided with the plurality of pixels, and The third wiring layer is arranged between the second semiconductor layer and the circuit substrate, wherein A portion of the conductor included in the first wiring layer and a portion of the conductor included in the third wiring layer are joined to each other.

9. The imaging device according to claim 1, wherein The sensor substrate comprises: a second semiconductor layer provided with the plurality of pixels, and a third wiring layer disposed between the second semiconductor layer and the circuit substrate, The circuit substrate comprises: a third semiconductor layer having a third face facing the sensor substrate and a fourth face located on an opposite side of the third face, and a fourth wiring layer disposed on the third surface side of the third semiconductor layer, and A portion of the conductor included in the fourth wiring layer and a portion of the conductor included in the third wiring layer are joined to each other.

10. The imaging device according to claim 9, wherein The circuit substrate includes a fifth wiring layer disposed on the fourth surface side of the third semiconductor layer, and A portion of the conductor included in the fifth wiring layer and a portion of the conductor included in the first wiring layer are joined to each other.

11. The imaging device according to claim 10, wherein The circuit substrate includes a third via hole that penetrates between the third surface and the fourth surface of the third semiconductor layer and connects the fourth wiring layer and the fifth wiring layer to each other, and The third via hole is arranged at a position overlapping with the pixel area in the thickness direction of the laminate substrate.

12. The imaging device according to claim 11, wherein A diameter of the third via hole is greater than or equal to a minimum gate length of a transistor included in the circuit and less than or equal to 1000 nm.

13. The imaging device according to claim 11, wherein The circuit substrate includes a fourth via hole that penetrates between the third surface and the fourth surface of the third semiconductor layer and connects the fourth wiring layer and the fifth wiring layer to each other. The sensor substrate has a peripheral region located around the pixel region, and The fourth via hole is arranged at a position overlapping with the peripheral region in the thickness direction of the laminate substrate.

14. The imaging device according to claim 13, wherein A diameter of the fourth via hole is greater than a diameter of the third via hole.

15. The imaging device according to claim 1, further comprising: A plurality of voltage supply terminals, wherein The plurality of voltage supply terminals are arranged side by side in a first direction and a second direction intersecting the first direction in a plan view viewed in the thickness direction of the laminated substrate.

16. The imaging device according to claim 1, further comprising: a lens disposed on an opposite side of the one surface of the sensor substrate; and A color filter is provided between the lens and the sensor substrate.

17. An electronic device comprising: Imaging device; and an optical system that causes the imaging device to form an image of image light from a subject, wherein The imaging device comprises: a sensor substrate including a pixel region in which a plurality of pixels performing photoelectric conversion are arranged side by side; a circuit substrate bonded to one surface side of the sensor substrate, the circuit substrate including a circuit for processing a signal input to or output from the sensor substrate; and a voltage supply terminal which is provided on the opposite side of the surface of the circuit substrate facing the sensor substrate and supplies a power supply voltage or a reference voltage to the circuit, wherein At least a portion of the voltage supply terminal is arranged at a position overlapping with the pixel region in a thickness direction of a laminate substrate including the sensor substrate and the circuit substrate.

Images