TSV Bonding Pre-Test Circuit and Test Method Based on Enhanced Ring Oscillator

Abstract

TSV pre-bonding test circuit and test method based on an enhanced ring oscillator, relating to the field of TSV testing. The present invention is to solve the problem that the existing TSV pre-bonding test methods are difficult to simultaneously meet accuracy and integration requirements. In both the TSV open-circuit fault test and the leakage fault test modes of the present invention, the test results of each loop will be output from the counting port to the automatic test equipment in the form of frequency counting, and the automatic test equipment will analyze and calculate to give the corresponding open-circuit position and leakage conductance information. The present invention can effectively detect TSV open-circuit, leakage, and open-circuit leakage mixed faults, and can quantitatively diagnose the severity of the faults. For open-circuit faults, the coverage rate can reach 95%, and the minimum capacitance resolution is 2.98 fF; for leakage faults, the minimum measurable leakage conductance is 4 n Siemens, and the leakage conductance diagnosis error does not exceed 11%.

Description

Technical Field

[0001] The present invention belongs to the field of circuits, and particularly relates to the pre-bonding test of TSVs. Background Art

[0002] As the vertical interconnection path in three-dimensional integrated circuits, TSV (Through Silicon Via) may have open circuit, leakage, and mixed open circuit and leakage faults during its manufacturing process. Pre-bonding testing of TSVs can effectively detect faulty TSVs, so as to choose to abandon faulty circuits or adopt corresponding repair strategies, and improve the yield of three-dimensional integrated circuits. Currently, many pre-bonding test methods for TSVs have been proposed:

[0003] A pre-bonding test method for TSVs based on a sense amplifier, which judges whether a TSV has a fault by measuring the time required for the TSV to be charged to a preset level. Its main disadvantage is that it is vulnerable to Process, Voltage, Temperature variations (PVT variations).

[0004] A pre-bonding test method for TSVs based on a ring oscillator, which judges whether a TSV has a fault by measuring the oscillation frequency after the TSV is connected to the ring oscillator. Its main disadvantages are that it is vulnerable to PVT variations and cannot effectively detect faults occurring at the end of the TSV.

[0005] A pre-bonding test method for TSVs resistant to PVT variations, which has a higher fault resolution for open circuit and leakage faults of TSVs, but the main defect is that it cannot distinguish mixed open circuit and leakage faults.

[0006] A pre-bonding test method for TSVs based on pulse reduction, which uses a pulse reduction circuit to detect the transmission delay of the TSV, so as to judge whether the TSV has a fault. Its main advantage is that it can effectively detect open circuit, leakage, and mixed open circuit and leakage faults of TSVs, and the disadvantage is that it is vulnerable to PVT variations.

[0007] A pre-bonding test method for TSVs based on a self-biased current source, which uses the self-biased current source to charge and discharge the TSV, and judges whether the TSV has a fault by the change in the total charge and discharge time. The main advantages of this method are that it can effectively detect open circuit, leakage, and mixed open circuit and leakage faults of TSVs and has good robustness. Its main drawback is that the test circuit uses a mixed-signal circuit, which is not as easy to integrate as a pure digital circuit.

[0008] In summary, the existing pre-bonding test methods for TSVs all have certain disadvantages, which are not conducive to the accuracy and integration of pre-bonding testing of TSVs. Summary of the Invention

[0009] The present invention aims to solve the problem that the existing pre - bonding test methods for TSVs are difficult to simultaneously meet the requirements of accuracy and integration. Now, a pre - bonding test circuit and method for TSVs based on an enhanced ring oscillator are provided.

[0010] The pre - bonding test circuit for TSVs based on an enhanced ring oscillator includes: a mode port, an instruction port, a clock port, a counting port, D flip - flops 1 to D flip - flops 2k, and rings 1 to rings k;

[0011] Each of rings 3 to rings k is connected to a TSV under test.

[0012] D flip - flops 1 to D flip - flops k respectively correspond to rings 1 to rings k one by one, and D flip - flops k + 1 to D flip - flops 2k respectively correspond to rings 1 to rings k one by one;

[0013] The D flip - flops 1 to D flip - flops 2k are connected in series end - to - end. The output ports of D flip - flops 1 to D flip - flops k are respectively connected to the input enable ports of the corresponding rings, and the output ports of D flip - flops k + 1 to D flip - flops 2k are respectively connected to the selection ports of the corresponding rings;

[0014] The clock port is respectively connected to the clock ports of D flip - flops 1 to D flip - flops 2k;

[0015] The instruction port is connected to the instruction input port of D flip - flop 1;

[0016] The mode port is respectively connected to the mode enable ports of each ring;

[0017] The counting port is respectively connected to the output ports of each ring.

[0018] Furthermore, rings 1 and rings 3 to rings k have the same structure and each includes two upper - layer tri - state drivers, two lower - layer tri - state drivers, and a multiplexer;

[0019] Ring 2 includes two upper - layer tri - state drivers, six lower - layer tri - state drivers, and a multiplexer;

[0020] In each ring, the output ends of the upper - layer tri - state driver and the lower - layer tri - state driver at the front end are respectively connected to the input ends of the upper - layer tri - state driver and the lower - layer tri - state driver at the back end. The output end of the multiplexer is connected to the enable end of the upper - layer tri - state driver at the front end. The enable ends of all lower - layer tri - state drivers together serve as the mode enable port of the corresponding ring. The enable end of the upper - layer tri - state driver at the back end and one input end of the multiplexer together serve as the input enable port of the corresponding ring. The selection end of the multiplexer serves as the selection port of the corresponding ring. The output end of the upper - layer tri - state driver at the back end serves as the output port of the corresponding ring;

[0021] In Loops 3 to Loop k, the output terminals of the upper tri-state driver and the lower tri-state driver at the front end in each loop are each connected to a TSV under test.

[0022] Furthermore, the above TSV pre-bonding test circuit further includes a delay circuit, an inverter, and a non-inverter;

[0023] The output ports of all loops are connected to the input terminal of the delay circuit, the output terminal of the delay circuit is respectively connected to a counting port, the input terminal of the inverter, and the input terminal of the non-inverter. The output terminal of the inverter is respectively connected to the other input terminals of each multiplexer, and the output terminal of the non-inverter is respectively connected to the input terminals of the upper tri-state drivers at the front end in each loop.

[0024] Furthermore, in Loops 3 to Loop k, the input terminal of the lower tri-state driver at the front end and the output terminal of the lower tri-state driver at the rear end are each connected to the logic circuit of the TSV under test.

[0025] Furthermore, the above TSV pre-bonding test circuit includes an open-circuit fault test mode and a leakage fault test mode.

[0026] Furthermore, within k + 1 clock cycles, make the instruction port input a "0" signal in the first clock cycle and input "1" signals in the remaining k clock cycles, so that D flip-flops 1 to D flip-flops k sequentially provide enable signals En1 to Enk for the upper tri-state drivers in Loops 1 to Loop k. Under the action of these enable signals En1 to Enk, Loops 1 to Loop k sequentially enter the open-circuit fault test mode.

[0027] Furthermore, within k + 1 clock cycles, make the instruction port input a "0" signal in the first clock cycle and input "1" signals in the remaining k clock cycles, so that D flip-flops 1 to D flip-flops k sequentially provide enable signals En1 to Enk for the upper tri-state drivers at the rear end in Loops 1 to Loop k. At the same time, D flip-flops k + 1 to D flip-flops 2k sequentially provide "0" selection signals for the multiplexers in Loops 1 to Loop k. Under the combined action of the enable signals En1 to Enk and the "0" selection signals, Loops 1 to Loop k sequentially enter the leakage fault test mode.

[0028] Furthermore, the above TSV pre-bonding test method is implemented based on the above TSV pre-bonding test circuit based on an enhanced loop oscillator, and the TSV pre-bonding test method includes:

[0029] In the open-circuit fault test mode, calculate the open-circuit position x according to the following formula:

[0030] x = ΔT2 / ΔT1,

[0031] where, ΔT2 = T 待测 - T c1 , ΔT1 = T 无故障 - T c1 , T c1 and T c2 are respectively the oscillation periods of Loop 1 and Loop 2 in the open - circuit fault test mode, T 无故障 and T 待测 are respectively the oscillation periods of the loop where the fault - free TSV is located and the loop where the TSV to be detected is located;

[0032] In the leakage - fault test mode, calculate the leakage conductance G of the TSV to be measured according to the following formula TSV :

[0033]

[0034] where, R on , R off and C p are respectively the on - resistance, high - impedance resistance and total parasitic capacitance of the three - state driver, V DD is the power - supply voltage of the test circuit, V th is the driving threshold voltage of the three - state driver, C TSV is the load capacitance of the fault - free TSV, ΔT6 = T 待测 - T 无故障 .

[0035] Furthermore, when x = 0.5, it indicates that the open - circuit is in the middle of the TSV; when x = 0.1, it indicates that the open - circuit is at the upper 10% of the TSV; when x = 1, it indicates that there is no open - circuit fault in the TSV.

[0036] Furthermore, the on - resistance, high - impedance resistance and total parasitic capacitance R on , R off and C p of the above - mentioned three - state driver are obtained through the following formula:

[0037]

[0038] ΔT5 = R off C p ln(V DD / V th ) - R on 2C p ln(V DD / V th ),

[0039]

[0040] where, ΔT3 = T R1 - Tc1 , ΔT4 = T c2 - T c1 , ΔT5 = T R2 - T c2 , T R1 and T R2 are the oscillation periods of Loop 1 and Loop 2 respectively in the leakage fault test mode.

[0041] The pre - bonding test circuit for TSV based on the enhanced ring oscillator of the present invention has the following main advantages:

[0042] 1. It can effectively detect TSV open - circuit, leakage and open - circuit leakage hybrid faults, and can quantitatively diagnose the severity of the faults. For open - circuit faults, the coverage rate can reach 95%, and the minimum capacitance resolution is 2.98 fF; for leakage faults, the minimum measurable leakage conductance is 4 nSiemens, and the leakage conductance diagnosis error does not exceed 11%.

[0043] 2. It can resist the influence of PVT variations and has good robustness.

[0044] 3. The test circuit is designed with standard gate circuits and has a pure digital structure, making it easier to integrate.

[0045] 4. The test time overhead and chip area overhead are small. The average test time required for each TSV is 4.27 microseconds, and the chip area occupied by the test circuit for each TSV is about 7.27 square micrometers. Description of the Drawings

[0046] Figure 1 is the overall structure diagram of the pre - bonding test circuit for TSV based on the enhanced ring oscillator;

[0047] Figure 2 is the test effect diagram of the pre - bonding test circuit for TSV based on the enhanced ring oscillator. Detailed Embodiments

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0049] Detailed Embodiment 1: Refer to Figure 1Specifically describing this embodiment, the TSV pre-bonding test circuit based on an enhanced ring oscillator in this embodiment has a total of three test control signal input ports, namely: a mode port, an instruction port, and a clock port, and one test result output port: a count port; k loops, namely: Loop 1 to Loop k; 2k D flip-flops, namely D flip-flop 1 to D flip-flop 2k.

[0050] Loop 1 and Loops 3 to k have the same structure, each including two upper tri-state drivers, two lower tri-state drivers, and one multiplexer. The output terminals of the upper tri-state driver and the lower tri-state driver at the front end are both connected to the input terminals of the upper tri-state driver and the lower tri-state driver at the rear end; the output terminals of the upper tri-state drivers at the rear end are all connected to the input terminals of the delay circuit. The output terminal of the multiplexer is connected to the enable terminal of the upper tri-state driver at the front end.

[0051] The difference between Loop 2 and other loops is that it includes 6 lower tri-state drivers, including three front-end lower tri-state drivers and three rear-end lower tri-state drivers. The output terminals of all front-end tri-state drivers are connected to the input terminals of the respective rear-end tri-state drivers.

[0052] Loops 1 and 2 do not contain the TSVs under test, and their test results will be used for de-embedding to improve the robustness of the test circuit against PVT variations. The output terminals of the two tri-state drivers at the front end in Loops 3 to k are both connected to a TSV under test. The input terminals of the lower tri-state drivers at the front end and the output terminals of the lower tri-state drivers at the rear end in Loops 3 to k are both used to connect to the logic circuits corresponding to the TSVs.

[0053] The output terminals of the delay circuit are respectively connected to the input terminals of the inverter, the input terminals of the non-inverter, and the count port. The output terminals of the non-inverter are respectively connected to one input terminal of each multiplexer. The output terminals of the inverter are respectively connected to the input terminals of the upper tri-state drivers at the front end.

[0054] The mode port is connected to the enable terminal Mode of the lower tri-state drivers in each loop.

[0055] When the enable signal input to the mode port is valid (the signal is "0"), these lower tri-state drivers are in the working state, connecting each TSV to its corresponding logic circuit, and all TSVs are in the normal working state; when the enable signal input to the mode port is invalid (the signal is "1"), these lower tri-state drivers are in the high-impedance state, isolating each TSV from its corresponding logic circuit, and all TSVs are in the test state.

[0056] The 2k D flip-flops are connected end to end to form a shift register.

[0057] The instruction port is connected to the instruction input port of D flip-flop 1.

[0058] The clock port is respectively connected to the clock ports of all D flip-flops.

[0059] The output terminals of D flip-flop 1 to D flip-flop k are respectively connected to the enable terminals of the upper three-state drivers located at the rear end in each loop and the other input terminals of the multiplexers.

[0060] The output terminals of D flip-flop k + 1 to D flip-flop 2k are respectively connected to the selection terminals (Control1 to Control k) of the multiplexers in each loop.

[0061] The working principle of the TSV pre-bonding test circuit based on the enhanced loop oscillator in this embodiment is as follows:

[0062] When the TSV is in the normal working state, let the instruction port input "1", and after inputting "2k" clock cycles at the clock port, all D flip-flops will output the "1" signal, which makes the upper two three-state drivers in each loop in the high-impedance state, and each TSV will be isolated from the test circuit.

[0063] When the TSV is in the test state, it can be divided into two cases:

[0064] First, let the instruction port input "0" for one clock cycle and then continue to hold "1", then within k clock cycles, D flip-flop 1 to D flip-flop k will successively provide the enable signals En1 to Enk for the upper two three-state drivers in loop 1 to loop k. Under the action of this enable signal, loop 1 to loop k will successively enter the open-circuit fault test mode. Under the action of the clock signal, loop 3 to loop k successively complete the open-circuit fault test of the TSV to be measured.

[0065] Secondly, after completing the open-circuit fault test, let the instruction port input "0" for one clock cycle and then continue to hold "1", then within the next k clock cycles, D flip-flop 1 to D flip-flop k will successively provide the enable signals En1 to Enk for the upper right three-state drivers in loop 1 to loop k and D flip-flop k + 1 to D flip-flop 2k will successively provide the "0" selection signal for the multiplexers in loop 1 to loop k. Under the combined action of the enable signals En1 to Enk and the "0" selection signal, loop 1 to loop k will successively enter the leakage fault test mode. Under the action of the clock signal, loop 3 to loop k successively complete the leakage fault test of the TSV to be measured.

[0066] Regardless of whether it is in the open-circuit fault test or the leakage fault test mode of the TSV, the test results of each loop will be output to the automatic test equipment in the form of frequency counting, and the automatic test equipment will analyze and calculate to give the corresponding open-circuit position and leakage conductance information.

[0067] Embodiment 2 of the specific implementation method: The pre-TSV bonding test method based on an enhanced ring oscillator described in this embodiment includes:

[0068] Assume that in the open-circuit fault test, the oscillation period measured by Loop 1 is T c1 , and the oscillation period measured by Loop 2 is T c2 , the oscillation period of the loop where the fault-free TSV is located is T 无故障 , and the oscillation period measured by the loop where the TSV to be detected is located is T 待测 , according to the TSV bonding pre-test circuit design principle described in Embodiment 1, if the effective load capacitance of the TSV to be detected is C TSV1 , and the load capacitance of the fault-free TSV is C TSV , then it satisfies the open-circuit capacitance calculation formula:

[0069]

[0070] where, ΔT2 = T 待测 - T c1 , ΔT1 = T 无故障 - T c1 .

[0071] And the effective load capacitance C of the TSV to be measured TSV1 is also in a proportional relationship with the open-circuit position x, and it satisfies x = C TSV1 / C TSV ;

[0072] When x = 0.5, it indicates that the open circuit is in the middle of the TSV;

[0073] When x = 0.1, it indicates that the open circuit is at the upper 10% of the TSV;

[0074] When x = 1, it indicates that there is no open-circuit fault in the TSV.

[0075] Since the failure rate of the TSV is between 0.1% and 0.01%, this means that most of the TSVs to be detected in a test group are fault-free TSVs. Therefore, in the calculation process, the oscillation period T of the loop where the fault-free TSV is located 无故障 can be obtained from the average value of the oscillation periods of each loop.

[0076] Assume that in the leakage fault test, the oscillation period measured by Loop 1 is T R1 , and the oscillation period measured by Loop 2 is T R2 , and the oscillation period measured by the loop where the TSV to be detected is located is T 待测 , then using T R1 , T R2 , T c1 , T c2The on-resistance R of the three-state driver can be obtained on , the high-impedance resistance R off and the total parasitic capacitance C p :

[0077]

[0078] ΔT5 = R off C p ln(V DD / V th ) - R on 2C p ln(V DD / V th ),

[0079]

[0080] where ΔT3 = T R1 -T c1 , ΔT4 = T c2 -T c1 , ΔT5 = T R2 -T c2 .

[0081] Finally, the leakage conductance G of the TSV to be measured can be obtained according to the leakage conductance calculation formula TSV :

[0082]

[0083] where ΔT6 = T 待测 -T 无故障 ; V DD is the power supply voltage of the test circuit, with a magnitude of 1.1V; V th is the driving threshold voltage of the three-state driver, with a magnitude of 0.5V.

[0084] Specific Embodiment 3: Refer to Figure 2 to specifically describe this embodiment. The TSV pre-bonding test circuit based on the enhanced loop oscillator described in this embodiment.

[0085] Figure 2Shows the test effect diagram of the TSV pre-bonding test circuit based on an enhanced ring oscillator with k = 32, that is, 32 rings (including 30 TSVs) for open-circuit leakage fault testing of TSVs. In the figure, Ring 1 and Ring 2 do not contain TSVs, and their test results are only used for de-embedding. Each of Ring 3 to Ring 32 contains a TSV under test. Among them, the TSV in Ring 12 has an open-circuit fault in the middle, the TSV in Ring 17 has an open-circuit fault at 1 / 6 of its inlet depth, the TSV in Ring 22 has a leakage fault of 100 microsiemens, and the TSV in Ring 32 has an open-circuit leakage mixed fault. The open-circuit position is at 3 / 4 of its inlet depth, and the leakage magnitude is 20 microsiemens. The TSVs in all other rings are fault-free TSVs. The T at the top of the figure c1 represents the oscillation period measured by Ring 1 in the open-circuit fault test, and T c2 represents the oscillation period measured by Ring 2 in the open-circuit fault test, and so on; T R22 represents the oscillation period measured by Ring 22 in the leakage fault test, and T R32 represents the oscillation period measured by Ring 32 in the leakage fault test, and so on. According to the above test period, open-circuit resistance, and leakage conductance calculation formula and the principle of the ring oscillator, the fault detection and diagnosis results shown in Table 1 can be given.

[0086] Table 1 Fault Detection and Diagnosis Results

[0087]

[0088] As can be seen from the results in Table 1, the test circuit can effectively detect and diagnose TSV open-circuit, leakage, and open-circuit leakage mixed faults, and has a high fault resolution and a small diagnostic error.

[0089] Although the present invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed, as long as they do not depart from the spirit and scope of the present invention as defined by the appended claims. It should be understood that different dependent claims and the features described herein can be combined in a manner different from that described in the original claims. It should also be understood that the features described in connection with a single embodiment can be used in other described embodiments.

Claims

1. A TSV pre-bonding test circuit based on an enhanced ring oscillator, characterized in that Comprising: A mode port, an instruction port, a clock port, a counting port, D flip-flops 1 to D flip-flops 2k, and loops 1 to loops k; Each of loops 3 to loops k is connected to a TSV under test; D flip-flops 1 to D flip-flops k respectively correspond one-to-one with loops 1 to loops k, and D flip-flops k + 1 to D flip-flops 2k respectively correspond one-to-one with loops 1 to loops k; The D flip-flops 1 to D flip-flops 2k are connected in series end to end, the output ports of D flip-flops 1 to D flip-flops k are respectively connected to the input enable ports of the corresponding loops, and the output ports of D flip-flops k + 1 to D flip-flops 2k are respectively connected to the selection ports of the corresponding loops; The clock port is respectively connected to the clock ports of D flip-flops 1 to D flip-flops 2k; The instruction port is connected to the instruction input port of D flip-flop 1; The mode port is respectively connected to the mode enable ports of each loop; The counting port is respectively connected to the output ports of each loop; The structures of loop 1 and loops 3 to loops k are the same and each includes two upper tri-state drivers, two lower tri-state drivers, and a multiplexer; Loop 2 includes two upper tri-state drivers, six lower tri-state drivers, and a multiplexer; In each loop, the output ends of the upper tri-state driver and the lower tri-state driver at the front end are respectively connected to the input ends of the upper tri-state driver and the lower tri-state driver at the back end, the output end of the multiplexer is connected to the enable end of the upper tri-state driver at the front end, the enable ends of all the lower tri-state drivers together serve as the mode enable port of the loop where they are located, the enable end of the upper tri-state driver at the back end and one input end of the multiplexer together serve as the input enable port of the loop where they are located, the selection end of the multiplexer serves as the selection port of the loop where it is located, and the output end of the upper tri-state driver at the back end serves as the output port of the loop where it is located; In loops 3 to loops k, the output ends of the upper tri-state driver and the lower tri-state driver at the front end of each loop are both connected to a TSV under test; In loops 3 to loops k, the input end of the lower tri-state driver at the front end and the output end of the lower tri-state driver at the back end are both connected to the logic circuit of the TSV under test; 2. The pre-TSV bonding test circuit based on an enhanced ring oscillator according to claim 1, wherein It further includes a delay circuit, an inverter, and a non-inverter; The output ports of all loops are connected to the input end of the delay circuit, the output end of the delay circuit is respectively connected to the counting port, the input end of the inverter, and the input end of the non-inverter, the output end of the inverter is respectively connected to the other input ends of each multiplexer, and the output end of the non-inverter is respectively connected to the input ends of the upper tri-state drivers at the front end of each loop; 3. The pre-TSV bonding test circuit based on an enhanced ring oscillator according to claim 1 or 2, wherein The pre-TSV bonding test circuit includes an open-circuit fault test mode and a leakage fault test mode.

4. The pre-TSV bonding test circuit based on an enhanced loop oscillator according to claim 3, wherein, Within k + 1 clock cycles, make the instruction port input a "0" signal in the first clock cycle and "1" signals in the remaining k clock cycles, so that D flip - flops 1 to D flip - flop k sequentially provide enable signals En1 to Enk for the upper - layer tri - state drivers in loops 1 to loop k. Under the action of these enable signals En1 to Enk, loops 1 to loop k sequentially enter the open - circuit fault test mode.

5. The pre - TSV - bonding test circuit based on the enhanced ring oscillator according to claim 3, characterized in that Within k + 1 clock cycles, make the instruction port input a "0" signal in the first clock cycle and "1" signals in the remaining k clock cycles, so that D flip - flops 1 to D flip - flop k sequentially provide enable signals En1 to Enk for the upper - layer tri - state drivers located at the back end in loops 1 to loop k. At the same time, D flip - flops k + 1 to D flip - flop 2k sequentially provide "0" selection signals for the multiplexers in loops 1 to loop k. Under the combined action of the enable signals En1 to Enk and the "0" selection signals, loops 1 to loop k sequentially enter the leakage - fault test mode.

6. The pre-bonding test method for TSV based on an enhanced ring oscillator, characterized in that, The pre - TSV - bonding test method is implemented based on the pre - TSV - bonding test circuit based on the enhanced ring oscillator according to any one of claims 1 to 5. The pre - TSV - bonding test method includes: In the open - circuit fault test mode, calculate the open - circuit position x according to the following formula: x = ΔT2 / ΔT1, where, ΔT2 = T 待测 - T c1 , ΔT1 = T 无故障 - T c1 , T c1 and T c2 are the oscillation periods of Loop 1 and Loop 2 respectively in the open - circuit fault test mode, T 无故障 and T 待测 are the oscillation periods of the loop where the fault - free TSV is located and the loop where the TSV to be detected is located respectively; In the leakage fault test mode, the leakage conductance G of the TSV to be measured is calculated according to the following formula TSV :[[]]END]] Among them, R on , R off and C p are the on-resistance, high-impedance resistance, and total parasitic capacitance of the three-state driver respectively, V DD is the power supply voltage of the test circuit, V th is the driving threshold voltage of the three-state driver, C TSV is the load capacitance of the TSV without faults, ΔT6 = T 待测 - T 无故障 .

7. The pre-bonding test method for TSV based on an enhanced ring oscillator according to claim 6, wherein When x = 0.5, it indicates that the open - circuit is in the middle of the TSV; When x = 0.1, it indicates that the open - circuit is at the upper 10% of the TSV; When x = 1, it indicates that there is no open - circuit fault in the TSV.

8. The pre-TSV bonding test method based on an enhanced ring oscillator according to claim 6, characterized in that The on-resistance, high-impedance resistance, and total parasitic capacitance R on 、R off and C p are obtained by the following formula: ΔT5 = R off C p ln(V DD / V th ) - R on 2C p ln(V DD / V th ) where, ΔT3 = T R1 - T c1 , ΔT4 = T c2 - T c1 , ΔT5 = T R2 - T c2 , T R1 and T R2 are the oscillation periods of Loop 1 and Loop 2 respectively in the leakage fault test mode.

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