Memory management method and memory storage device

Abstract

The invention provides a memory management method and a memory storage device. The memory management method is used for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity erasing units. The memory management method comprises the following steps of: obtaining a plurality of pieces of state information respectively corresponding to the plurality of entity erasing units, wherein the plurality of pieces of state information reflect an operation mode of each entity erasing unit and an effective count value of each entity erasing unit; and performing a target consolidation operation based on the plurality of state information, where the target consolidation operation is a first data consolidation operation or a second data consolidation operation, the first data consolidation operation being different from the second data consolidation operation.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a memory storage device. Background Art

[0002] Smart phones, tablet computers and personal computers have grown rapidly in the past few years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable multimedia devices listed above because they are non-volatile, power-saving, small in size, and have no mechanical structure.

[0003] In order to improve the data processing capability of the storage device, the storage space may be optimized by performing data consolidation operations such as garbage collection (GC), thereby achieving the purpose of improving the performance and / or response speed of the storage device.

[0004] How to improve the efficiency of garbage collection operations is a topic of concern to those skilled in the art. Summary of the invention

[0005] An exemplary embodiment of the present invention provides a memory management method and a memory storage device, which can improve a conventional data consolidation operation (ie, a garbage collection operation) to enhance the performance of the memory storage device.

[0006] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erase units, and the memory management method includes: obtaining a plurality of status information corresponding to the plurality of physical erase units, wherein the plurality of status information reflects an operation mode of each of the physical erase units and a valid count value of each of the physical erase units; and performing a target consolidation operation based on the plurality of status information, wherein the target consolidation operation is a first data consolidation operation or a second data consolidation operation, and the first data consolidation operation is different from the second data consolidation operation.

[0007] In an exemplary embodiment of the present invention, the operation mode of each of the physical erase units is one of a single-level memory cell mode, a second-level memory cell mode, a third-level memory cell mode, and a fourth-level memory cell mode.

[0008] In an exemplary embodiment of the present invention, the step of performing the target consolidation operation based on the multiple status information includes: determining a source physical erase unit from candidate physical erase units according to the multiple status information; collecting valid data from the source physical erase unit; and moving the valid data to a target physical erase unit, and associating the source physical erase unit with an idle area.

[0009] In an exemplary embodiment of the present invention, the memory management method further comprises: based on the plurality of status information, selecting a physical erasing unit having the valid count value lower than a pre-designed value among the plurality of physical erasing units as the candidate physical erasing unit.

[0010] In an exemplary embodiment of the present invention, the first data consolidation operation includes: selecting the source physical erase unit from the candidate physical erase units belonging to the single-level storage cell mode; collecting the valid data from the source physical erase unit; and moving the valid data to the target physical erase unit, and associating the source physical erase unit with the idle area.

[0011] In an exemplary embodiment of the present invention, the second data consolidation operation includes: selecting the source physical erase unit from the candidate physical erase units that do not belong to the single-level storage cell mode; collecting the valid data from the source physical erase unit; and moving the valid data to the target physical erase unit, and associating the source physical erase unit with the idle area.

[0012] In an exemplary embodiment of the present invention, the step of performing the target consolidation operation based on the multiple status information includes: determining the number of the candidate physical erase units belonging to the single-level storage cell mode; determining whether there are target candidate physical erase units whose number is greater than a preset number, wherein the target candidate physical erase unit is at least one of the candidate physical erase units belonging to the single-level storage cell mode; and if the target candidate physical erase unit exists, performing the first data consolidation operation.

[0013] In an exemplary embodiment of the present invention, the memory management method further includes: if the target candidate physical erase unit does not exist, calculating a total valid count value based on the valid count values ​​of the candidate physical erase units belonging to the single-level storage unit mode; determining whether the total valid count value is greater than a preset total value; if the total valid count value is greater than the preset total value, executing the first data consolidation operation; and if the total valid count value is not greater than the preset total value, executing the second data consolidation operation.

[0014] In an exemplary embodiment of the present invention, the preset total value is associated with the capacity of the physical erasing unit.

[0015] In an exemplary embodiment of the present invention, the valid count value is used to represent the number of physical programming units for storing valid data in each of the physical erasing units.

[0016] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory control circuit unit is used to obtain a plurality of status information corresponding to the plurality of physical erase units, respectively, wherein the plurality of status information reflects the operation mode of each of the physical erase units and the effective count value of each of the physical erase units. The memory control circuit unit is also used to perform a target consolidation operation based on the plurality of status information, wherein the target consolidation operation is a first data consolidation operation or a second data consolidation operation, and the first data consolidation operation is different from the second data consolidation operation.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine a source physical erase unit from candidate physical erase units according to the plurality of state information. The memory control circuit unit is further used to collect valid data from the source physical erase unit. The memory control circuit unit is further used to move the valid data to a target physical erase unit and associate the source physical erase unit with an idle area.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select a physical erase unit having the valid count value lower than a pre-designed value among the plurality of physical erase units as the candidate physical erase unit based on the plurality of state information.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to select the source physical erase unit from the candidate physical erase units belonging to the single-level memory cell mode. The memory control circuit unit is further used to collect the valid data from the source physical erase unit. The memory control circuit unit is further used to move the valid data to the target physical erase unit and associate the source physical erase unit with the idle area.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to select the source physical erase unit from the candidate physical erase units that do not belong to the single-level memory cell mode. The memory control circuit unit is further used to collect the valid data from the source physical erase unit. The memory control circuit unit is further used to move the valid data to the target physical erase unit and associate the source physical erase unit with the idle area.

[0021] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine the number of the candidate physical erase units belonging to the single-level storage cell mode. The memory control circuit unit is further used to determine whether there are target candidate physical erase units whose number is greater than a preset number, wherein the target candidate physical erase unit is at least one of the candidate physical erase units belonging to the single-level storage cell mode. If the target candidate physical erase unit exists, the memory control circuit unit is further used to perform the first data consolidation operation.

[0022] In an exemplary embodiment of the present invention, if the target candidate physical erase unit does not exist, the memory control circuit unit is further used to calculate a total effective count value according to the effective count value of the candidate physical erase unit belonging to the single-level memory cell mode. The memory control circuit unit is further used to determine whether the total effective count value is greater than a preset total value. If the total effective count value is greater than the preset total value, the memory control circuit unit is further used to perform the first data consolidation operation. If the total effective count value is not greater than the preset total value, the memory control circuit unit is further used to perform the second data consolidation operation.

[0023] Based on the above, the present invention provides a memory management method and a memory storage device, which can perform a first data consolidation operation using a source physical erase unit belonging to a single-level storage cell mode or a second data consolidation operation using a source physical erase unit that does not belong to a single-level storage cell mode (for example, a second-level storage cell mode, a third-level storage cell mode, or a fourth-level storage cell mode) based on the status information of the physical erase unit to improve the performance of the memory storage device.

[0024] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0031] Figure 7 is a flow chart of a memory management method according to an exemplary embodiment of the present invention;

[0032] Figure 8 is a flowchart of performing a first data merging operation according to an exemplary embodiment of the present invention;

[0033] Fig. 9 is a flowchart of performing a second data merging operation according to an exemplary embodiment of the present invention;

[0034] Fig.10 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0037] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0039] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0040] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0041] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the host system 11 is a vehicle-mounted system. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0043] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0044] Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0045] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0047] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0048] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0049] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0050] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0051] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

[0052] In an exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasure unit contains the minimum number of storage cells that are erased together. For example, the physical erasure unit is a physical block.

[0053] Figure 5 FIG. 4 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0055] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are recorded in the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0057] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0058] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0059] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0060] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations (for example, changing a read voltage level or performing a garbage collection operation, etc.). These command sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. may be included.

[0061] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0062] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0063] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0064] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0065] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0066] Please refer to Figure 6 , the memory management circuit 51 can logically group the physical units 610(0)-610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. A physical unit refers to a virtual block (VB). A virtual block may include multiple physical programming units. For example, a virtual block may include one or more physical erasing units.

[0067] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0068] The memory management circuit 51 can configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0069] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in this physical unit contains valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in this physical unit does not contain any valid data.

[0070] The memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may perform a data access operation on the memory storage device 10 according to the information in the logical-to-physical mapping table.

[0071] Most of today's memory storage devices 10 have a copyback function. Under the copyback architecture, data that is frequently accessed or updated (also called hot data) is stored in a physical erase unit based on a single-level cell (SLC) mode. Data that is infrequently accessed or updated (also called cold data) is stored in a physical erase unit based on a second-level cell (MLC) mode, a third-level cell (TLC) mode, or a fourth-level cell (QLC) mode according to the specifications of the memory storage device 10.

[0072] It should be noted that, since conventional data consolidation operations (e.g., garbage collection operations) use the effective count value as a basis for determining the source physical erase unit, the memory management circuit 51 will often use the physical erase unit of the single-level storage cell mode as the source physical erase unit, so that the hot data and the cold data (e.g., the data stored in the physical erase unit of the three-level storage cell mode) in the physical erase unit of the single-level storage cell mode are mixed in one physical erase unit (i.e., the target physical erase unit). Accordingly, when the hot data in this physical erase unit is overwritten in a write operation, the effective count value of this physical erase unit will decrease, and it will be used as the source physical erase unit for the subsequent data consolidation operation.

[0073] According to the above, under conventional data consolidation operations, hot and cold data will be mixed, so that the same physical erase unit is repeatedly used as a source physical erase unit, which will increase the frequency of data consolidation operations and cause wear on the rewritable non-volatile memory module 43, thereby reducing the performance of the memory storage device 10.

[0074] In view of this, the present invention provides a memory management method, which can adopt different data consolidation operations based on multiple state information corresponding to multiple physical erasing units in the rewritable non-volatile memory module 43 to avoid the above problems.

[0075] Figure 7 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Figure 7 Steps shown:

[0076] In step S701 , the memory management circuit 51 may obtain a plurality of status information respectively corresponding to a plurality of physical erasing units.

[0077] In an exemplary embodiment, the state information may, for example, reflect the operation mode and valid count value of the corresponding physical erase unit. The operation mode may include but is not limited to a single-level cell (SLC) mode, a second-level cell (MLC) mode, a third-level cell (TLC) mode, or a fourth-level cell (QLC) mode. That is, a physical erase unit may, for example, be written with data based on a single-level cell mode, a second-level cell mode, a third-level cell mode, or a fourth-level cell mode.

[0078] The valid count value is used to indicate the number of physical programming units used to store valid data in a physical erasing unit. In other words, the valid count value can reflect the occupied capacity of the valid data stored in a physical erasing unit.

[0079] It should be noted that after obtaining a write command from the host system 11, the memory management circuit 51 may write data into at least one physical programming unit (for example, 2) in a corresponding physical erasing unit according to the write command. After the memory management circuit 51 writes the data into the two physical programming units, the memory management circuit 51 may increase the effective count value of the physical erasing unit by 2. On the other hand, when the data stored in at least one physical programming unit (for example, 3) in a physical erasing unit is deleted or marked as invalid data, the memory management circuit 51 may reduce the effective count value of the physical erasing unit by 3.

[0080] In step S702 , the memory management circuit 51 may select a physical erasing unit having a valid count value lower than a pre-designed value among the plurality of physical erasing units as a candidate physical erasing unit based on the plurality of state information.

[0081] In an exemplary embodiment, the memory management circuit 51 can determine whether the valid count value corresponding to each physical erase unit is lower than the pre-designed value to select a candidate physical erase unit for subsequent target consolidation operations. Specifically, the valid count value corresponding to a physical erase unit can reflect the occupied capacity of the valid data stored therein. The pre-designed value is used to represent the lower limit number of physical programming units that need to be used to store valid data in a physical erase unit. In other words, the pre-designed value can reflect the lower limit occupied capacity of the valid data stored in a physical erase unit. The pre-designed value can be designed by the user according to actual needs, and the present invention is not limited thereto.

[0082] If the effective count value of a physical erase unit is lower than the pre-designed value, that is, the occupied capacity of the valid data stored in the physical erase unit is lower than the preset capacity reflected by the pre-designed value, the memory management circuit 51 can select the physical erase unit as a candidate physical erase unit. On the contrary, if the effective count value of a physical erase unit is not lower than the pre-designed value, that is, the occupied capacity of the valid data stored in the physical erase unit is not lower than the preset capacity reflected by the pre-designed value, the physical erase unit is not selected as a candidate physical erase unit.

[0083] In step S703 , the memory management circuit 51 may determine the number of candidate physical erase cells belonging to the single-level memory cell mode.

[0084] In an exemplary embodiment, the operation mode of the candidate physical erase unit may be, for example, a single-level cell (SLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode. The memory management circuit 51 may obtain the operation mode of each candidate physical erase unit based on the state information corresponding to each candidate physical erase unit, and calculate the number of candidate physical erase units belonging to the single-level cell mode among all candidate physical erase units.

[0085] In step S704 , the memory management circuit 51 may determine whether there are target candidate physical erase units whose number is greater than a preset number.

[0086] Specifically, the preset number can be designed by the user according to actual needs, and the present invention is not limited thereto. In an exemplary embodiment, the target candidate physical erase unit is at least one of the candidate physical erase units belonging to the single-level memory cell mode.

[0087] If there is a target candidate physical erase unit, the process proceeds to step S705 to perform a first data consolidation operation, wherein the first data consolidation operation is performed on a candidate physical erase unit in a single-level memory cell mode.

[0088] In step S705, the memory management circuit 51 may perform a first data consolidation operation. Figure 8 As shown, Figure 8 is a flowchart of performing a first data merging operation according to an exemplary embodiment of the present invention, please refer to Figure 7 and Figure 8 .

[0089] In step S7051 , the memory management circuit 51 may select a source physical erase unit from candidate physical erase units belonging to the single-level memory cell mode, and select a target physical erase unit.

[0090] In an exemplary embodiment, the memory management circuit 51 uses a candidate physical erase unit belonging to the single-level memory cell mode as a source physical erase unit of the first data consolidation operation. In other words, a candidate physical erase unit that does not belong to the single-level memory cell mode (i.e., a candidate physical erase unit that belongs to the third-level memory cell mode or the fourth-level memory cell mode) cannot be used as a source physical erase unit of the first data consolidation operation. In addition, the memory management circuit 51 can select a physical erase unit as a target physical erase unit of the first data consolidation operation.

[0091] In step S7052 , the memory management circuit 51 may collect valid data from the source physical erase unit. Next, in step S7053 , the memory management circuit 51 may move the valid data to the target physical erase unit and associate the source physical erase unit with the idle area 602 .

[0092] In an exemplary embodiment, after the valid data in the source physical erase unit is moved (or copied) to the target physical erase unit, the memory management circuit 51 may erase the source physical erase unit and release the erased source physical erase unit to the idle area 602. That is, after the valid data in the source physical erase unit is moved (or copied), the memory management circuit 51 may perform an erase operation on the source physical erase unit that does not store valid data (that is, only stores invalid data) to associate the source physical erase unit with the idle area 602, so as to increase the storage space of the rewritable non-volatile memory module 43.

[0093] In contrast, if there is no target candidate physical erase unit, the process proceeds to step S706, where the memory management circuit 51 can calculate the total valid count value based on the valid count values ​​of the candidate physical erase units belonging to the single-level memory cell mode. In an exemplary embodiment, the memory management circuit 51 sums up the valid count values ​​of the candidate physical erase units belonging to the single-level memory cell mode among all the candidate physical erase units to calculate the total valid count value.

[0094] In step S707, the memory management circuit 51 may determine whether the total valid count value is greater than a preset total count value. In an exemplary embodiment, the preset total count value is associated with the capacity of a physical erase unit. If the total valid count value is greater than the preset total count value, for example, the valid data in the candidate physical erase units belonging to the single-level storage unit mode among all candidate physical erase units is sufficient to fill the target physical erase unit, then step S705 is entered to perform the first data consolidation operation.

[0095] On the contrary, if the total valid count value is not greater than the preset total count value, the process proceeds to step S708 to perform a second data consolidation operation, wherein the second data consolidation operation is performed on candidate physical erasure units of the third-level memory cell mode or the fourth-level memory cell mode.

[0096] In step S708, the memory management circuit 51 may perform a second data consolidation operation. Fig. 9 As shown, Fig. 9 is a flowchart of performing the second data merging operation according to an exemplary embodiment of the present invention, please refer to Figure 7 and Fig. 9 .

[0097] In step S7081 , the memory management circuit 51 may select a source physical erase unit from candidate physical erase units that do not belong to the single-level memory cell mode, and select a target physical erase unit.

[0098] In an exemplary embodiment, the memory management circuit 51 uses a candidate physical erase unit that does not belong to the single-level memory cell mode (that is, belongs to the third-level memory cell mode or the fourth-level memory cell mode) as a source physical erase unit for the second data consolidation operation. In other words, a candidate physical erase unit that belongs to the single-level memory cell mode cannot be used as a source physical erase unit for the second data consolidation operation. In addition, the memory management circuit 51 can select a physical erase unit as a target physical erase unit for the second data consolidation operation.

[0099] In step S7082 , the memory management circuit 51 may collect valid data from the source physical erase unit. Next, in step S7083 , the memory management circuit 51 may move the valid data to the target physical erase unit and associate the source physical erase unit with the idle area 602 .

[0100] In an exemplary embodiment, after the valid data in the source physical erase unit is moved (or copied) to the target physical erase unit, the memory management circuit 51 can perform an erase operation on the source physical erase unit to associate the source physical erase unit with the idle area 602 to increase the storage space of the rewritable non-volatile memory module 43.

[0101] Specifically, in Figure 7 In the memory management method, before the target consolidation operation (i.e., the first data consolidation operation or the second data consolidation operation) is executed, the memory management circuit 51 performs a round of query operation to determine the source physical erase unit used for the target consolidation operation, wherein the query operation includes searching for physical erase units belonging to different operation modes such as a single-level storage cell mode, a three-level storage cell mode, and a four-level storage cell mode to determine the valid count value of the physical erase unit belonging to each operation mode.

[0102] Next, the memory management circuit 51 will take the physical erase unit with a valid count value lower than the pre-designed value as a candidate physical erase unit. Specifically, the valid count value corresponding to a physical erase unit can reflect the occupied capacity of the valid data stored therein. The pre-designed value can reflect the lower limit occupied capacity of the valid data stored in a physical erase unit. The memory management circuit 51 can take the physical erase unit that does not store enough valid data as a candidate physical erase unit for the target consolidation operation.

[0103] Further, the memory management circuit 51 may determine whether to use the candidate physical erase unit belonging to the single-level memory cell mode as the source physical erase unit of the target merge operation. In this regard, if the first point is satisfied: the number of the candidate physical erase units belonging to the single-level memory cell mode is greater than the preset number, or the second point is satisfied: the total valid count value of all the candidate physical erase units belonging to the single-level memory cell mode is greater than the preset total count value, then the memory management circuit 51 may use the candidate physical erase unit belonging to the single-level memory cell mode as the source physical erase unit of the target merge operation (i.e., the first data merge operation). On the other hand, if both of the above two points are not satisfied, then the memory management circuit 51 may use the candidate physical erase unit belonging to the third-level memory cell mode or the fourth-level memory cell mode as the source physical erase unit of the target merge operation (i.e., the second data merge operation).

[0104] Regarding the above point (1), in detail, if the number of candidate physical erase units (SLC Num) belonging to the single-level storage cell mode is greater than a preset number (assuming it is n, where n is a positive integer), it means that there are enough physical erase units belonging to the single-level storage cell mode in the candidate physical erase units that can be used as source physical erase units for the target consolidation operation, so the memory management circuit 51 can choose to perform the first data consolidation operation. Wherein n is a positive integer, and the value of n can be dynamically set according to actual usage, that is, the memory management circuit 51 can dynamically adjust the pre-designed value (n) according to the actual usage and performance indicators to achieve the best data consolidation performance.

[0105] Regarding the above point (2), in detail, in the application of the valid count value, in addition to considering the valid count value of each physical erase unit, the memory management circuit 51 will further calculate the total valid count value (Total Valid Cnt) of the candidate physical erase units belonging to the single-level storage cell mode, and determine whether to perform the first data consolidation operation or the second data consolidation operation based on the total valid count value.

[0106] Specifically, if the total valid count value is greater than the capacity of k physical erase units, it means that there is enough valid data in the candidate physical erase units belonging to the single-level storage unit mode to fill the target physical erase units, so the memory management circuit 51 can choose to perform the first data consolidation operation. Wherein, k is a positive integer, and the value of k can be dynamically set according to actual usage, that is, the memory management circuit 51 can dynamically adjust the value of k according to actual usage and performance indicators to achieve the best data consolidation performance.

[0107] According to the above, the exemplary embodiment of the present invention can determine whether to use the first data consolidation operation or the second data consolidation operation by setting the above two points, which can reduce the mixing of cold data and hot data. Further explanation, since hot data has a greater probability of being stored in a physical erase unit belonging to a single-level storage unit mode, and cold data has a greater probability of being stored in a physical erase unit belonging to a third-level storage unit or a fourth-level storage unit. By preferentially using a physical erase unit belonging to a single-level storage unit mode for data consolidation operations, the fast access performance of hot data can be maintained. In addition, by selecting an appropriate physical erase unit as the source physical erase unit for the data consolidation operation, unnecessary data movement and copying can be reduced, thereby improving the efficiency of the data consolidation operation.

[0108] Fig.10 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Fig.10 In step S1001, a plurality of state information corresponding to a plurality of physical erase units are obtained, wherein the plurality of state information reflects an operation mode of each physical erase unit and a valid count value of each physical erase unit. In step S1002, a target merge operation is performed based on the plurality of state information, wherein the target merge operation is a first data merge operation or a second data merge operation, and the first data merge operation is different from the second data merge operation.

[0109] However, Fig.10 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.10 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.10The method can be used in combination with the above embodiments or can be used alone, and the present invention is not limited thereto.

[0110] In summary, the memory management method and memory storage device proposed in the exemplary embodiments of the present invention can perform a first data consolidation operation using a source physical erase unit belonging to a single-level storage cell mode or a second data consolidation operation using a source physical erase unit that does not belong to a single-level storage cell mode (for example, a second-level storage cell mode, a third-level storage cell mode, or a fourth-level storage cell mode) based on the status information of the physical erase unit, so as to avoid the situation where the same physical erase unit is repeatedly used as the source physical erase unit due to the mixing of cold and hot data, thereby reducing the wear of the rewritable non-volatile memory module and effectively improving the performance of the memory storage device.

[0111] Finally, it should be noted that the above exemplary embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above exemplary embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above exemplary embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the exemplary embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, and the memory management method includes: Acquire a plurality of status information respectively corresponding to the plurality of physical erasing units, wherein the plurality of status information reflects an operation mode of each of the physical erasing units and a valid count value of each of the physical erasing units; and Based on the plurality of state information, a target merge operation is performed, wherein the target merge operation is a first data merge operation or a second data merge operation, and the first data merge operation is different from the second data merge operation.

2. The memory management method according to claim 1, wherein: The operation mode of each of the physical erasing units is one of a single-level memory cell mode, a second-level memory cell mode, a third-level memory cell mode, and a fourth-level memory cell mode.

3. The memory management method according to claim 2, wherein the step of performing the target consolidation operation based on the plurality of status information comprises: Determine a source physical erasure unit from candidate physical erasure units according to the plurality of state information; Collecting valid data from the source physical erase unit; as well as The valid data is moved to a target physical erase unit, and the source physical erase unit is associated with an idle area.

4. The memory management method according to claim 3, further comprising: Based on the plurality of state information, a physical erasing unit having the valid count value lower than a pre-designed value among the plurality of physical erasing units is taken as the candidate physical erasing unit.

5. The memory management method according to claim 3, wherein: The first data consolidation operation includes: Selecting the source physical erasing unit from the candidate physical erasing units belonging to the single-level memory cell mode; Collecting the valid data from the source physical erase unit; and The valid data is moved to the target physical erase unit, and the source physical erase unit is associated with the idle area.

6. The memory management method according to claim 3, wherein the second data consolidation operation comprises: Selecting the source physical erasing unit from the candidate physical erasing units that do not belong to the single-level memory cell mode; Collecting the valid data from the source physical erase unit; as well as The valid data is moved to the target physical erase unit, and the source physical erase unit is associated with the idle area.

7. The memory management method according to claim 3, wherein the step of performing the target consolidation operation based on the plurality of state information comprises: Determining the number of the candidate physical erase cells belonging to the single-level storage cell mode; Determining whether there are target candidate physical erasure units whose number is greater than a preset number, wherein the target candidate physical erasure unit is at least one of the candidate physical erasure units belonging to the single-level storage cell mode; as well as If the target candidate physical erasure unit exists, the first data consolidation operation is performed.

8. The memory management method according to claim 7, further comprising: If the target candidate physical erase unit does not exist, calculating a total valid count value according to the valid count values ​​of the candidate physical erase units belonging to the single-level storage cell mode; Determine whether the total valid count value is greater than a preset total count value; If the total valid count value is greater than the preset total count value, performing the first data consolidation operation; as well as If the total valid count value is not greater than the preset total count value, the second data consolidation operation is performed.

9. The memory management method according to claim 8, wherein: The preset total value is associated with the capacity of the physical erasing unit.

10. The memory management method according to claim 1, wherein: The valid count value is used to indicate the number of physical programming units for storing valid data in each of the physical erasing units.

11. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Acquire a plurality of status information respectively corresponding to the plurality of physical erasing units, wherein the plurality of status information reflects an operation mode of each of the physical erasing units and a valid count value of each of the physical erasing units; and Based on the plurality of state information, a target merge operation is performed, wherein the target merge operation is a first data merge operation or a second data merge operation, and the first data merge operation is different from the second data merge operation.

12. The memory storage device according to claim 11, wherein: The operation mode of each of the physical erasing units is one of a single-level memory cell mode, a second-level memory cell mode, a third-level memory cell mode, and a fourth-level memory cell mode.

13. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to: Determine a source physical erasure unit from candidate physical erasure units according to the plurality of state information; Collecting valid data from the source physical erase unit; and The valid data is moved to a target physical erase unit, and the source physical erase unit is associated with an idle area.

14. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Based on the plurality of state information, a physical erasing unit having the valid count value lower than a pre-designed value among the plurality of physical erasing units is taken as the candidate physical erasing unit.

15. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Selecting the source physical erasing unit from the candidate physical erasing units belonging to the single-level memory cell mode; Collecting the valid data from the source physical erase unit; and The valid data is moved to the target physical erase unit, and the source physical erase unit is associated with the idle area.

16. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Selecting the source physical erasing unit from the candidate physical erasing units that do not belong to the single-level memory cell mode; Collecting the valid data from the source physical erase unit; and The valid data is moved to the target physical erase unit, and the source physical erase unit is associated with the idle area.

17. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: Determining the number of the candidate physical erase cells belonging to the single-level storage cell mode; determining whether there are target candidate physical erase units whose number is greater than a preset number, wherein the target candidate physical erase unit is at least one of the candidate physical erase units belonging to the single-level memory cell mode; and If the target candidate physical erasure unit exists, the first data consolidation operation is performed.

18. The memory storage device according to claim 17, wherein the memory control circuit unit is further configured to: If the target candidate physical erase unit does not exist, calculating a total valid count value according to the valid count values ​​of the candidate physical erase units belonging to the single-level storage cell mode; Determine whether the total valid count value is greater than a preset total count value; If the total valid count value is greater than the preset total count value, performing the first data consolidation operation; as well as If the total valid count value is not greater than the preset total count value, the second data consolidation operation is performed.

19. The memory storage device of claim 18, wherein: The preset total value is associated with the capacity of the physical erasing unit.

20. The memory storage device of claim 11, wherein: The valid count value is used to indicate the number of physical programming units for storing valid data in each of the physical erasing units.

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