Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method includes: detecting a usage imbalance event for a first mode of operation; according to the use imbalance event, under the condition that the counting information meets a preset condition, executing a first type of cross-region extraction operation so as to extract a third entity unit from a third type of idle entity units, and using the third entity unit based on the first operation mode; updating counting information according to the first type of cross-region extraction operation; and if the counting information does not meet the preset condition, prohibiting execution of the first type of cross-region unit extraction operation. Therefore, the performance and the stability of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] In recent years, with the rapid advancement of electronic product technology, consumers have increasingly higher requirements for the experience of electronic storage products, and the market demand for higher speed and more convenient storage solutions is also growing. NAND flash memory (FLASH) has shown outstanding advantages in mobile applications such as mobile phones and smart sensor devices due to its non-volatility, low power consumption, compact design, no moving parts, and fast read and write speeds.

[0003] With the rapid evolution of flash memory technology, NAND flash memory has undergone a transformation from two-dimensional (2D) to three-dimensional (3D), and in terms of storage cells, it has also gradually evolved from single-layer storage cells (SLC) to three-layer (TLC) and even four-layer (QLC) storage cells. This series of technological innovations has greatly improved the storage density of NAND flash memory and reduced the cost per unit capacity. However, as the thickness of the oxide layer inside the flash memory continues to decrease, the impact of the erase and write operation on the storage medium has become more significant, thus affecting the durability and reliability of the flash memory.

[0004] In view of this, how to effectively manage NAND flash memory has become one of the core topics that engineers in the industry are currently concerned about. Optimizing management strategies not only helps to extend the service life of flash memory, but also further improves the overall performance and stability of the system, ensuring that users have a smoother and more reliable experience. Summary of the invention

[0005] The invention provides a memory management method and a memory device, which can improve the performance and stability of the memory device.

[0006] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: extracting a first physical unit from a first type of idle physical unit among the multiple physical units, and using the first physical unit based on a first operating mode; extracting a second physical unit from a second type of idle physical unit among the multiple physical units, and using the second physical unit based on a second operating mode; detecting a usage imbalance event for the first operating mode; based on the usage imbalance event, if counting information meets a preset condition, performing a first type of cross-region extraction operation to extract a third physical unit from a third type of idle physical unit among the multiple physical units, and using the third physical unit based on the first operating mode; based on the first type of cross-region extraction operation, updating the counting information; if the counting information does not meet the preset condition, prohibiting the execution of the first type of cross-region unit extraction operation.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: extract a first physical unit from a first type of idle physical unit in the plurality of physical units, and use the first physical unit based on a first operation mode; extract a second physical unit from a second type of idle physical unit in the plurality of physical units, and use the second physical unit based on a second operation mode; detect a usage imbalance event for the first operation mode; according to the usage imbalance event, if the counting information meets the preset condition, perform a first type of cross-region extraction operation to extract a third physical unit from a third type of idle physical unit in the plurality of physical units, and use the third physical unit based on the first operation mode; according to the first type of cross-region extraction operation, update the counting information; if the counting information does not meet the preset condition, prohibit the execution of the first type of cross-region unit extraction operation.

[0008] Based on the above, the first physical unit can be extracted from the first type of idle physical units and used based on the first operation mode. The second physical unit can be extracted from the second type of idle physical units and used based on the second operation mode. After detecting a usage imbalance event for the first operation mode, if the counting information meets the preset conditions, the first type of cross-region extraction operation can be performed to extract from the third type of idle physical units and use based on the first operation mode. According to the first type of cross-region extraction operation, the counting information can be updated. In addition, if the counting information does not meet the preset conditions, the first type of cross-region unit extraction operation can be prohibited. Thereby, the performance and stability of the storage device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of a first type of cross-region extraction operation and a first type of cross-region return operation according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of a second type of cross-region extraction operation and a second type of cross-region return operation according to an embodiment of the present invention;

[0014] Figure 6 is a flowchart of a memory management method according to an embodiment of the present invention;

[0015] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0022] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0026] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B) and 302 ( 1 ) to 302 (E). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner.

[0027] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0028] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A), 302(1)-302(C), 301(A+1)-301(B), 302(C+1)-302(D), and 302(D+1)-302(E) to the data area (also called the first data area) 31, the data area (also called the second data area) 32, the idle area (also called the first idle area) 33, the idle area (also called the second idle area) 34, and the idle area (also called the third idle area) 35. The physical units 301(1)-301(A) and 302(1)-302(C) in the data areas 31 and 32 store data (also called user data) from the host system 11. For example, any physical unit in the data areas 31 and 32 can store valid data and / or invalid data. In addition, the physical units 301 (A+1)-301 (B), 302 (C+1)-302 (D), and 302 (D+1)-302 (E) in the idle areas 33-35 do not store data (eg, valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with one of the idle areas 33-35. In addition, the physical units in the idle areas 33-35 can be erased to clear the data in the physical units. In one embodiment, the physical units in the idle areas 33-35 are also called idle physical units. In one embodiment, the idle areas 33-35 are also called free pools.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle areas 33-35 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31 or 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 310(1)-310(F) to map the physical units in the data areas 31 and 32 (i.e., the physical units 301(1)-301(A) and 302(1)-302(C)). For example, one logical unit may correspond to one logical block address (LBA) or other logical management unit. One logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the physical units 301(1)-301(B) belong to the first type of physical units, and the physical units 302(1)-302(E) belong to the second type of physical units. In one embodiment, the physical units 301(1)-301(A) in the data area 31 are also called the first type of data physical units, and the physical units 301(A+1)-301(B) in the idle area 33 are also called the first type of idle physical units. In one embodiment, the physical units 302(1)-302(C) in the data area 32 are also called the second type of data physical units, and the physical units 302(C+1)-301(D) in the idle area 34 are also called the second type of idle physical units. In one embodiment, the physical units 302(D+1)-301(E) in the idle area 35 are also called the third type of idle physical units.

[0038] In one embodiment, the total number of physical units 301(1)-301(B) may account for 5%-10% of the total number of physical units in the memory module 122. In one embodiment, the total number of physical units 302(1)-302(D) may account for 80%-90% of the total number of physical units in the memory module 122. In one embodiment, the total number of physical units 302(D+1)-302(E) may account for 5%-10% of the total number of physical units in the memory module 122. In one embodiment, the total number of each type of physical units in the memory module 122 may be adjusted according to practical needs, and the present invention is not limited thereto.

[0039] In one embodiment, the memory control circuit 23 may perform an extraction operation (also referred to as a first type of non-cross-region extraction operation) to extract at least one physical unit (also referred to as a first physical unit) from the first type of idle physical units (i.e., the physical units 301(A+1) to 301(B) in the idle region 33). Then, the memory control circuit 23 may use (e.g., operate) the first physical unit based on an operation mode (also referred to as a first operation mode). For example, the memory control circuit 23 may instruct the memory module 122 to program the first physical unit based on the first operation mode to store data (also referred to as first data) in the first physical unit. At the same time, the first physical unit for storing the first data may be associated with the data region 31. In response to the first physical unit being associated with the data region 31, the total number of physical units belonging to the data region 31 (i.e., the first type of data physical units) will increase, and the total number of physical units belonging to the idle region 33 (i.e., the first type of idle physical units) will decrease accordingly.

[0040] In one embodiment, the memory control circuit 23 may further perform a return operation (also referred to as a first type non-cross-region return operation) to return the first physical unit from the data region 31 to the idle region 33. For example, when the data stored in the first physical unit (i.e., the first data) does not include valid data, the memory control circuit 23 may re-associate the first physical unit to the idle region 33 through the first type non-cross-region return operation. In response to returning (i.e., re-association) the first physical unit to the idle region 33, the total number of physical units belonging to the data region 31 (i.e., the first type of data physical units) will decrease, and the total number of physical units belonging to the idle region 33 (i.e., the first type of idle physical units) will increase accordingly.

[0041] In one embodiment, the memory control circuit 23 may perform another extraction operation (also referred to as a second type of non-cross-region extraction operation) to extract at least one physical unit (also referred to as a second physical unit) from the second type of idle physical units (i.e., the physical units 302(C+1) to 302(D) in the idle region 34). Then, the memory control circuit 23 may use (e.g., operate) the second physical unit based on another operation mode (also referred to as a second operation mode). For example, the memory control circuit 23 may instruct the memory module 122 to program the second physical unit based on the second operation mode to store data (also referred to as second data) in the second physical unit. At the same time, the second physical unit for storing the second data may be associated with the data region 32. In response to the second physical unit being associated with the data region 32, the total number of physical units belonging to the data region 32 (i.e., the second type of data physical units) will increase, and the total number of physical units belonging to the idle region 34 (i.e., the second type of idle physical units) will decrease accordingly.

[0042] In one embodiment, the memory control circuit 23 may further perform another return operation (also referred to as a second type non-cross-region return operation) to return the second physical unit from the data region 32 to the idle region 34. For example, when the data stored in the second physical unit (i.e., the second data) does not include valid data, the memory control circuit 23 may re-associate the second physical unit to the idle region 34 through the second type non-cross-region return operation. In response to returning (i.e., re-association) the second physical unit to the idle region 34, the total number of physical units belonging to the data region 32 (i.e., the second type of data physical units) will decrease, and the total number of physical units belonging to the idle region 34 (i.e., the second type of idle physical units) will increase accordingly.

[0043] In one embodiment, after operating (e.g., programming) a physical unit based on a first operation mode, a storage unit in the physical unit may store a certain number (also referred to as a first number) of bit data. In addition, after operating (e.g., programming) a physical unit based on a second operation mode, a storage unit in the physical unit may store another number (also referred to as a second number) of bit data. The first number may be less than the second number. For example, the first number may be "1", and the second number may be "2", "3", "4", or other values ​​greater than "1".

[0044] In one embodiment, the first operation mode may include an SLC mode or a virtual SLC mode. In addition, the second operation mode may be one of an MLC mode, a TLC mode, or a QLC mode. It should be noted that the first operation mode and the second operation mode may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0045] In one embodiment, the third type of idle physical cells (i.e., the physical cells 302(D+1)-301(E) in the idle area 35) can be used to replace damaged physical cells (also called bad blocks) in the physical cells 301(1)-301(B) and 302(1)-302(D). For example, the memory control circuit 23 can detect whether there are damaged physical cells in the physical cells 301(1)-301(B) and 302(1)-302(D). If there are damaged physical cells in the physical cells 301(1)-301(B) and 302(1)-302(D), the memory control circuit 23 can select at least one physical cell from the idle area 35 to replace the damaged physical cell. In this way, the normal operation of the storage device 12 can be maintained.

[0046] In one embodiment, the memory control circuit 23 can detect a usage imbalance event for the first operation mode, wherein the usage imbalance event refers to that the first type of physical cells (eg, physical cells 301 ( 1 ) to 301 (B)) in the memory module 122 are overused.

[0047] In one embodiment, the durability of the first type of physical units (e.g., physical units 301(1)-301(B)) in the memory module 122 is higher than the durability of the second type of physical units (e.g., physical units 302(1)-302(D)) in the memory module 122. However, if the usage level of the first type of physical units (e.g., physical units 301(1)-301(B)) in the memory module 122 exceeds the usage level of the second type of physical units (e.g., physical units 302(1)-302(D)) in the memory module 122 by a large margin, the memory control circuit 23 may determine that the usage imbalance event occurs.

[0048] In one embodiment, the memory control circuit 23 may obtain usage level information (also referred to as first usage level information) of a plurality of physical units (also referred to as first target physical units) used in the memory module 122 based on the first operation mode. For example, the first target physical unit includes part or all of the first type of physical units. The first usage level information reflects the usage level of the first target physical unit. In addition, the memory control circuit 23 may obtain usage level information (also referred to as second usage level information) of a plurality of physical units (also referred to as second target physical units) used in the memory module 122 based on the second operation mode. For example, the second target physical unit includes part or all of the second type of physical units. The second usage level information reflects the usage level of the second target physical unit. Then, the memory control circuit 23 may determine whether the usage imbalance event occurs based on the first usage level information and the second usage level information.

[0049] In one embodiment, the first usage level information includes a usage level evaluation value (also referred to as a first usage level evaluation value). The first usage level evaluation value may reflect the average usage level of the first target entity unit. For example, the first usage level evaluation value may be positively correlated to the average usage level of the first target entity unit. That is, if the average usage level of the first target entity unit is higher, the first usage level evaluation value may be larger.

[0050] In one embodiment, the first usage evaluation value may be determined according to the read count, programming count, erase count and / or bit error rate of at least one physical unit in the first target physical unit. For example, if the average read count, average programming count, average erase count and / or average bit error rate of at least one physical unit in the first target physical unit is higher, the first usage evaluation value may be larger.

[0051] In one embodiment, the second usage level information includes another usage level evaluation value (also referred to as a second usage level evaluation value). The second usage level evaluation value may reflect the average usage level of the second target entity unit. For example, the second usage level evaluation value may be positively correlated to the average usage level of the second target entity unit. That is, if the average usage level of the second target entity unit is higher, the second usage level evaluation value may be larger.

[0052] In one embodiment, the second usage evaluation value may be determined based on the read count, programming count, erase count and / or bit error rate of at least one physical unit in the second target physical unit. For example, if the average read count, average programming count, average erase count and / or average bit error rate of at least one physical unit in the second target physical unit is higher, the second usage evaluation value may be larger.

[0053] In one embodiment, the memory control circuit 23 may obtain the difference between the first usage level evaluation value and the second usage level evaluation value. For example, assuming that the first usage level evaluation value and the second usage level evaluation value are values ​​V1 and V2, respectively, the memory control circuit 23 may subtract V2 from V1 or subtract V1 from V2 to obtain the difference. Then, the memory control circuit 23 may determine whether the usage imbalance event occurs based on the difference.

[0054] In one embodiment, the memory control circuit 23 may compare the difference with a preset value. If the difference is greater than the preset value, the memory control circuit 23 may determine that the usage imbalance event has occurred. However, if the difference is not greater than (e.g., less than or equal to) the preset value, the memory control circuit 23 may determine that the usage imbalance event has not occurred.

[0055] In one embodiment, according to the usage imbalance event, the memory control circuit 23 may determine whether a count information meets a preset condition. According to whether the count information meets the preset condition, the memory control circuit 23 may perform corresponding processing actions to improve or resolve the usage imbalance event.

[0056] In one embodiment, when the counting information meets the preset condition, the memory control circuit 23 may perform a cross-region extraction operation (also referred to as a first-type cross-region extraction operation) to extract at least one physical unit (also referred to as a third physical unit) from the third-type idle physical units (i.e., the physical units 302 (D+1) to 302 (E) in the idle region 35). Then, the memory control circuit 23 may use (e.g., operate) the third physical unit based on the first operation mode. For example, the memory control circuit 23 may instruct the memory module 122 to program the third physical unit based on the first operation mode to store data (also referred to as third data) in the third physical unit. At the same time, the third physical unit for storing the third data may be associated with the data region 31. In response to the third physical unit being associated with the data region 31, the total number of physical units belonging to the data region 31 (i.e., the first-type data physical unit) will increase, and the total number of physical units belonging to the idle region 35 (i.e., the third-type idle physical unit) will decrease accordingly.

[0057] In one embodiment, the counting information may include a counting value. The counting value may reflect the total number of third physical units that have not been restored to the third type of idle physical units. That is, the counting value may reflect the total number of physical units in the data area 31 that have not been returned to the idle area 35.

[0058] In one embodiment, the memory control circuit 23 may compare the count value with the critical value to obtain a comparison result. Then, the memory control circuit 23 may determine whether the count information meets the preset condition based on the comparison result. For example, if the comparison result reflects that the count value is not greater than (e.g., less than or equal to) the critical value, the memory control circuit 23 may determine that the count information meets the preset condition. However, if the comparison result reflects that the count value is greater than the critical value, the memory control circuit 23 may determine that the count information does not meet the preset condition.

[0059] In one embodiment, the memory control circuit 23 may determine the critical value according to the total number of the third type of idle physical units. For example, the memory control circuit 23 may set the critical value to be not greater than (i.e., less than or equal to) the total number of the third type of idle physical units. For example, assuming that the total number of physical units 302(D+1)-302(E) in the current or preset idle area 35 is N, the memory control circuit 23 may set the critical value to M, and M is not greater than N.

[0060] In one embodiment, after performing the first type of cross-region extraction operation, the memory control circuit 23 may update the counting information according to the first type of cross-region extraction operation. For example, the memory control circuit 23 may add "1" to the counting value to reflect the total number of physical units in the current data area 31 that have not been returned to the idle area 35.

[0061] In one embodiment, if the counting information does not meet the preset condition, the memory control circuit 23 may prohibit the execution of the first type of cross-region unit extraction operation. That is, after detecting the usage imbalance event, if the counting information does not meet the preset condition, the memory control circuit 23 may not execute the first type of cross-region unit extraction operation. In this way, the physical units in the current data area 31 that have not been returned to the idle area 35 can be controlled to a preset number (i.e., not exceeding the critical value at most), thereby preventing the physical units in the idle area 35 (i.e., the third type of idle physical units) from being overused.

[0062] In one embodiment, the physical units in the idle area 35 (i.e., the third type of idle physical units) are used as the first type of physical units through the first type of cross-area extraction operation. In the event of the usage imbalance event, the third type of idle physical units can help share the large amount of usage of the first type of physical units by the storage device 12. In this way, the usage levels of the first type of physical units and the second type of physical units can be brought closer, thereby improving or resolving the usage imbalance event. By improving or resolving the usage imbalance event, the performance and stability of the storage device 12 can be effectively improved, and the service life of the storage device 12 can also be effectively extended.

[0063] In one embodiment, after performing the first type of cross-region extraction operation, the memory control circuit 23 may perform a data consolidation operation on the data region 31 to return at least part of the physical units in the data region 31 that have not been returned to the idle region 35 to the idle region 35. For example, the data consolidation operation may include a garbage collection (GC) operation.

[0064] In one embodiment, the data consolidation operation may include a cross-region return operation (also referred to as a first-type cross-region return operation). This first-type cross-region return operation is used to restore the third physical unit previously used based on the first operation mode to a third-type idle physical unit. For example, by performing the data consolidation operation, the valid data originally stored in the third physical unit can be moved or copied to other physical units for storage, so that the valid data in the third physical unit is converted into invalid data. When all the data stored in the third physical unit is invalid data, the memory control circuit 23 can return (i.e., re-associate) the third physical unit to the idle area 35 through the first-type cross-region return operation. In this way, the total number of physical units (i.e., the third-type idle physical units) in the idle area 35 can be gradually restored (i.e., increased).

[0065] Figure 4 is a schematic diagram of the first type of cross-region extraction operation and the first type of cross-region return operation according to an embodiment of the present invention. Figure 4In the first type of cross-region extraction operation, the physical unit 302 (i) can be extracted from the idle area 35 and used (e.g., programmed) based on the first operation mode. Then, the physical unit 302 (i) can be associated with the data area 31 to share the large amount of use of the first type of physical units by the storage device 12.

[0066] After performing the first type of cross-region extraction operation, in the first type of cross-region return operation, the data consolidation operation can be used to move or clear the valid data currently stored in the physical unit 302 (i). Then, the physical unit 302 (i) can be reassociated from the data area 31 to the idle area 35 to ensure that there are still enough physical units (i.e., the third type of idle physical units) in the idle area 35 for subsequent use.

[0067] In one embodiment, according to the usage imbalance event, when the counting information does not meet the preset condition (for example, the third type of idle physical cells have been used up or are almost used up), the memory control circuit 23 may perform another cross-region extraction operation (also referred to as the second type of cross-region extraction operation) to extract at least one physical cell (also referred to as the fourth physical cell) from the second type of idle physical cells (i.e., the physical cells 302(C+1) to 302(D) in the idle area 34). Then, the memory control circuit 23 may use (e.g., operate) the fourth physical cell based on the first operation mode. For example, the memory control circuit 23 may instruct the memory module 122 to program the fourth physical cell based on the first operation mode to store data (also referred to as the fourth data) in the fourth physical cell. At the same time, the fourth physical cell for storing the fourth data may be associated with the data area 31. In response to the fourth physical cell being associated with the data area 31, the total number of physical cells belonging to the data area 31 (i.e., the first type of data physical cells) will increase, and the total number of physical cells belonging to the idle area 34 (i.e., the second type of idle physical cells) will decrease accordingly. Thus, even if the third type of idle physical units have been used up or almost used up, the second type of idle physical units can be used to help share the large amount of use of the first type of physical units by the storage device 12, thereby improving or resolving the usage imbalance event. By improving or resolving the usage imbalance event, the performance and stability of the storage device 12 can be effectively improved, and the service life of the storage device 12 can also be effectively extended.

[0068] In one embodiment, after performing the second type of cross-region extraction operation, the memory control circuit 23 may also perform the data consolidation operation on the data region 31 to return at least part of the physical units in the data region 31 that have not been returned to the idle region 34 to the idle region 34 .

[0069] In one embodiment, the data consolidation operation may include another cross-region return operation (also referred to as a second-type cross-region return operation). This second-type cross-region return operation is used to restore the fourth physical unit previously used based on the first operation mode to a second-type idle physical unit. For example, by performing the data consolidation operation, the valid data originally stored in the fourth physical unit can be moved or copied to other physical units for storage, so that the valid data in the fourth physical unit is converted into invalid data. When all the data stored in the fourth physical unit is invalid data, the memory control circuit 23 can return (i.e., re-associate) the fourth physical unit to the idle area 34 through the second-type cross-region return operation. In this way, the total number of physical units (i.e., the second-type idle physical units) in the idle area 34 can be gradually restored (i.e., increased).

[0070] Figure 5 Schematic diagram of the second type of cross-region extraction operation and the second type of cross-region return operation according to an embodiment of the present invention. Figure 5 In the second type of cross-region extraction operation, the physical unit 302 (j) can be extracted from the idle area 34 and used (e.g., programmed) based on the first operation mode. Then, the physical unit 302 (j) can be associated with the data area 31 to share the large amount of use of the first type of physical unit by the storage device 12.

[0071] After performing the second type of cross-region extraction operation, in the second type of cross-region return operation, the data consolidation operation can be used to move or clear the valid data currently stored in the physical unit 302 (j). Then, the physical unit 302 (j) can be reassociated from the data area 31 to the idle area 34 to ensure that there are still enough physical units (i.e., second type of idle physical units) in the idle area 34 for subsequent use.

[0072] In one embodiment, according to the second type of cross-region fetch operation executed, the memory control circuit 23 can dynamically adjust the trigger threshold of the data consolidation operation. The trigger threshold can be used to trigger the data consolidation operation.

[0073] In one embodiment, the trigger threshold includes a value (also referred to as a first trigger threshold). The first trigger threshold is used to trigger a data consolidation operation (also referred to as a first data consolidation operation) for the data area 31. For example, when the total number of physical units in the idle area 33 (i.e., the first type of idle physical units) is less than the first trigger threshold, the first data consolidation operation may be triggered. In response to the first data consolidation operation being triggered, the memory control circuit 23 may perform the first data consolidation operation on at least one physical unit in the data area 31. For example, the first data consolidation operation may include at least one of the first type of cross-area return operation and the second type of cross-area return operation. In addition, the first data consolidation operation may also include returning at least one physical unit in the idle area 31 to the idle area 33 to increase the total number of physical units belonging to the idle area 33 (i.e., the first type of idle physical units).

[0074] In one embodiment, the trigger threshold value includes another value (also referred to as a second trigger threshold value). The second trigger threshold value is used to trigger a data consolidation operation (also referred to as a second data consolidation operation) for the data area 32. For example, when the total number of physical cells in the idle area 34 (i.e., the second type of idle physical cells) is less than the second trigger threshold value, the second data consolidation operation may be triggered. In response to the second data consolidation operation being triggered, the memory control circuit 23 may perform the second data consolidation operation on at least one physical cell in the data area 32. For example, the second data consolidation operation may include returning at least one physical cell in the idle area 32 to the idle area 34 to increase the total number of physical cells belonging to the idle area 34 (i.e., the second type of idle physical cells).

[0075] In one embodiment, the memory control circuit 23 can detect whether the total number of physical cells (i.e., the second type of idle physical cells) in the idle area 34 is less than a preset number. In one embodiment, the memory control circuit 23 can decide to adjust at least one of the first trigger threshold and the second trigger threshold according to whether the total number of the second type of idle physical cells is less than the preset number.

[0076] In one embodiment, when the total number of the second type of idle physical units is less than the preset number, the memory control circuit 23 may synchronously adjust the first trigger threshold and the second trigger threshold according to the second type of cross-region extraction operation performed. For example, the memory control circuit 23 may adjust the first trigger threshold from a certain value (also referred to as the first value) to another value (also referred to as the second value) to trigger the first data consolidation operation in advance. The second value may be less than the first value. In addition, the memory control circuit 23 may adjust the second trigger threshold from a certain value (also referred to as the third value) to another value (also referred to as the fourth value) to trigger the second data consolidation operation in advance. The fourth value may be less than the third value.

[0077] In one embodiment, when the total number of the second type of idle physical units is not less than (e.g., greater than or equal to) the preset number, the memory control circuit 23 may (only) adjust the second trigger threshold value according to the second type of cross-region extraction operation performed. For example, the memory control circuit 23 may adjust the second trigger threshold value from the third value to the fourth value to trigger the second data consolidation operation in advance.

[0078] In one embodiment, when the second type of cross-area extraction operation is performed and the total number of the second type of idle physical units is less than the preset number, it means that all types of idle physical units may have been used in large quantities. In this case, by synchronously adjusting the first trigger threshold and the second trigger threshold, the data consolidation operation for the storage areas 31 and 32 can be forced to be triggered in advance, thereby accelerating the release (i.e., return) of various types of idle physical units. Therefore, although the access performance of the storage device 12 may be greatly reduced, the stability of the subsequent operation of the storage device 12 can be effectively ensured.

[0079] On the other hand, when the second type of cross-area extraction operation is performed and the total number of the second type of idle physical units is not less than the preset number, it means that although the third type of idle physical units have been used in large quantities, the number of the second type of idle physical units is still sufficient. In this case, by adjusting the second trigger threshold value separately, the data consolidation operation for the storage area 32 is forced to be triggered in advance. In this way, the stability of the subsequent operation of the storage device 12 can be effectively ensured without affecting the access performance of the storage device 12 to a small extent.

[0080] Figure 6 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 6 In step S601, a first physical unit is extracted from a first type of idle physical unit in a memory module, and the first physical unit is used based on a first operation mode. In step S602, a second physical unit is extracted from a second type of idle physical unit in a memory module, and the second physical unit is used based on a second operation mode. In step S603, a usage imbalance event for the first operation mode is detected. In step S604, it is determined whether the counting information meets a preset condition.

[0081] If the counting information meets the preset condition, in step S605, according to the usage imbalance event, when the counting information meets the preset condition, a first-type cross-region extraction operation is performed to extract a third physical unit from the third-type idle physical unit in the memory module, and the third physical unit is used based on the first operation mode. In step S606, the counting information is updated according to the first-type cross-region extraction operation. On the other hand, if the judgment result of step S604 is that the counting information does not meet the preset condition, then in step S607, the first-type cross-region unit extraction operation is prohibited.

[0082] Figure 7 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Figure 7 In step S701, a second type of cross-region extraction operation is performed to extract a fourth physical unit from the second type of idle physical units in the memory module, and the fourth physical unit is used based on the first operation mode. In step S702, a trigger threshold value of the data consolidation operation is adjusted according to the second type of cross-region extraction operation.

[0083] However, Figure 6 and Figure 7 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 6 and Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 6 and Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0084] In summary, the memory management method and storage device proposed in the embodiment of the present invention can perform cross-region extraction operations at an appropriate time to help share the large-scale use of the first type of physical units by the storage device through one or more types of idle physical units. In this way, the use levels of the first type of physical units and the second type of physical units can be brought closer, thereby improving or resolving the use imbalance event. By improving or resolving the use imbalance event, the performance and stability of the storage device can be effectively improved, and the service life of the storage device can also be effectively extended.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: Extracting a first entity unit from a first type of idle entity units among the plurality of entity units, and using the first entity unit based on a first operation mode; extracting a second entity unit from a second type of idle entity units among the plurality of entity units, and using the second entity unit based on a second operation mode; detecting a usage imbalance event for the first operating mode; According to the usage imbalance event, when the counting information meets a preset condition, performing a first type of cross-region extraction operation to extract a third physical unit from a third type of idle physical units among the plurality of physical units, and using the third physical unit based on the first operation mode; updating the counting information according to the first type of cross-region extraction operation; and If the counting information does not meet the preset condition, the first type of cross-region unit extraction operation is prohibited.

2. The memory management method according to claim 1, wherein the counting information comprises a counting value, and the memory management method further comprises: Comparing the count value with a threshold value to obtain a comparison result, wherein the count value reflects the total number of the third physical units that have not been restored to the third type of idle physical units; as well as According to the comparison result, it is determined whether the counting information meets the preset condition.

3. The memory management method according to claim 2, further comprising: The critical value is set according to the total number of the third type of idle entity units.

4. The memory management method according to claim 1, further comprising: According to the usage imbalance event, when the counting information does not meet the preset condition, performing a second type of cross-region extraction operation to extract a fourth physical unit from the second type of idle physical units, and using the fourth physical unit based on the first operation mode; as well as According to the second type of cross-region extraction operation, the triggering threshold of the data consolidation operation is adjusted.

5. The memory management method according to claim 4, wherein the step of adjusting the trigger threshold of the data consolidation operation comprises: Detecting whether the total number of the second-type idle entity units is less than a preset number; If the total number of the second-type idle physical units is not less than the preset number, adjusting a second trigger threshold value of a second data consolidation operation for the second-type idle physical units; as well as If the total number of the second-type idle physical units is less than the preset number, the second trigger threshold and the first trigger threshold of the first data consolidation operation for the first-type idle physical units are adjusted.

6. The memory management method according to claim 5, wherein the first data consolidation operation comprises at least one of a first type cross-region return operation and a second type cross-region return operation, The first type of cross-region return operation is used to restore the third physical unit used based on the first operation mode to the third type of idle physical unit, and The second-type cross-region return operation is used to restore the fourth physical unit used based on the first operation mode to the second-type idle physical unit.

7. The memory management method according to claim 5, wherein the step of adjusting the first trigger threshold comprises: The first trigger threshold is adjusted from a first value to a second value to trigger the first data consolidation operation in advance, wherein the second value is smaller than the first value, and The step of adjusting the second trigger threshold includes: The second trigger threshold is adjusted from a third value to a fourth value to trigger the second data merging operation in advance, wherein the fourth value is smaller than the third value.

8. The memory management method according to claim 1, wherein the step of detecting the usage imbalance event for the first operation mode comprises: Obtaining first usage level information of a plurality of first target entity units used based on the first operation mode; Acquire second usage level information of a plurality of second target entity units used based on the second operation mode; as well as It is determined whether the usage imbalance event occurs according to the first usage level information and the second usage level information.

9. The memory management method according to claim 8, wherein the first usage level information comprises a first usage level evaluation value, the second usage level information comprises a second usage level evaluation value, and the step of determining whether the usage imbalance event occurs according to the first usage level information and the second usage level information comprises: determining whether the usage imbalance event occurs according to a difference between the first usage level evaluation value and the second usage level evaluation value, The first usage level evaluation value reflects an average usage level of the plurality of first target entity units, and the second usage level evaluation value reflects an average usage level of the plurality of second target entity units.

10. The memory management method according to claim 9, wherein the step of determining whether the usage imbalance event occurs according to the difference between the first usage level evaluation value and the second usage level evaluation value comprises: comparing the difference with a preset value; as well as If the difference is greater than the preset value, it is determined that the usage imbalance event occurs.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: Extracting a first entity unit from a first type of idle entity units among the plurality of entity units, and using the first entity unit based on a first operation mode; extracting a second entity unit from a second type of idle entity units among the plurality of entity units, and using the second entity unit based on a second operation mode; detecting a usage imbalance event for the first operating mode; According to the usage imbalance event, when the counting information meets a preset condition, performing a first type of cross-region extraction operation to extract a third physical unit from a third type of idle physical units among the plurality of physical units, and using the third physical unit based on the first operation mode; updating the counting information according to the first type of cross-region extraction operation; as well as If the counting information does not meet the preset condition, the first type of cross-region unit extraction operation is prohibited.

12. The storage device according to claim 11, wherein the count information comprises a count value, and the memory controller is further configured to: comparing the count value with a threshold value to obtain a comparison result, wherein the count value reflects the total number of the third physical units that have not been restored to the third type of idle physical units; and According to the comparison result, it is determined whether the counting information meets the preset condition.

13. The storage device according to claim 12, wherein the memory controller is further configured to: The critical value is set according to the total number of the third type of idle entity units.

14. The storage device according to claim 11, wherein the memory controller is further configured to: According to the usage imbalance event, when the counting information does not meet the preset condition, performing a second type of cross-region extraction operation to extract a fourth physical unit from the second type of idle physical units, and using the fourth physical unit based on the first operation mode; and According to the second type of cross-region extraction operation, the triggering threshold of the data consolidation operation is adjusted.

15. The storage device according to claim 14, wherein the operation of the memory controller adjusting the trigger threshold of the data consolidation operation comprises: Detecting whether the total number of the second-type idle entity units is less than a preset number; If the total number of the second-type idle physical units is not less than the preset number, adjusting a second trigger threshold value of a second data consolidation operation for the second-type idle physical units; as well as If the total number of the second-type idle physical units is less than the preset number, the second trigger threshold and the first trigger threshold of the first data consolidation operation for the first-type idle physical units are adjusted.

16. The storage device according to claim 15, wherein the first data consolidation operation comprises at least one of a first type cross-region return operation and a second type cross-region return operation, The first type of cross-region return operation is used to restore the third physical unit used based on the first operation mode to the third type of idle physical unit, and The second-type cross-region return operation is used to restore the fourth physical unit used based on the first operation mode to the second-type idle physical unit.

17. The storage device according to claim 15, wherein the operation of the memory controller adjusting the first trigger threshold comprises: The first trigger threshold is adjusted from a first value to a second value to trigger the first data consolidation operation in advance, wherein the second value is smaller than the first value, and The operation of adjusting the second trigger threshold value includes: The second trigger threshold is adjusted from a third value to a fourth value to trigger the second data merging operation in advance, wherein the fourth value is smaller than the third value.

18. The memory device of claim 11, wherein the operation of the memory controller detecting the usage imbalance event for the first operation mode comprises: Obtaining first usage level information of a plurality of first target entity units used based on the first operation mode; Acquire second usage level information of a plurality of second target entity units used based on the second operation mode; as well as It is determined whether the usage imbalance event occurs according to the first usage level information and the second usage level information.

19. The storage device according to claim 18, wherein the first usage level information comprises a first usage level evaluation value, the second usage level information comprises a second usage level evaluation value, and the memory controller determines whether the usage imbalance event occurs according to the first usage level information and the second usage level information, comprising: determining whether the usage imbalance event occurs according to a difference between the first usage level evaluation value and the second usage level evaluation value, The first usage level evaluation value reflects an average usage level of the plurality of first target entity units, and the second usage level evaluation value reflects an average usage level of the plurality of second target entity units.

20. The storage device according to claim 19, wherein the operation of the memory controller determining whether the usage imbalance event occurs according to the difference between the first usage level assessment value and the second usage level assessment value comprises: comparing the difference with a preset value; as well as If the difference is greater than the preset value, it is determined that the usage imbalance event occurs.

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