FPGA simulation verification platform building method and device, medium and equipment

Abstract

The invention provides an FPGA simulation verification platform building method and device, a medium and equipment, and the method comprises the steps: generating a simulation excitation script frame according to a source code file of a test object; adding the target calling statement to a simulation incentive script framework to obtain a simulation incentive script; and when the user selects the simulation tool starting script, starting a corresponding target simulation tool, so that the target simulation tool scans the simulation excitation script and executes the statement in the simulation excitation script, thereby completing the establishment of the simulation verification platform. According to the technical scheme, a worker does not need to spend a large amount of time for coding, the simulation verification platform executes automatic generation of the script through the simulation tool, simulation environment establishment and configuration can be rapidly completed in different third-party simulation tools, and therefore the software verification efficiency of the programmable logic device is effectively improved. The FPGA simulation verification platform building method provided by the embodiment of the invention also has the characteristics of being repeatable and expandable.

Description

Technical Field

[0001] The present invention relates to the field of simulation verification, and in particular to a method, device, medium and equipment for building an FPGA simulation verification platform. Background Art

[0002] In recent years, the application areas of programmable logic device software have continued to expand. In addition to large-scale applications in traditional industrial automation control, communications, digital signal processing, image processing, etc., the scale of application in aerospace, shipbuilding, weapons and equipment and other fields has also grown explosively. In addition, emerging artificial intelligence, autonomous driving, dedicated chip prototype verification, and hardware acceleration have also seen significant applications and development. In addition to the continuous expansion of application areas, the design scale of programmable logic devices has also shown a trend of increasing year by year, and the annual growth rate continues to rise.

[0003] While the application fields and scale of programmable logic devices are steadily expanding, their verification cycle and difficulty are also increasing day by day. At the same time, the phenomenon that the verification work of programmable logic device software takes up more than half of its R&D cycle is still common. Therefore, how to effectively improve the efficiency of programmable logic device software verification has become a problem that technicians in this field need to solve urgently. Summary of the invention

[0004] The purpose of the present invention is to provide a method, device, medium and equipment for building an FPGA simulation verification platform to improve the above-mentioned problems.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a method for building an FPGA simulation verification platform, the method comprising: Generate a simulation excitation script framework according to the source code file of the test object, including: extracting the top-level file port information in the source code file; generating the simulation excitation script framework including target elements according to the top-level file port information, wherein the target elements include program framework keyword elements, input signal elements, output signal elements, instantiation elements, clock elements and reset elements; Adding a target call statement to the simulation stimulus script framework to obtain a simulation stimulus script, wherein the target call statement is used to call a target processing rule under a target protocol; When the user selects the simulation tool startup script, the corresponding target simulation tool is started, so that the target simulation tool scans the simulation stimulus script and executes the statements therein, thereby completing the construction of the simulation verification platform.

[0006] In a second aspect, an embodiment of the present invention provides a device for building an FPGA simulation verification platform, the device comprising: The first processing unit is used to generate a simulation stimulus script framework according to a source code file of a test object, including: extracting top-level file port information in the source code file; generating the simulation stimulus script framework including target elements according to the top-level file port information, wherein the target elements include a program framework keyword element, an input signal element, an output signal element, an instantiation element, a clock element, and a reset element; The first processing unit is further used to add a target call statement to the simulation stimulus script framework to obtain a simulation stimulus script, wherein the target call statement is used to call a target processing rule under a target protocol; The second processing unit is used to start the corresponding target simulation tool when the user selects the simulation tool startup script, so that the target simulation tool scans the simulation stimulus script and executes the statements therein, thereby completing the construction of the simulation verification platform.

[0007] In a third aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, and the computer program implements the above method when executed by a processor.

[0008] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store one or more programs; when the one or more programs are executed by the processor, the above method is implemented.

[0009] Compared with the prior art, the embodiment of the present invention provides a method, device, medium and equipment for building an FPGA simulation verification platform. According to the source code file of the test object, a simulation excitation script framework is generated, including: extracting the top-level file port information in the source code file; generating a simulation excitation script framework including target elements according to the top-level file port information, and the target elements include program framework keyword elements, input signal elements, output signal elements, instantiation elements, clock elements and reset elements; adding the target call statement to the simulation excitation script framework to obtain a simulation excitation script, wherein the target call statement is used to call the target processing rule under the target protocol; when the user selects the simulation tool to start the script, the corresponding target simulation tool is started, so that the target simulation tool scans the simulation excitation script and executes the statements therein, thereby completing the construction of the simulation verification platform. Without the need for staff to spend a lot of time on coding, the simulation verification platform automatically generates scripts through the simulation tool execution, which is conducive to quickly completing the construction and configuration of the simulation environment in different third-party simulation tools, thereby effectively improving the efficiency of programmable logic device software verification. The FPGA simulation verification platform construction method provided by the embodiment of the present invention also has the characteristics of repeatability and scalability.

[0010] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0013] Figure 2 One of the flow charts of the method for building an FPGA simulation verification platform provided by an embodiment of the present invention.

[0014] Figure 3 The second flowchart of the method for building an FPGA simulation verification platform provided by an embodiment of the present invention.

[0015] Figure 4 The third flowchart of the method for building an FPGA simulation verification platform provided by an embodiment of the present invention.

[0016] Figure 5 A schematic diagram of the units of the FPGA simulation verification platform construction device provided by an embodiment of the present invention.

[0017] In the figure: 10 - processor; 11 - memory; 12 - bus; 13 - communication interface; 501 - first processing unit; 502 - second processing unit. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0021] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0022] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0023] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0025] An embodiment of the present invention provides an electronic device, which may be a computer device or a server device. Figure 1, a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12, and the processor 10 is used to execute an executable module stored in the memory 11, such as a computer program.

[0026] The processor 10 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the FPGA simulation verification platform construction method can be completed by the hardware integrated logic circuit or software instructions in the processor 10. The above-mentioned processor 10 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0027] The memory 11 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0028] The bus 12 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Figure 1 Although only one bidirectional arrow is used in the figure, it does not mean that there is only one bus 12 or only one type of bus 12 .

[0029] The memory 11 is used to store programs, such as programs corresponding to the FPGA simulation verification platform building device. The FPGA simulation verification platform building device includes at least one software function module that can be stored in the memory 11 in the form of software or firmware or solidified in the operating system (OS) of the electronic device. After receiving the execution instruction, the processor 10 executes the program to implement the FPGA simulation verification platform building method.

[0030] Possibly, the electronic device provided by the embodiment of the present invention further includes a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0031] It should be understood that Figure 1 The structure shown is only a schematic diagram of a portion of the electronic device. The electronic device may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0032] The FPGA simulation verification platform construction method provided by the embodiment of the present invention can be applied to but not limited to Figure 1 For detailed procedures, please refer to the electronic equipment shown in Figure 2 ,The FPGA simulation verification platform building method includes: S11, S16 and S18, which are described in detail as follows.

[0033] S11, generating a simulation stimulus script framework according to the source code file of the test object, including: extracting the top-level file port information in the source code file; generating a simulation stimulus script framework including target elements according to the top-level file port information, the target elements including program framework keyword elements, input signal elements, output signal elements, instantiation elements, clock elements and reset elements.

[0034] Optionally, a source code file import window is displayed in the user interaction interface for the user to import the source code file corresponding to the test object. The user interaction interface supports *.v and *.vhd file import. The user can specify the imported source code file, and then read the specified source code file, and generate a simulation stimulus script framework according to the source code file of the test object. The default file format of the simulation stimulus script framework is .sv.

[0035] After generating the simulation excitation script framework, the script parameter input interface can also be displayed in the user interaction interface. The script parameter input interface is used to obtain the user-input script framework correction parameters; after obtaining the script framework correction parameters, the simulation excitation script framework is adjusted according to the obtained script framework correction parameters to achieve different script contents, such as generating simulation clock cycles of different frequencies.

[0036] It should be noted that the test object is a programmable logic device (FPGA for short).

[0037] S16, adding the target call statement to the simulation stimulus script framework to obtain the simulation stimulus script.

[0038] The target call statement is used to call the target processing rule under the target protocol.

[0039] Optionally, a target call statement is added to the work area of ​​the simulation stimulus script framework.

[0040] S18, when the user selects the simulation tool startup script, the corresponding target simulation tool is started, so that the target simulation tool scans the simulation stimulus script and executes the statements therein, thereby completing the construction of the simulation verification platform.

[0041] The simulation tool startup script is configured with any one or more of source code file reading instruction statements, simulation library startup instruction statements, environment library call instruction statements, simulation stimulus script reading instruction statements, and adding top-level port simulation waveform instruction statements.

[0042] It should be understood that after the target simulation tool is started, it will automatically execute the statements in the simulation tool startup script configuration. After the simulation stimulus script is read in, the target simulation tool will also execute the statements in the simulation stimulus script, thereby building test cases, completing the simulation verification environment construction, and establishing a simulation verification platform.

[0043] The FPGA simulation verification platform construction method provided by the embodiment of the present invention does not require the staff to spend a lot of time on coding. The simulation verification platform automatically generates scripts through simulation tools, which is conducive to quickly completing the simulation environment construction and configuration in different third-party simulation tools, thereby effectively improving the efficiency of programmable logic device software verification. The FPGA simulation verification platform construction method provided by the embodiment of the present invention also has the characteristics of repeatability and scalability.

[0044] exist Figure 2 On the basis of the content in S16, the embodiment of the present invention also provides an optional implementation method, please refer to the following. When the number of target call statements is greater than 1, S16, adding the target call statement to the simulation incentive script framework to obtain the simulation incentive script step includes: S161, S162 and S163, which are specifically described as follows.

[0045] S161, adding a target call statement to the task encapsulation text template.

[0046] During the construction of the FPGA simulation verification platform, the task encapsulation function can be called to generate a task encapsulation text template. Users can add necessary syntax keywords and handle declarations to the task encapsulation text template through instructions.

[0047] After obtaining the task encapsulation text template, a target call statement selected by the user may be added to (the working area of) the task encapsulation text template.

[0048] S162, adding the execution order of the target call statement in the task encapsulation text template according to the user instruction.

[0049] It should be noted that the user interaction interface also provides an execution order modification window to obtain user instructions, and then add the execution order of the target call statement in the task encapsulation text template according to the user instructions.

[0050] Optionally, when determining the execution order, the processing rules that consume simulation time and those that do not consume simulation time are alternately sorted, making scenario construction simpler. Verifiers do not need to switch back and forth between hardware description language and verification description language, and need to use a large amount of code and complex module structure to build simulation timing. Instead, they only need a few simple lines of method calls to achieve it.

[0051] In some optional implementations, the task encapsulation text template provides a basic syntax insertion tool, such as fixed delay statements, sensitive vector statements, loop and repeat statements, etc. Of course, the user can also actively modify the above statements.

[0052] S163, adding the calling statement of the task encapsulation text template to the simulation incentive script framework to obtain the simulation incentive script.

[0053] Optionally, the call statement of the task encapsulation text template is added to the work area of ​​the simulation stimulus script framework. When the simulation stimulus script is executed, the target call statement can be executed in the execution order agreed in the task encapsulation text template.

[0054] By encapsulating tasks, it is easier for staff to build test cases and test scenarios. A task contains one or more function methods or task methods, which is itself a set of operations that consume simulation time. Completely executing a packaged operation can simulate the normal working state of the FPGA in a scenario. When building test cases, the verification personnel need to call methods to generate bus read and write timing. In addition, they also need to select the appropriate data verification method, configure the bus working mode, set the length of the received and sent data, etc.

[0055] Based on the above, regarding how to determine the target call statement, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 In S16, before adding the target call statement to the simulation stimulus script framework to obtain the simulation stimulus script, the FPGA simulation verification platform building method also includes: S12, S13, S14 and S15, which are specifically described as follows.

[0056] S12, displaying a file list on the user interaction interface for the user to select.

[0057] The file list includes identification information of each library file in the method library, and each library file corresponds to a protocol, which is any one of a communication protocol, a bus protocol, and a transcoding protocol.

[0058] Optionally, the user interaction interface supports a keyword search function. When the user enters a corresponding keyword in the search window, the file list displays the identifier of the library file corresponding to the keyword, thereby improving the user's operating efficiency.

[0059] S13, displaying the processing rules under the target protocol for the user to select.

[0060] Among them, the target protocol is the protocol corresponding to the target library file, the target library file is the library file selected by the user in the file list, and the processing rules include any one or more of the protocol timing generation rules, protocol parameter configuration rules, protocol status monitoring rules, data verification rules and algorithm integration rules.

[0061] When the user selects a certain protocol as the target protocol, all processing rules under the target library file corresponding to the target protocol can be displayed in the user interaction interface in the form of a tree diagram for the user to select. When the user selects a processing responsibility as the target processing rule, the method description prompt information API parameter description prompt information corresponding to the target processing rule can be displayed in the brief prompt window for the user's reference.

[0062] S14, displaying a parameter pop-up window corresponding to the target processing rule, so that the user can input the API parameters corresponding to the target processing rule.

[0063] The target processing rule is the processing rule selected by the user, and the API parameter refers to the variable or data passed to the API when calling the application programming interface (API).

[0064] S15, after the user completes the API parameter input, a target calling statement corresponding to the target processing rule is generated.

[0065] The user interaction interface provides a text editing tool that supports opening files in *.v, *.vhd, *.sv, *.svh, *.tcl, *.do and other formats. In addition to automatically generating scripts, users can also manually modify the script content.

[0066] Regarding protocol timing generation rules, protocol parameter configuration rules, protocol status monitoring rules, data verification rules and algorithm integration rules, the embodiment of the present invention also provides an optional limitation, please refer to the following.

[0067] Protocol timing generation rules are used to build the working timing of the communication protocol and / or the working timing of the bus interface. The working timing of the communication protocol consumes simulation time resources to realize the scenario described in the use case, and is also the most important step in building simulation test cases.

[0068] The protocol parameter configuration rules are used to configure the working mode and parameters of the communication protocol and / or to configure the working mode and parameters of the bus interface; including but not limited to setting the protocol data length (parameters) and setting the protocol read and write mode, etc.

[0069] Protocol status monitoring rules are used to indicate immediate assertion monitoring rules and concurrent assertion monitoring rules. Common immediate assertions include level monitoring, edge monitoring, pulse width monitoring, etc. Concurrent assertions are used for complex function monitoring. Functional characteristics are described by one or more sets of properties, and functional timing is constructed by sequence. Warning, error, and fatal information are generated when violations occur. Status monitoring can effectively assist verification personnel in monitoring important signals. The combination of immediate assertions and concurrent assertions can be used for any complex function and timing tests.

[0070] Immediate assertions are often used for state monitoring with a single capability; concurrent assertions are often used for functional monitoring with complex capabilities and multi-dimensional complex timing, and are used to monitor a series of complex function sets.

[0071] The data verification rule is used to indicate the data verification method corresponding to the communication protocol.

[0072] The data verification method can be a commonly used data verification method, or a customized special protocol verification method. By calling such a method, the interface protocol function verification is implemented while the data validity is analyzed and verified.

[0073] Algorithm integration rules are used to indicate the operation formulas and data processing algorithms of the process encapsulated by functions.

[0074] Among them, the algorithm integration rules include function algorithm and Reference model (comparison reference model algorithm). Function algorithm does not consume simulation time, and directly obtains the operation result through input. During the simulation process, it is only effective at the time of calling; Reference model (comparison reference model algorithm): consumes simulation time, and the input will go through a series of steps to output the operation result in a specific time sequence. During the simulation process, it takes effect from the time of calling to the end of the simulation, and the process is continuously effective.

[0075] Please refer to Figure 4 In an optional implementation, the FPGA simulation verification platform building method further includes: S31, S32 and S33, which are specifically described as follows.

[0076] S31, obtaining the content of the protocol to be added.

[0077] The protocol to be added is any one of a communication protocol, a bus protocol and a transcoding protocol.

[0078] S32, determining a processing rule corresponding to the protocol to be added according to the content of the protocol to be added, so as to generate a library file corresponding to the protocol to be added.

[0079] Each library file contains application flow rules for a protocol implementation.

[0080] S31, adding the library file corresponding to the protocol to be added to the method library, and updating the file list.

[0081] The method library is object-oriented, written and packaged in the hardware verification language SystemVerilog, and is compatible with hardware description languages ​​such as Verilog and VHDL. Since the method library has a complete protocol application process and supports the generation of standard protocol timing, in addition, the FPGA simulation verification platform also supports the online configuration of protocol parameters and working modes through the API during construction. Such as switching data bit width, changing data verification method, configuring the total length of data transmission, channel switching, master-slave protocol switching, etc. By providing function methods and task methods, developers and verification personnel can build different test cases and simulate more test scenarios to improve the coverage of FPGA simulation verification.

[0082] Please continue to refer to Figure 3 In an optional implementation, the method for building an FPGA simulation verification platform also includes: S17.

[0083] S17, generating a simulation tool startup script according to the target simulation tool selected by the user and a preset startup script framework.

[0084] The simulation tool startup script is configured with any one or more of the following: source code file read instruction statement, simulation library startup instruction statement, environment library call instruction statement, simulation stimulus script read instruction statement, and top-level port simulation waveform add instruction statement. The simulation tool startup script supports *.tcl and *.do formats by default.

[0085] Please continue to refer to Figure 3 In an optional implementation, the method for building an FPGA simulation verification platform also includes: S19.

[0086] S19, recording the operation log during the construction of the FPGA simulation verification platform and saving the operation log.

[0087] In order to enable verification personnel to review historical operation steps and re-construct test cases and test scenarios, the test platform will record the content of this operation and print it to the operation log every time it performs an operation. The operation log is saved in the root directory of the simulation verification platform.

[0088] See also Figure 5 , Figure 5 An FPGA simulation verification platform construction device is provided in an embodiment of the present invention. Optionally, the FPGA simulation verification platform construction device is applied to the electronic device described above.

[0089] The FPGA simulation verification platform building device includes: a first processing unit 501 and a second processing unit 502.

[0090] The first processing unit 501 is used to generate a simulation stimulus script framework according to the source code file of the test object, including: extracting the top-level file port information in the source code file; generating a simulation stimulus script framework including target elements according to the top-level file port information, wherein the target elements include a program framework keyword element, an input signal element, an output signal element, an instantiation element, a clock element, and a reset element; The first processing unit 501 is also used to add a target call statement to the simulation incentive script framework to obtain a simulation incentive script, wherein the target call statement is used to call a target processing rule under a target protocol; The second processing unit 502 is used to start the corresponding target simulation tool when the user selects the simulation tool startup script, so that the target simulation tool scans the simulation stimulus script and executes the statements therein, thereby completing the construction of the simulation verification platform.

[0091] Optionally, the second processing unit 502 may execute the above-mentioned S18, and the first processing unit 501 may execute the above-mentioned other steps.

[0092] It should be noted that the FPGA simulation verification platform construction device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the above embodiment.

[0093] The embodiment of the present invention further provides a storage medium, which stores computer instructions and programs, and when the computer instructions and programs are read and run, the FPGA simulation verification platform construction method of the above embodiment is executed. The storage medium may include a memory, a flash memory, a register, or a combination thereof.

[0094] The following provides an electronic device, which may be a computer device or a server device. Figure 1As shown, the above-mentioned FPGA simulation verification platform construction method can be implemented; specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 can be a CPU. The memory 11 is used to store one or more programs. When the one or more programs are executed by the processor 10, the FPGA simulation verification platform construction method of the above-mentioned embodiment is executed.

[0095] In summary, the embodiment of the present invention provides a method, device, medium and equipment for building an FPGA simulation verification platform. According to the source code file of the test object, a simulation excitation script framework is generated, including: extracting the top-level file port information in the source code file; generating a simulation excitation script framework including target elements according to the top-level file port information, and the target elements include program framework keyword elements, input signal elements, output signal elements, instantiation elements, clock elements and reset elements; adding the target call statement to the simulation excitation script framework to obtain a simulation excitation script, wherein the target call statement is used to call the target processing rule under the target protocol; when the user selects the simulation tool to start the script, the corresponding target simulation tool is started, so that the target simulation tool scans the simulation excitation script and executes the statements therein, thereby completing the construction of the simulation verification platform. Without the need for staff to spend a lot of time on coding, the simulation verification platform automatically generates scripts through the simulation tool execution, which is conducive to quickly completing the construction and configuration of the simulation environment in different third-party simulation tools, thereby effectively improving the efficiency of programmable logic device software verification. The FPGA simulation verification platform construction method provided by the embodiment of the present invention also has the characteristics of repeatability and scalability.

[0096] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0097] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for building an FPGA simulation verification platform, characterized in that: The method comprises: Generate a simulation excitation script framework according to the source code file of the test object, including: extracting the top-level file port information in the source code file; generating the simulation excitation script framework including target elements according to the top-level file port information, wherein the target elements include program framework keyword elements, input signal elements, output signal elements, instantiation elements, clock elements and reset elements; Adding a target call statement to the simulation stimulus script framework to obtain a simulation stimulus script, wherein the target call statement is used to call a target processing rule under a target protocol; When the user selects the simulation tool startup script, the corresponding target simulation tool is started, so that the target simulation tool scans the simulation stimulus script and executes the statements therein, thereby completing the construction of the simulation verification platform.

2. The method for building an FPGA simulation verification platform according to claim 1, wherein: When the number of target call statements is greater than 1, the step of adding the target call statement to the simulation incentive script framework to obtain the simulation incentive script includes: Adding the target call statement to the task encapsulation text template; Adding the execution order of the target call statement in the task encapsulation text template according to the user instruction; Add the calling statement of the task encapsulation text template to the simulation stimulus script framework to obtain the simulation stimulus script.

3. The FPGA simulation verification platform construction method according to claim 1, characterized in that: Before adding the target call statement to the simulation stimulus script framework to obtain the simulation stimulus script, the method further includes: Displaying a file list on a user interaction interface for user selection, wherein the file list includes identification information of each library file in the method library, each library file corresponds to a protocol, and the protocol is any one of a communication protocol, a bus protocol, and a transcoding protocol; Display the processing rules under the target protocol for the user to select, wherein the target protocol is the protocol corresponding to the target library file, the target library file is the library file selected by the user in the file list, and the processing rules include any one or more of the protocol timing generation rules, protocol parameter configuration rules, protocol status monitoring rules, data verification rules and algorithm integration rules; Display a parameter pop-up window corresponding to the target processing rule, so that the user can input the API parameters corresponding to the target processing rule, wherein the target processing rule is the processing rule selected by the user; After the user completes the API parameter input, a target calling statement corresponding to the target processing rule is generated.

4. The method for building an FPGA simulation verification platform as claimed in claim 3, characterized in that: The protocol timing generation rule is used to construct the working timing of the communication protocol and / or the working timing of the bus interface; The protocol parameter configuration rules are used to configure the working mode and parameters of the communication protocol, and / or to configure the working mode and parameters of the bus interface; The protocol status monitoring rule is used to indicate the immediate assertion monitoring rule and the concurrent assertion monitoring rule; The data verification rule is used to indicate the data verification method corresponding to the communication protocol; Algorithm integration rules are used to indicate the operation formulas and data processing algorithms of the process encapsulated by functions.

5. The method for building an FPGA simulation verification platform as claimed in claim 3, characterized in that: The method further comprises: Get the content of the protocol to be added; Determine the processing rule corresponding to the protocol to be added according to the content of the protocol to be added, so as to generate a library file corresponding to the protocol to be added; Add the library file corresponding to the protocol to be added to the method library, and update the file list.

6. The method for building an FPGA simulation verification platform according to claim 1, wherein: The method further comprises: A simulation tool startup script is generated based on the target simulation tool selected by the user and the preset startup script framework, wherein the simulation tool startup script is configured with any one or more of source code file read instruction statements, simulation library startup instruction statements, environment library call instruction statements, simulation stimulus script read instruction statements, and top-level port simulation waveform add instruction statements.

7. The method for building an FPGA simulation verification platform according to claim 1, wherein: The method further comprises: Record the operation log during the construction of the FPGA simulation verification platform and save the operation log.

8. A device for building an FPGA simulation verification platform, characterized in that: The device comprises: The first processing unit is used to generate a simulation stimulus script framework according to a source code file of a test object, including: extracting top-level file port information in the source code file; generating the simulation stimulus script framework including target elements according to the top-level file port information, wherein the target elements include a program framework keyword element, an input signal element, an output signal element, an instantiation element, a clock element, and a reset element; The first processing unit is further used to add a target call statement to the simulation stimulus script framework to obtain a simulation stimulus script, wherein the target call statement is used to call a target processing rule under a target protocol; The second processing unit is used to start the corresponding target simulation tool when the user selects the simulation tool startup script, so that the target simulation tool scans the simulation stimulus script and executes the statements therein, thereby completing the construction of the simulation verification platform.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: A processor and a memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

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