Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel is provided with a control unit, so that grid electrodes of control transistors electrically connected with scanning lines of odd-numbered groups are connected with first control signal lines, and grid electrodes of control transistors electrically connected with scanning lines of even-numbered groups are connected with second control signal lines; when a display panel adopting a non-strip pixel framework and an asymmetric pull-down gate drive circuit framework needs to be lightened, the first control signal line and the second control signal line can be used for respectively controlling the scanning lines of the odd-numbered group and the even-numbered group to input effective levels; according to the display panel, the sub-pixel units in the odd-numbered lines and the even-numbered lines are correspondingly controlled to be sequentially lightened or simultaneously lightened in one frame, and the input signals of the data lines are controlled, so that the display of a pure-color picture can be realized, and the pure-color picture of the display panel is detected.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the process of manufacturing display devices, in order to prevent defective display panels from being taped out to the module stage, affecting the module yield and causing increased costs, the display panel will be tested after the display panel is manufactured. Specifically, a detection lighting fixture will be used to light up the display panel, but for an asymmetric pull-down gate drive circuit architecture and a non-strip pixel architecture (a strip pixel architecture refers to a column of sub-pixels with the same luminous color connected to the same data line, and a data line is only connected to a column of sub-pixels), the driving capability of the lighting fixture is insufficient and cannot provide a driving signal for a pure color image, resulting in an inability to detect the pure color image, which in turn causes a defective display panel to be taped out to the module stage, resulting in a low module yield.

[0003] Therefore, the existing detection process of display devices has the technical problem that it is impossible to perform pure color image detection on a display panel that adopts an asymmetric pull-down gate drive circuit architecture and a non-strip pixel architecture. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem that the detection process of the existing display device cannot detect pure color images for display panels using an asymmetric pull-down gate drive circuit architecture and a non-strip pixel architecture.

[0005] An embodiment of the present application provides a display panel, the display panel comprising a display area and a non-display area arranged on at least one side of the display area, the non-display area comprising a gate driving circuit, the display area comprising a plurality of groups of scan lines, a plurality of data lines and a plurality of pixel units, each group of the scan lines comprising at least one scan line, each group of the scan lines outputs the same signal, and each pixel unit comprises at least three sub-pixel units of different luminous colors; wherein the gate driving circuit comprises:

[0006] A plurality of cascaded gate driving units, each gate driving unit comprising a signal output terminal, wherein one of the signal output terminals is connected to a group of the scanning lines;

[0007] A plurality of control units, connected to the gate driving units correspondingly, the control units comprising a control transistor, a first control signal line, a second control signal line and a detection signal line, the first electrode of the control transistor being connected to the detection signal line, the second electrode of the control transistor being connected to the signal output terminal, the gate of the control transistor electrically connected to the scan lines of the odd array being connected to the first control signal line, and the gate of the control transistor electrically connected to the scan lines of the even array being connected to the second control signal line;

[0008] Wherein, when the display panel is configured as a detection stage, in a first time period, the first control signal line is configured to output a valid level, and the second control signal line is configured to output an invalid level; in a second time period, the first control signal line is configured to output an invalid level, and the second control signal line is configured to output a valid level; the detection stage includes the first time period and the second time period.

[0009] At the same time, an embodiment of the present application provides a display panel, which includes a display area and a non-display area arranged on at least one side of the display area, the non-display area includes a gate driving circuit, the display area includes multiple groups of scan lines, multiple data lines and multiple pixel units, each group of the scan lines includes at least one scan line, each group of the scan lines outputs the same signal, and each pixel unit includes at least three sub-pixel units with different luminous colors; wherein the gate driving circuit includes:

[0010] A plurality of cascaded gate driving units, each gate driving unit comprising a signal output terminal, wherein one of the signal output terminals is connected to a group of the scanning lines;

[0011] A plurality of control units, connected to the gate driving units correspondingly, the control units comprising a control transistor, a first control signal line, a second control signal line and a detection signal line, the first electrode of the control transistor being connected to the detection signal line, the second electrode of the control transistor being connected to the signal output terminal, the gate of the control transistor electrically connected to the scan lines of the odd array being connected to the first control signal line, and the gate of the control transistor electrically connected to the scan lines of the even array being connected to the second control signal line;

[0012] Among them, one of the data lines is connected to multiple sub-pixel units of the same luminous color, and when the display panel is configured as a detection stage, the first control signal line is configured to output a valid level, and the second control signal line is configured to output a valid level.

[0013] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0014] Beneficial effects: The present application provides a display panel and a display device; the display panel is provided with a control unit so that the gate of the control transistor electrically connected to the scan lines of the odd group is connected to the first control signal line, and the gate of the control transistor electrically connected to the scan lines of the even group is connected to the second control signal line. Then, when it is necessary to light up the display panel adopting a non-strip pixel architecture and an asymmetric pull-down gate drive circuit architecture, the first control signal line and the second control signal line can be used to control the input effective level of the scan lines of the odd group and the even group respectively, and the sub-pixel units of the odd rows and the even rows are controlled to light up in sequence or at the same time within one frame accordingly, and by controlling the input signal of the data line, the display of a pure color picture can be realized, and the pure color picture of the display panel can be detected. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0016] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0017] Figure 2 A first pixel architecture diagram of a display panel provided in an embodiment of the present application.

[0018] Figure 3 A first schematic diagram of a driving architecture of a display panel provided in an embodiment of the present application.

[0019] Figure 4 A circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0020] Figure 5 for Figure 2 : Timing diagram of the detection phase of the display panel.

[0021] Figure 6 A second schematic diagram of a driving architecture of a display panel provided in an embodiment of the present application.

[0022] Figure 7 A second pixel architecture diagram of a display panel provided in an embodiment of the present application.

[0023] Figure 8 for Figure 7 A first timing diagram of the detection phase of the display panel.

[0024] Fig. 9 for Figure 7 A second timing diagram of the detection phase of the display panel in FIG.

[0025] Fig.10A third pixel architecture diagram of the display panel provided in an embodiment of the present application.

[0026] Fig.11 for Fig.10 : Timing diagram of the detection phase of the display panel.

[0027] Fig.12 A fourth pixel architecture diagram of the display panel provided in an embodiment of the present application.

[0028] Fig.13 for Fig.12 A first timing diagram of the detection phase of the display panel.

[0029] Fig.14 for Fig.12 A second timing diagram of the detection phase of the display panel in FIG. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0031] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0032] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0034] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0035] In order to illustrate the principle of the technical problem existing in the embodiments of the present application, some comparative display devices are provided for illustration. Specifically, the pixel architecture of the display device includes a strip pixel architecture and a flip (inverted) pixel architecture. For a display panel adopting a 1G1D (the same column of sub-pixel units are connected to the same data line, and the same row of sub-pixel units are connected to the same scan line) strip pixel architecture, when performing detection, a DC signal of the 255th grayscale can be input to the data lines connected to the red sub-pixel, the green sub-pixel, and the blue sub-pixel in turn, and a DC signal of the 0th grayscale can be input to the data lines connected to the corresponding other two sub-pixels, thereby realizing the detection of a pure color picture. For display panels using a non-strip pixel architecture, such as a display panel using a 1G1D flip pixel architecture or a DLS (dataline share) pixel architecture, since each column of sub-pixels is driven by two adjacent data lines, or two columns of pixels are driven by one data line, when detecting a pure color image, taking a display panel using a 1G1D flip pixel architecture as an example, the first row of red sub-pixels is driven by the first data line, and the second row of red sub-pixels is driven by the second data line. Therefore, multiple data lines in each row need to be alternately switched.

[0036] For the display panel using a symmetrical pull-down gate drive circuit architecture, there are two cases for the above problem. One is a gate drive circuit using a bilateral drive architecture. The gate drive circuit can be divided into several symmetrical drive groups. Pure color picture detection can also be achieved with data signals. Taking the display panel using a 1G1D flip pixel architecture as an example, for example, the gate drive circuit is divided into four groups, and four start signal lines are used to drive them respectively. The odd rows are controlled by two of the start signal lines, and the even rows are controlled by the other two start signal lines. A frame signal is divided into two writes. During the first write, two of the start signal lines input valid levels, and the other two start signal lines input invalid levels to control the sub-pixels of the odd rows to turn on. During the second write, two of the start signal lines input valid levels, and the other two start signal lines input invalid levels to control the sub-pixels of the even rows to turn on. Pure color picture display can be achieved with the sub-pixels of the corresponding luminous color input valid levels. The other is a gate drive circuit that adopts a cross-drive architecture. In this architecture, the scan lines of odd rows are driven by the gate drive circuit on the left, and the scan lines of even rows are driven by the gate drive circuit on the right. Therefore, a frame signal can also be divided into two writes and combined with the input of data signals to achieve the detection of pure color images.

[0037] However, the load of the display panel using the symmetrical pull-down gate drive circuit architecture needs to be less than 50%. With the development of high refresh rate and high resolution products, the load requirements are higher, and it is necessary to introduce an asymmetrical pull-down gate drive architecture. The asymmetrical pull-down gate drive architecture refers to the output signal of the gate drive circuit of the odd rows as the input signal of the gate drive circuit of the even rows. Since the decibel output of the gate drive circuit of the odd rows and the even rows cannot be controlled separately, it is impossible to detect pure color images by controlling the writing order of the gate drive circuit and the data line. Therefore, the detection process of the existing display device has the technical problem that it is impossible to detect pure color images for display panels using an asymmetrical pull-down gate drive circuit architecture and a non-strip pixel architecture.

[0038] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0039] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 2 A first pixel architecture diagram of a display panel provided in an embodiment of the present application. Figure 3 A first schematic diagram of a driving architecture of a display panel provided in an embodiment of the present application. Figure 4 A circuit diagram of a gate drive circuit provided in an embodiment of the present application. Figure 5 for Figure 2 A timing diagram of the detection phase of the display panel in FIG. Figure 5 (a) in Figure 2 A timing diagram when the display panel in is configured as a first detection stage; Figure 5 (b) in Figure 2 A timing diagram when the display panel in is configured as the second detection stage; Figure 5 (c) in Figure 2 0 is a timing diagram when the display panel is configured as the third detection stage. Figure 6 A second schematic diagram of the display panel driving architecture provided in an embodiment of the present application. Figure 7 A second pixel architecture diagram of a display panel provided in an embodiment of the present application. Figure 8 for Figure 7 A first timing diagram of a detection phase of a display panel in FIG. Figure 8 (a) is for Figure 7 A first timing diagram when a first sub-pixel unit of a display panel performs pure color detection; Figure 8 (b) is for Figure 7 A first timing diagram when a second sub-pixel unit of a display panel performs pure color detection; Figure 8 (c) is for Figure 7 A first timing diagram when the third sub-pixel unit of the display panel performs pure color detection. Fig. 9 for Figure 7 A second timing diagram of the detection phase of the display panel in FIG. Fig. 9 (a) is for Figure 7 A second timing diagram when the first sub-pixel unit of the display panel performs pure color detection; Fig. 9 (b) is for Figure 7 A second timing diagram when the second sub-pixel unit of the display panel performs pure color detection; Fig. 9 (c) is for Figure 7 A second timing diagram when the third sub-pixel unit of the display panel performs pure color detection. Fig.10 A third pixel architecture diagram of the display panel provided in an embodiment of the present application. Fig.11 for Fig.10 A timing diagram of the detection phase of the display panel in FIG. Fig.11 (a) in Fig.10 A timing diagram when the display panel in is configured as a first detection stage; Fig.11 (b) in Fig.10 A timing diagram when the display panel in is configured as the second detection stage; Fig.11 (c) in Fig.10 0 is a timing diagram when the display panel is configured as the third detection stage. Fig.12 A fourth pixel architecture diagram of the display panel provided in an embodiment of the present application. Fig.13 for Fig.12 A first timing diagram of a detection phase of a display panel in FIG. Fig.13 (a) in Fig.12 A first timing diagram when the display panel is configured as a first detection stage;

[0040] Fig.13 (b) in Fig.12 A first timing diagram when the display panel is configured as a second detection stage;

[0041] Fig.13 (c) in Fig.12 The display panel in is configured as the first timing diagram of the third detection stage. Fig.14 for Fig.12 A second timing diagram of the detection phase of the display panel in FIG. Fig.14 (a) in Fig.12 A second timing diagram when the display panel is configured as a first detection stage; Fig.14 (b) in Fig.12 A second timing diagram when the display panel is configured as a second detection stage; Fig.14 (c) in Fig.12 The second timing diagram when the display panel is configured as the third detection stage.

[0042] like Figures 1 to 4 As shown, an embodiment of the present application provides a display panel, the display panel 1 includes a display area AA and a non-display area NA arranged on at least one side of the display area AA, the non-display area NA includes a gate driving circuit 12, the display area 11 includes a plurality of scan lines 111, a plurality of data lines 112 and a plurality of pixel units 113, each group of the scan lines 111 includes at least one scan line 111, each group of the scan lines 111 outputs the same signal, each of the pixel units 113 includes at least three sub-pixel units with different luminous colors (for example, a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c), wherein the gate driving circuit 12 includes:

[0043] A plurality of cascaded gate driving units 12a, each gate driving unit 12a comprising a signal output terminal G(m), wherein one of the signal output terminals G(m) is connected to a group of the scanning lines 111;

[0044] Multiple control units 12b are connected to the gate driving units 12a accordingly, and the control unit 12b includes a control transistor T0, a first control signal line SW1, a second control signal line SW2 and a detection signal line GCH. The first electrode of the control transistor T0 is connected to the detection signal line GCH, the second electrode of the control transistor T0 is connected to the signal output terminal G(m), the gate of the control transistor T0 electrically connected to the scan lines of the odd group (for example, the first group of scan lines G1) is connected to the first control signal line SW1, and the gate of the control transistor T0 electrically connected to the scan lines of the even group (for example, the second group of scan lines G2) is connected to the second control signal line SW2.

[0045] An embodiment of the present application provides a display panel, which sets a control transistor, a first control signal line, a second control signal line and a detection signal line in a gate driving circuit, so that the gate of the control transistor electrically connected to the scanning lines of the odd group is connected to the first control signal line, and the gate of the control transistor electrically connected to the scanning lines of the even group is connected to the second control signal line. By controlling the timing of each signal line, the sub-pixel units of the odd rows and the even rows can be turned on in time, or the sub-pixel units of the odd rows and the even rows can be turned on at the same time, and the detection of a pure color picture can be achieved by controlling the timing of each signal line.

[0046] In some embodiments, when the display panel 1 is configured as a detection phase, in a first time period t1, the first control signal line SW1 is configured to output a valid level, and the second control signal line SW2 is configured to output an invalid level; in a second time period t2, the first control signal line SW1 is configured to output an invalid level, and the second control signal line SW2 is configured to output a valid level; the detection phase includes the first time period t1 and the second time period t2.

[0047] An embodiment of the present application provides a display panel, which, by setting a control unit, connects the gate of a control transistor electrically connected to an odd-numbered array of scan lines to a first control signal line, and connects the gate of a control transistor electrically connected to an even-numbered array of scan lines to a second control signal line. When it is necessary to light up a display panel that adopts a non-strip pixel architecture and an asymmetric pull-down gate drive circuit architecture, the first control signal line and the second control signal line can be used to control the input effective levels of the odd-numbered array and the even-numbered array of scan lines, respectively, and correspondingly control the sub-pixel units of the odd-numbered rows and the even-numbered rows to light up in sequence or at the same time within a frame, and by controlling the input signal of the data line, the display of a pure color picture can be realized, and the pure color picture of the display panel can be detected.

[0048] In some embodiments, Figure 7 , Fig.12 As shown, one data line 112 is connected to a plurality of sub-pixel units of the same luminous color, such as Figure 8 , Fig.14 As shown, when the display panel 1 is configured in the detection stage, the first control signal line SW1 is configured to output a valid level, and the second control signal line SW2 is configured to output a valid level.

[0049] An embodiment of the present application provides a display panel, which, by setting a control unit, connects the gate of a control transistor electrically connected to an odd-numbered array of scan lines to a first control signal line, and connects the gate of a control transistor electrically connected to an even-numbered array of scan lines to a second control signal line, and the data lines in the display panel are connected to sub-pixel units of the same luminous color. When the display panel needs to be lit, all scan lines can be controlled to input effective levels through the first control signal line and the second control signal line, and the sub-pixel units of the odd-numbered rows and the even-numbered rows can be controlled to light up simultaneously within one frame accordingly, and by controlling the input signal of the data line, the display of a pure color picture can be realized, and the pure color picture of the display panel can be detected.

[0050] Specifically, it can be understood that the embodiments of the present application do not limit the pixel architecture in the display panel to a non-strip pixel architecture. For a display panel adopting a strip pixel architecture, the design of the gate drive circuit of the embodiments of the present application can also be adopted; at the same time, the embodiments of the present application do not limit the architecture of the gate drive circuit in the display panel to an asymmetric pull-down gate drive circuit architecture. The architecture of the gate drive circuit in the display panel can also be a symmetric pull-down gate drive circuit architecture. Therefore, the design of the display panel in the embodiments of the present application is suitable for different pixel architectures and different gate drive circuits, such as a display panel adopting a strip pixel architecture and a symmetric pull-down gate drive circuit architecture, or a display panel adopting a strip pixel architecture and an asymmetric pull-down gate drive circuit architecture, or a display panel adopting a non-strip pixel architecture and a symmetric pull-down gate drive circuit architecture, or a display panel adopting a non-strip pixel architecture and an asymmetric pull-down gate drive circuit architecture.

[0051] Specifically, it can be understood that the pixel unit 113 includes at least a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c. When the display panel is subjected to pure color image detection, at least three detections are required. Therefore, the duration of the detection phase includes at least the duration of three frames. One frame t0 includes a first time period t1 and a second time period t2. One pure color image can be detected within one frame. Therefore, in Figure 5 In other figures, the timing of the corresponding signal lines in each frame is used for explanation. In fact, each frame can be a continuous plurality of frames. For example, the timing of the display panel in the first frame is as follows: Figure 5 As shown in (a) in FIG. 1 , the timing of the display panel in the second frame is as follows: Figure 5 As shown in (b) in FIG. 1 , the timing of the display panel in the third frame is as follows: Figure 5 Similarly, other figures and corresponding timing sequences can refer to the above description.

[0052] Specifically, the effective level refers to a signal that can normally turn on a transistor or light up a pixel unit, and the invalid level refers to a signal that turns off a transistor or turns off a pixel unit. For example, when a high-potential signal is input to the first control signal line, the control transistor can be turned on, and when a low-potential signal is input to the first control signal line, the control transistor is turned off, then the high-potential signal is an effective level, and the low-potential signal is an invalid level; but when a high-potential signal is input to the first control signal line, the control transistor is turned off, and when a low-potential signal is input to the first control signal line, the control transistor is turned on, then the high-potential signal is an invalid level, and the low-potential signal is an effective level; similarly, for the description of the effective level and invalid level of the signal output on other signal lines, please refer to the above description. Specifically, the following embodiments are described by taking the high-potential signal as an effective level and the low-potential signal as an invalid level as an example.

[0053] Specifically, it can be understood that since the gate driving circuit in the embodiment of the present application is suitable for different pixel architectures, when a partial pixel architecture is adopted (for example, a data line in the pixel architecture is connected to multiple sub-pixel units of the same luminous color), whether the scan lines are divided into odd rows and even rows and turned on respectively, or the scan lines of odd rows and even rows are turned on at the same time, the detection of pure color images can be achieved by controlling the write signal of the data line. Therefore, different timings may exist for some pixel architectures, but it can be understood that each pixel architecture in the embodiment of the present application can adopt the same gate driving circuit, for example Figure 4 Specifically, it can be understood that the display panel includes different pixel architectures. In some pixel architectures, a group of scan lines includes one scan line, and each scan line inputs different signals, such as Figure 2 , Figure 7 , Fig.10 In the pixel architecture, each group of scan lines includes only one scan line; in some pixel architectures, a group of scan lines includes two or more scan lines, and each group of scan lines inputs the same signal, for example Fig.12 In the embodiment, the first group of scan lines G1 includes a first scan line G11 and a second scan line G12, the second group of scan lines G2 includes a third scan line G21 and a fourth scan line G22, two scan lines in the same group of scan lines are connected to the same signal output terminal of the gate drive circuit, and the same signal is input to two adjacent scan lines.

[0054] In some embodiments, Figure 1 , Figure 3As shown, the display panel 1 includes non-display areas NA arranged on both sides of the display area AA, which are respectively a first non-display area NA1 and a second non-display area NA2, the gate driving circuit 12 includes a first gate driving circuit 121 respectively arranged in the first non-display area NA1 and a second gate driving circuit 122 arranged in the second non-display area NA2, the gate driving units of each level in the first gate driving circuit 121 and the corresponding gate driving units in the second gate driving circuit 122 are connected to the same group of the scanning lines (for example, the first left gate driving unit 121a in the first gate driving circuit 121 and the first right gate driving unit 122a in the second gate driving circuit 122 are connected to the first group of scanning lines G1, and the second left gate driving unit 122 in the first gate driving circuit 121 is connected to the first group of scanning lines G2. 121b is connected to the second right gate drive unit 122b in the second gate drive circuit 122) and the second group of scan lines G2, the gate of the control transistor T0 connected to the gate drive units of the odd rows in the first gate drive circuit 121 is connected to the first control signal line SW1, and the gate of the control transistor T0 connected to the gate drive units of the even rows in the first gate drive circuit 121 is connected to the second control signal line SW2; the gate of the control transistor T0 connected to the gate drive units of the odd rows in the second gate drive circuit 122 is connected to the first control signal line SW1, and the gate of the control transistor T0 connected to the gate drive units of the even rows in the second gate drive circuit 122 is connected to the second control signal line SW2.

[0055] Specifically, Figure 3 As shown, it can be seen that the gate of the control transistor T0 connected to the first left gate driving unit 121a and the first right gate driving unit 122a located in the odd rows are both connected to the first control signal line SW1, and the gate of the control transistor T0 connected to the second left gate driving unit 121b and the second right gate driving unit 122b located in the even rows are both connected to the second control signal line SW2, so that the gate driving unit connected to the scan lines of the odd array and the gate driving unit connected to the scan lines of the even array can output signals to the scan lines of the odd array and the scan lines of the even array in a time-sharing manner under the control of the first control signal line and the second control signal line, thereby realizing the detection of pure color pictures.

[0056] Specifically, when a bilaterally driven gate driving circuit is adopted, two gate driving units connected to the same group of scan lines can be connected to the same control unit, that is, the control unit can be set only on one side to reduce the number of control units, but the embodiment of the present application is not limited to this, and two control units can be set to connect two gate driving units respectively.

[0057] Specifically, it can be understood that the embodiment of the present application only shows two levels of gate driving units. When the gate driving circuit on each side includes multiple gate driving units, the design and connection relationship of other levels of gate driving units can refer to the above description.

[0058] Specifically, for a display panel using a bilateral gate driving circuit architecture, the gates of the control transistors connected to the corresponding gate driving units in the gate driving circuits on both sides may be connected to the same control signal line, so that the bilateral gate driving circuits input the same signal to the same group of scan lines.

[0059] Specifically, one of the first gate driving circuit and the second gate driving circuit may be arranged on the left side of the display area, and the other may be arranged on the right side of the display area.

[0060] In some embodiments, Figure 1 , Figure 6 As shown, the display panel 1 includes non-display areas NA arranged on both sides of the display area AA, which are respectively a first non-display area NA1 and a second non-display area NA2, the gate driving circuit 12 includes a third gate driving circuit 123 respectively arranged in the first non-display area NA1 and a fourth gate driving circuit 124 arranged in the second non-display area NA2, the gate driving units at each stage in the third gate driving circuit 123 are connected to the scan lines of the odd array, the gate driving units at each stage in the fourth gate driving circuit 124 are connected to the scan lines of the even array, the gate of the control transistor T0 connected to the gate driving units at each stage in the third gate driving circuit 123 is connected to the first control signal line SW1, and the gate of the control transistor T0 connected to the gate driving units at each stage in the fourth gate driving circuit is connected to the second control signal line SW2.

[0061] Specifically, Figure 6 As shown, the third gate driving circuit 123 includes a first gate driving unit 123a and a third gate driving unit 123b, and the fourth gate driving circuit 124 includes a second gate driving unit 124a and a fourth gate driving unit 124b, the first gate driving unit 123a is connected to the first group of scan lines G1, the second gate driving unit 124a is connected to the second group of scan lines G2, the third gate driving unit 123b is connected to the third group of scan lines G3, and the fourth gate driving unit 124b is connected to the fourth group of scan lines G4, the gate of the control transistor T0 connected to the first gate driving unit 123a and the third gate driving unit 123b is connected to the first control signal line SW1, and the gate of the control transistor T0 connected to the second gate driving unit 124a and the fourth gate driving unit 124b is connected to the second control signal line SW2.

[0062] Specifically, for a display panel adopting a cross-drive gate drive circuit architecture, the number of gate drive units can be reduced. It can be understood that, relative to a display panel with a bilateral gate drive circuit architecture, a display panel adopting a cross-drive gate drive circuit architecture can reduce the number of gate drive units by half, thereby reducing the border.

[0063] Specifically, by connecting the gates of the control transistors connected to the gate drive units at each stage in the third gate drive circuit to the first control signal line, and connecting the gates of the control transistors connected to the gate drive units at each stage in the fourth gate drive circuit to the second control signal line, the gate drive units connected to the scan lines of the odd array and the gate drive units connected to the scan lines of the even array can output signals to the scan lines of the odd array and the scan lines of the even array in a time-sharing manner under the control of the first control signal line and the second control signal line, thereby realizing the detection of pure color images.

[0064] Specifically, it can be understood that the embodiment of the present application only shows two levels of gate driving units. When the gate driving circuit on each side includes multiple gate driving units, the design and connection relationship of other levels of gate driving units can refer to the above description.

[0065] Specifically, one of the third gate driving circuit and the fourth gate driving circuit may be arranged on the left side of the display area, and the other may be arranged on the right side of the display area.

[0066] In some embodiments, the gate driving unit 12a further includes a signal input terminal (eg Figure 4 The signal output terminal G(m-7) of the m-7th level gate driving circuit is the signal input terminal of the gate driving unit at this level), and in the gate driving circuit 12 on either side of the display area AA, the signal output terminal G(m) of the gate driving unit 12a of the odd rows is connected to the signal input terminal of the gate driving unit 12a of the even rows. For a display panel in which the signal output end of the gate driving unit of the odd rows is connected to the signal input end of the gate driving unit of the even rows, that is, a display panel adopting an asymmetric pull-down gate driving circuit architecture, the gate of the control transistor electrically connected to the scanning line of the odd rows can be connected to the first control signal line, and the gate of the control transistor electrically connected to the scanning line of the even rows can be connected to the second control signal line by making the gate driving circuit include a control unit. Then, when it is necessary to light up the display panel adopting the non-strip pixel architecture and the asymmetric pull-down gate driving circuit architecture, the scanning lines of the odd rows and the even rows can be respectively controlled to input effective levels through the first control signal line and the second control signal line, and the sub-pixel units of the odd rows and the even rows can be controlled accordingly to light up in sequence within one frame, and the input signal of the data line can be controlled to display a pure color picture, and the pure color picture of the display panel can be detected.

[0067] Specifically, for example, if the gate driving unit at this level is an eighth-level gate driving unit, then the gate driving unit at this level is a gate driving unit of an even-numbered row, and the signal input end of the gate driving unit at this level (the gate of the first pull-up maintaining transistor T11 can be regarded as the signal input end of the gate driving unit at this level) is the signal output end G(1) of the first-level gate driving unit, that is, the signal input end of the eighth-level gate driving unit is connected to the signal output end of the first-level gate driving unit, and the first-level gate driving unit is a gate driving unit of an odd-numbered row, then it can be seen that the signal output end of the gate driving unit of the odd-numbered row is connected to the signal input end of the gate driving unit of the even-numbered row.

[0068] Specifically, it can be understood that when the gate driving circuit adopts a bilateral driving architecture, the gate driving units of odd rows refer to gate driving units connected to the scan lines of the odd group, and the gate driving units of even rows refer to gate driving units connected to the scan lines of the even group; when the gate driving circuit adopts cross driving, the gate driving units of odd rows refer to gate driving units located in odd rows in the gate driving circuit, and the gate driving units of even rows refer to gate driving units located in even rows in the gate driving circuit. For example, the third gate driving circuit includes a first gate driving unit and a third gate driving unit, and the fourth gate driving circuit includes a second gate driving unit and a fourth gate driving unit. The first gate driving unit and the second gate driving unit are respectively gate driving units of the first row on the left and the first row on the right. Then the first gate driving unit and the second gate driving unit are gate driving units of odd rows, and the third gate driving unit and the fourth gate driving unit are respectively gate driving units of the second row on the left and the second row on the right. Then the third gate driving unit and the fourth gate driving unit are gate driving units of even rows. Similarly, the types of other gate driving units can be determined.

[0069] In some embodiments, the gate driving unit also includes a signal input terminal. In the gate driving circuit on either side of the display area, the signal output terminal of the gate driving unit of the odd rows is connected to the signal input terminal of the gate driving unit of the odd rows, and the signal output terminal of the gate driving unit of the even rows is connected to the signal input terminal of the gate driving unit of the even rows. For a display panel in which the signal output end of the gate driving unit of the odd rows is connected to the signal input end of the gate driving unit of the odd rows, and the signal output end of the gate driving unit of the even rows is connected to the signal input end of the gate driving unit of the even rows, that is, a display panel adopting a symmetrical pull-down gate driving circuit architecture, the gate of the control transistor electrically connected to the scanning lines of the odd array is connected to the first control signal line, and the gate of the control transistor electrically connected to the scanning lines of the even array is connected to the second control signal line. Then, when it is necessary to light up the display panel adopting a non-strip pixel architecture and an asymmetrical pull-down gate driving circuit architecture, the scanning lines of the odd array and the even array can be respectively controlled to input effective levels through the first control signal line and the second control signal line, and the sub-pixel units of the odd rows and the even rows are correspondingly controlled to light up in sequence or at the same time within one frame, and the input signal of the data line can be controlled to display a pure color picture, and the pure color picture of the display panel can be detected.

[0070] In some embodiments, Figure 7 , Fig. 9 As shown, a group of the scan lines 111 includes one scan line 111, the pixel units 113 located in the same row are connected to the same scan line 111, and the plurality of sub-pixel units located in the same column are connected to the same data line 112, the pixel unit 113 includes a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c, the first sub-pixel unit 113a is connected to the 3n+1th data line, the second sub-pixel unit 113b is connected to the 3n+2th data line, the third sub-pixel unit 113c is connected to the 3n+3th data line, n is greater than or equal to 0, and n is an integer;

[0071] The detection stage includes a first detection stage corresponding to the first sub-pixel unit 113a, a second detection stage corresponding to the second sub-pixel unit 113b, and a third detection stage corresponding to the third sub-pixel unit 113c; the first detection stage, the second detection stage, and the third detection stage all include a first time period t1 and a second time period t2;

[0072] When the display panel 1 is configured for the first detection stage, in the first time period t1 and the second time period t2, the 3n+1th data line is configured to output a valid level; when the display panel is configured for the second detection stage, in the first time period t1 and the second time period t2, the 3n+2th data line is configured to output a valid level; when the display panel is configured for the third detection stage, in the first time period t1 and the second time period t2, the 3n+3th data line is configured to output a valid level.

[0073] Specifically, Fig. 9 As shown, from Fig. 9 As can be seen from (a) in one frame t0, the first control signal line SW1 is configured to output a valid level in the first time period t1, and the second control signal line SW2 is configured to output a valid level in the second time period t2. In the first time period t1 and the second time period t2, the 3n+1th data line D 3n+1 Configured to output valid level, the 3n+2th data line D 3n+2 and the 3n+3rd data line D 3n+3 is configured to output an invalid level, so that the first sub-pixel unit can be lit up and a pure color picture detection is performed on the first sub-pixel unit; Fig. 9 As shown in (b), in one frame t0, the first control signal line SW1 is configured to output a valid level in the first time period t1, and the second control signal line SW2 is configured to output a valid level in the second time period t2. In the first time period t1 and the second time period t2, the 3n+2 data line D 3n+2 Configured to output valid level, the 3n+1th data line D 3n+1 and the 3n+3rd data line D 3n+3 is configured to output an invalid level, so that the second sub-pixel unit can be lit up and a pure color picture detection is performed on the second sub-pixel unit; Fig. 9 As shown in (c), in one frame t0, the first control signal line SW1 is configured to output a valid level in the first time period t1, and the second control signal line SW2 is configured to output a valid level in the second time period t2. In the first time period t1 and the second time period t2, the 3n+3 data line D 3n+3 Configured to output valid level, the 3n+1th data line D 3n+1 and the 3n+2nd data line D 3n+2 It is configured to output an invalid level, so that the third sub-pixel unit can be lit up, and a pure color picture detection is performed on the third sub-pixel unit.

[0074] Specifically, by making the 3n+1th data line, the 3n+2th data line and the 3n+3th data line output valid levels in three frames, pure color image detection can be performed on three sub-pixel units with different luminous colors, thereby realizing pure color image detection of the display panel. Figure 7 , Figure 8 As shown, a group of the scan lines includes one scan line, the pixel units 113 located in the same row are connected to the same scan line, and the multiple sub-pixel units located in the same column are connected to the same data line, the pixel unit 113 includes a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c, the first sub-pixel unit 113a is connected to the 3n+1th data line, the second sub-pixel unit 113b is connected to the 3n+2th data line, and the third sub-pixel unit 113c is connected to the 3n+3th data line, where n is greater than or equal to 0 and is an integer;

[0075] Wherein, the detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; when the display panel 1 is configured as the first detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, and the 3n+1th data line is configured to output a valid level; when the display panel 1 is configured as the second detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, and the 3n+2th data line is configured to output a valid level; when the display panel 1 is configured as the third detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level.

[0076] Specifically, Figure 7 As shown, it can be seen that each column of the first sub-pixel unit 113a is respectively connected to the first data line D1 and the fourth data line D4, each column of the second sub-pixel unit 113b is respectively connected to the second data line D2 and the fifth data line D5, and each column of the third sub-pixel unit 113c is respectively connected to the third data line D3 and the sixth data line D6; the first row of pixel units is connected to the first group of scan lines G1, and the second row of pixel units is connected to the second group of scan lines G2.

[0077] Specifically, Figure 8 As shown, from Figure 8 As can be seen from (a) in the figure, within a frame t0, the display panel is configured as the first detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, and the 3n+1th data line D 3n+1Configured to output valid level, the 3n+2th data line D 3n+2 and the 3n+3rd data line D 3n+3 is configured to output an invalid level, so that the first sub-pixel unit can be lit up and a pure color picture detection is performed on the first sub-pixel unit; Figure 8 As shown in (b), within a frame t0, the display panel is configured as the second detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, and the 3n+2nd data line D 3n+2 Configured to output valid level, the 3n+1th data line D 3n+1 and the 3n+3rd data line D 3n+3 is configured to output an invalid level, so that the second sub-pixel unit can be lit up and a pure color picture detection is performed on the second sub-pixel unit; Figure 8 As shown in (c), within a frame t0, the display panel is configured as the third detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, and the 3n+3 data line D 3n+3 Configured to output valid level, the 3n+1th data line D 3n+1 and the 3n+2nd data line D 3n+2 It is configured to output an invalid level, so that the third sub-pixel unit can be lit up, and a pure color picture detection is performed on the third sub-pixel unit.

[0078] Specifically, by making the 3n+1th data line, the 3n+2th data line and the 3n+3th data line output valid levels respectively within three frames, pure color picture detection can be performed on three sub-pixel units of different luminous colors respectively, thereby realizing pure color picture detection of the display panel.

[0079] Specifically, the three frames may be three consecutive frames or three non-consecutive frames. Specifically, when only one sub-pixel needs to be detected, the detection stage may have only one frame. Figure 7 For the pixel architecture shown, the corresponding gate drive circuit can be a bilateral drive architecture, a cross drive architecture, and the gate drive circuit can be a symmetrical pull-down gate drive circuit architecture, an asymmetrical pull-down gate drive circuit architecture. Similarly, for other pixel architectures, the corresponding gate drive circuit can adopt various architectures.

[0080] In some embodiments, Figure 2 , Figure 5As shown, a group of the scan lines 111 includes one scan line 111, one data line 112 is provided between two adjacent columns of the sub-pixel units, the pixel units 113 located in the same row are connected to the same scan line 111, and two adjacent sub-pixel units located in the same column are respectively connected to two adjacent data lines 112, the pixel units 113 include a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c, and the first sub-pixel unit 113a located in odd rows is connected to the 3rd sub-pixel unit 113c. The first sub-pixel unit 113a located in an even-numbered row is connected to the 3n+2th data line, the second sub-pixel unit 113b located in an odd-numbered row is connected to the 3n+2th data line, the second sub-pixel unit 113b located in an even-numbered row is connected to the 3n+3th data line, the third sub-pixel unit 113c located in an odd-numbered row is connected to the 3n+3th data line, and the third sub-pixel unit 113c located in an even-numbered row is connected to the 3n+4th data line, where n is greater than or equal to 0 and is an integer;

[0081] Wherein, the detection stage includes a first detection stage corresponding to the first sub-pixel unit 113a, a second detection stage corresponding to the second sub-pixel unit 113b, and a third detection stage corresponding to the third sub-pixel unit 113c; the first detection stage, the second detection stage, and the third detection stage all include a first time period t1 and a second time period t2; when the display panel 1 is configured as the first detection stage, in the first time period t1, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level; in the second time period t2, the 3n+2th data line is configured to output a valid level, and the 3n+1th data line and the 3n+3th data line are configured to output an invalid level; when the display panel 1 is configured as the second During the detection stage, in the first time period t1, the 3n+2th data line is configured to output a valid level, the 3n+1th data line and the 3n+3th data line are configured to output an invalid level, and in the second time period t2, the 3n+3th data line is configured to output a valid level, and the 3n+1th data line and the 3n+2th data line are configured to output an invalid level; when the display panel 1 is configured as the third detection stage, in the first time period t1, the 3n+3th data line is configured to output a valid level, the 3n+1th data line and the 3n+2th data line are configured to output an invalid level, and in the second time period t2, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level.

[0082] Specifically, Figure 2As shown in the figure, a data line 112 is provided between two adjacent columns of sub-pixel units, a first sub-pixel unit 113a in the first row of the first column and a first sub-pixel unit 113a in the second row of the first column are connected to the first data line D1 and the second data line D2 respectively, a first sub-pixel unit 113a in the first row of the fourth column and a first sub-pixel unit 113a in the second row of the fourth column are connected to the fourth data line D4 and the fifth data line D5 respectively; a second sub-pixel unit 113b in the first row of the second column and a second sub-pixel unit in the second row of the second column are connected to the second data line D2 and the third data line D3 respectively, and the first sub-pixel unit 113a in the first row of the fourth column and a first sub-pixel unit 113b in the second row of the second column are connected to the second data line D2 and the third data line D3 respectively. The second sub-pixel unit 113b in the first row of the fifth column and the second sub-pixel unit in the second row of the fifth column are connected to the fifth data line D5 and the sixth data line D6 respectively, the third sub-pixel unit 113c in the first row of the third column and the third sub-pixel unit 113c in the second row of the third column are connected to the third data line D3 and the fourth data line D4 respectively, the third sub-pixel unit 113c in the first row of the sixth column and the third sub-pixel unit in the second row of the sixth column are connected to the sixth data line D6 and the seventh data line respectively; the first row of pixel units is connected to the first group of scan lines G1, and the second row of pixel units is connected to the second group of scan lines G2.

[0083] Specifically, Figure 5 As shown in (a), when the display panel is configured in the first detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs an invalid level, and the 3n+1th data line D 3n+1 Input valid level, 3n+2 data line D 3n+2 and the 3n+3rd data line D 3n+3 In the second time period t2, the first control signal line SW1 inputs an invalid level, the second control signal line SW2 inputs a valid level, and the 3n+2nd data line D 3n+2 Input valid level, 3n+1th data line D 3n+1 and the 3n+3rd data line D 3n+3 An invalid level is input, so that only the first sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the first sub-pixel unit; Figure 5 As shown in (b), when the display panel is configured in the second detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs an invalid level, and the 3n+2nd data line D 3n+2 Input valid level, 3n+1th data line D 3n+1 and the 3n+3rd data line D 3n+3In the second time period t2, the first control signal line SW1 inputs an invalid level, the second control signal line SW2 inputs a valid level, and the 3n+3 data line D 3n+3 Input valid level, 3n+1th data line D 3n+1 and the 3n+2nd data line D 3n+2 An invalid level is input, so that only the second sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the second sub-pixel unit; Figure 5 As shown in (c), when the display panel is configured in the third detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs an invalid level, and the 3n+3 data line D 3n+3 Input valid level, 3n+1th data line D 3n+1 and the 3n+2nd data line D 3n+2 In the second time period t2, the first control signal line SW1 inputs an invalid level, the second control signal line SW2 inputs a valid level, and the 3n+1th data line D 3n+1 Input valid level, 3n+2 data line D 3n+2 and the 3n+3rd data line D 3n+3 An invalid level is input, so that only the third sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the third sub-pixel unit.

[0084] Specifically, three detection stages may be configured in three frames respectively, so that pure color picture detection can be performed on three sub-pixel units with different luminous colors respectively, thereby realizing pure color picture detection of the display panel.

[0085] Specifically, it can be understood that the third sub-pixel unit located in an even row is connected to the 3n+4th data line, which is equivalent to the third sub-pixel unit located in an even row being connected to the 3(n+1)+1th data line. Therefore, when the display panel is configured to the third detection stage, within the second time period, the 3n+1th data line can be configured to output a valid level, and the 3n+4th data line can also be configured to output a valid level.

[0086] In some embodiments, Fig.10 , Fig.11As shown, a group of the scan lines includes one scan line, two scan lines 111 are arranged between the sub-pixel units in two adjacent rows, two adjacent sub-pixel units in the same row are respectively connected to the two adjacent scan lines 111, two adjacent columns of the sub-pixel units are connected to the same data line 112, the pixel unit 113 includes a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c, one of the first sub-pixel units 113a in the two adjacent columns is connected to the 3n+1th data line, and the other of the first sub-pixel units 113a in the two adjacent columns is connected to the 3n+1th data line. The sub-pixel unit 113a is connected to the 3n+2th data line, one of the second sub-pixel units 113b in two adjacent columns is connected to the 3n+1th data line, the other of the second sub-pixel units 113b in two adjacent columns is connected to the 3n+3th data line, one of the third sub-pixel units 113c in two adjacent columns is connected to the 3n+2th data line, and the other of the third sub-pixel units 113c in two adjacent columns is connected to the 3n+3th data line, where n is greater than or equal to 0, and n is an integer;

[0087] Wherein, the detection stage includes a first detection stage corresponding to the first sub-pixel unit 113a, a second detection stage corresponding to the second sub-pixel unit 113b, and a third detection stage corresponding to the third sub-pixel unit 113c, and the first detection stage, the second detection stage, and the third detection stage all include a first time period t1 and a second time period t2; when the display panel 1 is configured as the first detection stage, in the first time period t1, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level; in the second time period t2, the 3n+2th data line is configured to output a valid level, and the 3n+1th data line and the 3n+3th data line are configured to output an invalid level; when the display panel 1 is configured as the second detection stage, During the detection stage, in the first time period t1, the 3n+3th data line is configured to output a valid level, the 3n+1th data line and the 3n+2th data line are configured to output an invalid level, and in the second time period t2, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level; when the display panel 1 is configured as the third detection stage, in the first time period t1, the 3n+2th data line is configured to output a valid level, the 3n+1th data line and the 3n+3th data line are configured to output an invalid level, and in the second time period t2, the 3n+3th data line is configured to output a valid level, and the 3n+1th data line and the 3n+2th data line are configured to output an invalid level.

[0088] Specifically, Fig.10 As shown, two scanning lines 111 are arranged between two adjacent rows of sub-pixel units, and the first sub-pixel unit 113a located in the first column, the first sub-pixel unit 113a located in the fourth column, the first sub-pixel unit 113a located in the seventh column, and the first sub-pixel unit 113a located in the tenth column are connected to the first data line D1, the second data line D2, the fourth data line D4, and the fifth data line D5 respectively; the second sub-pixel unit 113b located in the second column, the second sub-pixel unit 113b located in the fifth column, and the first sub-pixel unit 113a located in the eighth column are connected to the first data line D1, the second data line D2, the fourth data line D4, and the fifth data line D5 respectively. The second sub-pixel unit 113b and the second sub-pixel unit 113b located in the eleventh column are respectively connected to the first data line D1, the third data line D3, the fourth data line D4 and the sixth data line D6; the third sub-pixel unit 113c located in the third column, the third sub-pixel unit 113c located in the sixth column, the third sub-pixel unit 113c located in the ninth column and the third sub-pixel unit 113c located in the twelfth column are respectively connected to the second data line D2, the third data line D3, the fifth data line D5 and the sixth data line D6.

[0089] The first sub-pixel unit located in the first row of the first column and the first sub-pixel unit located in the first row of the seventh column are connected to the first group of scan lines G1, the first sub-pixel unit located in the first row of the fourth column and the first sub-pixel unit located in the first row of the tenth column are connected to the second group of scan lines G2, the first sub-pixel unit located in the second row of the first column and the first sub-pixel unit located in the second row of the seventh column are connected to the third group of scan lines G3, the first sub-pixel unit located in the second row of the fourth column and the first sub-pixel unit located in the second row of the tenth column are connected to the fifth group of scan lines G4, the first sub-pixel unit located in the third row of the first column and the first sub-pixel unit located in the third row of the seventh column are connected to the fifth group of scan lines G5, and the first sub-pixel unit located in the third row of the fourth column and the first sub-pixel unit located in the third row of the tenth column are connected to the sixth group of scan lines G6.

[0090] The second sub-pixel unit located in the first row of the fifth column and the second pixel unit located in the first row of the eleventh column are connected to the first group of scan lines G1, the second sub-pixel unit located in the first row of the second column and the second pixel unit located in the first row of the eighth column are connected to the second group of scan lines G2, the second sub-pixel unit located in the second row of the fifth column and the second pixel unit located in the second row of the eleventh column are connected to the third group of scan lines G3, the second sub-pixel unit located in the second row of the second column and the second pixel unit located in the second row of the eighth column are connected to the fourth group of scan lines G4, the second sub-pixel unit located in the third row of the fifth column and the second pixel unit located in the third row of the eleventh column are connected to the fifth group of scan lines G5, and the second sub-pixel unit located in the third row of the second column and the second pixel unit located in the third row of the eighth column are connected to the sixth group of scan lines G6.

[0091] The third sub-pixel unit located in the first row of the third column and the third sub-pixel unit located in the first row of the ninth column are connected to the first group of scan lines G1, the third sub-pixel unit located in the first row of the sixth column and the third sub-pixel unit located in the first row of the twelfth column are connected to the second group of scan lines G2, the third sub-pixel unit located in the second row of the third column and the third sub-pixel unit located in the second row of the ninth column are connected to the third group of scan lines G3, the third sub-pixel unit located in the second row of the sixth column and the third sub-pixel unit located in the second row of the twelfth column are connected to the fourth group of scan lines G4, the third sub-pixel unit located in the third row of the third column and the third sub-pixel unit located in the third row of the ninth column are connected to the fifth group of scan lines G5, and the third sub-pixel unit located in the third row of the sixth column and the third sub-pixel unit located in the third row of the twelfth column are connected to the sixth group of scan lines G6.

[0092] Specifically, Fig.11As shown in (a), when the display panel is configured in the first detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs an invalid level, and the 3n+1th data line D 3n+1 Input valid level, 3n+2 data line D 3n+2 and the 3n+3rd data line D 3n+3 In the second time period t2, the first control signal line SW1 inputs an invalid level, the second control signal line SW2 inputs a valid level, and the 3n+2nd data line D 3n+2 Input valid level, 3n+1th data line D 3n+1 and the 3n+3rd data line D 3n+3 An invalid level is input, so that only the first sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the first sub-pixel unit; Fig.11 As shown in (b), when the display panel is configured in the second detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs an invalid level, and the 3n+3 data line D 3n+3 Input valid level, 3n+1th data line D 3n+1 and the 3n+2nd data line D 3n+2 In the second time period t2, the first control signal line SW1 inputs an invalid level, the second control signal line SW2 inputs a valid level, and the 3n+1th data line D 3n+1 Input valid level, 3n+2 data line D 3n+2 and the 3n+3rd data line D 3n+3 An invalid level is input, so that only the second sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the second sub-pixel unit; Fig.11 As shown in (c), when the display panel is configured in the third detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs an invalid level, and the 3n+2nd data line D 3n+2 Input valid level, 3n+1th data line D 3n+1 and the 3n+3rd data line D 3n+3 In the second time period t2, the first control signal line SW1 inputs an invalid level, the second control signal line SW2 inputs a valid level, and the 3n+3 data line D 3n+3 Input valid level, 3n+1th data line D 3n+1 and the 3n+2nd data line D 3n+2 An invalid level is input, so that only the third sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the third sub-pixel unit.

[0093] Specifically, three detection stages may be configured in three frames respectively, so that pure color picture detection can be performed on three sub-pixel units with different luminous colors respectively, thereby realizing pure color picture detection of the display panel.

[0094] In some embodiments, Fig.12 , Fig.13 As shown, a group of the scan lines 111 includes two adjacent scan lines 111, two data lines 112 are arranged between the sub-pixel units of two adjacent columns, the pixel units 113 located in the same row are connected to the same scan line, the pixel units located in two adjacent rows are respectively connected to two adjacent scan lines in the same group of the scan lines (for example, the pixel units in the first row are connected to the first scan line G11 in the first group of scan lines G1, the pixel units in the second row are connected to the second scan line G12 in the first group of scan lines G1, the pixel units in the third row are connected to the third scan line G21 in the second group of scan lines G2, and the pixel units in the fourth row are connected to the fourth scan line G22 in the second group of scan lines G2), and the two adjacent sub-pixel units located in the same column are respectively connected to the two adjacent sub-pixel units. the data lines 112, the pixel units 113 include a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c, the first sub-pixel unit 113a located in odd rows is connected to the 6n+1th data line, the first sub-pixel unit 113a located in even rows is connected to the 6n+2th data line, the second sub-pixel unit 113b located in odd rows is connected to the 6n+3th data line, the second sub-pixel unit 113b located in even rows is connected to the 6n+4th data line, the third sub-pixel unit 113c located in odd rows is connected to the 6n+5th data line, the third sub-pixel unit 113c located in even rows is connected to the 6n+6th data line, n is greater than or equal to 0, and n is an integer;

[0095] The detection stage includes a first detection stage corresponding to the first sub-pixel unit 113a, a second detection stage corresponding to the second sub-pixel unit 113b, and a third detection stage corresponding to the third sub-pixel unit 113c, and the first detection stage, the second detection stage, and the third detection stage all include a first time period t1 and a second time period t2; when the display panel 1 is configured as the first detection stage, in the first time period t1 and the second time period t2, the 6n+1th data line and the 6n+2th data line are configured to output a valid level, and the 6n+3th data line, the 6n+4th data line, the 6n+5th data line, and the 6n+6th data line are configured to output an invalid level; When the display panel 1 is configured for the second detection stage, in the first time period t1 and the second time period t2, the 6n+3th data line and the 6n+4th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+5th data line and the 6n+6th data line are configured to output an invalid level; when the display panel 1 is configured for the third detection stage, in the first time period t1 and the second time period t2, the 6n+5th data line and the 6n+6th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+3th data line and the 6n+4th data line are configured to output an invalid level.

[0096] Specifically, Fig.12As shown, two data lines 112 are arranged between the sub-pixel units of two adjacent columns, the first sub-pixel unit 113a in the first row of the first column and the first sub-pixel unit 113a in the third row of the first column are connected to the first data line D1, the first sub-pixel unit 113a in the second row of the first column and the first sub-pixel unit 113a in the fourth row of the first column are connected to the second data line D2, the first sub-pixel unit 113a in the first row of the fourth column and the first sub-pixel unit 113a in the third row of the fourth column are connected to the seventh data line D7, the first sub-pixel unit 113a in the second row of the fourth column and the first sub-pixel unit 113a in the fourth row of the fourth column are connected to the eighth data line D8; the second sub-pixel unit 113b in the first row of the second column and the second sub-pixel unit 113b in the third row of the second column are connected to the third data line D3, the second sub-pixel unit in the second row of the second column and the second sub-pixel unit in the fourth row of the second column are connected to the fourth data line D4, and the second sub-pixel unit 113b in the first row of the fifth column and the second sub-pixel unit 113b in the fourth row of the fourth column are connected to the eighth data line D8. The first sub-pixel unit 113a in the third row of the fifth column and the second sub-pixel unit 113b in the third row of the fifth column are connected to the ninth data line D9, the second sub-pixel unit in the second row of the fifth column and the second sub-pixel unit in the fourth row of the fifth column are connected to the tenth data line D10, the third sub-pixel unit 113c in the first row of the third column and the third sub-pixel unit in the third row of the third column are connected to the fifth data line D5, the third sub-pixel unit 113c in the second row of the third column and the third sub-pixel unit 113c in the fourth row of the third column are connected to the sixth data line D10. The third sub-pixel unit 113c located in the first row of the sixth column and the third sub-pixel unit located in the third row of the sixth column are connected to the eleventh data line D11, the third sub-pixel unit located in the second row of the sixth column and the third sub-pixel unit located in the fourth row of the sixth column are connected to the twelfth data line D12; the first row of pixel units is connected to the first group of scan lines G1, the second row of pixel units is connected to the second group of scan lines G2, the third row of pixel units is connected to the third group of scan lines G3, and the fourth row of pixel units is connected to the fourth group of scan lines G4.

[0097] Specifically, Fig.13 As shown in (a), when the display panel is configured in the first detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, and the second control signal line SW2 inputs an invalid level. In the second time period t2, the first control signal line SW1 inputs an invalid level, and the second control signal line SW2 inputs a valid level. In the first time period t1 and the second time period t2, the 6n+1th data line D 6n+1 and the 6n+2th data line D 6n+2 Input valid level, 6n+3th data line D 6n+3 To the 6n+6th data line D6n+6 An invalid level is input, so that only the first sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the first sub-pixel unit; Fig.13 As shown in (b), when the display panel is configured in the second detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, and the second control signal line SW2 inputs an invalid level. In the second time period t2, the first control signal line SW1 inputs an invalid level, and the second control signal line SW2 inputs a valid level. In the first time period t1 and the second time period t2, the 6n+3th data line D 6n+3 and the 6n+4th data line D 6n+4 Input valid level, 6n+1th data line D 6n+1 To the 6n+2th data line D 6n+2 , 6n+5th data line D 6n+5 To the 6n+6th data line D 6n+6 An invalid level is input, so that only the second sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the second sub-pixel unit; Fig.13 As shown in (c), when the display panel is configured in the third detection stage, in the first time period t1, the first control signal line SW1 inputs a valid level, and the second control signal line SW2 inputs an invalid level. In the second time period t2, the first control signal line SW1 inputs an invalid level, and the second control signal line SW2 inputs a valid level. In the first time period t1 and the second time period t2, the 6n+5th data line D 6n+5 and the 6n+6th data line D 6n+6 Input valid level, 6n+1th data line D 6n+1 To the 6n+4th data line D 6n+4 An invalid level is input, so that only the third sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the third sub-pixel unit.

[0098] In some embodiments, Fig.12 , Fig.14As shown, a group of the scan lines 111 includes two adjacent scan lines 111, two data lines 112 are arranged between the sub-pixel units of two adjacent columns, the pixel units 113 located in the same row are connected to the same scan line, the pixel units located in two adjacent rows are respectively connected to two adjacent scan lines in the same group of the scan lines (for example, the pixel units in the first row are connected to the first scan line G11 in the first group of scan lines G1, the pixel units in the second row are connected to the second scan line G12 in the first group of scan lines G1, the pixel units in the third row are connected to the third scan line G21 in the second group of scan lines G2, and the pixel units in the fourth row are connected to the fourth scan line G22 in the second group of scan lines G2), and the two adjacent sub-pixel units located in the same column are respectively connected to the two adjacent sub-pixel units. the data lines 112, the pixel units 113 include a first sub-pixel unit 113a, a second sub-pixel unit 113b and a third sub-pixel unit 113c, the first sub-pixel unit 113a located in odd rows is connected to the 6n+1th data line, the first sub-pixel unit 113a located in even rows is connected to the 6n+2th data line, the second sub-pixel unit 113b located in odd rows is connected to the 6n+3th data line, the second sub-pixel unit 113b located in even rows is connected to the 6n+4th data line, the third sub-pixel unit 113c located in odd rows is connected to the 6n+5th data line, the third sub-pixel unit 113c located in even rows is connected to the 6n+6th data line, n is greater than or equal to 0, and n is an integer;

[0099] Wherein, the detection stage includes a first detection stage corresponding to the first sub-pixel unit 113a, a second detection stage corresponding to the second sub-pixel unit 113b, and a third detection stage corresponding to the third sub-pixel unit 113c; when the display panel 1 is configured as the first detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, the 6n+1th data line and the 6n+2th data line are configured to output a valid level, and the 6n+3th data line, the 6n+4th data line, the 6n+5th data line, and the 6n+6th data line are configured to output an invalid level; when the display panel 1 is configured as the second detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, and the 6n+1th data line and the 6n+2th data line are configured to output a valid level. SW1 and the second control signal line SW2 are configured to output a valid level, the 6n+3th data line and the 6n+4th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+5th data line and the 6n+6th data line are configured to output an invalid level; when the display panel 1 is configured as the third detection stage, the first control signal line SW1 and the second control signal line SW2 are configured to output a valid level, the 6n+5th data line and the 6n+6th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+3th data line and the 6n+4th data line are configured to output an invalid level.

[0100] Specifically, in Fig.14 In Fig.14 As shown in (a), in a frame t0, the display panel is configured as the first detection stage, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs a valid level, and the 6n+1th data line D 6n+1 and the 6n+2th data line D 6n+2 Input valid level, 6n+3th data line D 6n+3 To the 6n+6th data line D 6n+6 An invalid level is input, so that only the first sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the first sub-pixel unit; Fig.14 As shown in (b), within a frame t0, the display panel is configured as the second detection stage, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs a valid level, and the 6n+3 data line D 6n+3 and the 6n+4th data line D 6n+4 Input valid level, 6n+1th data line D 6n+1 To the 6n+2th data line D 6n+2 , 6n+5th data line D 6n+5 To the 6n+6th data line D 6n+6An invalid level is input, so that only the second sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the second sub-pixel unit; Fig.14 As shown in (c), within a frame t0, the display panel is configured as the third detection stage, the first control signal line SW1 inputs a valid level, the second control signal line SW2 inputs a valid level, and the 6n+5th data line D 6n+5 and the 6n+6th data line D 6n+6 Input valid level, 6n+1th data line D 6n+1 To the 6n+4th data line D 6n+4 An invalid level is input, so that only the third sub-pixel unit can be lit in one frame, and a pure color picture detection is performed on the third sub-pixel unit.

[0101] Specifically, three detection stages may be configured in three frames respectively, so that pure color picture detection can be performed on three sub-pixel units with different luminous colors respectively, thereby realizing pure color picture detection of the display panel.

[0102] In some embodiments, Figure 4 As shown, the gate driving unit 12a includes:

[0103] The pull-up maintaining module 211 includes a first pull-up maintaining transistor T11 and a second pull-up maintaining transistor T41, wherein the gate of the first pull-up maintaining transistor T11 and the first electrode of the first pull-up maintaining transistor T11 are connected to the signal output terminal of the gate driving unit 12a of the first level ( Figure 4 In the example, the gate of the first pull-up maintenance transistor T11 is connected to the signal output terminal G(m-7) of the m-7th level gate driving unit, the second electrode of the first pull-up maintenance transistor T11 is connected to the second electrode of the second pull-up maintenance transistor T41, and the gate of the second pull-up maintenance transistor T41 is connected to the signal output terminal of the m+ith level gate driving unit 12a ( Figure 4 In the example, the gate of the second pull-up maintaining transistor T41 is connected to the signal output terminal G(m+7) of the m+7th gate driving unit, and the first electrode of the second pull-up maintaining transistor T41 is connected to the low potential signal line VGL;

[0104] A pull-up module 212 is connected to the control node QN with the pull-up maintaining module 211, and the pull-up module 212 includes a pull-up transistor T21, a gate of the pull-up transistor T21 is connected to the control node QN, a first electrode of the pull-up transistor T21 is connected to the clock signal line CK, and a second electrode of the pull-up transistor T21 is connected to the signal output terminal G(m) of the gate driving unit at this stage;

[0105] The inversion module 213 includes a first inversion transistor T51, a second inversion transistor T52, a third inversion transistor T53 and a fourth inversion transistor T54, wherein the gate of the first inversion transistor T51 and the first electrode of the first inversion transistor T51 are connected to the detection signal line GCH, the second electrode of the first inversion transistor T51 is connected to the second electrode of the second inversion transistor T52 and the gate of the third inversion transistor T53, the gate of the second inversion transistor T52 is connected to the control node QN, the first electrode of the second inversion transistor T52 is connected to the low potential signal line VGL, the first electrode of the third inversion transistor T53 is connected to the detection signal line CGH, the second electrode of the third inversion transistor T53 is connected to the second electrode of the fourth inversion transistor T54, the gate of the fourth inversion transistor T54 is connected to the control node QN, and the first electrode of the fourth inversion transistor T54 is connected to the low potential signal line VGL;

[0106] The pull-down module 214 includes a first pull-down transistor T42 and a second pull-down transistor T32, wherein the gate of the first pull-down transistor T42 is connected to the second electrode of the third inverting transistor T53, the first electrode of the first pull-down transistor T42 is connected to the low potential signal line VGL, the second electrode of the first pull-down transistor T42 is connected to the control node QN, the gate of the second pull-down transistor T32 is connected to the second electrode of the third inverting transistor T53, the first electrode of the second pull-down transistor T32 is connected to the low potential signal line VGL, and the second electrode of the second pull-down transistor T32 is connected to the signal output terminal G(m) of the gate driving unit at this stage;

[0107] The reset module 215 includes a first reset transistor TrQ and a second reset transistor TrG, wherein the gate of the first reset transistor TrQ is connected to the reset signal line REST, the first electrode of the first reset transistor TrQ is connected to the low potential signal line VGL, the second electrode of the first reset transistor TrQ is connected to the control node QN, the gate of the second reset transistor TrG is connected to the reset signal line REST, the first electrode of the second reset transistor TrG is connected to the low potential signal line VGL, and the second electrode of the second reset transistor TrG is connected to the signal output terminal G(m) of the gate driving unit at this stage;

[0108] Wherein, m is greater than or equal to 2 and is a positive integer, and i is less than m and is a positive integer.

[0109] Specifically, by multiplexing the control signal lines with the signal lines in the gate driving unit, the number of signal lines can be reduced.

[0110] Specifically, Figure 4 In the description, the control transistor in the control unit is connected to the first control signal line as an example. It can be understood that when the control transistor is connected to the second control signal line, the circuit of the display panel can refer to the above description.

[0111] Specifically, Figure 4 In the figure, the signal input end of the gate driving unit at this level is connected to the signal output end of the gate driving unit at the m-7th level for explanation, but the embodiments of the present application are not limited to this. According to different architectures of the gate driving circuit (symmetrical pull-down gate driving circuit architecture or asymmetrical pull-down gate driving circuit architecture, bilateral driving or cross driving), the signal input end of the gate driving unit at this level can be connected to the signal output end of the gate driving unit at other levels. For example, the signal input end of the gate driving unit at this level is connected to the signal output end of the gate driving unit at the m-5th level. Similarly, the gate of the second pull-up maintaining transistor can be connected to the signal output end of the gate driving unit at other levels.

[0112] Specifically, Figure 4 As shown, the gate driving unit 12a further includes a storage capacitor C, one plate of the storage capacitor C is connected to the control node QN, and the other plate of the storage capacitor C is connected to the signal output terminal G(m) of the gate driving unit at this stage.

[0113] Specifically, it can be understood that the embodiment of the present application is described by taking the gate driving unit as 11T1C (11 thin film transistors and 1 capacitor) as an example, but the embodiment of the present application is not limited to this, and the gate driving unit can be other circuit structures.

[0114] Specifically, the wiring to which the gate of the first inverter transistor is connected may be different from the detection signal line.

[0115] Specifically, when the display panel is configured in the detection phase, the clock signal line CK, the reset signal line REST, the start signal line (not shown), and the low potential signal line VGL are all input with low potential signals.

[0116] Specifically, when the display panel is configured in the display stage, the first control signal line and the second control signal line both output invalid signals, and each signal line in the gate driving unit outputs a normal signal.

[0117] Specifically, when the display panel is configured in the detection stage, the detection signal line outputs a valid level.

[0118] Specifically, in the embodiments of the present application, unless otherwise specified, the signal output terminal refers to the signal output terminal of the gate driving unit at this level.

[0119] Specifically, it can be understood that the gate drive circuit in the embodiment of the present application can be applied to display panels using different pixel architectures and different gate drive circuit architectures, so as to meet the lighting detection requirements of all types of display panels without affecting the normal operation of the display panel.

[0120] Specifically, the display panel may be a display panel using low-temperature polysilicon thin film transistors, or a display panel using oxide semiconductor thin film transistors. The display panel may be a liquid crystal display panel, or an organic light emitting diode display panel.

[0121] Specifically, it can be understood that the above embodiments respectively provide detailed descriptions of the display panel from various pixel architectures, gate drive circuit architectures and other aspects. When there is no conflict between the embodiments, the embodiments can be combined. For example, the gate drive unit also includes a signal input terminal. In the gate drive circuit on either side of the display area, the signal output terminal of the gate drive unit in the odd-numbered rows is connected to the signal input terminal of the gate drive unit in the even-numbered rows, and a group of the scan lines includes one scan line, the pixel units in the same row are connected to the same scan line, and the two adjacent sub-pixel units in the same column are connected to each other. Connected to the same data line, the pixel unit includes a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit is connected to the 3n+1th data line, the second sub-pixel unit is connected to the 3n+2th data line, and the third sub-pixel unit is connected to the 3n+3th data line, n is greater than or equal to 0, and n is an integer; wherein, when the display panel is configured as a detection stage, the first control signal line and the second control signal line are configured to output a valid level, and the 3n+1th data line, the 3n+2th data line and the 3n+3th data line output valid levels in sequence.

[0122] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0123] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0124] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a display area and a non-display area arranged at least on one side of the display area, wherein the non-display area comprises a gate driving circuit, the display area comprises a plurality of groups of scan lines, a plurality of data lines and a plurality of pixel units, each group of the scan lines comprises at least one scan line, each group of the scan lines outputs the same signal, and each pixel unit comprises at least three sub-pixel units of different luminous colors; wherein the gate driving circuit comprises: A plurality of cascaded gate driving units, each gate driving unit comprising a signal output terminal, wherein one of the signal output terminals is connected to a group of the scanning lines; A plurality of control units, connected to the gate driving units correspondingly, the control units comprising a control transistor, a first control signal line, a second control signal line and a detection signal line, the first electrode of the control transistor being connected to the detection signal line, the second electrode of the control transistor being connected to the signal output terminal, the gate of the control transistor electrically connected to the scan lines of the odd array being connected to the first control signal line, and the gate of the control transistor electrically connected to the scan lines of the even array being connected to the second control signal line; Wherein, when the display panel is configured as a detection stage, in a first time period, the first control signal line is configured to output a valid level, and the second control signal line is configured to output an invalid level; in a second time period, the first control signal line is configured to output an invalid level, and the second control signal line is configured to output a valid level; the detection stage includes the first time period and the second time period.

2. The display panel according to claim 1, wherein: The display panel includes non-display areas arranged on both sides of the display area, which are respectively a first non-display area and a second non-display area, the gate driving circuit includes a first gate driving circuit respectively arranged in the first non-display area and a second gate driving circuit arranged in the second non-display area, and the gate driving units of each level in the first gate driving circuit and the corresponding gate driving units in the second gate driving circuit are connected to the same group of scanning lines; The gates of the control transistors connected to the gate drive units in odd rows in the first gate drive circuit are connected to the first control signal line, and the gates of the control transistors connected to the gate drive units in even rows in the first gate drive circuit are connected to the second control signal line; The gates of the control transistors connected to the gate drive units in odd rows in the second gate drive circuit are connected to the first control signal line, and the gates of the control transistors connected to the gate drive units in even rows in the second gate drive circuit are connected to the second control signal line.

3. The display panel according to claim 1, wherein: The display panel includes non-display areas arranged on both sides of the display area, which are respectively a first non-display area and a second non-display area, the gate driving circuit includes a third gate driving circuit respectively arranged in the first non-display area and a fourth gate driving circuit arranged in the second non-display area, the gate driving units of each stage in the third gate driving circuit are connected to the scan lines of the odd group, and the gate driving units of each stage in the fourth gate driving circuit are connected to the scan lines of the even group; The gate of the control transistor connected to the gate drive unit at each stage in the third gate drive circuit is connected to the first control signal line, and the gate of the control transistor connected to the gate drive unit at each stage in the fourth gate drive circuit is connected to the second control signal line.

4. The display panel according to any one of claims 1 to 3, characterized in that: The gate driving unit further includes a signal input terminal. In the gate driving circuit on either side of the display area, the signal output terminal of the gate driving unit in the odd-numbered rows is connected to the signal input terminal of the gate driving unit in the even-numbered rows.

5. The display panel according to any one of claims 1 to 3, characterized in that: A group of the scan lines includes one scan line, the pixel units located in the same row are connected to the same scan line, and the plurality of sub-pixel units located in the same column are connected to the same data line, the pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit is connected to the 3n+1th data line, the second sub-pixel unit is connected to the 3n+2th data line, the third sub-pixel unit is connected to the 3n+3th data line, n is greater than or equal to 0, and n is an integer; The detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; the first detection stage, the second detection stage, and the third detection stage all include a first time period and a second time period; When the display panel is configured in the first detection phase, in the first time period and the second time period, the 3n+1th data line is configured to output a valid level; When the display panel is configured in the second detection phase, in the first time period and the second time period, the 3n+2th data line is configured to output a valid level; When the display panel is configured in the third detection phase, in the first time period and the second time period, the 3n+3 th data line is configured to output a valid level.

6. The display panel according to any one of claims 1 to 3, characterized in that: A group of the scan lines includes one scan line, one data line is arranged between two adjacent columns of the sub-pixel units, the pixel units located in the same row are connected to the same scan line, and two adjacent sub-pixel units located in the same column are respectively connected to two adjacent data lines, the pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit located in an odd row is connected to the 3n+1th data line, the first sub-pixel unit located in an even row is connected to the 3n+2th data line, the second sub-pixel unit located in an odd row is connected to the 3n+2th data line, the second sub-pixel unit located in an even row is connected to the 3n+3th data line, the third sub-pixel unit located in an odd row is connected to the 3n+3th data line, and the third sub-pixel unit located in an even row is connected to the 3n+4th data line, where n is greater than or equal to 0 and n is an integer; The detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; the first detection stage, the second detection stage, and the third detection stage all include a first time period and a second time period; When the display panel is configured as the first detection stage, in the first time period, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level; in the second time period, the 3n+2th data line is configured to output a valid level, and the 3n+1th data line and the 3n+3th data line are configured to output an invalid level; When the display panel is configured as the second detection stage, in the first time period, the 3n+2th data line is configured to output a valid level, and the 3n+1th data line and the 3n+3th data line are configured to output an invalid level, and in the second time period, the 3n+3th data line is configured to output a valid level, and the 3n+1th data line and the 3n+2th data line are configured to output an invalid level; When the display panel is configured for the third detection stage, in the first time period, the 3n+3th data line is configured to output a valid level, the 3n+1th data line and the 3n+2th data line are configured to output an invalid level, and in the second time period, the 3n+1th data line is configured to output a valid level, the 3n+2th data line and the 3n+3th data line are configured to output an invalid level.

7. The display panel according to any one of claims 1 to 3, characterized in that: A group of the scan lines includes one scan line, two scan lines are arranged between the sub-pixel units in two adjacent rows, two adjacent sub-pixel units in the same row are connected to the two adjacent scan lines respectively, and the sub-pixel units in two adjacent columns are connected to the same data line, the pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, one of the first sub-pixel units in the two adjacent columns is connected to the 3n+1th data line, another of the first sub-pixel units in the two adjacent columns is connected to the 3n+2th data line, one of the second sub-pixel units in the two adjacent columns is connected to the 3n+1th data line, another of the second sub-pixel units in the two adjacent columns is connected to the 3n+3th data line, one of the third sub-pixel units in the two adjacent columns is connected to the 3n+2th data line, and another of the third sub-pixel units in the two adjacent columns is connected to the 3n+3th data line, n is greater than or equal to 0, and n is an integer; The detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; the first detection stage, the second detection stage, and the third detection stage all include a first time period and a second time period; When the display panel is configured as the first detection stage, in the first time period, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level; in the second time period, the 3n+2th data line is configured to output a valid level, and the 3n+1th data line and the 3n+3th data line are configured to output an invalid level; When the display panel is configured as the second detection stage, in the first time period, the 3n+3th data line is configured to output a valid level, and the 3n+1th data line and the 3n+2th data line are configured to output an invalid level, and in the second time period, the 3n+1th data line is configured to output a valid level, and the 3n+2th data line and the 3n+3th data line are configured to output an invalid level; When the display panel is configured for the third detection stage, in the first time period, the 3n+2th data line is configured to output a valid level, the 3n+1th data line and the 3n+3th data line are configured to output an invalid level, and in the second time period, the 3n+3th data line is configured to output a valid level, the 3n+1th data line and the 3n+2th data line are configured to output an invalid level.

8. The display panel according to any one of claims 1 to 3, characterized in that: A group of the scan lines includes two adjacent scan lines, two data lines are arranged between the sub-pixel units in two adjacent columns, the pixel units in the same row are connected to the same scan line, the pixel units in two adjacent rows are respectively connected to two adjacent scan lines in the same group of the scan lines, and two adjacent sub-pixel units in the same column are respectively connected to two adjacent data lines, the pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit in the odd row is connected to the 6n+1th data line, the first sub-pixel unit in the even row is connected to the 6n+2th data line, the second sub-pixel unit in the odd row is connected to the 6n+3th data line, the second sub-pixel unit in the even row is connected to the 6n+4th data line, the third sub-pixel unit in the odd row is connected to the 6n+5th data line, and the third sub-pixel unit in the even row is connected to the 6n+6th data line, n is greater than or equal to 0, and n is an integer; The detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; the first detection stage, the second detection stage, and the third detection stage all include a first time period and a second time period; When the display panel is configured as the first detection stage, in the first time period and the second time period, the 6n+1th data line and the 6n+2th data line are configured to output a valid level, and the 6n+3th data line, the 6n+4th data line, the 6n+5th data line, and the 6n+6th data line are configured to output an invalid level; when the display panel is configured as the second detection stage, in the first time period and the second time period, the 6n+3th data line and the 6n+4th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+5th data line, and the 6n+6th data line are configured to output an invalid level; When the display panel is configured for the third detection stage, in the first time period and the second time period, the 6n+5th data line and the 6n+6th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+3th data line and the 6n+4th data line are configured to output an invalid level.

9. The display panel according to any one of claims 1 to 3, characterized in that: The gate driving unit comprises: A pull-up maintenance module, comprising a first pull-up maintenance transistor and a second pull-up maintenance transistor, wherein the gate of the first pull-up maintenance transistor and the first electrode of the first pull-up maintenance transistor are connected to the signal output end of the gate driving unit of the mi-th level, the second electrode of the first pull-up maintenance transistor is connected to the second electrode of the second pull-up maintenance transistor, the gate of the second pull-up maintenance transistor is connected to the signal output end of the gate driving unit of the m+i-th level, and the first electrode of the second pull-up maintenance transistor is connected to a low potential signal line; A pull-up module, connected to the control node with the pull-up maintaining module, the pull-up module comprises a pull-up transistor, a gate of the pull-up transistor is connected to the control node, a first electrode of the pull-up transistor is connected to a clock signal line, and a second electrode of the pull-up transistor is connected to a signal output end of a gate driving unit at this stage; An inversion module, comprising a first inversion transistor, a second inversion transistor, a third inversion transistor and a fourth inversion transistor, wherein the gate of the first inversion transistor and the first electrode of the first inversion transistor are connected to the detection signal line, the second electrode of the first inversion transistor is connected to the second electrode of the second inversion transistor and the gate of the third inversion transistor, the gate of the second inversion transistor is connected to the control node, the first electrode of the second inversion transistor is connected to the low potential signal line, the first electrode of the third inversion transistor is connected to the detection signal line, the second electrode of the third inversion transistor is connected to the second electrode of the fourth inversion transistor, the gate of the fourth inversion transistor is connected to the control node, and the first electrode of the fourth inversion transistor is connected to the low potential signal line; A pull-down module, comprising a first pull-down transistor and a second pull-down transistor, wherein the gate of the first pull-down transistor is connected to the second electrode of the third inverter transistor, the first electrode of the first pull-down transistor is connected to the low potential signal line, the second electrode of the first pull-down transistor is connected to the control node, the gate of the second pull-down transistor is connected to the second electrode of the third inverter transistor, the first electrode of the second pull-down transistor is connected to the low potential signal line, and the second electrode of the second pull-down transistor is connected to the signal output terminal of the gate driving unit at this stage; A reset module, comprising a first reset transistor and a second reset transistor, wherein the gate of the first reset transistor is connected to a reset signal line, the first electrode of the first reset transistor is connected to the low potential signal line, the second electrode of the first reset transistor is connected to the control node, the gate of the second reset transistor is connected to the reset signal line, the first electrode of the second reset transistor is connected to the low potential signal line, and the second electrode of the second reset transistor is connected to a signal output terminal of a gate driving unit at this stage; Wherein, m is greater than or equal to 2 and is a positive integer, and i is less than m and is a positive integer.

10. A display panel, characterized in that: The invention comprises a display area and a non-display area arranged at least on one side of the display area, wherein the non-display area comprises a gate driving circuit, the display area comprises a plurality of groups of scan lines, a plurality of data lines and a plurality of pixel units, each group of the scan lines comprises at least one scan line, each group of the scan lines outputs the same signal, and each pixel unit comprises at least three sub-pixel units of different luminous colors; wherein the gate driving circuit comprises: A plurality of cascaded gate driving units, each gate driving unit comprising a signal output terminal, wherein one of the signal output terminals is connected to a group of the scanning lines; A plurality of control units, connected to the gate driving units correspondingly, the control units comprising a control transistor, a first control signal line, a second control signal line and a detection signal line, the first electrode of the control transistor being connected to the detection signal line, the second electrode of the control transistor being connected to the signal output terminal, the gate of the control transistor electrically connected to the scan lines of the odd array being connected to the first control signal line, and the gate of the control transistor electrically connected to the scan lines of the even array being connected to the second control signal line; Among them, one of the data lines is connected to multiple sub-pixel units of the same luminous color, and when the display panel is configured as a detection stage, the first control signal line is configured to output a valid level, and the second control signal line is configured to output a valid level.

11. The display panel according to claim 10, wherein: The display panel includes non-display areas arranged on both sides of the display area, which are respectively a first non-display area and a second non-display area, the gate driving circuit includes a first gate driving circuit respectively arranged in the first non-display area and a second gate driving circuit arranged in the second non-display area, and the gate driving units of each level in the first gate driving circuit and the corresponding gate driving units in the second gate driving circuit are connected to the same group of scanning lines; The gates of the control transistors connected to the gate drive units in odd rows in the first gate drive circuit are connected to the first control signal line, and the gates of the control transistors connected to the gate drive units in even rows in the first gate drive circuit are connected to the second control signal line; The gates of the control transistors connected to the gate drive units in odd rows in the second gate drive circuit are connected to the first control signal line, and the gates of the control transistors connected to the gate drive units in even rows in the second gate drive circuit are connected to the second control signal line.

12. The display panel according to claim 10, wherein: The display panel includes non-display areas arranged on both sides of the display area, which are respectively a first non-display area and a second non-display area, the gate driving circuit includes a third gate driving circuit respectively arranged in the first non-display area and a fourth gate driving circuit arranged in the second non-display area, the gate driving units of each stage in the third gate driving circuit are connected to the scan lines of the odd group, and the gate driving units of each stage in the fourth gate driving circuit are connected to the scan lines of the even group; The gate of the control transistor connected to the gate drive unit at each stage in the third gate drive circuit is connected to the first control signal line, and the gate of the control transistor connected to the gate drive unit at each stage in the fourth gate drive circuit is connected to the second control signal line.

13. The display panel according to any one of claims 10 to 12, characterized in that: The gate driving unit further includes a signal input terminal. In the gate driving circuit on either side of the display area, the signal output terminal of the gate driving unit in the odd-numbered rows is connected to the signal input terminal of the gate driving unit in the even-numbered rows.

14. The display panel according to any one of claims 10 to 12, characterized in that: A group of the scan lines includes one scan line, the pixel units located in the same row are connected to the same scan line, and the multiple sub-pixel units located in the same column are connected to the same data line, the pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit is connected to the 3n+1th data line, the second sub-pixel unit is connected to the 3n+2th data line, and the third sub-pixel unit is connected to the 3n+3th data line, n is greater than or equal to 0, and n is an integer; wherein the detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; When the display panel is configured in the first detection phase, the 3n+1th data line is configured to output a valid level; When the display panel is configured in the second detection stage, the 3n+2th data line is configured to output a valid level; When the display panel is configured in the third detection phase, the 3n+3 th data line is configured to output a valid level.

15. The display panel according to any one of claims 10 to 12, characterized in that: A group of the scan lines includes two adjacent scan lines, two data lines are arranged between the sub-pixel units in two adjacent columns, the pixel units in the same row are connected to the same scan line, the pixel units in two adjacent rows are respectively connected to two adjacent scan lines in the same group of the scan lines, and two adjacent sub-pixel units in the same column are respectively connected to two adjacent data lines, the pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit, the first sub-pixel unit in the odd row is connected to the 6n+1th data line, the first sub-pixel unit in the even row is connected to the 6n+2th data line, the second sub-pixel unit in the odd row is connected to the 6n+3th data line, the second sub-pixel unit in the even row is connected to the 6n+4th data line, the third sub-pixel unit in the odd row is connected to the 6n+5th data line, and the third sub-pixel unit in the even row is connected to the 6n+6th data line, n is greater than or equal to 0, and n is an integer; Wherein, the detection stage includes a first detection stage corresponding to the first sub-pixel unit, a second detection stage corresponding to the second sub-pixel unit, and a third detection stage corresponding to the third sub-pixel unit; When the display panel is configured as the first detection stage, the 6n+1th data line and the 6n+2th data line are configured to output a valid level, and the 6n+3th data line, the 6n+4th data line, the 6n+5th data line and the 6n+6th data line are configured to output an invalid level; When the display panel is configured as the second detection stage, the 6n+3th data line and the 6n+4th data line are configured to output a valid level, and the 6n+1th data line, the 6n+2th data line, the 6n+5th data line and the 6n+6th data line are configured to output an invalid level; When the display panel is configured for the third detection stage, the 6n+5th data line and the 6n+6th data line are configured to output valid levels, and the 6n+1th data line, the 6n+2th data line, the 6n+3th data line and the 6n+4th data line are configured to output invalid levels.

16. The display panel according to any one of claims 10 to 12, characterized in that: The gate driving unit comprises: A pull-up maintenance module, comprising a first pull-up maintenance transistor and a second pull-up maintenance transistor, wherein the gate of the first pull-up maintenance transistor and the first electrode of the first pull-up maintenance transistor are connected to the signal output end of the gate driving unit of the mi-th level, the second electrode of the first pull-up maintenance transistor is connected to the second electrode of the second pull-up maintenance transistor, the gate of the second pull-up maintenance transistor is connected to the signal output end of the gate driving unit of the m+i-th level, and the first electrode of the second pull-up maintenance transistor is connected to a low potential signal line; A pull-up module, connected to the control node with the pull-up maintaining module, the pull-up module comprises a pull-up transistor, a gate of the pull-up transistor is connected to the control node, a first electrode of the pull-up transistor is connected to a clock signal line, and a second electrode of the pull-up transistor is connected to a signal output end of a gate driving unit at this stage; An inversion module, comprising a first inversion transistor, a second inversion transistor, a third inversion transistor and a fourth inversion transistor, wherein the gate of the first inversion transistor and the first electrode of the first inversion transistor are connected to the detection signal line, the second electrode of the first inversion transistor is connected to the second electrode of the second inversion transistor and the gate of the third inversion transistor, the gate of the second inversion transistor is connected to the control node, the first electrode of the second inversion transistor is connected to the low potential signal line, the first electrode of the third inversion transistor is connected to the detection signal line, the second electrode of the third inversion transistor is connected to the second electrode of the fourth inversion transistor, the gate of the fourth inversion transistor is connected to the control node, and the first electrode of the fourth inversion transistor is connected to the low potential signal line; A pull-down module, comprising a first pull-down transistor and a second pull-down transistor, wherein the gate of the first pull-down transistor is connected to the second electrode of the third inverter transistor, the first electrode of the first pull-down transistor is connected to the low potential signal line, the second electrode of the first pull-down transistor is connected to the control node, the gate of the second pull-down transistor is connected to the second electrode of the third inverter transistor, the first electrode of the second pull-down transistor is connected to the low potential signal line, and the second electrode of the second pull-down transistor is connected to the signal output terminal of the gate driving unit at this stage; A reset module, comprising a first reset transistor and a second reset transistor, wherein the gate of the first reset transistor is connected to a reset signal line, the first electrode of the first reset transistor is connected to the low potential signal line, the second electrode of the first reset transistor is connected to the control node, the gate of the second reset transistor is connected to the reset signal line, the first electrode of the second reset transistor is connected to the low potential signal line, and the second electrode of the second reset transistor is connected to a signal output terminal of a gate driving unit at this stage; Wherein, m is greater than or equal to 2 and is a positive integer, and i is less than m and is a positive integer.

17. A display device, characterized in that: Comprising the display panel as described in any one of claims 1 to 16.

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