Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims at solving the problem that in the related technology, a display panel is prone to generating horizontal cross grains. The display panel comprises a gate drive circuit, and a power signal line and a clock signal line group which are positioned on one side of the gate drive circuit and are sequentially arranged, the power signal line is electrically connected with the gate drive circuit, and the power signal line extends along a first direction. The clock signal line group comprises a first clock signal line and a second clock signal line which are sequentially arranged in the direction away from the gate drive circuit; the first clock signal line is electrically connected with the gate drive circuit through a first connecting line, and the second clock signal line is electrically connected with the gate drive circuit through a second connecting line. Wherein the power supply signal line is provided with a recess, and an opening of the recess faces the gate drive circuit or the clock signal line group. The first connecting line comprises a main body part and a bending part connected with the main body part, and the bending part is located in the area where the recess is located in the thickness direction of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] GOA (Gate Driver on Array) technology refers to integrating a gate driving circuit on an array substrate of a display panel so that it can replace an external integrated circuit (IC) to drive a horizontal scan line.

[0003] In large-size display panels, the gate drive circuit is usually connected to multiple clock signal lines. However, due to the position differences of the clock signal lines, the lengths of the connecting lines used to connect the gate drive circuit and the clock signal lines are different, resulting in resistance differences in the connecting lines, which in turn makes it easy for the display interface of the display panel to produce horizontal stripes and other problems. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which are used to alleviate the problem that horizontal stripes are easily generated on display panels in the related art.

[0005] On the one hand, an embodiment of the present application provides a display panel, which includes a gate drive circuit, a power signal line and a clock signal line group; the power signal line is located on one side of the gate drive circuit and is electrically connected to the gate drive circuit, and the power signal line extends along a first direction; the clock signal line group is located on the side of the power signal line away from the gate drive circuit, and the clock signal line group includes at least one first clock signal line and a second clock signal line arranged in sequence along a direction away from the gate drive circuit; the first clock signal line is electrically connected to the gate drive circuit through a first connecting line, and the second clock signal line is electrically connected to the gate drive circuit through a second connecting line; wherein the power signal line has at least one recess, and the opening of the recess faces one of the gate drive circuit and the clock signal line group; the first connecting line includes a main body and a bending portion connected to the main body, and the bending portion is located in the area where the recess is located in the thickness direction of the display panel.

[0006] In some embodiments, at least some of the first connecting lines have the same length.

[0007] In some embodiments, the length of each of the first connecting lines is equal to the length of the second connecting lines.

[0008] In some embodiments, along the first direction, multiple first connecting lines are divided into multiple connecting line groups arranged in sequence, wherein the lengths of different first connecting lines in the same connecting line group are equal, and along the first direction, the lengths of the first connecting lines in multiple connecting line groups gradually change.

[0009] In some embodiments, the resistance difference of the first connection lines in any two adjacent connection line groups is the same.

[0010] In some embodiments, the length of the second connecting line is equal to the length of a first connecting line in the connecting line group close to the second connecting line.

[0011] In some embodiments, the power signal line includes a first portion, a second portion, and a third portion sequentially connected along the first direction, and a width of the first portion and a width of the third portion are greater than a width of the second portion to form the recess.

[0012] In some embodiments, the first part and the third part respectively include M first sub-routes that are spaced apart from each other and arranged in parallel, and the second part includes N second sub-routes that are spaced apart from each other and arranged in parallel, M is greater than N, and the consecutive N first sub-routes are connected one-to-one with the N second sub-routes.

[0013] In some embodiments, each first connecting line is further provided with an extension portion at one end away from the gate driving circuit, and the extension portion is connected to the main body portion; for different first connecting lines, the sum of the lengths of the main body portion and the extension portion connected thereto is equal.

[0014] In some embodiments, the display panel also includes a first capacitor balancing part connected to the second connecting line, and a second capacitor balancing part connected to each of the bending parts, the power signal line also has an auxiliary recess, and the first capacitor balancing part is located in the area where the auxiliary recess is located in the thickness direction of the display panel; the second capacitor balancing part is located in the area where the recess is located in the thickness direction of the display panel; wherein, along the first direction, the sum of the sizes of the bending part and the second capacitor balancing part is equal to the sum of the sizes of the second connecting line and the first capacitor balancing part.

[0015] In some embodiments, the power signal line is adjacent to the gate driving circuit, and an opening of the recess faces the gate driving circuit.

[0016] In some embodiments, the power signal line includes a first power sub-signal line and a second power sub-signal line, and the first power sub-signal line and the second power sub-signal line are arranged in sequence along a direction away from the clock signal line group; the first power sub-signal line has the recess, and the opening of the recess faces the gate drive circuit, and the second power sub-signal line has at least one opposing recess, and the opposing recess is arranged relative to the recess, and the bending portion is also located in the area where the opposing recess is located in the thickness direction of the display panel.

[0017] On the other hand, an embodiment of the present application further provides a display device, which includes the display panel as described in any of the above embodiments.

[0018] For the display panel provided in the embodiment of the present application, since the power signal line has at least one recess, and the first connection line is bent in the area corresponding to the recess and forms a bent portion, the length of the first connection line can be effectively compensated, so that the length of the first connection line matches the length of the second connection line, thereby reducing the difference in resistance between the first connection line and the second clock signal line, so as to alleviate the problem of horizontal stripes on the display panel. In addition, the bent portion does not overlap with the power signal line in the area of ​​the recess K, so that the signal transmitted in the first connection line and the signal in the power signal line can be prevented from generating crosstalk. In addition, since the power signal line has a recess K for realizing partial bending of the first connection line, the problem that the display panel with a narrow frame or an ultra-narrow frame does not have enough space in the frame area to realize partial bending of the first connection line can be alleviated, so that the display panel can be suitable for display panels with narrow frames or ultra-narrow frames. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a partial structure of a display panel in the related art;

[0020] Figure 2 is a schematic diagram of the structure of a display panel provided in some embodiments of the present application;

[0021] Figure 3 yes Figure 2 A structural schematic diagram of a local structure in;

[0022] Figure 4 yes Figure 2 Another structural schematic diagram of the local structure in;

[0023] Figure 5 is a partial structural schematic diagram of a connecting line according to some embodiments of the present application;

[0024] Figure 6 yes Figure 2 Another structural schematic diagram of the local structure in;

[0025] Figure 7 yes Figure 2 Another structural schematic diagram of the local structure in;

[0026] Figure 8 yes Figure 2 Another structural schematic diagram of the local structure in . DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0028] In the description of this application, it should be understood that the terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0029] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0030] The use of "suitable for" or "configured to" in this application is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values ​​can be based on additional conditions or values ​​beyond the stated values ​​in practice.

[0031] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is provided to enable any person skilled in the art to implement and use the present application.

[0032] The various embodiments of the present application are similar, and features in different embodiments and / or different examples may be combined with each other.

[0033] In the related art, the length of the connection wires used to connect the gate drive circuit and the clock signal line varies, resulting in resistance differences in the connection wires, which in turn causes problems such as horizontal stripes on the display interface of the display panel. In order to reduce the resistance difference, winding is currently usually used to increase the length of some connection wires, thereby reducing the resistance difference between different signal lines.

[0034] The winding method requires that the border area of ​​the display panel has enough space to meet the winding requirements of the connecting wires. Conventional display panels can achieve winding by increasing the width of the border area, but for display panels with narrow or ultra-narrow borders, the border area is difficult to provide enough area to meet the winding requirements of the connecting wires.

[0035] like Figure 1 As shown, the display panel 100' in the related art includes a gate driving circuit 11', a plurality of clock signal lines 13', and a connection line 12' connecting the clock signal line 13' and the gate driving circuit 11'. Since the border area of ​​the display panel 100' with a narrow or ultra-narrow border is limited, it is difficult to bend the connection line 12' to achieve winding, which causes the display panel 100' to have horizontal stripes and other problems.

[0036] Based on this, some embodiments of the present application provide a display panel, such as Figure 2 As shown, the display panel 100 may include an effective display area AA and a bezel area BA.

[0037] The effective display area AA includes a pixel array composed of a plurality of pixels, and the pixel array can be used to realize the picture display of the display panel.

[0038] In addition, signal lines for providing various signals (such as clock signals, high-level signals, low-level signals, etc.) are provided in the frame area BA. Figure 3 The specific details of the local structure P located in the border area BA are described in detail.

[0039] like Figure 3 As shown, the display panel 100 includes a gate driving circuit 11, a power signal line 12, and a clock signal line group 13. The power signal line 12 is located on a side of the gate driving circuit 11 away from the effective display area AA, and the clock signal line group 13 is located on a side of the power signal line 12 away from the gate driving circuit 11. That is, the gate driving circuit 11, the power signal line 12, and the clock signal line group 13 are sequentially arranged in a direction away from the effective display area AA.

[0040] The power signal line 12 is electrically connected to the gate drive circuit 11, and the power signal line 12 extends along the first direction X. The power signal line 12 has at least one recess K, and the opening of the recess K faces at least one of the gate drive circuit 11 and the clock signal line group 13 ( Figure 3 Only the opening of the recess K is shown toward the gate drive circuit 11).

[0041] In this embodiment, the clock signal line group 13 includes at least one (for example, a plurality of) first clock signal lines 131 and second clock signal lines 132 which are sequentially arranged side by side in a direction away from the gate driving circuit 11 . Figure 3 7 first clock signal lines 131 and 1 second clock signal line 132 are shown, and the second clock signal line 132 is located on the side of all the first clock signal lines 131 away from the gate drive circuit 11. The first clock signal line 131 is electrically connected to the gate drive circuit 11 through the first connecting line 14, and the second clock signal line 132 is electrically connected to the gate drive circuit 11 through the second connecting line 15. The first connecting line 14 includes a main body 141 and a bending portion 142 connected to the main body 141, and the bending portion 142 is located in the area where the recess K is located in the thickness direction of the display panel 100. The bending portion 142 can be used to compensate for the length of the first connecting line 14 to increase the length of the first connecting line 14.

[0042] For the display panel 100 provided in the embodiment of the present application, since the power signal line 12 has at least one recess K, and the first connection line 14 is bent in the area corresponding to the recess K to form a bent portion 142, the length of the first connection line 14 can be effectively compensated, so that the length of the first connection line 14 matches the length of the second connection line 15, thereby reducing the difference in resistance between the first connection line 14 and the second connection line 15, so as to alleviate the problem of horizontal stripes on the display panel 100. In addition, the bent portion 142 does not overlap with the power signal line 12 in the area of ​​the recess K, so that the signal transmitted in the first connection line 14 and the signal in the power signal line 12 can be prevented from generating crosstalk. In addition, since the power signal line 12 has a recess K for realizing partial bending of the first connection line 14, it can also be applied to display panels with narrow or ultra-narrow borders, thereby alleviating the problem of horizontal stripes on the display panel 100 with narrow or ultra-narrow borders.

[0043] In some examples, the extension direction of the main body 141 of the first connection line 14 is the same as the extension direction of the second connection line 15 .

[0044] In some examples, the sum of the lengths of the main body 141 and the bent portion 142 is substantially equal to the length of the second connection line 15. That is, the length of the first connection line 14 is substantially equal to the length of the second connection line 15. In this way, the resistance values ​​of the first connection line 14 and the second connection line 15 can be equal, which helps to avoid problems such as horizontal stripes on the display panel 100.

[0045] It is worth noting that the "A and B are approximately equal" mentioned in this article may mean that A and B are completely equal, or the difference between A and B is within a set range. For example, the absolute value of the difference between A and B is less than 10% of A.

[0046] In some embodiments, the gate driving circuit 11 may be a GOA circuit. Figure 3 and Figure 4 As shown, the gate driving circuit 11 includes a plurality of shift register units 111 arranged in a first direction X and cascaded. Different clock signal lines are electrically connected to different shift register units 111. For example, the first clock signal line 131 is electrically connected to one shift register unit 111 in the gate driving circuit 11 through the first connection line 14, and the second clock signal line 132 is electrically connected to another shift register unit 111 in the gate driving circuit 11 through the second connection line 15.

[0047] In some examples, the clock signal line group 13 includes multiple clock signal lines (i.e., a first clock signal line 131 and a second clock signal line 132), and the multiple clock signal lines are arranged along a second direction, and the second direction Y intersects the first direction X. For example, the second direction Y and the first direction X may be perpendicular to each other.

[0048] In some examples, the first connection line 14 and the second connection line 15 are arranged in the same layer, and the metal layer where the first connection line 14 and the second connection line 15 are located is located in a different layer from the metal layer where the clock signal line group 13 is located. An insulating layer is provided between the two metal layers for spacing, and a via is also provided in the insulating layer. One end of the first connection line 14 is electrically connected to the corresponding first clock signal line 131 through the via, and the other end of the first connection line 14 is used to be electrically connected to the corresponding shift register unit 111, thereby realizing the transmission of the clock signal. In addition, one end of the second connection line 15 is electrically connected to the second clock signal line 132 through the via, and the other end of the second connection line 15 is used to be electrically connected to the corresponding shift register unit 111, thereby realizing the transmission of the clock signal.

[0049] In some embodiments, Figure 4 and Figure 5 As shown, the power signal line 12 includes a first portion 121, a second portion 122 and a third portion 123 which are sequentially arranged and connected to each other along the first direction X. In the second direction Y, the size of the first portion 121 and the size of the third portion 123 are respectively larger than the size of the second portion 122 to form a recess K. In other words, the width of the first portion 121 and the width of the third portion 123 are respectively larger than the width of the second portion 122, so that the second portion 122 is retracted compared to the first portion 121 and the third portion 123 to form the recess K.

[0050] In some examples, the size of the first portion 121 and the size of the third portion 123 may be equal, so that the shape of the recess K may be more uniform, thereby having a relatively large opening area to facilitate the layout of the bending portion 142 .

[0051] It is worth noting that the "depression" in the present application does not only include the depression formed by the above-mentioned first part 121, the second part 122 and the third part 123, but also includes at least the following situations. The power signal line 12 includes a first part 121 and a second part 122 arranged in sequence along the first direction X and connected to each other. In the second direction Y, the size of the first part 121 is larger than the size of the second part 122 to form a depression K. In other words, the depression can also be in a step shape. Therefore, as long as the size of a part of the power signal line 12 in the second direction Y is reduced, and the bending portion 142 can be arranged in the area where the depression is located, it is within the scope of consideration of the present application.

[0052] In some embodiments, Figure 4 and Figure 5 As shown, the first portion 121 and the third portion 123 respectively include M first sub-routes 1210 that are spaced apart from each other and arranged in parallel, and the second portion 122 includes N second sub-routes 1220 that are spaced apart from each other and arranged in parallel.

[0053] By respectively setting the first part 121, the second part 122 and the third part 123 as a plurality of mutually spaced sub-routes, not only the stress of the power signal line 12 can be reduced, but also the overlapping area between the power signal line 12 and other routes (such as the first connecting line 14) in the thickness direction of the display panel 100 can be reduced, thereby reducing the interference between different signals.

[0054] In some examples, M is greater than N, and the N consecutive first sub-routes 1210 are connected one-to-one with the N second sub-routes 1220. In this way, the N first sub-routes 1210 can be gathered to expand the depth of the recess K, thereby increasing the opening area of ​​the recess K to facilitate the layout of the bending portion 142.

[0055] In some examples, N is greater than or equal to M / 2. For example, when M=6, the value of N can be 3, 4, or 5.

[0056] By setting N to be greater than or equal to M / 2, the width of the second portion 122 can be at least half of the width of the power signal line 12, thereby ensuring the stability of the structure of the power signal line 12 and the effective transmission of the power signal.

[0057] In some embodiments, Figure 3 As shown, when the clock signal line group 13 includes a plurality of first clock signal lines 131, the plurality of first clock signal lines 131 are electrically connected to the gate driving circuit 11 through a plurality of first connecting lines 14. Among them, at least some of the plurality of first connecting lines 14 have the same length.

[0058] In some examples, the lengths of all the first connection lines 14 are equal, so that the resistance values ​​of all the first connection lines 14 are equal, thereby effectively avoiding the problem of horizontal stripes on the display panel 100 .

[0059] In this case, the length of each first connection line 14 is equal to the length of each second connection line 15 , so that the resistance values ​​of all the connection lines are equal, thereby further avoiding the problem of horizontal stripes on the display panel 100 .

[0060] In other examples, the lengths of some of the first connection lines 14 are equal. In this case, in the area of ​​the display panel 100 corresponding to the first connection lines 14, the resistance values ​​of the first connection lines 14 are equal because the lengths of the first connection lines 14 are equal, thereby effectively avoiding the problem of horizontal stripes in the area of ​​the display panel 100 corresponding to the first connection lines 14.

[0061] In some cases, the size of the power signal line 12 in the second direction Y is limited, so that the depth of the recess K of the power signal line 12 is limited, resulting in a limited length of the first connection line 14 that can be compensated by the bent portion 142 .

[0062] Based on this, in some embodiments of the present application, Figure 6 As shown, along the first direction X, the plurality of first connection lines 14 are divided into a plurality of sequentially arranged connection line groups 140, wherein the lengths of different first connection lines 14 in the same connection line group 140 are equal. Also, along the first direction X, the lengths of the first connection lines 14 in the plurality of connection line groups 140 gradually change.

[0063] For example, Figure 6 It is shown that the five first connecting lines 14 are divided into two connecting line groups 140. In the same connecting line group 140, the lengths of the first connecting lines 14 are equal, while in different connecting line groups 140, the lengths of the first connecting lines 14 are not equal, and along the first direction X, the lengths of the first connecting lines 14 in different connecting line groups 140 gradually increase or decrease.

[0064] By making the lengths of the first connection lines 14 in different connection line groups 140 change regularly, it is possible to avoid the problem of obvious horizontal stripes on the display panel 100 caused by the large differences in the first connection lines 14 in different connection line groups 140. In addition, this can effectively reduce the length differences of the first connection lines 14, thereby reducing the resistance differences of the first connection lines 14, and further effectively reducing the risk of horizontal stripes on the display panel 100.

[0065] In some embodiments, Figure 6As shown, the length of the second connection line 15 is equal to the length of the first connection line 14 in the connection line group 140 close to the second connection line 15. In other words, the second connection line 15 can be divided into the connection line group 140, so as to have the same length as the first connection line 14 in the connection line group 140. In this case, the resistance value of the second connection line 15 is equal to the resistance value of the first connection line 14 in the connection line group 140. This is conducive to reducing the resistance difference between different connection lines, thereby effectively reducing the risk of horizontal stripes appearing on the display panel 100.

[0066] In some embodiments, Figure 6 As shown, the resistance difference of the first connection lines 14 in any two adjacent connection line groups 140 is the same.

[0067] This arrangement can reduce the resistance variation of the first connection lines 14 in different connection line groups 140 , thereby facilitating the control of the resistance difference of different first connection lines 14 , thereby effectively reducing the risk of horizontal stripes on the display panel 100 .

[0068] In order to further reflect the beneficial effects of the above embodiments, the following is an example in which a display panel includes 12 clock signal lines. Correspondingly, there are also 12 connecting lines for connecting the clock signal lines and the gate drive circuit. As shown in Table 1, Table 1 shows the resistance values ​​of the connecting lines in different display panels. In Table 1, CK1 to CK12 correspond to the connecting lines connecting the clock signal lines, respectively. Example 1 shows the resistance values ​​of the connecting lines in the display panel 100' in the related art, and Example 2 shows the resistance values ​​of the connecting lines in the display panel 100 provided in the embodiment of the present application.

[0069] Table 1

[0070] Connection lines Example 1 Example 2 CK1 3.4 4.2 CK2 3.5 4.2 CK3 3.6 4.2 CK4 3.7 4.3 CK5 3.8 4.3 CK6 3.9 4.4 CK7 4.0 4.4 CK8 4.1 4.4 CK9 4.2 4.5 CK10 4.3 4.5 CK11 4.4 4.6 CK12 4.5 4.6

[0071] Since all the connecting lines of the display panel 100' in the related art have length differences, the resistance of each connecting line gradually changes, so the final overall resistance difference reaches 1.2; while for the display panel 100 provided in the embodiment of the present application, since the first connecting line includes a bending portion, the lengths of different first connecting lines are compensated, so that the final overall resistance difference can be reduced to 0.4, which can effectively alleviate or even overcome the problem of horizontal stripes.

[0072] In some embodiments, Figure 4 As shown, the power signal line 12 is adjacent to the gate driving circuit 11 , and the opening of the recess K faces the gate driving circuit 11 .

[0073] It is worth noting that the power signal line 12 usually has a relatively large width, so the power signal line 12 can have a relatively large area to set the recess K, thereby meeting the requirement of forming the bending portion 142 of the first connecting line 14 .

[0074] In some examples, the power signal line 12 may be a low-level power signal line VSS. As an implementation, a plurality of (eg, two) low-frequency clock signal lines LS may be provided between the power signal line 12 and the clock signal line group 13 .

[0075] In some embodiments, Figure 7 As shown, the power signal line 12 includes a first power sub-signal line 121 and a second power sub-signal line 122, which are sequentially arranged in a direction away from the clock signal line group 13; the first power sub-signal line 121 has the recess K, and the opening of the recess K faces the gate drive circuit 11, and the second power sub-signal line 122 has at least one opposing recess M, the opposing recess M and the recess K are arranged oppositely, and the bending portion 142 is also located in the area where the opposing recess M is located in the thickness direction of the display panel 100. That is, when the second power sub-signal line 122 has the opposing recess M, the bending portion 142 is located in the recess K and the opposing recess M at the same time.

[0076] In this case, the opposing recess M can further expand the area that can be used to arrange the bending portion 142, which can further improve the use scenario of the display panel 100, that is, the display panel 100 can be suitable for scenario requirements of 12 clock signal lines (12CK), 16 clock signal lines (16CK) or even more clock signal lines.

[0077] In some examples, the first power sub-signal line 121 and the second power sub-signal line 122 may be a high-level power signal line VDD and a low-level power signal line VSS, respectively; or, the first power sub-signal line 121 and the second power sub-signal line 122 may both be high-level power signal lines VDD; or, the first power sub-signal line 121 and the second power sub-signal line 122 may both be low-level power signal lines VSS. This application does not limit this.

[0078] In some embodiments, Figure 8 As shown, each first connection line 14 has an extension portion 16 at one end away from the gate driving circuit 11, and the extension portion 16 is connected to the main body 141. For different first connection lines 14, the sum of the lengths of the main body 141 and the extension portion 16 connected thereto is equal.

[0079] With such a configuration, the extension portion 16 can be used to extend the length of the first connecting line 14, so that different first connecting lines 14 cross the same number of clock signal lines, thereby keeping the capacitance of different first connecting lines 14 the same. This can effectively avoid the problem of horizontal stripes on the display panel that is easily caused by the different capacitances of the first connecting lines 14.

[0080] In some examples, the first end of the second connection line 15 connecting the second clock signal line 132 is flush with the second end of the extension portion 16 away from the main body 141 , and the line between the first end and the second end extends along the first direction X.

[0081] In this case, the number of clock signal lines crossed by the first connection line 14 is equal to the number of clock signal lines crossed by the second connection line 15 , which can further avoid the problem of horizontal stripes on the display panel caused by the different capacitances of the second connection line 15 and the first connection line 14 .

[0082] In some embodiments, Figure 8 As shown, the second connecting line 15 is also connected to the first capacitor balancing part 17, the power signal line 12 also has an auxiliary recess N, and the first capacitor balancing part 17 is located in the area where the auxiliary recess N is located in the thickness direction of the display panel 100; each bending part 142 is also connected to the second capacitor balancing part 18, and the second capacitor balancing part 18 is located in the area where the recess K is located in the thickness direction of the display panel 100.

[0083] Wherein, along the first direction X, the sum of the sizes of the bending portion 142 and the second capacitor balancing portion 18 is equal to the size of the second connecting line 15 and the first capacitor balancing portion 17. Figure 7 As shown, along the first direction X, the size of the bending portion 142 is D1, the size of the second capacitor balancing portion 18 is D2, the size of the second connecting line 15 is D3, and the size of the first capacitor balancing portion 17 is D4, that is, D1+D2=D3+D4.

[0084] In this case, the capacitance formed between the first capacitor balancing portion 17 and the power signal line 12 is equal to the capacitance formed between the bending portion 142 and the second capacitor balancing portion 18 and the power signal line 12. This can effectively improve the capacitance difference caused by the bending portion 142 of the first connecting line 14, thereby making the uniformity at each position on the display panel 100 good, thereby effectively ensuring the display effect of the display panel 100.

[0085] In some examples, the bending portion 142 includes two first bending segments extending along the first direction X and a first connecting segment located between the two first bending segments, and two ends of the first connecting segment are respectively connected to the two first bending segments, thereby achieving bending of the bending portion 142.

[0086] In some examples, the second capacitor balancing portion 18 includes two second bending segments extending along the first direction X and a second connecting segment located between the two second bending segments, the second connecting segment and the first connecting segment are arranged opposite to each other, and the two second bending segments, the second connecting segment and the first connecting segment form a rectangle.

[0087] In some examples, the first capacitor balancing portion 17 includes two third bending segments extending along the first direction X and a third connecting segment located between the two third bending segments, the third connecting segment and the second connecting line 15 are arranged opposite to each other, and the third connecting segment and the second connecting line 15 are respectively located at two ends of any third bending segment.

[0088] It is worth mentioning that Figure 3 , Figure 4 as well as Figures 6 to 8 Only for Figure 2 The local structure P may also include other signal lines, which are not limited in the embodiment of the present application.

[0089] In addition, for a display panel with an ultra-narrow frame, the frame area is usually only about 2.7 mm wide, while the width of the connecting wire at the bending part usually needs to be tens or even hundreds of microns. Usually, the gap between two adjacent lines in the frame area cannot meet the bending requirements of the connecting wire. Therefore, the display panel provided by the present application uses the power signal line to set a recess to meet the bending requirements of the connecting wire, thereby effectively alleviating or even avoiding the problem of horizontal stripes on the display panel with an ultra-narrow frame.

[0090] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: Gate drive circuit; a power signal line, located at one side of the gate driving circuit and electrically connected to the gate driving circuit, the power signal line extending along a first direction; as well as a clock signal line group, located at a side of the power signal line away from the gate drive circuit, the clock signal line group comprising at least one first clock signal line and a second clock signal line sequentially arranged in a direction away from the gate drive circuit; the first clock signal line is electrically connected to the gate drive circuit through a first connecting line, and the second clock signal line is electrically connected to the gate drive circuit through a second connecting line; Among them, the power signal line has at least one recess, the opening of the recess faces the gate drive circuit and one of the clock signal line groups; the first connecting line includes a main body and a bending portion connected to the main body, and the bending portion is located in the area where the recess is located in the thickness direction of the display panel.

2. The display panel according to claim 1, characterized in that: At least some of the first connecting lines have the same length.

3. The display panel according to claim 2, characterized in that: The length of each of the first connecting lines is equal to the length of the second connecting lines.

4. The display panel according to claim 2, characterized in that: Along the first direction, the plurality of first connection lines are divided into a plurality of connection line groups arranged sequentially, wherein different first connection lines in the same connection line group have the same length, and along the first direction, the lengths of the first connection lines in the plurality of connection line groups gradually change.

5. The display panel according to claim 4, characterized in that: The resistance difference between the first connecting lines in any two adjacent connecting line groups is the same.

6. The display panel according to claim 4, characterized in that: The length of the second connecting line is equal to the length of a first connecting line in the connecting line group close to the second connecting line.

7. The display panel according to any one of claims 1 to 6, characterized in that: The power signal line includes a first portion, a second portion, and a third portion sequentially connected along the first direction, and a width of the first portion and a width of the third portion are greater than a width of the second portion to form the recess.

8. The display panel according to claim 7, characterized in that: The first part and the third part respectively include M first sub-routes that are spaced apart from each other and arranged in parallel, and the second part includes N second sub-routes that are spaced apart from each other and arranged in parallel, M is greater than N, and the consecutive N first sub-routes are connected one-to-one with the N second sub-routes.

9. The display panel according to any one of claims 1 to 6, characterized in that: An extension portion is further provided at one end of each first connection line away from the gate driving circuit, and the extension portion is connected to the main body portion; for different first connection lines, the sum of the lengths of the main body portion and the extension portion connected thereto is equal.

10. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: a first capacitor balancing portion connected to the second connecting line, the power signal line further having an auxiliary recess, and the first capacitor balancing portion being located in a region where the auxiliary recess is located in a thickness direction of the display panel; a second capacitor balancing portion connected to each of the bent portions, wherein the second capacitor balancing portion is located in the region where the depression is located in the thickness direction of the display panel; Wherein, along the first direction, the sum of the sizes of the bending portion and the second capacitor balancing portion is equal to the sum of the sizes of the second connecting line and the first capacitor balancing portion.

11. The display panel according to any one of claims 1 to 6, characterized in that: The power signal line is adjacent to the gate driving circuit, and the opening of the recess faces the gate driving circuit.

12. The display panel according to any one of claims 1 to 6, characterized in that: The power signal line includes a first power sub-signal line and a second power sub-signal line, and the first power sub-signal line and the second power sub-signal line are arranged in sequence in a direction away from the clock signal line group; The first power sub-signal line has the recess, and the opening of the recess faces the gate drive circuit. The second power sub-signal line has at least one opposing recess, and the opposing recess and the recess are arranged relative to each other. The bending portion is also located in the area where the opposing recess is located in the thickness direction of the display panel.

13. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 12.

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