Display substrate and display device

Abstract

The present invention provides a display substrate and a display device, which relate to the field of display technology and are for improving the transmittance of OLED display devices. The display substrate comprises: a substrate and a plurality of sub-pixels arranged on the substrate; the sub-pixels comprise: a reset signal line, an initialization signal line and a first transistor, at least a portion of the reset signal line extends along a first direction; at least a portion of the initialization signal line extends along the first direction; the gate of the first transistor is coupled to the reset signal line, the first electrode of the first transistor is coupled to the initialization signal line, and the orthographic projection of at least a portion of the first electrode of the first transistor on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate. The display substrate provided by the present invention is used for display.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display devices are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high clarity, good flexibility and high luminous efficiency.

[0003] When OLED display devices are applied to under-screen sensor products that have requirements for transmittance, if the transmittance of the OLED display devices does not meet the requirements, it may cause poor functionality of the sensor products. Summary of the invention

[0004] The object of the present invention is to provide a display substrate and a display device for improving the transmittance of an OLED display device.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on the substrate; the sub-pixels include:

[0007] a reset signal line, at least a portion of which extends along a first direction;

[0008] an initialization signal line, at least a portion of which extends along the first direction;

[0009] A first transistor, wherein a gate of the first transistor is coupled to the reset signal line, a first electrode of the first transistor is coupled to the initialization signal line, and an orthographic projection of at least part of the first electrode of the first transistor on the substrate is located between an orthographic projection of the reset signal line on the substrate and an orthographic projection of the initialization signal line on the substrate.

[0010] Optionally, the sub-pixel also includes a conductive connection portion, which is respectively coupled to the first electrode of the first transistor and the initialization signal line, and the orthographic projection of the conductive connection portion on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate; along the second direction, the length of the conductive connection portion is less than the distance between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate.

[0011] Optionally, an orthographic projection of the conductive connection portion on the substrate does not overlap with an orthographic projection of the reset signal line on the substrate.

[0012] Optionally, an orthographic projection of the first electrode of the first transistor on the substrate partially overlaps with an orthographic projection of the initialization signal line on the substrate.

[0013] Optionally, the initialization signal line includes a main body and a protruding portion, the main body extends along the first direction, and an orthographic projection of the protruding portion on the substrate at least partially overlaps with an orthographic projection of the first electrode of the first transistor on the substrate.

[0014] Optionally, the sub-pixel further includes a gate line, at least a portion of the gate line extends along the first direction;

[0015] The orthographic projection of the initialization signal line on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the gate line on the substrate.

[0016] Optionally, the sub-pixel further includes a second transistor, a gate of the second transistor is coupled to the gate line, a first electrode of the second transistor is coupled to a second electrode of the driving transistor, and a second electrode of the second transistor is coupled to the gate of the driving transistor.

[0017] Optionally, an orthographic projection of the initialization signal line on the substrate at least partially overlaps with an orthographic projection of the gate of the second transistor on the substrate.

[0018] Optionally, the second transistor includes a second active pattern, the second active pattern includes a conductor portion and two semiconductor portions, and the conductor portion is coupled to the two semiconductor portions respectively;

[0019] The sub-pixel further includes a shielding pattern coupled to the initialization signal line, and an orthographic projection of the shielding pattern on the substrate at least partially overlaps with an orthographic projection of the conductor portion on the substrate.

[0020] Optionally, the shielding pattern and the initialization signal line form an integrated structure.

[0021] Optionally, the shielding pattern includes a first sub-pattern and a second sub-pattern, the first sub-pattern extends along a second direction, the second direction intersects with the first direction, the second sub-pattern extends along the first direction, and the orthographic projection of the second sub-pattern on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate.

[0022] Optionally, the sub-pixel further includes a light-emitting element and a seventh transistor, a gate of the seventh transistor is coupled to a reset signal line in a next sub-pixel adjacent along the second direction, a first electrode of the seventh transistor is coupled to an initialization signal line in a next sub-pixel adjacent along the second direction, a second electrode of the seventh transistor is coupled to the light-emitting element, and the second direction intersects with the first direction;

[0023] The positive projection of the first electrode of the seventh transistor on the substrate is located between the positive projection of the reset signal line in the next sub-pixel adjacent along the second direction on the substrate and the positive projection of the initialization signal line in the next sub-pixel adjacent along the second direction on the substrate.

[0024] Optionally, the first electrode of the seventh transistor forms an integrated structure with the first electrode of the first transistor in the next sub-pixel adjacent to the second direction.

[0025] Optionally, the sub-pixel further includes:

[0026] a light-emitting control signal line, at least a portion of which extends along a first direction;

[0027] a power line, at least a portion of which extends along a second direction;

[0028] a data line, at least a portion of which extends along the second direction;

[0029] a fourth transistor, wherein a gate of the fourth transistor is coupled to the gate line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0030] a fifth transistor, wherein a gate of the fifth transistor is coupled to the light emitting control signal line, a first electrode of the fifth transistor is coupled to the power line, and a second electrode of the fifth transistor is coupled to the first electrode of the driving transistor;

[0031] a sixth transistor, wherein a gate of the sixth transistor is coupled to the light emitting control signal line, a first electrode of the sixth transistor is coupled to a second electrode of the driving transistor, and a second electrode of the sixth transistor is coupled to the light emitting element;

[0032] A storage capacitor, wherein the gate of the driving transistor is reused as a first plate of the storage capacitor, and a second plate of the storage capacitor is coupled to the power line.

[0033] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present invention provides a display device, comprising the above-mentioned display substrate.

[0034] In the technical solution provided by the present invention, by setting the orthographic projection of at least part of the first electrode of the first transistor T1 on the substrate, it is located between the orthographic projection of the reset signal line RST (N) on the substrate and the orthographic projection of the initialization signal line VINT (N) on the substrate, so that the distance between the initialization signal line and the first electrode of the first transistor in the sub-pixel to which it belongs, and the first electrode of the seventh transistor in the previous sub-pixel adjacent in the second direction are both close, so that when the initialization signal line and the first electrode of the first transistor in the sub-pixel to which it belongs are connected through the conductive connection part, and the initialization signal line and the first electrode of the seventh transistor in the previous sub-pixel adjacent in the second direction are connected through the conductive connection part, the size of the conductive connection part can be effectively reduced. Therefore, in the technical solution provided by the present invention, the shielding area of ​​the conductive connection part is reduced, so that the display substrate has good transmittance, and when the display substrate is applied to the under-screen sensing product with requirements for transmittance, the under-screen sensing product can be guaranteed to have good functionality. Moreover, in the technical solution provided by the present invention, by reducing the size of the conductive connection part, it is more conducive to avoiding crosstalk between the conductive connection part and other structures around it, and effectively improving the stability of the display substrate. In addition, by reducing the size of the conductive connection portion, the layout space occupied by the conductive connection portion is reduced, thereby better reducing the overall layout difficulty of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0036] Figure 1 A schematic diagram of the structure of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0037] Figure 2 for Figure 1 The working flow diagram of the neutron pixel driving circuit;

[0038] Figure 3 for Figure 1 A first layout flow chart of a neutron pixel driving circuit;

[0039] Figure 4 for Figure 1 A second layout flow chart of a neutron pixel driving circuit;

[0040] Figure 5 for Figure 1 and Figure 2 A schematic diagram of the layout of the active layer and the first gate metal layer;

[0041] Figure 6 for Figure 2 A schematic diagram of the layout of the active layer and the first source and drain metal layer;

[0042] Figure 7 for Figure 2 A schematic diagram of the layout of the second gate metal layer and the first source and drain metal layer;

[0043] Figure 8 for Figure 2 Schematic diagram of the layout of the active layer;

[0044] Fig. 9 for Figure 2 A schematic diagram of the layout of the first gate metal layer;

[0045] Fig.10 for Figure 2 A schematic diagram of the layout of the second gate metal layer;

[0046] Fig.11 for Figure 2 A schematic diagram of the layout of the first source and drain metal layer;

[0047] Fig.12 The schematic diagram is a layout diagram of four sub-pixel driving circuits distributed in an array. DETAILED DESCRIPTION

[0048] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, they are described in detail below with reference to the accompanying drawings.

[0049] See also Figure 1 , Figure 3 and Figure 5 The present invention provides a display substrate, which includes a substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0050] Each sub-pixel further includes an initialization signal line VINT(N), a reset signal line RST(N), a gate line GA, a light-emitting control signal line EM, a power line ELVDD, a data line DA, a first connection portion, a second connection portion, and a third connection portion. The initialization signal line VINT(N), the reset signal line RST(N), the gate line GA, and the light-emitting control signal line EM all extend at least partially along a first direction. The power line ELVDD and the data line DA all extend at least partially along a second direction, and the second direction intersects the first direction.

[0051] In the same sub-pixel, the orthographic projection of the initialization signal line VINT(N) on the substrate, the orthographic projection of the reset signal line RST(N) on the substrate, the orthographic projection of the gate line GA on the substrate, and the orthographic projection of the light-emitting control signal line EM on the substrate are arranged in sequence along the second direction.

[0052] The gate of the first transistor T1 is coupled to the reset signal line RST(N), the first electrode of the first transistor T1 is coupled to the initialization signal line VINT(N) through the third connection portion 403, and the second electrode of the first transistor T1 is coupled to the gate of the third transistor T3.

[0053] The gate of the second transistor T2 is coupled to the gate line GA, the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3 , and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3 through the first connecting portion 401 .

[0054] A gate of the fourth transistor T4 is coupled to the gate line GA, a first electrode of the fourth transistor T4 is coupled to the data line DA, and a second electrode of the fourth transistor T4 is coupled to a first electrode of the third transistor T3.

[0055] A gate of the fifth transistor T5 is coupled to the light emitting control signal line EM, a first electrode of the fifth transistor T5 is coupled to the power line ELVDD, and a second electrode of the fifth transistor T5 is coupled to a first electrode of the third transistor T3.

[0056] The gate of the sixth transistor T6 is coupled to the light emitting control signal line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel.

[0057] The gate of the seventh transistor T7 is coupled to the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction through the second connection portion 402, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0058] The gate of the third transistor T3 is multiplexed as the first plate of the storage capacitor, and the second plate of the storage capacitor is coupled to the power line ELVDD.

[0059] It should be noted that the second connection portion is reused as the third connection portion in the next sub-pixel adjacent along the second direction.

[0060] In the above-mentioned display substrate, since the distance between the first electrode of the first transistor T1 and the initialization signal line VINT(N) is relatively far, it is necessary to set the third connection portion 403 to extend along the second direction to be longer, resulting in a larger size of the third connection portion 403. This not only has a certain impact on the transmittance of the display substrate, which is not conducive to the working stability of the display substrate, but also increases the difficulty of layout of the display substrate.

[0061] See also Figure 4 and Figure 5 An embodiment of the present invention provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on the substrate; the sub-pixels include:

[0062] a reset signal line RST(N), at least a portion of which extends along a first direction;

[0063] an initialization signal line VINT(N), at least a portion of which extends along the first direction;

[0064] a first transistor T1, wherein a gate of the first transistor T1 is coupled to the reset signal line RST(N), a first electrode of the first transistor T1 is coupled to the initialization signal line VINT(N), and a second electrode of the first transistor T1 is coupled to a gate of a driving transistor (i.e., a third transistor T3); an orthographic projection of at least part of the first electrode of the first transistor T1 on the substrate is located between an orthographic projection of the reset signal line RST(N) on the substrate and an orthographic projection of the initialization signal line VINT(N) on the substrate;

[0065] Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0066] Exemplarily, the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source and drain metal layer and a planarization layer, which are stacked in sequence in a direction away from the base.

[0067] Exemplarily, the first gate metal layer includes the reset signal line RST(N) and the gate line GA, and the second gate metal layer includes the initialization signal line VINT(N).

[0068] Exemplarily, the sub-pixel includes a pixel driving circuit and a light-emitting element, wherein the pixel driving circuit is coupled to an anode of the light-emitting element to drive the light-emitting element to emit light. The plurality of pixel driving circuits included in the plurality of sub-pixels are distributed in an array on the substrate.

[0069] Exemplarily, the plurality of pixel driving circuits can be divided into a plurality of rows of pixel driving circuits and a plurality of columns of pixel driving circuits. The plurality of rows of pixel driving circuits are arranged along the second direction, and each row of pixel driving circuits includes a plurality of pixel driving circuits arranged along the first direction. The plurality of columns of pixel driving circuits are arranged along the first direction, and each column of pixel driving circuits includes a plurality of pixel driving circuits arranged along the second direction.

[0070] Exemplarily, the pixel driving circuit includes a driving transistor, a first transistor T1 and a seventh transistor T7, the first transistor T1 is used to reset the gate of the driving transistor, the first electrode of the first transistor T1 is coupled to the initialization signal line VINT(N), the seventh transistor T7 is used to reset the anode of the light-emitting element, and the first electrode of the seventh transistor T7 is coupled to the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction.

[0071] Exemplarily, in the same row of pixel driving circuits, the reset signal lines RST(N) coupled corresponding to each pixel driving circuit are coupled in sequence to form an integrated structure, the initialization signal lines VINT(N) coupled corresponding to each pixel driving circuit are coupled in sequence to form an integrated structure, and the gate lines GA coupled corresponding to each pixel driving circuit are coupled in sequence to form an integrated structure.

[0072] Exemplarily, when each sub-pixel further includes a light-emitting control signal line EM, a power line ELVDD, and a data line DA, in the same row of pixel driving circuits, the light-emitting control signal lines EM coupled to the corresponding pixel driving circuits are sequentially coupled to form an integrated structure. In the same column of pixel driving circuits, the power lines ELVDD coupled to the corresponding pixel driving circuits are sequentially coupled to form an integrated structure. In the same column of pixel driving circuits, the data lines DA coupled to the corresponding pixel driving circuits are sequentially coupled to form an integrated structure.

[0073] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, by setting the orthographic projection of at least part of the first electrode of the first transistor T1 on the substrate to be located between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the initialization signal line VINT(N) on the substrate, the distances between the first electrode of the initialization signal line VINT(N) and the first electrode of the first transistor T1 in the sub-pixel to which it belongs, and the first electrode of the seventh transistor T7 in the previous sub-pixel adjacent along the second direction are all close. In this way, when the initialization signal line VINT(N) and the first electrode of the first transistor T1 in the sub-pixel to which it belongs are connected through the conductive connection portion 404, and the initialization signal line VINT(N) and the first electrode of the seventh transistor T7 in the previous sub-pixel adjacent along the second direction are connected through the conductive connection portion 404, the size of the conductive connection portion 404 can be effectively reduced. Therefore, in the display substrate provided by the embodiment of the present invention, the shielding area of ​​the conductive connection part 404 is reduced, so that the display substrate has good transmittance. When the display substrate is applied to the under-screen sensing (sensor) product with requirements for transmittance, the functionality of the sensor product can be guaranteed to be good. Moreover, in the display substrate provided by the embodiment of the present invention, by reducing the size of the conductive connection part 404, it is more conducive to avoiding crosstalk between the conductive connection part 404 and other structures around it, and effectively improving the stability of the display substrate. In addition, by reducing the size of the conductive connection part 404, the layout space occupied by the conductive connection part 404 is reduced, thereby better reducing the overall layout difficulty of the display substrate.

[0074] like Figure 4 to Figure 7 As shown, in some embodiments, the sub-pixel also includes a conductive connection portion 404, which is respectively coupled to the first electrode of the first transistor T1 and the initialization signal line VINT(N), and the orthographic projection of the conductive connection portion on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate; along the second direction, the length of the conductive connection portion 404 is less than the distance between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the initialization signal line VINT(N) on the substrate.

[0075] Exemplarily, the conductive connection portion 404 , the power line ELVDD and the data line DA are all provided in the same layer and the same material.

[0076] Illustratively, the conductive connection portion 404 extends along the second direction.

[0077] Exemplarily, the length of the conductive connection portion 404 in the second direction is less than or equal to the maximum width of the initialization signal line VINT(N) in the second direction.

[0078] like Figure 4 to Figure 7 As shown, exemplarily, the orthographic projection of the first end of the conductive connection portion 404 on the substrate and the orthographic projection of the first electrode of the first transistor T1 on the substrate have a first overlapping area, and the first end of the conductive connection portion 404 is coupled to the first electrode of the first transistor T1 through a first via 801; the orthographic projection of the second end of the conductive connection portion 404 on the substrate respectively has a second overlapping area with the orthographic projection of the main body portion 61 on the substrate and the orthographic projection of the protrusion 60 on the substrate, and the second end of the conductive connection portion 404 is coupled to the main body portion 61 and the protrusion 60 through a second via 802.

[0079] Exemplarily, the first via hole penetrates the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; and the second via hole penetrates the interlayer insulating layer and the second gate insulating layer.

[0080] In the display substrate provided in the above embodiment, by setting the length of the conductive connection part 404 along the second direction to be smaller than the distance between the orthographic projection of the reset signal line RST (N) on the substrate and the orthographic projection of the initialization signal line VINT (N) on the substrate, the size of the conductive connection part 404 is effectively reduced. Therefore, in the display substrate provided in the above embodiment, the shielding area of ​​the conductive connection part 404 is reduced, so that the display substrate has good transmittance, and when the display substrate is applied to the under-screen sensing (sensor) product with requirements for transmittance, the functionality of the sensor product can be guaranteed. Moreover, in the display substrate provided in the embodiment of the present invention, by reducing the size of the conductive connection part 404, it is more conducive to avoiding crosstalk between the conductive connection part 404 and other structures around it, and effectively improving the stability of the operation of the display substrate. In addition, by reducing the size of the conductive connection part 404, the layout space occupied by the conductive connection part 404 is reduced, thereby better reducing the overall layout difficulty of the display substrate.

[0081] like Figure 4 to Figure 7 As shown, in some embodiments, the orthographic projection of the conductive connection portion 404 on the substrate is set to not overlap with the orthographic projection of the reset signal line RST(N) on the substrate.

[0082] The above configuration avoids the generation of overlapping capacitance between the conductive connection portion 404 and the reset signal line RST(N), helps to avoid crosstalk between the conductive connection portion 404 and the reset signal line RST(N), and effectively improves the working stability of the display substrate.

[0083] like Figures 4 to 8 , Fig.11 As shown, in some embodiments, the sub-pixel further includes: a driving transistor, the first transistor T1 and the second transistor T2;

[0084] A gate of the second transistor T2 is coupled to the gate line GA, a first electrode of the second transistor T2 is coupled to a second electrode of the driving transistor, and a second electrode of the second transistor T2 is coupled to a gate of the driving transistor.

[0085] Exemplarily, the reset signal line RST(N) is multiplexed as the gate of the first transistor T1.

[0086] Exemplarily, the first transistor T1 is a dual-gate structure, and the first transistor T1 includes a first active pattern 101, at least a portion of the first active pattern 101 is similar to an n-shaped structure, and the orthographic projection of the first active pattern 101 on the substrate and the orthographic projection of the reset signal line RST (N) on the substrate can form two independent overlapping areas.

[0087] Exemplarily, the first end of the first active pattern 101 serves as the first electrode of the first transistor T1 , and the second end of the second active pattern 102 serves as the second electrode of the first transistor T1 .

[0088] Exemplarily, the second transistor T2 is a dual-gate structure, and the second transistor T2 includes a second active pattern 102 , and the second active pattern 102 is a “┓”-shaped structure.

[0089] Exemplarily, the second transistor T2 is a compensation transistor, which is used to compensate for the threshold voltage of the driving transistor.

[0090] In the display substrate provided in the above embodiment, the orthographic projection of the first electrode of the first transistor T1 on the substrate is set between the orthographic projection of the reset signal line RST (N) on the substrate and the orthographic projection of the gate line GA on the substrate, so that the distance between the first electrode of the first transistor T1 and the initialization signal line VINT (N) is relatively close, so that when the initialization signal line VINT (N) is connected to the first electrode of the first transistor T1 in the sub-pixel to which it belongs through the conductive connection part 404, the size of the conductive connection part 404 can be effectively reduced, and the shielding area of ​​the conductive connection part 404 can be reduced. Therefore, the display substrate provided in the above embodiment has good transmittance, and when the display substrate is applied to an under-screen sensor product that has requirements for transmittance, the functionality of the sensor product can be guaranteed to be good.

[0091] like Figure 4 and Figure 5 As shown, in some embodiments, the orthographic projection of the first electrode of the first transistor T1 on the substrate is set to partially overlap with the orthographic projection of the initialization signal line VINT(N) on the substrate.

[0092] The above-mentioned setting method further reduces the distance between the first electrode of the first transistor T1 and the initialization signal line VINT(N). When the initialization signal line VINT(N) is connected to the first electrode of the first transistor T1 in the sub-pixel to which it belongs through the conductive connection part 404, the size of the conductive connection part 404 can be further reduced, thereby reducing the shielding area of ​​the conductive connection part 404.

[0093] like Figure 4 , Figure 5 and Fig.10 As shown, in some embodiments, the initialization signal line VINT(N) is set to include a main body 61 and a protrusion 60, the main body 61 extends along the first direction, and the positive projection of the protrusion 60 on the substrate at least partially overlaps with the positive projection of the first electrode of the first transistor T1 on the substrate.

[0094] Exemplarily, the main body 61 and the protrusion 60 are formed as an integral structure.

[0095] Exemplarily, the orthographic projection of the protrusion 60 on the substrate is located between the orthographic projection of the main body 61 on the substrate and the orthographic projection of the reset signal line RST(N) on the substrate.

[0096] Exemplarily, an orthographic projection of the main body 61 on the substrate at least partially overlaps with an orthographic projection of the first electrode of the first transistor T1 on the substrate.

[0097] In the display substrate provided in the above embodiment, the orthographic projection of the protrusion 60 on the substrate is set to at least partially overlap with the orthographic projection of the first electrode of the first transistor T1 on the substrate, thereby reducing the distance between the first electrode of the first transistor T1 and the initialization signal line VINT(N). When the initialization signal line VINT(N) is connected to the first electrode of the first transistor T1 in the sub-pixel to which it belongs through the conductive connection part 404, the size of the conductive connection part 404 can be effectively reduced, thereby reducing the shielding area of ​​the conductive connection part 404.

[0098] Moreover, the above configuration also avoids a large overlapping area between the first electrode of the first transistor T1 and the initialization signal line VINT(N), thereby avoiding a large parasitic capacitance between the first electrode of the first transistor T1 and the initialization signal line VINT(N), thereby affecting the working stability of the display substrate.

[0099] like Figure 4 , Figure 5 and Fig. 9 As shown, in some embodiments, the sub-pixel further includes: a gate line GA, at least a portion of which extends along the first direction; an orthographic projection of the initialization signal line VINT(N) on the substrate, located between an orthographic projection of the reset signal line RST(N) on the substrate and an orthographic projection of the gate line GA on the substrate.

[0100] In the display substrate provided in the above embodiment, the orthographic projection of the first electrode of the first transistor T1 on the substrate is set to be located between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the gate line GA on the substrate; and the orthographic projection of the initialization signal line VINT(N) on the substrate is set to be located between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the gate line GA on the substrate; so that the distance between the first electrode of the first transistor T1 and the initialization signal line VINT(N) is closer, so that when the initialization signal line VINT(N) is connected to the first electrode of the first transistor T1 in the sub-pixel to which it belongs through the conductive connecting portion 404, the size of the conductive connecting portion 404 can be effectively reduced.

[0101] like Figure 4 , Figure 5 , Fig. 9 and Fig.10 As shown, in some embodiments, the orthographic projection of the initialization signal line VINT(N) on the substrate at least partially overlaps with the orthographic projection of the gate 202g of the second transistor T2 on the substrate.

[0102] Exemplarily, an orthographic projection of the main body 61 on the substrate is arranged to at least partially overlap with an orthographic projection of the gate 202g of the second transistor T2 on the substrate.

[0103] The above-mentioned configuration makes the main body 61 closer to the second electrode of the second transistor T2, which is beneficial to the stability of the second electrode of the second transistor T2. The second electrode of the second transistor T2 is coupled to the gate of the driving transistor, so that the potential of the gate of the driving transistor is not easily affected by external crosstalk.

[0104] like Figure 4 , Figure 5 , Figure 7 , Figure 8 and Fig.10 As shown, in some embodiments, the second transistor T2 includes a second active pattern 102, the second active pattern 102 includes a conductor portion 1021 and two semiconductor portions 1022, the conductor portion 1021 is coupled to the two semiconductor portions 1022 respectively;

[0105] The sub-pixel further includes a shielding pattern 62 , which is coupled to the initialization signal line VINT(N). The orthographic projection of the shielding pattern 62 on the substrate at least partially overlaps with the orthographic projection of the conductor portion 1021 on the substrate.

[0106] Exemplarily, the second active pattern 102 includes a conductor portion 1021 and two semiconductor portions 1022, the conductor portion 1021 has a better conductivity than the two semiconductor portions 1022, and the orthographic projections of the two semiconductor portions 1022 on the substrate are located inside the orthographic projection of the gate of the second transistor T2 on the substrate.

[0107] Exemplarily, an initialization signal with a fixed potential is transmitted on the initialization signal line VINT(N), and the shielding pattern 62 is coupled to the initialization signal line VINT(N), so that the shielding pattern 62 has a fixed potential.

[0108] In the display substrate provided by the above embodiment, the shielding pattern 62 is arranged to have an orthographic projection on the substrate that at least partially overlaps with the orthographic projection of the conductor portion 1021 on the substrate, so that the shielding pattern 62 has a good shielding effect on the conductor portion 1021, thereby preventing the data signal jump on the data line DA in the adjacent sub-pixels along the first direction from affecting the conductor portion 1021, thereby ensuring the stability of the operation of the second transistor T2 and the driving transistor coupled thereto.

[0109] In addition, by setting the shielding pattern 62 to be coupled with the initialization signal line VINT(N), the size of the shielding pattern 62 is effectively reduced, the shielding area of ​​the shielding pattern 62 is reduced, and the display substrate has good transmittance. When the display substrate is applied to an under-screen sensing (sensor) product that has requirements for transmittance, the functionality of the sensor product can be guaranteed to be good. Moreover, in the display substrate provided in the above embodiment, by reducing the size of the shielding pattern 62, it is more conducive to avoiding the generation of parasitic capacitance between the shielding pattern 62 and other structures around it, and effectively improving the working stability of the display substrate. In addition, by reducing the size of the shielding pattern 62, the layout space occupied by the shielding pattern 62 is reduced, thereby better reducing the overall layout difficulty of the display substrate.

[0110] In some embodiments, the shielding pattern 62 and the initialization signal line VINT(N) are configured to form an integrated structure.

[0111] The above configuration enables the shielding pattern 62 and the initialization signal line VINT(N) to be formed in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and saving the manufacturing cost of the display substrate.

[0112] like Figure 4 , Figure 5 , Figure 7 , Figure 8 and Fig.10 As shown, in some embodiments, the shielding pattern 62 includes a first sub-pattern 620 and a second sub-pattern 621, the first sub-pattern 620 extends along a second direction, the second direction intersects with the first direction, the second sub-pattern 621 extends along the first direction, and the orthographic projection of the second sub-pattern 621 on the substrate at least partially overlaps with the orthographic projection of the conductor portion 1021 on the substrate.

[0113] Exemplarily, the first sub-graph 620 and the second sub-graph 621 are formed as an integral structure.

[0114] Exemplarily, the shielding pattern 62 is formed into an L-shaped structure.

[0115] Exemplarily, the width of the first sub-pattern 620 in the direction perpendicular to its own extension direction is smaller than the width of the second sub-pattern 621 in the direction perpendicular to its own extension direction.

[0116] In the display substrate provided in the above embodiment, by setting the shielding pattern 62 to include the first sub-pattern 620 and the second sub-pattern 621, the shielding pattern 62 occupies a smaller layout space while playing a good shielding role, which is beneficial to improving the resolution of the display substrate.

[0117] like Figure 5 and Fig.12 As shown, in some embodiments, the sub-pixel further includes a light-emitting element and a seventh transistor T7, the gate of the seventh transistor T7 is coupled to a reset signal line RST(N+1) in a next sub-pixel adjacent along the second direction, the first electrode of the seventh transistor T7 is coupled to an initialization signal line VINT(N+1) in a next sub-pixel adjacent along the second direction, the second electrode of the seventh transistor T7 is coupled to the light-emitting element, and the second direction intersects with the first direction;

[0118] The positive projection of the first electrode of the seventh transistor T7 on the substrate is located between the positive projection of the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction on the substrate and the positive projection of the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction on the substrate.

[0119] Exemplarily, the seventh transistor T7 is turned on under the control of the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction, coupling the anode of the light-emitting element with the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction, thereby resetting the anode of the light-emitting element.

[0120] Exemplarily, in the next adjacent sub-pixel along the second direction, the positive projection of the initialization signal line VINT(N+1) on the substrate is located between the positive projection of the reset signal line RST(N+1) on the substrate and the positive projection of the gate line GA on the substrate.

[0121] In the display substrate provided by the above embodiment, by setting the orthographic projection of the first electrode of the seventh transistor T7 on the substrate to be located between the orthographic projection of the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction on the substrate and the orthographic projection of the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction on the substrate, the distance between the first electrode of the seventh transistor T7 and the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction is closer, so that when the first electrode of the seventh transistor T7 and the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction are connected through the conductive connecting portion 404, the size of the conductive connecting portion 404 can be effectively reduced, and the shielding area of ​​the conductive connecting portion 404 can be reduced.

[0122] like Figure 5 and Fig.12 As shown, in some embodiments, the first electrode of the seventh transistor T7 is arranged to form an integral structure with the first electrode of the first transistor T1 in the next sub-pixel adjacent to the second direction.

[0123] The above configuration enables the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 in the next adjacent sub-pixel along the second direction to be connected to the initialization signal line VINT(N) through the same conductive connection portion 404, thereby further improving the transmittance of the array substrate.

[0124] like Figure 1 , Figure 4 and Fig.12 As shown, in some embodiments, the sub-pixel further includes:

[0125] a light emitting control signal line EM, at least a portion of which extends along a first direction;

[0126] a power line ELVDD, at least a portion of which extends along a second direction;

[0127] a data line DA, at least a portion of which extends along the second direction;

[0128] a fourth transistor T4, wherein a gate of the fourth transistor T4 is coupled to the gate line GA, a first electrode of the fourth transistor T4 is coupled to the data line DA, and a second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor;

[0129] a fifth transistor T5, wherein a gate of the fifth transistor T5 is coupled to the light emitting control signal line EM, a first electrode of the fifth transistor T5 is coupled to the power line ELVDD, and a second electrode of the fifth transistor T5 is coupled to the first electrode of the driving transistor;

[0130] a sixth transistor T6, wherein a gate of the sixth transistor T6 is coupled to the light emitting control signal line EM, a first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and a second electrode of the sixth transistor T6 is coupled to the light emitting element;

[0131] A storage capacitor, the gate of the driving transistor is reused as a first plate of the storage capacitor, and a second plate of the storage capacitor is coupled to the power line ELVDD.

[0132] like Figure 1 , Figure 4 and Fig.12 As shown, the sub-pixel includes a sub-pixel driving circuit distributed in an array. Taking one sub-pixel driving circuit as an example, the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor. Each transistor included in the sub-pixel driving circuit is a P-type transistor, the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode.

[0133] The first transistor T1 (i.e., the reset transistor) is a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the reset signal line RST(N), the source S1 of the first transistor T1 is coupled to the initialization signal line VINT(N) through the first via 801, the conductive connection portion 404, and the second via 802, and the drain D1 of the first transistor T1 is coupled to the drain D2 of the second transistor T2. The first via 801 penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer; the second via 802 penetrates the interlayer insulating layer.

[0134] The second transistor T2 is a dual-gate structure, the gate 202g of the second transistor T2 (i.e., the compensation transistor) is coupled to the gate line GA, the source S2 of the second transistor T2 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor), and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3 through the third via 803, the first connecting portion 401, and the fourth via 804. The third via 803 penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer; the fourth via 804 penetrates the second gate insulating layer and the interlayer insulating layer.

[0135] The gate 204g of the fourth transistor T4 (i.e., the data writing transistor) is coupled to the gate line GA, the source S4 of the fourth transistor T4 is coupled to the data line DA through the fifth via 805, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3. The fifth via 805 penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0136] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line EM, the source S5 of the fifth transistor T5 is coupled to the power line ELVDD through the sixth via 806, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3. The sixth via 806 penetrates the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.

[0137] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element EL through the seventh via hole 807, the fourth connecting portion 405, and the via hole penetrating the flat layer. The seventh via hole 807 penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0138] The gate 207g of the seventh transistor T7 is coupled to the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction, the drain D7 of the seventh transistor T7 is coupled to the drain D6 of the sixth transistor T6, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction through the eighth via 808.

[0139] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power line ELVDD through at least one ninth via 809. The ninth via 809 penetrates the interlayer insulating layer.

[0140] like Figure 2 As shown, when the sub-pixel driving circuit of the above structure is working, each working cycle includes a first reset period P1, a writing compensation period P2, a second reset period P3 and a light emitting period P4.

[0141] In the first reset period P1, the reset signal input by the reset signal line RST(N) is at a valid level, the first transistor T1 is turned on, and the initialization signal transmitted by the initialization signal line VINT(N) is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0142] During the write compensation period P2, the reset signal is at a non-valid level, the first transistor T1 is turned off, the gate scan signal input by the gate line GA is at a valid level, the second transistor T2 and the fourth transistor T4 are controlled to be turned on, the data line DA writes the data signal, and transmits it to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the second transistor T2 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage compensation of the third transistor T3 is achieved through the cooperation of the second transistor T2, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to finally reach Vdata+Vth, wherein Vdata represents the data signal voltage value, and Vth represents the threshold voltage of the third transistor T3.

[0143] In the second reset period P3, the gate scan signal is at a non-valid level, the second transistor T2 and the fourth transistor T4 are both turned off, the reset signal input by the reset signal line RST(N+1) is at a valid level, the seventh transistor T7 is controlled to be turned on, and the initialization signal transmitted by the initialization signal line graph VINT(N+1) is input to the anode of the light-emitting element EL, controlling the light-emitting element EL not to emit light.

[0144] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line graphic EM is at a valid level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power line is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, wherein VDD is the voltage value corresponding to the power signal, and the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0145] When manufacturing the above sub-pixels, the layout of each film layer corresponding to the sub-pixels is as follows:

[0146] The active layer, the first gate insulating layer, the first gate metal layer, the second gate insulating layer, the second gate metal layer, the interlayer insulating layer, the first source-drain metal layer, the first flat layer, the second source-drain metal layer, the second flat layer, the anode layer, the organic light-emitting functional layer and the cathode layer are sequentially stacked in a direction away from the substrate. The cathode is connected to a negative power supply signal ELVSS.

[0147] like Figure 1 , Figure 4 and Figure 5As shown, in the display substrate provided by the present disclosure, in the second direction, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are two sides opposite to each other along the second direction, and further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor. The lower side, for example, the side of the display substrate used for binding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor that is closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor that is farther away from the IC.

[0148] In the first direction, the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 202g of the second transistor T2 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. Exemplarily, the third side and the fourth side of the gate of the driving transistor are two sides opposite to each other along the first direction; further, the third side of the gate of the driving transistor may be the left side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor may be the right side of the gate of the driving transistor.

[0149] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0150] In the display substrate provided in the above embodiment, by setting the positive projection of the initialization signal line on the substrate, it is located between the positive projection of the reset signal line on the substrate and the positive projection of the gate line on the substrate, so that the distance between the initialization signal line and the first electrode of the first transistor in the sub-pixel to which it belongs, and the first electrode of the seventh transistor in the previous sub-pixel adjacent along the second direction are both close, so that when the initialization signal line is connected to the first electrode of the first transistor in the sub-pixel to which it belongs through the conductive connection part 404, and the initialization signal line is connected to the first electrode of the seventh transistor in the previous sub-pixel adjacent along the second direction through the conductive connection part 404, the size of the conductive connection part 404 can be effectively reduced, and the shielding area of ​​the conductive connection part 404 can be reduced. Therefore, the display substrate provided in the above embodiment has good transmittance, and when the display substrate is applied to an under-screen sensor product that has requirements for transmittance, the functionality of the sensor product can be guaranteed to be good.

[0151] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0152] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0153] The embodiment of the present invention further provides a method for manufacturing a display substrate, the manufacturing method comprising: manufacturing a plurality of sub-pixels on a substrate, the steps of manufacturing each sub-pixel specifically comprising:

[0154] Making a reset signal line, wherein at least a portion of the reset signal line extends along a first direction;

[0155] manufacturing an initialization signal line, wherein at least a portion of the initialization signal line extends along the first direction;

[0156] A first transistor is manufactured, wherein a gate of the first transistor is coupled to the reset signal line, a first electrode of the first transistor is coupled to the initialization signal line, and an orthographic projection of at least part of the first electrode of the first transistor on the substrate is located between an orthographic projection of the reset signal line on the substrate and an orthographic projection of the initialization signal line on the substrate.

[0157] In the display substrate manufactured by the manufacturing method provided by the embodiment of the present invention, by setting the orthographic projection of at least part of the first electrode of the first transistor T1 on the substrate to be located between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the initialization signal line VINT(N) on the substrate, the distance between the first electrode of the initialization signal line VINT(N) and the first electrode of the first transistor T1 in the sub-pixel to which it belongs, and the first electrode of the seventh transistor T7 in the previous sub-pixel adjacent along the second direction are all close. In this way, when the initialization signal line VINT(N) and the first electrode of the first transistor T1 in the sub-pixel to which it belongs are connected through the conductive connection part 404, and the initialization signal line VINT(N) and the first electrode of the seventh transistor T7 in the previous sub-pixel adjacent along the second direction are connected through the conductive connection part 404, the size of the conductive connection part 404 can be effectively reduced. Therefore, in the display substrate manufactured by the manufacturing method provided by the embodiment of the present invention, the shielding area of ​​the conductive connection part 404 is reduced, so that the display substrate has good transmittance. When the display substrate is applied to the under-screen sensing (sensor) product with requirements for transmittance, the functionality of the sensor product can be guaranteed to be good. Moreover, in the display substrate manufactured by the manufacturing method provided by the embodiment of the present invention, by reducing the size of the conductive connection part 404, it is more conducive to avoiding crosstalk between the conductive connection part 404 and other structures around it, and effectively improving the working stability of the display substrate. In addition, by reducing the size of the conductive connection part 404, the layout space occupied by the conductive connection part 404 is reduced, thereby better reducing the overall layout difficulty of the display substrate.

[0158] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0159] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0160] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0161] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0162] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixel comprises: a reset signal line, at least a portion of which extends along a first direction; an initialization signal line, at least a portion of which extends along the first direction; A first transistor, wherein a gate of the first transistor is coupled to the reset signal line, a first electrode of the first transistor is coupled to the initialization signal line, and an orthographic projection of at least part of the first electrode of the first transistor on the substrate is located between an orthographic projection of the reset signal line on the substrate and an orthographic projection of the initialization signal line on the substrate.

2. The display substrate according to claim 1, characterized in that: The sub-pixel further includes a conductive connection portion, the conductive connection portion is coupled to the first electrode of the first transistor and the initialization signal line respectively, and the orthographic projection of the conductive connection portion on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate; Along the second direction, the length of the conductive connection portion is smaller than the distance between an orthographic projection of the reset signal line on the substrate and an orthographic projection of the initialization signal line on the substrate.

3. The display substrate according to claim 2, characterized in that: An orthographic projection of the conductive connection portion on the substrate does not overlap with an orthographic projection of the reset signal line on the substrate.

4. The display substrate according to claim 2, characterized in that: An orthographic projection of the first electrode of the first transistor on the substrate partially overlaps with an orthographic projection of the initialization signal line on the substrate.

5. The display substrate according to claim 4, characterized in that: The initialization signal line includes a main portion and a protruding portion, the main portion extends along the first direction, and an orthographic projection of the protruding portion on the substrate at least partially overlaps with an orthographic projection of the first electrode of the first transistor on the substrate.

6. The display substrate according to claim 1, characterized in that: The sub-pixel further includes a gate line, at least a portion of which extends along the first direction; The orthographic projection of the initialization signal line on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the gate line on the substrate.

7. The display substrate according to claim 6, characterized in that: The sub-pixel further includes a second transistor, a gate of the second transistor is coupled to the gate line, a first electrode of the second transistor is coupled to a second electrode of the driving transistor, and a second electrode of the second transistor is coupled to the gate of the driving transistor.

8. The display substrate according to claim 6, characterized in that: An orthographic projection of the initialization signal line on the substrate at least partially overlaps with an orthographic projection of the gate of the second transistor on the substrate.

9. The display substrate according to claim 7, characterized in that: The second transistor includes a second active pattern, the second active pattern includes a conductor portion and two semiconductor portions, the conductor portion is coupled to the two semiconductor portions respectively; The sub-pixel further includes a shielding pattern coupled to the initialization signal line, and an orthographic projection of the shielding pattern on the substrate at least partially overlaps with an orthographic projection of the conductor portion on the substrate.

10. The display substrate according to claim 9, characterized in that: The shielding pattern and the initialization signal line are formed into an integral structure.

11. The display substrate according to claim 9, characterized in that: The shielding pattern includes a first sub-pattern and a second sub-pattern, the first sub-pattern extends along a second direction, the second direction intersects with the first direction, the second sub-pattern extends along the first direction, and the orthographic projection of the second sub-pattern on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate.

12. The display substrate according to claim 7, characterized in that: The sub-pixel further includes a light-emitting element and a seventh transistor, a gate of the seventh transistor is coupled to a reset signal line in a next sub-pixel adjacent along a second direction, a first electrode of the seventh transistor is coupled to an initialization signal line in a next sub-pixel adjacent along the second direction, a second electrode of the seventh transistor is coupled to the light-emitting element, and the second direction intersects the first direction; The positive projection of the first electrode of the seventh transistor on the substrate is located between the positive projection of the reset signal line in the next sub-pixel adjacent along the second direction on the substrate and the positive projection of the initialization signal line in the next sub-pixel adjacent along the second direction on the substrate.

13. The display substrate according to claim 12, characterized in that: The first electrode of the seventh transistor forms an integrated structure with the first electrode of the first transistor in the next sub-pixel adjacent to the second direction.

14. The display substrate according to claim 12, characterized in that: The sub-pixel further includes: a light-emitting control signal line, at least a portion of which extends along a first direction; a power line, at least a portion of which extends along a second direction; a data line, at least a portion of which extends along the second direction; a fourth transistor, wherein a gate of the fourth transistor is coupled to the gate line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; a fifth transistor, wherein a gate of the fifth transistor is coupled to the light emitting control signal line, a first electrode of the fifth transistor is coupled to the power line, and a second electrode of the fifth transistor is coupled to the first electrode of the driving transistor; a sixth transistor, wherein a gate of the sixth transistor is coupled to the light emitting control signal line, a first electrode of the sixth transistor is coupled to a second electrode of the driving transistor, and a second electrode of the sixth transistor is coupled to the light emitting element; A storage capacitor, wherein the gate of the driving transistor is reused as a first plate of the storage capacitor, and a second plate of the storage capacitor is coupled to the power line.

15. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 14.

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