Pixel driving circuit and display panel

Abstract

The invention relates to a pixel driving circuit and a display panel, and the pixel driving circuit comprises a plurality of pixel units which are arranged in an array; the plurality of scanning lines extend along the row direction, and the scanning lines are alternately inserted between two rows of pixel units; the at least one pin line is electrically connected with the plurality of scanning lines; a plurality of signal lines extending in a column direction; the grid electrode of each transistor is electrically connected with one signal line, the first end of each transistor is electrically connected with one scanning line, the second end of each transistor is electrically connected with one signal line or one pin line, and the number of the transistors connected with the pin lines is equal to the number of the scanning lines. The structure that one pin line controls three scanning lines is adopted, the conventional design that the pin lines and the scanning lines are controlled in a one-to-one mode is broken, the number of the pin lines is effectively reduced, use of an integrated circuit is reduced, the overall manufacturing cost is reduced, the occupied area of a non-display area is reduced, the requirement of consumers for a narrow frame is met, the wiring difficulty is reduced, and the production efficiency is improved. The working efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of drive circuits, and in particular to a pixel drive circuit and a display panel. Background Art

[0002] The drive signal wiring of the display panel is arranged in the non-display area of ​​the display panel, which is also the location of the border of the display panel. As the pixel units increase, the drive signal wiring also increases. The increase of the drive signal wiring will lead to an increase in the area occupied by the non-display area, and then lead to an increase in the width of the border of the display panel, which is not conducive to improving the screen-to-body ratio. In addition, the increase of the drive signal wiring brings difficulties to the layout of the electrical connection between the drive signal wiring and the display driver chip.

[0003] Existing display screens have developed in a diversified manner. Consumers have increasingly higher requirements for narrow borders, and display panels must be compatible with high resolutions. Therefore, the demand for the number of ICs (integrated circuits) has also increased, which in turn has led to an increase in overall costs.

[0004] Therefore, it is necessary to provide a pixel driving circuit and a display panel that can reduce the use of integrated circuits, lower costs, and meet the requirements of narrow bezels. Summary of the invention

[0005] In order to overcome the deficiencies of the prior art, the present invention provides a pixel driving circuit and a display panel.

[0006] The technical solution of the present invention is as follows:

[0007] A pixel driving circuit, comprising:

[0008] A plurality of pixel units, wherein the plurality of pixel units are arranged in an array;

[0009] A plurality of scanning lines, wherein the plurality of scanning lines extend along a row direction and are alternately interspersed between two rows of pixel units;

[0010] at least one pin line, the pin line being electrically connected to the plurality of scan lines;

[0011] A plurality of signal lines, wherein the plurality of signal lines extend along a column direction;

[0012] A plurality of transistors, wherein the gate of each transistor is electrically connected to a signal line, the first end of each transistor is electrically connected to a scan line, the second end of each transistor is electrically connected to a signal line or a pin line, and the number of transistors connected to the pin lines is equal to the number of scan lines.

[0013] As a further improvement of the present invention, one of the pin lines is electrically connected to the three scan lines, and when one of the scan lines outputs a high level, the other two scan lines maintain a low level.

[0014] As a further improvement of the present invention, eight transistors are arranged between the three scan lines and the pin lines, the three scan lines are respectively a first scan line, a second scan line, and a third scan line, the eight transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, there are four signal lines, the four signal lines are respectively a first signal line, a second signal line, a third signal line, and a fourth signal line, the first end of the first transistor is electrically connected to the first scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the first signal line; the first end of the second transistor is electrically connected to the first scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the second signal line; the first end of the third transistor is electrically connected The first scan line and the second end are electrically connected to the first signal line, and the gate is electrically connected to the third signal line; the first end of the fourth transistor is electrically connected to the second scan line, the second end is electrically connected to the second signal line, and the gate is electrically connected to the first signal line; the first end of the fifth transistor is electrically connected to the second scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the second signal line; the first end of the sixth transistor is electrically connected to the second scan line, the second end is electrically connected to the first signal line, and the gate is electrically connected to the third signal line; the first end of the seventh transistor is electrically connected to the third scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the third signal line; the first end of the eighth transistor is electrically connected to the third scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the fourth signal line.

[0015] As a further improvement of the present invention, the cycle period of the output signals of the four signal lines is a first cycle period, the first cycle period is 3T, and the first cycle period is divided into three intervals, including a first interval, a second interval, and a third interval.

[0016] As a further improvement of the present invention, in the first interval, the first signal line is at a high level, the second signal line is at a low level, the third signal line is at a low level, and the fourth signal line is at a high level; in the second interval, the first signal line is at a low level, the second signal line is at a high level, the third signal line is at a low level, and the fourth signal line is at a high level; in the third interval, the first signal line is at a low level, the second signal line is at a low level, the third signal line is at a high level, and the fourth signal line is at a low level.

[0017] As a further improvement of the present invention, the cycle period of the output signal of the pin line is a second cycle period, the second cycle period covers at least two of the first cycle periods, the second cycle period is n times the first cycle period, n is an integer, and at least three consecutive intervals in the second cycle period output a high level.

[0018] As a further improvement of the present invention, the number of the pin lines is m, n≥m.

[0019] As a further improvement of the present invention, the output signals of two adjacent pin lines differ by one of the first cycle periods.

[0020] As a further improvement of the present invention, there are two pin lines, the second cycle period is equal to two of the first cycle periods, the second cycle period is 6T and is divided into six intervals, three consecutive intervals in the second cycle period output the same level, and the other three intervals output another level.

[0021] A display panel comprises a display driving chip and the above-mentioned pixel driving circuit.

[0022] According to the present invention of the above scheme, the beneficial effects of the present invention are:

[0023] The present invention provides a pixel driving circuit and a display panel, which adopt a structure in which one pin line controls three scan lines, breaking the conventional design of one-to-one control of the pin line and the scan line, and can effectively reduce the number of pin lines, thereby reducing the use of integrated circuits, which can not only reduce the overall manufacturing cost, but also reduce the occupied area of ​​the non-display area, promote narrow frame design, meet consumers' demand for narrow frame, reduce wiring difficulty, and improve work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of a pixel driving circuit of the present invention;

[0025] Figure 2 It is a timing diagram of the pixel driving circuit of the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] See also Figure 1 The present invention provides a pixel driving circuit, comprising:

[0030] A plurality of pixel units are arranged in an array, and the AA area is a pixel module composed of the plurality of pixel units;

[0031] Multiple scan lines, multiple scan lines extend along the row direction, all scan lines pass through the pixel module, and the scan lines are alternately interspersed between two rows of pixel units, each scan line is electrically connected to a row of pixel units, and similarly, the arrangement positions of the scan lines can be appropriately adjusted according to specific usage requirements, such as the scan lines and the row pixel units are alternately arranged in pairs, that is, two scan lines, two rows of pixel units, two scan lines, two rows of pixel units are sequentially arranged along the column direction, and the arrangement continues in this way;

[0032] at least one pin line, one pin line electrically connected to a pin of the integrated circuit, and the pin line electrically connected to a plurality of scan lines;

[0033] A plurality of signal lines, wherein the plurality of signal lines extend along a column direction;

[0034] A plurality of transistors, each of which has a gate electrically connected to a signal line, that is, the transistor is controlled to be turned on and off by one of the signal lines, a first end of each transistor is electrically connected to a scan line, and a second end of each transistor is electrically connected to a signal line or a pin line, that is, when the transistor is turned on, a scan line can be turned on to a signal line or a scan line can be turned on to a pin line, so that the voltage level on the signal line or the pin line is transferred to the corresponding scan line, and the number of transistors connected to the pin lines is equal to the number of scan lines, so that a transistor is provided between each scan line and the pin line to control the on and off between the two, thereby ensuring the normal operation of the pixel driving circuit.

[0035] The present invention adopts a structure in which one pin line controls multiple scan lines, breaking the conventional design of one-to-one control of pin lines and scan lines, and can effectively reduce the number of pin lines, thereby reducing the use of integrated circuits, which can not only reduce the overall manufacturing cost, but also reduce the area occupied by the non-display area, promote narrow frame design, meet consumers' demand for narrow frame, reduce wiring difficulty, and improve work efficiency.

[0036] As an embodiment of the present invention, one pin line is electrically connected to three scan lines. For example, the pin line is pin1, and the three scan lines are the first scan line G1, the second scan line G2, and the third scan line G3. When one scan line outputs a high level, the other two scan lines maintain a low level; when the first scan line G1 outputs a high level, the second scan line G2 and the third scan line G3 maintain a low level; when the second scan line G2 outputs a high level, the first scan line G1 and the third scan line G3 maintain a low level; when the third scan line G3 outputs a high level, the first scan line G1 and the second scan line G2 maintain a low level. The design of controlling three scan lines with one pin line can save 2 / 3 of the pin line usage compared to the conventional one-to-one control structure. When the number of scan lines is huge and multiple integrated circuits are required, the present invention can save 2 / 3 of the number of integrated circuits, which can effectively reduce costs.

[0037] As an embodiment of the present invention, eight transistors are provided between three scan lines and the pin lines, and the eight transistors are respectively a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8. There are four signal lines, and the four signal lines are respectively a first signal line V1, a second signal line V2, a third signal line V3, and a fourth signal line V4. Through the mutual cooperation between the eight transistors and the four signal lines, it can be achieved that only one of the three scan lines is at a high level at the same time, and the other two scan lines maintain a low level.

[0038] As an embodiment of the present invention, the first end of the first transistor Q1 is electrically connected to the first scan line G1, the second end is electrically connected to the pin line, and the gate is electrically connected to the first signal line V1; the first end of the second transistor Q2 is electrically connected to the first scan line G1, the second end is electrically connected to the third signal line V3, and the gate is electrically connected to the second signal line V2; the first end of the third transistor Q3 is electrically connected to the first scan line G1, the second end is electrically connected to the first signal line V1, and the gate is electrically connected to the third signal line V3; the first end of the fourth transistor Q4 is electrically connected to the second scan line G2, the second end is electrically connected to the second signal line V2, and the gate is electrically connected to the first signal line V1; the first end of the fifth transistor Q5 is electrically connected to the second scan line G2, the second end is electrically connected to the pin line, and the gate is electrically connected to the second signal line V2; the first end of the sixth transistor Q6 is electrically connected to the second scan line G2, the second end is electrically connected to the first signal line V1, and the gate is electrically connected to the third signal line V3; the first end of the seventh transistor Q7 is electrically connected to the third scan line G3, the second end is electrically connected to the pin line, and the gate is electrically connected to the third signal line V3; the first end of the eighth transistor Q8 is electrically connected to the third scan line G3, the second end is electrically connected to the third signal line V3, and the gate is electrically connected to the fourth signal line V4, wherein the first transistor Q1 is controlled on and off by the first signal line V1 to achieve the on and off between the first scan line G1 and the pin line pin1, the fifth transistor Q5 is controlled on and off by the second signal line V2 to achieve the on and off between the second scan line G2 and the pin line pin1, the seventh transistor Q7 is controlled on and off by the third signal line V3 to achieve the on and off between the third scan line G3 and the pin line pin1, and the remaining transistors and the fourth signal line V4 are used to maintain the low level of the first scan line G1 or the second scan line G2 or the third scan line G3 to ensure the working stability of the pixel driving circuit.

[0039] See also Figure 2 As an embodiment of the present invention, the cycle period of the output signals of the four signal lines is the first cycle period, the first cycle period is 3T, and the first cycle period is divided into three intervals, including the first interval T1, the second interval T2, and the third interval T3; preferably, in the first interval T1, the first signal line V1 is high level, the second signal line V2 is low level, the third signal line V3 is low level, and the fourth signal line V4 is high level; in the second interval T2, the first signal line V1 is low level, the second signal line V2 is high level, the third signal line V3 is low level, and the fourth signal line V4 is high level; in the third interval T3, the first signal line V1 is low level, the second signal line V2 is low level, the third signal line V3 is high level, and the fourth signal line V4 is low level, and the pin line pin1 outputs the same level in a first cycle period;

[0040] When pin 1 outputs a high level,

[0041] In the first interval T1, the first signal line V1 is at a high level to turn on the first transistor Q1, so that the pin line pin1 is connected to the first scan line G1, so the first scan line G1 inputs a high level, and also turns on the fourth transistor Q4, so that the second scan line G2 is connected to the second signal line V2. Since the second signal line V2 is at a low level, the second scan line G2 inputs a low level. The second signal line V2 is at a low level and cannot turn on the second transistor Q2 and the fifth transistor Q5. The third signal line V3 is at a low level and cannot turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7. The fourth signal line V4 is at a high level to turn on the eighth transistor Q8, so that the third scan line G3 is connected to the third signal line V3. Since the third signal line V3 is at a low level, the third scan line G3 inputs a low level, that is, only the first scan line G1 inputs a high level, and the second scan line G2 and the third scan line G3 both maintain a low level.

[0042] In the second interval T2, the first signal line V1 is at a low level and cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is at a high level and turns on the second transistor Q2, so that the first scan line G1 is connected to the third signal line V3, and since the third signal line V3 is at a low level, the first scan line G1 inputs a low level, and also turns on the fifth transistor Q5, so that the second scan line G2 is connected to the pin line pin1, so the second scan line G2 inputs a high level, the third signal line V3 is at a low level and cannot turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7, the fourth signal line V4 is at a high level and turns on the eighth transistor Q8, so that the third scan line G3 is connected to the third signal line V3, and since the third signal line V3 is at a low level, the third scan line G3 inputs a low level, that is, only the second scan line G2 inputs a high level, and the first scan line G1 and the third scan line G3 both maintain a low level;

[0043] In the third interval T3, the first signal line V1 is at a low level and cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is at a low level and cannot turn on the second transistor Q2 and the fifth transistor Q5, the third signal line V3 is at a high level and turns on the third transistor Q3, so that the first scan line G1 is connected to the first signal line V1, and since the first signal line V1 is at a low level, the first scan line G1 inputs a low level, and at the same time turns on the sixth transistor Q6, so that the second scan line G2 is connected to the first signal line V1, and since the first signal line V1 is at a low level, the second scan line G2 inputs a low level, and at the same time turns on the seventh transistor Q7, so that the third scan line G3 is connected to the pin line pin1, so the third scan line G3 inputs a high level, and the fourth signal line V4 is at a low level and cannot turn on the eighth transistor Q8, that is, only the third scan line G3 inputs a high level, and the first scan line G1 and the second scan line G2 both maintain a low level;

[0044] When pin 1 outputs a low level,

[0045] In the first interval T1, the first signal line V1 is at a high level to turn on the first transistor Q1, so that the pin line pin1 is connected to the first scan line G1. Since the pin line pin1 is at a low level, the first scan line G1 inputs a low level, and the fourth transistor Q4 is also turned on, so that the second scan line G2 is connected to the second signal line V2. Since the second signal line V2 is at a low level, the second scan line G2 inputs a low level. The second signal line V2 is at a low level and cannot turn on the second transistor Q2 and the fifth transistor Q5. The third signal line V3 is at a low level and cannot turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7. The fourth signal line V4 is at a high level to turn on the eighth transistor Q8, so that the third scan line G3 is connected to the third signal line V3. Since the third signal line V3 is at a low level, the third scan line G3 inputs a low level, that is, the first scan line G1, the second scan line G2 and the third scan line G3 all maintain a low level.

[0046] In the second interval T2, the first signal line V1 is at a low level and cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is at a high level and turns on the second transistor Q2, so that the first scan line G1 is connected to the third signal line V3, and since the third signal line V3 is at a low level, the first scan line G1 inputs a low level, and also turns on the fifth transistor Q5, so that the second scan line G2 is connected to the pin line pin1, and since the pin line pin1 is at a low level, the second scan line G2 inputs a low level, the third signal line V3 is at a low level and cannot turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7, the fourth signal line V4 is at a high level and turns on the eighth transistor Q8, so that the third scan line G3 is connected to the third signal line V3, and since the third signal line V3 is at a low level, the third scan line G3 inputs a low level, that is, the first scan line G1, the second scan line G2 and the third scan line G3 all maintain a low level;

[0047] In the third interval T3, the first signal line V1 is at a low level and cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is at a low level and cannot turn on the second transistor Q2 and the fifth transistor Q5, the third signal line V3 is at a high level and turns on the third transistor Q3, so that the first scan line G1 is connected to the first signal line V1, and since the first signal line V1 is at a low level, the first scan line G1 inputs a low level, and at the same time turns on the sixth transistor Q6, so that the second scan line G2 is connected to the first signal line V1, and since the first signal line V1 is at a low level, the second scan line G2 inputs a low level, and at the same time turns on the seventh transistor Q7, so that the third scan line G3 is connected to the pin line pin1, and since the pin line pin1 is at a low level, the third scan line G3 inputs a low level, and the fourth signal line V4 is at a low level and cannot turn on the eighth transistor Q8, that is, the first scan line G1, the second scan line G2, and the third scan line G3 all maintain a low level;

[0048] Therefore, in the first interval T1 , the second interval T2 , and the third interval T3 , the first scan line G1 , the second scan line G2 , and the third scan line G3 all maintain a low level.

[0049] As an embodiment of the present invention, the cycle period of the output signal of the pin line is a second cycle period, the second cycle period covers at least two first cycle periods, and the duration of the second cycle period is n times that of the first cycle period, n is an integer, the number of pin lines is m, n≥m, and three consecutive intervals in the second cycle period output a high level, and the duration of the second cycle period can be adjusted according to specific usage requirements. Preferably, the second cycle period is equal to two first cycle periods, the second cycle period is 6T and is divided into six intervals, three consecutive intervals in the second cycle period output the same level, and the other three intervals output another level, that is, if three consecutive intervals output a high level, the other three intervals output a low level, and if three consecutive intervals output a low level, the other three intervals output a high level.

[0050] As an embodiment of the present invention, the output signals of two adjacent pin lines differ by a first cycle period, which can ensure that only one pin line is at a high level at the same time, and the rest of the pin lines are at low levels, that is, only one scan line outputs a high level at the same time. Similarly, the output signal difference between two adjacent pin lines can be adjusted according to specific usage requirements, but the difference between the two shall not be less than the first cycle period.

[0051] Working principle: If there are two pin lines, namely pin line pin1 and pin line pin2, the driving signal cycle period of the pin line is 6T, pin line pin1 corresponds to the first scan line G1, the second scan line G2, and the third scan line G3, and pin line pin2 corresponds to the fourth scan line G4, the fifth scan line G5, and the sixth scan line G6. In the period T1-T3, pin line pin1 outputs a high level and pin line pin2 outputs a low level. In the period T4-T6, pin line pin1 outputs a low level and pin line pin2 outputs a high level.

[0052] If there are three pin lines, namely pin line pin1, pin line pin2 and pin line pin3, the driving signal cycle period of the pin lines is 9T, pin line pin1 corresponds to the first scan line G1, the second scan line G2, and the third scan line G3, pin line pin2 corresponds to the fourth scan line G4, the fifth scan line G5, and the sixth scan line G6, pin line pin3 corresponds to the seventh scan line G7, the eighth scan line G8, and the ninth scan line G9, within the period T1-T3, pin line pin1 outputs a high level, pin line pin2 outputs a low level, and pin line pin3 outputs a low level, within the period T4-T6, pin line pin1 outputs a low level, pin line pin2 outputs a high level, and pin line pin3 outputs a low level, within the period T7-T9, pin line pin1 outputs a low level, pin line pin2 outputs a low level, and pin line pin3 outputs a high level;

[0053] If the number of pin lines continues to increase, we can conclude by reasoning according to the above logic: if there are m pin lines, the three scan lines corresponding to the pin line pin(m) are G(3m-2), G(3m-1), and G(3m), that is, in the period T(3m-2)-T(3m), the pin line pin(m) outputs a high level, and the other pin lines all output a low level.

[0054] The present invention provides a display panel, including a display driver chip and the above-mentioned pixel driver circuit, which can reduce the use of integrated circuits and does not require additional masks. It can not only reduce the overall manufacturing cost, but also reduce the occupied area of ​​the non-display area, promote narrow frame design, meet consumers' demand for narrow frame, reduce wiring difficulty, and improve work efficiency.

[0055] In summary, the present invention provides a pixel driving circuit and a display panel, which adopt a structure in which one pin line controls multiple scanning lines, breaking the conventional design of one-to-one control of pin lines and scanning lines, and can effectively reduce the number of pin lines, thereby reducing the use of integrated circuits, and does not require additional masks, which can not only reduce the overall manufacturing cost, but also reduce the occupied area of ​​the non-display area, promote narrow frame design, meet consumers' demand for narrow frame, and reduce wiring difficulty, and improve work efficiency; through the mutual cooperation between eight transistors and four signal lines, it can be achieved that only one of the three scanning lines is at a high level at the same time, and the other two scanning lines maintain a low level, thereby ensuring the working stability of the pixel driving circuit; the duration of the second cycle period is an integer multiple of the first cycle period, and a high level is output for three consecutive intervals in the second cycle period, and the duration of the second cycle period can be adjusted according to specific usage requirements, thereby improving the overall scope of application, and improving the overall reliability and compatibility.

[0056] It should be emphasized that the above are only preferred embodiments of the present invention and do not limit the present invention in any form. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: A plurality of pixel units, wherein the plurality of pixel units are arranged in an array; A plurality of scanning lines, wherein the plurality of scanning lines extend along a row direction and are alternately interspersed between two rows of pixel units; at least one pin line, the pin line being electrically connected to the plurality of scan lines; A plurality of signal lines, wherein the plurality of signal lines extend along a column direction; A plurality of transistors, wherein the gate of each transistor is electrically connected to a signal line, the first end of each transistor is electrically connected to a scan line, the second end of each transistor is electrically connected to a signal line or a pin line, and the number of transistors connected to the pin lines is equal to the number of scan lines.

2. The pixel driving circuit according to claim 1, characterized in that: One of the pin lines is electrically connected to the three scan lines, and when one of the scan lines outputs a high level, the other two scan lines maintain a low level.

3. The pixel driving circuit according to claim 2, characterized in that: Eight transistors are arranged between the three scan lines and the pin lines, the three scan lines are respectively a first scan line, a second scan line, and a third scan line, the eight transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, there are four signal lines, the four signal lines are respectively a first signal line, a second signal line, a third signal line, and a fourth signal line, the first end of the first transistor is electrically connected to the first scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the first signal line; the first end of the second transistor is electrically connected to the first scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the second signal line; the first end of the third transistor is electrically connected to the first scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the second signal line; line, the second end is electrically connected to the first signal line, and the gate is electrically connected to the third signal line; the first end of the fourth transistor is electrically connected to the second scan line, the second end is electrically connected to the second signal line, and the gate is electrically connected to the first signal line; the first end of the fifth transistor is electrically connected to the second scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the second signal line; the first end of the sixth transistor is electrically connected to the second scan line, the second end is electrically connected to the first signal line, and the gate is electrically connected to the third signal line; the first end of the seventh transistor is electrically connected to the third scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the third signal line; the first end of the eighth transistor is electrically connected to the third scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the fourth signal line.

4. The pixel driving circuit according to claim 3, characterized in that: The cycle period of the output signals of the four signal lines is a first cycle period, the first cycle period is 3T, and the first cycle period is divided into three intervals, including a first interval, a second interval, and a third interval.

5. The pixel driving circuit according to claim 4, characterized in that: In the first interval, the first signal line is at a high level, the second signal line is at a low level, the third signal line is at a low level, and the fourth signal line is at a high level; in the second interval, the first signal line is at a low level, the second signal line is at a high level, the third signal line is at a low level, and the fourth signal line is at a high level; in the third interval, the first signal line is at a low level, the second signal line is at a low level, the third signal line is at a high level, and the fourth signal line is at a low level.

6. The pixel driving circuit according to claim 5, characterized in that: The cycle period of the output signal of the pin line is the second cycle period, the second cycle period covers at least two of the first cycle periods, the second cycle period is n times the first cycle period, n is an integer, and a high level is output for three consecutive intervals within the second cycle period.

7. The pixel driving circuit according to claim 6, characterized in that: The number of the pin lines is m, n≥m.

8. The pixel driving circuit according to claim 7, characterized in that: The output signals of two adjacent pin lines differ by one first cycle period.

9. The pixel driving circuit according to claim 8, characterized in that: There are two pin lines, the second cycle period is equal to two of the first cycle periods, the second cycle period is 6T and is divided into six intervals, three consecutive intervals in the second cycle period output the same level, and the other three intervals output another level.

10. A display panel, characterized in that: It comprises a display driver chip and a pixel driver circuit as claimed in any one of claims 1 to 9.

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