Stacked field sequence pixel circuit and control method

Abstract

The invention discloses a stack-in type field sequence pixel circuit and a control method, the stack-in type field sequence pixel circuit comprises a plurality of sub-circuits and pixel electrodes, and the circuit structures of the plurality of sub-circuits are the same; the plurality of sub-circuits are coupled to the same end of the pixel electrode, and the other end of the pixel electrode is coupled to a common signal line; the plurality of sub-circuits are provided with pre-storage capacitors which are used for pre-storage of data signal voltage. The beneficial effects of the invention are that the method achieves the simultaneous stacking of a plurality of frames of data signals through the arrangement of a plurality of sub-circuits, thereby improving the time utilization rate.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, in particular to a stacked field sequential pixel circuit and a control method. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] Taking the conventional 1T2C display mode as an example, for a product with a resolution of 1920*1080, the gate signal opening cycle for each row is 2us, and all 1080 rows are turned on as one frame, which takes about 2ms. For a 60HZ product, the RGB subframes need to be refreshed at 180HZ to achieve the same smoothness. Each subframe takes about 1 / 180≈5.6ms, leaving about 3.6ms for the backlight to light up and display R, G, and B. Without considering the delay of the liquid crystal, or using ferroelectric or blue phase liquid crystal with ultra-fast response at the us level, the time utilization rate = 3.6 / 5.6≈64.3%. Considering the delay of the liquid crystal, 1ms time is provided for its reversal, and the time utilization rate = 2.6 / 5.6≈46.4%. Since the time utilization rate of the field sequential display affects the overall brightness, how to improve the time utilization rate of the backlight display is conducive to reducing costs and improving the brightness of the display screen.

[0004] Therefore, the present invention proposes a stacked field sequential pixel circuit and a control method to increase the backlight display time, thereby improving the time utilization rate and achieving the purpose of increasing brightness. Summary of the invention

[0005] The purpose of the present invention is to provide a stacked field sequential pixel circuit and a control method, so as to increase the bright light time and improve the time utilization rate.

[0006] The purpose of the present invention is to achieve a stacked field sequential pixel circuit through the following technical solution, comprising a plurality of sub-circuits and a pixel electrode, wherein the circuit structures of the plurality of sub-circuits are the same; each of the sub-circuits is used to write a data signal voltage of a corresponding frame; the plurality of sub-circuits are all coupled to the same end of the pixel electrode, and the other end of the pixel electrode is coupled to a common signal line; The plurality of sub-circuits are each provided with a pre-storage capacitor for pre-storing a data signal voltage.

[0007] The plurality of sub-circuits include a first sub-circuit, a second sub-circuit and a third sub-circuit; the first sub-circuit, the second sub-circuit and the third sub-circuit are used to receive and pre-store a first data signal voltage, a second data signal voltage and a third data signal voltage, respectively.

[0008] The first subcircuit includes a first transistor, a first pre-storage capacitor, and a second transistor; a first source and a drain of the first transistor of the first subcircuit are coupled to a first data signal line, a gate of the first transistor of the first subcircuit is coupled to a first row gate signal line, a second source and a drain of the first transistor of the first subcircuit is coupled to one end of the first pre-storage capacitor; and the other end of the first pre-storage capacitor is coupled to a common signal line; The first source and drain of the second transistor of the first sub-circuit are coupled to the second source and drain of the first transistor of the first sub-circuit, the gate of the second transistor of the first sub-circuit is coupled to the first transfer signal line, the second source and drain of the second transistor of the first sub-circuit is coupled to one end of the pixel electrode; the other end of the pixel electrode is coupled to the common signal line.

[0009] The second subcircuit includes a first transistor, a second pre-storage capacitor, and a second transistor; a first source and a drain of the first transistor of the second subcircuit is coupled to a second data signal line, a gate of the first transistor of the second subcircuit is coupled to a second row gate signal line, a second source and a drain of the first transistor of the second subcircuit is coupled to one end of the second pre-storage capacitor; and the other end of the second pre-storage capacitor is coupled to a common signal line; The first source and drain of the second transistor of the second sub-circuit are coupled to the second source and drain of the first transistor of the second sub-circuit, the gate of the second transistor of the second sub-circuit is coupled to the second transfer signal line, and the second source and drain of the second transistor of the second sub-circuit is coupled to one end of the pixel electrode.

[0010] Further, the third sub-circuit includes a first transistor, a third pre-storage capacitor and a second transistor; the first source and drain of the first transistor of the third sub-circuit is coupled to the third data signal line, the gate of the first transistor of the third sub-circuit is coupled to the third row gate signal line, the second source and drain of the first transistor of the third sub-circuit is coupled to one end of the third pre-storage capacitor; the other end of the third pre-storage capacitor is coupled to the common signal line; The first source and drain of the second transistor of the third sub-circuit are coupled to the second source and drain of the first transistor of the third sub-circuit, the gate of the second transistor of the third sub-circuit is coupled to the third transfer signal line, and the second source and drain of the second transistor of the third sub-circuit is coupled to one end of the pixel electrode.

[0011] The present invention also provides a stacked field sequential pixel circuit control method, comprising: In the backlight off stage of the Nth frame, the levels of the row gate signal lines of the plurality of sub-circuits jump to a high level, The first transistor of the first sub-circuit is turned on, so that the first data signal line writes the first data signal voltage to the first pre-storage capacitor through the first transistor; The first transistor of the second sub-circuit is turned on, so that the second data signal line writes the second data signal voltage to the second pre-storage capacitor through the first transistor; The first transistor of the third sub-circuit is turned on, so that the third data signal line writes the third data signal voltage into the third pre-storage capacitor through the first transistor; After the writing is completed, the level of the row gate signal line jumps to a low level, and after the first transistor of the first subcircuit, the first transistor of the second subcircuit, and the first transistor of the third subcircuit are turned off, the gap before the backlight on stage of the Nth frame is entered, the first transfer signal line jumps to a high level and maintains a high level during the backlight on stage of the Nth frame, the second transistor of the first subcircuit is continuously turned on, and the first pre-storage capacitor transfers charge to the pixel electrode through the second transistor, so that the pixel electrode reaches the first pixel voltage, and the pixel display of the Nth frame is performed; After the pixel display of the Nth frame is completed, the first transfer signal line jumps to a low level, the second transistor of the first sub-circuit is turned off, and the gap before the backlight on stage of the N+1th frame is entered, the second transfer signal line jumps to a high level and remains at a high level during the backlight on stage of the N+1th frame, the second transistor of the second sub-circuit is continuously turned on, and the second pre-storage capacitor of the second sub-circuit transfers charge to the pixel electrode through the second transistor, so that the voltage of the pixel electrode reaches the second pixel voltage, and the pixel display of the N+1th frame is performed; After the pixel display of the N+1 frame is completed, the second transfer signal line jumps to a low level, and after the second transistor of the second sub-circuit is turned off, entering the gap before the backlight turn-on stage of the N+2 frame, the third transfer signal line jumps to a high level and maintains a high level during the backlight turn-on stage of the N+2 frame, the second transistor of the third sub-circuit is continuously turned on, and the third pre-storage capacitor of the third sub-circuit transfers charge to the pixel electrode through the second transistor, so that the voltage of the pixel electrode reaches the third pixel voltage, and the pixel display of the N+2 frame is performed.

[0012] The present invention has the following advantages: In the traditional pre-storage circuit, the capacitance of the pixel electrode changes with the voltage at both ends, and the second transistor is turned on for only a certain time (charge transfer stage). After that, a holding capacitor is used to maintain the voltage of the pixel electrode to the pixel voltage. Therefore, a larger holding capacitor is required in the traditional solution to maintain it.

[0013] Furthermore, in the prior art, a reset unit needs to be set to reset the pixel electrode. Since the ratio of the pre-storage capacitor and the holding capacitor is close, such as 1:1 or 2:1, the total voltage variation range of the pixel voltage before and after the sharing process is large, which is 1 times the sum of the holding capacitor and the pixel electrode voltage, which becomes 2 or 3 times. The voltage attenuation of the pixel voltage in the next frame will be too large. In order to compensate for the attenuation, it is necessary to write a data signal voltage exceeding the maximum grayscale corresponding voltage, or write a negative polarity data signal voltage in the positive frame number to achieve the final written potential to reach the expected. As a result, there is a situation where the data signal voltage input by the data signal line is too large or the existing driver chip does not support it. In order to avoid this situation, the pixel electrode needs to be reset so that the charge in the pre-storage capacitor can make the pixel electrode smoothly reach the pixel voltage required for the next frame.

[0014] In the circuit structure adopted by the present invention, there is no need to maintain a capacitor; the present invention transfers charges in the backlight-on stage, so the second transistor is always on in the display stage, which allows the pre-storage capacitor to transfer charges to the pixel electrode all the time to maintain the pixel voltage; further, because the liquid crystal capacitance of the pixel electrode changes with the voltage, it is only necessary to pay attention to the potential at both ends of the pixel electrode. Now that the second transistor is always on, the preset pixel voltage can be reached through the pre-storage capacitor, and a reset unit is not required; therefore, the circuit structure of the present invention can not only stack multiple frames of data signal voltage at one time, but also save a holding capacitor and a reset unit.

[0015] The present invention can simultaneously write corresponding data signal voltages into the pre-storage capacitor in the pixel circuit by setting a plurality of sub-circuits; after the display of the Nth frame is completed, the N+1th frame can be immediately transferred from the pre-storage capacitor to the pixel electrode for display of the N+1th frame, and the same applies to the N+2th frame; in this way, the pre-storage time of the original N+1th frame and the N+2th frame can be saved, and the saved time for writing the pre-storage of the next frame can be used for the display of the backlight-on stage of the current frame, so that the proportion of the backlight-on stage time increases, the time utilization rate is improved, and thus the display brightness is improved.

[0016] At the same time, multiple row gate signal lines are simultaneously switched to a high level to complete the pre-writing of multiple frames of data signal voltages; thereby reducing the number of times the row gate signal is refreshed up and down, and simplifying the complexity of controlling multiple row gate signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A circuit diagram of a first embodiment of the present invention; Figure 2 This is a flow chart of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of display time according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0019] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0021] See also Figure 1 The present invention provides a stacked field sequential pixel circuit, including multiple sub-circuits and a pixel electrode Clc. The multiple sub-circuits have the same circuit structure, and the multiple sub-circuits are all coupled to the same end of the pixel electrode Clc. The other end of the pixel electrode Clc is coupled to a common signal line Com. The multiple sub-circuits are all provided with pre-storage capacitors for pre-storing data signal voltages.

[0022] In this embodiment, the plurality of sub-circuits include a first sub-circuit, a second sub-circuit and a third sub-circuit; the first sub-circuit, the second sub-circuit and the third sub-circuit are used to receive and pre-store a first data signal voltage, a second data signal voltage and a third data signal voltage, respectively.

[0023] In this embodiment, the first sub-circuit includes a first transistor T1-1, a first pre-storage capacitor Cs1, and a second transistor T2-1; a first source and a drain of the first transistor T1 of the first sub-circuit are coupled to the first data signal line Data1, a gate of the first transistor T1-1 of the first sub-circuit is coupled to the first row gate signal line Scan1, and a second source and a drain of the first transistor T1-1 of the first sub-circuit is coupled to one end of the pre-storage capacitor Cs1; the other end of the first pre-storage capacitor Cs1 is coupled to the common signal line Com; The first source and drain of the second transistor T2-1 of the first sub-circuit are coupled to the second source and drain of the first transistor T1-1 of the first sub-circuit, the gate of the second transistor T2-1 of the first sub-circuit is coupled to the first transfer signal line Tran1, the second source and drain of the second transistor T2 is coupled to one end of the pixel electrode Clc; the other end of the pixel electrode Clc is coupled to the common signal line Com.

[0024] In this embodiment, the second sub-circuit includes a first transistor T1-2 of the second sub-circuit, a second pre-storage capacitor Cs2, and a second transistor T2-2; a first source and drain of the first transistor T1-2 of the second sub-circuit is coupled to the second data signal line Data2, a gate of the first transistor T1-2 of the second sub-circuit is coupled to the second row gate signal line Scan2, a second source and drain of the first transistor T1-2 of the second sub-circuit is coupled to one end of the second pre-storage capacitor Cs2; the other end of the second pre-storage capacitor Cs2 is coupled to the common signal line Com; The first source and drain of the second transistor T2-2 of the second sub-circuit is coupled to the second source and drain of the first transistor T1-2 of the second sub-circuit, the gate of the second transistor T2-2 of the second sub-circuit is coupled to the second transfer signal line Tran2, and the second source and drain of the second transistor T2-2 of the second sub-circuit is coupled to one end of the pixel electrode Clc.

[0025] In this embodiment, the third sub-circuit includes a first transistor T1-3, a third pre-storage capacitor Cs3, and a second transistor T2-3; a first source and a drain of the first transistor T1-3 of the third sub-circuit are coupled to a third data signal line Data3, a gate of the first transistor T1-3 of the third sub-circuit is coupled to a third row gate signal line Scan3, a second source and a drain of the first transistor T1-3 of the third sub-circuit is coupled to one end of the third pre-storage capacitor Cs3; the other end of the third pre-storage capacitor Cs3 is coupled to a common signal line Com; The first source and drain of the second transistor T2-3 of the third sub-circuit is coupled to the second source and drain of the first transistor T1-3 of the third sub-circuit, the gate of the second transistor T2-3 of the third sub-circuit is coupled to the third transfer signal line Tran3, and the second source and drain of the second transistor T2-3 of the third sub-circuit is coupled to one end of the pixel electrode Clc.

[0026] When operating, the timing diagram of the pixel circuit is configured as: In the backlight off stage of the Nth frame, the levels of the row gate signal lines of multiple sub-circuits jump to high level. The first transistor T1 - 1 of the first sub-circuit is turned on, so that the first data signal line Data1 writes the first data signal voltage to the first pre-storage capacitor Cs1 through the first transistor T1 - 1; The first transistor T1-2 of the second sub-circuit is turned on, so that the second data signal line Data2 writes the second data signal voltage to the second pre-storage capacitor Cs2 through the first transistor T1-2; The first transistor T1-3 of the third sub-circuit is turned on, so that the third data signal line Data3 writes the third data signal voltage to the third pre-storage capacitor Cs3 through the first transistor T1-3; After writing is completed, the level of the row gate signal line jumps to a low level, and after the first transistor T1-1 of the first sub-circuit, the first transistor T1-2 of the second sub-circuit, and the first transistor T1-3 of the third sub-circuit are turned off, entering the gap before the backlight on stage of the Nth frame, the first transfer signal line Tran1 jumps to a high level and maintains a high level during the backlight on stage of the Nth frame, the second transistor T2-1 of the first sub-circuit is continuously turned on, and the first pre-storage capacitor Cs1 transfers charge to the pixel electrode Clc through the second transistor T2-1, so that the pixel electrode Clc reaches the first pixel voltage, and the pixel display of the Nth frame is performed; After the pixel display of the Nth frame is completed, the first transfer signal line Tran1 jumps to a low level, and after the second transistor T2-1 of the first sub-circuit is turned off, the gap before the backlight on stage of the N+1th frame is entered, the second transfer signal line Tran2 jumps to a high level and maintains a high level during the backlight on stage of the N+1th frame, the second transistor T2-2 of the second sub-circuit is continuously turned on, and the second pre-storage capacitor Cs2 of the second sub-circuit transfers charge to the pixel electrode Clc through the second transistor T2-2, so that the voltage of the pixel electrode Clc reaches the second pixel voltage, and the pixel display of the N+1th frame is performed; After the pixel display of the N+1 frame is completed, the second transfer signal line Tran2 jumps to a low level, and after the second transistor T2-2 of the second sub-circuit is turned off, entering the gap before the backlight turn-on stage of the N+2 frame, the third transfer signal line Tran3 jumps to a high level and maintains a high level during the backlight turn-on stage of the N+2 frame, the second transistor T2-3 of the third sub-circuit is continuously turned on, and the third pre-storage capacitor Cs3 of the third sub-circuit transfers charge to the pixel electrode Clc through the second transistor T2-3, so that the voltage of the pixel electrode Clc reaches the third pixel voltage, and the pixel display of the N+2 frame is performed.

[0027] In the traditional pre-storage circuit, since the capacitance of the pixel electrode Clc changes with the voltage at both ends, and the second transistor T2 is turned on for only a certain period of time (charge transfer stage), a holding capacitor is used to maintain the voltage of the pixel electrode Clc to the pixel voltage. Therefore, a larger holding capacitor is required in the traditional solution to maintain it.

[0028] When there is no holding capacitor and no voltage is applied to the pixel electrode Clc, the capacitance of the pixel electrode Clc is 2, and the maximum voltage is 8V. When the external voltage is 4V, the charge on the pixel electrode Clc is 8. As the liquid crystal deflects, the liquid crystal capacitance changes from 2 to 4. At this time, the liquid crystal voltage potential will become 2V, so a larger holding capacitor is required to maintain it. For example: the pixel electrode Clc with a capacitance of 200ff will have a charge of 800 units after a voltage of 4V is applied. In the case of parallel holding capacitors, the pixel electrode Clc will be shared to a certain extent, and finally the pixel electrode potential is close to the initial 4V voltage, achieving maintenance.

[0029] Furthermore, in the prior art, a reset unit needs to be set to reset the pixel electrode Clc, because in order to avoid the situation where the voltage attenuation of the pixel voltage is too large in the next frame, it is necessary to write a data signal voltage exceeding the maximum grayscale corresponding voltage, or write a negative polarity data signal voltage in a positive frame number to achieve the final written potential to reach the expected level. As a result, there is a situation where the data signal voltage input by the data signal line is too large or the existing driver chip does not support it; in order to avoid this situation, the pixel electrode needs to be reset so that the charge in the pre-storage capacitor can make the pixel electrode smoothly reach the pixel voltage required for the next frame.

[0030] In the circuit structure adopted by the present invention, there is no need to maintain the capacitor; the present invention transfers charges in the backlight-on stage, so the second transistor T2 is always on in the display stage, which allows the pre-storage capacitor to transfer charges to the pixel electrode Clc to maintain the pixel voltage; further, because the capacitance of the pixel electrode Clc changes with the voltage, it is only necessary to pay attention to the potential at both ends of the pixel electrode. Now the second transistor T2 is always on, and the preset pixel voltage can be reached through the pre-storage capacitor, so there is no need for a reset unit; therefore, the circuit structure of the present invention can not only stack multiple frames of data signal voltage at one time, but also save holding capacitors and reset units.

[0031] At the same time, the present invention completes the pre-writing of multiple frames of data signal voltages by having multiple row gate signal lines jump to high level at the same time, thereby reducing the number of times the row gate signal is refreshed up and down and simplifying the complexity of controlling multiple row gate signal lines. Example

[0032] like Figure 2 and Figure 3 As shown, this embodiment is a stacked field sequential pixel circuit control method.

[0033] S1. In the backlight off stage of the Nth frame, the levels of the row gate signal lines of the plurality of sub-circuits jump to a high level. The first transistor T1 - 1 of the first sub-circuit is turned on, so that the first data signal line Data1 writes the first data signal voltage to the first pre-storage capacitor Cs1 through the first transistor T1 - 1; The first transistor T1-2 of the second sub-circuit is turned on, so that the second data signal line Data2 writes the second data signal voltage to the second pre-storage capacitor Cs2 through the first transistor T1-2; The first transistor T1-3 of the third sub-circuit is turned on, so that the third data signal line Data3 writes the third data signal voltage to the third pre-storage capacitor Cs3 through the first transistor T1-3; In some specific embodiments, Figure 3 As shown, the first data signal voltage, the second data signal voltage and the third data signal voltage respectively correspond to the R data signal voltage of the Nth frame, the G data signal voltage of the N+1th frame and the B data signal voltage of the N+2th frame; each frame of data is written simultaneously, and the writing time is approximately 2ms.

[0034] S2, after writing is completed, the level of the row gate signal line jumps to a low level, and the first transistor T1-1 of the first sub-circuit, the first transistor T1-2 of the second sub-circuit, and the first transistor T1-3 of the third sub-circuit are turned off, and then the gap before the backlight on stage of the Nth frame is entered. Because the gap is very short, the time accounts for a very short proportion in the whole process, that is, it is not Figure 3 In the expression, the first transfer signal line Tran1 jumps to a high level and maintains a high level in the backlight-on stage of the N+1th frame, the second transistor T2-1 of the first sub-circuit is continuously turned on, and the first pre-storage capacitor Cs1 transfers charge to the pixel electrode Clc through the second transistor T2-1, so that the pixel electrode Clc reaches the first pixel voltage, and the pixel display of the Nth frame is performed; the pixel display time of the Nth frame can reach 4.9ms.

[0035] S3, after the charge transfer of the Nth frame is completed, the first transfer signal line Tran1 jumps to a low level, the second transistor T2-1 of the first sub-circuit is turned off, and the gap before the backlight on stage of the N+1th frame is entered, the second transfer signal line Tran2 jumps to a high level and remains at a high level during the backlight on stage of the N+1th frame, the second transistor T2-2 of the second sub-circuit is continuously turned on, and the second pre-storage capacitor Cs2 of the second sub-circuit transfers the charge to the pixel electrode Clc through the second transistor T2-2, so that the voltage of the pixel electrode Clc reaches the second pixel voltage, and the pixel display of the N+1th frame is performed; The second data signal voltage pre-stored in the second pre-storage capacitor Cs2 is directly transferred to the pixel electrode Clc, and is displayed after the transfer is completed. The display time is also 4.9 ms.

[0036] S4. After the charge transfer of the N+1th frame is completed, the second transfer signal line Tran2 jumps to a low level, and after the second transistor T2-2 of the second sub-circuit is turned off, it enters the gap before the backlight turn-on stage of the N+2th frame, and the third transfer signal line Tran3 jumps to a high level and maintains a high level during the backlight turn-on stage of the N+2th frame. The second transistor T2-3 of the third sub-circuit is continuously turned on, and the third pre-storage capacitor Cs3 of the third sub-circuit transfers charge to the pixel electrode Clc through the second transistor T2-3, so that the voltage of the pixel electrode Clc reaches the third pixel voltage, and the pixel display of the N+2th frame is performed.

[0037] S5. Repeat steps S1 to S4.

[0038] Under the existing technology, for products with a refresh rate of 60Hz, the three-color RGB three-subframe data signal voltage requires a refresh rate of 180Hz to achieve the same smoothness. Therefore, each subframe takes approximately 1 / 180≈5.6ms, and the backlight is turned on for at least 3.6ms in 5.6ms.

[0039] See also Figure 3 When the present embodiment is adopted, when the refresh rate is 60 Hz, because the data signal voltages of multiple frames are stacked at the same time, there is no need for the pre-writing time of the N+1th frame and the N+2th frame, and the backlight-on time can occupy the original pre-writing time, from the original 3.6ms to the current backlight-on time of 4.9ms; thereby, the proportion of the backlight-on time is increased, thereby increasing the brightness.

[0040] At the same time, it can be calculated that if the response speed of the LCD is not taken into account or the ultra-fast us-level response LCD is used, the theoretical time utilization rate of 1 frame is: Time utilization rate T% = 4.9*3 / 5.6 / 3≈87.5%, which is 36% higher than the traditional time utilization rate of 64.3%; If the 1ms LC response time is taken into account and a dark field is given, the time utilization rate is =3.9*3 / 5.6 / 3=70%, which is 50% higher than the traditional method.

[0041] Therefore, in this embodiment, the proportion of backlight on time is increased, so that the brightness is improved; at the same time, the time utilization rate is also improved.

[0042] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A stacked field sequential pixel circuit, characterized in that: The device comprises a plurality of sub-circuits and a pixel electrode (Clc), wherein the plurality of sub-circuits have the same circuit structure; the plurality of sub-circuits are all coupled to the same end of the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to a common signal line (Com); The plurality of sub-circuits are each provided with a pre-storage capacitor for pre-storing a data signal voltage.

2. The stacked field sequential pixel circuit according to claim 1, characterized in that: The plurality of sub-circuits include a first sub-circuit, a second sub-circuit and a third sub-circuit; the first sub-circuit, the second sub-circuit and the third sub-circuit are used to receive and pre-store a first data signal voltage, a second data signal voltage and a third data signal voltage, respectively.

3. The stacked field sequential pixel circuit according to claim 2, characterized in that: The first sub-circuit comprises a first transistor (T1-1), a first pre-storage capacitor (Cs1), a second transistor (T2-1) and a pixel electrode (Clc); a first source and drain of the first transistor (T1-1) of the first sub-circuit is coupled to a first data signal line (Data1), a gate of the first transistor (T1-1) of the first sub-circuit is coupled to a first row gate signal line (Scan1), a second source and drain of the first transistor (T1-1) of the first sub-circuit is coupled to one end of the first pre-storage capacitor (Cs1); and the other end of the first pre-storage capacitor (Cs1) is coupled to a common signal line (Com); The first source and drain of the second transistor (T2-1) of the first sub-circuit is coupled to the second source and drain of the first transistor (T1-1) of the first sub-circuit, the gate of the second transistor (T2-1) of the first sub-circuit is coupled to the first transfer signal line (Tran1), and the second source and drain of the second transistor (T2-1) of the first sub-circuit is coupled to one end of the pixel electrode (Clc).

4. The stacked field sequential pixel circuit according to claim 2, characterized in that: The second sub-circuit comprises a first transistor (T1-2), a second first pre-storage capacitor (Cs1) and a second transistor (T2-1); a first source and drain of the first transistor (T1-2) of the second sub-circuit is coupled to a second data signal line (Data2), a gate of the first transistor (T1-2) of the second sub-circuit is coupled to a second row gate signal line (Scan2), a second source and drain of the first transistor (T1-2) of the second sub-circuit is coupled to one end of the second pre-storage capacitor (Cs2); the other end of the second pre-storage capacitor (Cs2) is coupled to a common signal line (Com); The first source and drain of the second transistor (T2-2) of the second sub-circuit is coupled to the second source and drain of the first transistor (T1-2) of the second sub-circuit, the gate of the second transistor (T2-2) of the second sub-circuit is coupled to the second transfer signal line (Tran2), and the second source and drain of the second transistor (T2-2) of the second sub-circuit is coupled to one end of the pixel electrode (Clc).

5. The stacked field sequential pixel circuit according to claim 2, characterized in that: The third sub-circuit comprises a first transistor (T1-3), a third pre-storage capacitor (Cs3) and a second transistor (T2-3); a first source and drain of the first transistor (T1-3) of the third sub-circuit is coupled to a third data signal line (Data3), a gate of the first transistor (T1-3) of the third sub-circuit is coupled to a third row gate signal line (Scan3), a second source and drain of the first transistor (T1-3) of the third sub-circuit is coupled to one end of the third pre-storage capacitor (Cs3); the other end of the third pre-storage capacitor (Cs3) is coupled to a common signal line (Com); The first source and drain of the second transistor (T2-3) of the third sub-circuit is coupled to the second source and drain of the first transistor (T1-3) of the third sub-circuit, the gate of the second transistor (T2-3) of the third sub-circuit is coupled to the third transfer signal line (Tran3), and the second source and drain of the second transistor (T2-3) of the third sub-circuit is coupled to one end of the pixel electrode (Clc).

6. A stacked field sequential pixel circuit control method, applied to any pixel circuit according to claim 1 to claim 5, characterized in that: include: In the backlight off stage of the Nth frame, the levels of the row gate signal lines of the plurality of sub-circuits jump to a high level, The first transistor (T1-1) of the first sub-circuit is turned on, so that the first data signal line (Data1) writes the first data signal voltage to the first pre-storage capacitor (Cs1) through the first transistor (T1-1); The first transistor (T1-2) of the second sub-circuit is turned on, so that the second data signal line (Data2) writes the second data signal voltage to the second pre-storage capacitor (Cs2) through the first transistor (T1-2); The first transistor (T1-3) of the third sub-circuit is turned on, so that the third data signal line (Data3) writes the third data signal voltage to the third pre-storage capacitor (Cs3) through the first transistor (T1-3); After writing is completed, the level of the row gate signal line jumps to a low level, and after the first transistor (T1-1) of the first sub-circuit, the first transistor (T1-2) of the second sub-circuit, and the first transistor (T1-3) of the third sub-circuit are turned off, entering the gap before the backlight on stage of the Nth frame, the first transfer signal line (Tran1) jumps to a high level and maintains a high level during the backlight on stage of the Nth frame, the second transistor (T2-1) of the first sub-circuit is continuously turned on, and the first pre-storage capacitor (Cs1) transfers charge to the pixel electrode (Clc) through the second transistor (T2-1), so that the pixel electrode (Clc) reaches the first pixel voltage, and the pixel display of the Nth frame is performed; After the pixel display of the Nth frame is completed, the first transfer signal line (Tran1) jumps to a low level, the second transistor (T2-1) of the first sub-circuit is turned off, and the gap before the backlight on stage of the N+1th frame is entered, the second transfer signal line (Tran2) jumps to a high level and remains at a high level during the backlight on stage of the N+1th frame, the second transistor (T2-2) of the second sub-circuit is continuously turned on, and the second pre-storage capacitor (Cs2) of the second sub-circuit transfers charge to the pixel electrode (Clc) through the second transistor (T2-2), so that the voltage of the pixel electrode (Clc) reaches the second pixel voltage, and the pixel display of the N+1th frame is performed; After the pixel display of the N+1 frame is completed, the second transfer signal line (Tran2) jumps to a low level, and after the second transistor (T2-2) of the second sub-circuit is turned off, the gap before the backlight start-up stage of the N+2 frame is entered, the third transfer signal line (Tran3) jumps to a high level and maintains a high level during the backlight start-up stage of the N+2 frame, the second transistor (T2-3) of the third sub-circuit is continuously turned on, and the third pre-storage capacitor (Cs3) of the third sub-circuit transfers charge to the pixel electrode (Clc) through the second transistor (T2-3), so that the voltage of the pixel electrode (Clc) reaches the third pixel voltage, and the pixel display of the N+2 frame is performed.

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