Method for preparing a semiconductor structure

Abstract

The present invention discloses a method for preparing a semiconductor structure, which belongs to the field of semiconductor technology. The preparation method at least includes the following steps: providing a substrate; forming a pad oxide layer, an intermediate material layer and a pad nitride layer on the substrate in sequence; etching the pad nitride layer, the intermediate material layer, the pad oxide layer and the substrate to form a shallow trench, forming an insulating dielectric layer in the shallow trench until the insulating dielectric layer in the shallow trench protrudes from the pad nitride layer; flattening the insulating dielectric layer until the pad nitride layer is exposed; oxidizing the intermediate material layer to obtain an oxide material layer; etching and removing the pad nitride layer; and flattening the oxide material layer and the insulating dielectric layer. The preparation method of the semiconductor structure provided by the present invention can avoid the appearance of a dish-shaped depression on the surface of the shallow trench isolation structure, and improve the flatness of the surface of the shallow trench isolation structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Shallow Trench Isolation (STI) is an important structure in integrated circuits. It is set between semiconductor devices to prevent current leakage between adjacent semiconductor devices and reduce the area of ​​the isolation region.

[0003] During the formation of the shallow trench isolation structure, when the insulating dielectric layer is planarized, it is easy to cause a dish-shaped depression to form on the surface of the shallow trench isolation structure, destroying the flatness of the surface of the shallow trench isolation structure, causing the surface of the shallow trench isolation structure to be lower than the substrate, thereby causing a short circuit in the semiconductor device and causing the electrical performance of the semiconductor device to deteriorate. Moreover, the dish-shaped depression will cause a yield loss in subsequent processes. For example, in the contact hole etching process, the dish-shaped depression will cause the photoresist layer or anti-reflection layer near it to be thicker. The thicker photoresist layer or anti-reflection layer will reduce the etching rate of the contact hole, resulting in yield problems such as the contact hole in the area near the dish-shaped depression not being etched. Therefore, how to avoid the formation of a dish-shaped depression on the surface of the shallow trench isolation structure is an urgent problem to be solved. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for preparing a semiconductor structure, which can avoid the appearance of dish-shaped depressions on the surface of the shallow trench isolation structure, improve the flatness of the surface of the shallow trench isolation structure, and improve the electrical performance and yield of the semiconductor structure.

[0005] To solve the above technical problems, the present invention is implemented through the following technical solutions.

[0006] The present invention provides a method for preparing a semiconductor structure, which at least comprises the following steps:

[0007] providing a substrate;

[0008] forming a pad oxide layer, an intermediate material layer and a pad nitride layer in sequence on the substrate;

[0009] Etching the pad nitride layer, the intermediate material layer, the pad oxide layer and the substrate to form a shallow trench, and forming an insulating dielectric layer in the shallow trench until the insulating dielectric layer in the shallow trench protrudes from the pad nitride layer;

[0010] planarizing the insulating dielectric layer until the pad nitride layer is exposed;

[0011] performing oxidation treatment on the intermediate material layer to obtain an oxidized material layer;

[0012] etching and removing the pad nitride layer; and

[0013] The oxide material layer and the insulating dielectric layer are planarized.

[0014] In one embodiment of the present invention, the material of the intermediate material layer includes amorphous silicon.

[0015] In one embodiment of the present invention, the thickness of the intermediate material layer is 800Å-1100Å.

[0016] In one embodiment of the present invention, the oxidation treatment of the intermediate material layer comprises at least the following steps:

[0017] injecting oxygen plasma into the intermediate material layer; and

[0018] The intermediate material layer is subjected to annealing treatment.

[0019] In one embodiment of the present invention, the injection energy of the oxygen plasma is 30keV-150keV, and the injection dose of the oxygen plasma is 1×10 12 ion / cm 2 -9×10 15 ion / cm 2 .

[0020] In one embodiment of the present invention, the thickness of the oxide material layer is less than or equal to the initial thickness of the intermediate material layer.

[0021] In one embodiment of the present invention, the method for planarizing the insulating dielectric layer is chemical mechanical polishing, and the pad nitride layer is used as a polishing stop layer.

[0022] In an embodiment of the present invention, the preparation method further comprises: after forming the pad nitride layer, sequentially forming a barrier layer, an anti-reflection layer and a photoresist layer on the pad nitride layer.

[0023] In one embodiment of the present invention, the preparation method further comprises:

[0024] Patterning the photoresist layer to form a photoresist layer, wherein the photoresist layer exposes a portion of the anti-reflection layer;

[0025] Using the photoresist layer as a mask, etching the exposed anti-reflection layer and the barrier layer; and

[0026] Using the barrier layer as a mask, the exposed pad nitride layer, the intermediate material layer, the pad oxide layer and the substrate are etched to form a shallow trench.

[0027] In one embodiment of the present invention, the preparation method further includes: after planarizing the oxide material layer and the insulating dielectric layer, removing the oxide material layer and the pad oxide layer by etching, or, after forming a well region by ion implantation, etching away the oxide material layer and the pad oxide layer.

[0028] In summary, the present invention provides a method for preparing a semiconductor structure. By improving the preparation method, the unexpected technical effect of the present application is that the surface of the shallow trench isolation structure can be prevented from having a dish-shaped depression, thereby improving the quality of the shallow trench isolation structure. Moreover, the method for preparing a semiconductor structure provided by the present invention can improve the flatness of the surface of the shallow trench isolation structure, thereby improving the quality of the subsequent process technology, and ultimately improving the quality and yield of the semiconductor structure. It can also improve the isolation performance of the shallow trench isolation structure, avoid leakage in the semiconductor structure, and improve the electrical performance of the semiconductor structure.

[0029] Of course, any method of implementing the present invention does not necessarily need to achieve all of the advantages mentioned above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0031] Figure 1 FIG. 4 is a schematic diagram of forming a pad oxide layer in one embodiment of the present invention.

[0032] Figure 2 Schematic diagram of forming an intermediate material layer.

[0033] Figure 3 Schematic diagram of forming a pad nitride layer.

[0034] Figure 4 Schematic diagram of forming a barrier layer.

[0035] Figure 5 Schematic diagram of forming an anti-reflection layer.

[0036] Figure 6 A schematic diagram of forming a photoresist layer.

[0037] Figure 7 A schematic diagram of forming a groove.

[0038] Figure 8 Schematic diagram of forming a shallow trench.

[0039] Fig. 9 A schematic diagram of forming an insulating dielectric layer.

[0040] Fig.10 Schematic diagram of planarizing the insulating dielectric layer.

[0041] Fig.11 Schematic diagram of forming an oxide material layer.

[0042] Fig.12 Schematic diagram of removing the pad nitride layer.

[0043] Fig.13 Schematic diagram of a planarized oxide material layer and an insulating dielectric layer.

[0044] Description of labels:

[0045] 100, substrate; 200, pad oxide layer; 300, intermediate material layer; 400, pad nitride layer; 500, shallow trench isolation structure; 501, opening; 502, groove; 503, shallow trench; 504, insulating dielectric layer; 600, oxide material layer; 700, blocking layer; 800, anti-reflection layer; 900, photoresist layer. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0047] It should be understood that the present invention can be implemented in different forms and should not be interpreted as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art.

[0048] The technical solution of the present invention is further described in detail below in conjunction with the embodiments and drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] See also Figures 1 to 13As shown, the present invention provides a method for preparing a semiconductor structure, which is used to prepare a high-quality shallow trench isolation structure 500. In the process of forming the shallow trench isolation structure 500, the pad nitride layer 400 is processed by etching and removing instead of planarization, and the oxidation material layer 600 is obtained by oxidizing the intermediate material layer 300, so that the chemical properties and physical properties of the oxidation material layer 600 and the insulating dielectric layer 504 are similar or the same, and then the oxidation material layer 600 and the insulating dielectric layer 504 are planarized, which can avoid the generation of dish-shaped depressions on the surface of the insulating dielectric layer 504, thereby improving the flatness of the surface of the insulating dielectric layer 504, and further improving the quality of the subsequent process technology, and improving the electrical performance and yield of the semiconductor structure.

[0050] See also Figure 1 As shown, in one embodiment of the present invention, a substrate 100 is first provided, and the substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire, silicon wafer or other semiconductor materials formed by III / V compounds, etc., including a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. Among them, the substrate 100 can be an intrinsic semiconductor, and ions can also be implanted in the substrate 100 to form an N-type semiconductor or a P-type semiconductor. Moreover, the present invention does not limit the thickness of the substrate 100. In this embodiment, for example, a silicon wafer substrate 100 is taken as an example to illustrate the preparation method of the semiconductor structure.

[0051] See also Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 200 is formed on a substrate 100. The pad oxide layer 200 is formed, for example, by thermal oxidation, liquid phase epitaxial growth, molecular beam epitaxial growth, chemical vapor deposition or evaporation growth, and the material of the pad oxide layer 200 includes, for example, silicon oxide, etc. The present invention does not limit the thickness of the pad oxide layer 200, which can be selected according to actual needs. In this embodiment, the pad oxide layer 200 is formed, for example, by thermal oxidation. Specifically, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900°C-1150°C, oxygen is introduced, and the substrate 100 reacts with oxygen at high temperature to generate a dense pad oxide layer 200. The thickness of the pad oxide layer 200 is, for example, 80Å-120Å, and specifically, 90Å, 100Å or 110Å, etc. By providing the pad oxide layer 200 , the substrate 100 can be protected from the effects of processes such as etching and grinding during the subsequent formation of the shallow trench isolation structure 500 , thereby preventing the substrate 100 from being subjected to unnecessary damage.

[0052] See also Figure 1 to Figure 2As shown, in one embodiment of the present invention, after the pad oxide layer 200 is formed, an intermediate material layer 300 is formed on the pad oxide layer 200. The material of the intermediate material layer 300 includes, for example, amorphous silicon, and the intermediate material layer 300 is formed, for example, by liquid phase epitaxial growth, molecular beam epitaxial growth, chemical vapor deposition, or evaporation growth. The present invention does not limit the thickness of the intermediate material layer 300, which can be selected according to actual needs. In this embodiment, the thickness of the intermediate material layer 300 is, for example, 800Å-1100Å, specifically, for example, 900Å, 1000Å, or 1100Å.

[0053] See also Figures 2 to 3 As shown, in one embodiment of the present invention, after the intermediate material layer 300 is formed, a pad nitride layer 400 is formed on the intermediate material layer 300. The material of the pad nitride layer 400 includes, for example, silicon nitride, etc. The pad nitride layer 400 is formed, for example, by a liquid phase epitaxial growth method, a molecular beam epitaxial growth method, a chemical vapor deposition method, or an evaporation growth method. The present invention does not limit the thickness of the pad nitride layer 400, and it can be selected according to actual needs. In this embodiment, the pad nitride layer 400 is formed, for example, by a chemical vapor deposition method. Specifically, the substrate 100 with the pad oxide layer 200 and the intermediate material layer 300 is placed in a chamber containing a nitrogen source and a silicon source, and the pad nitride layer 400 is deposited on the intermediate material layer 300 under the conditions of a pressure of, for example, 2Torr-10Torr and a temperature of, for example, 600°C-800°C. Wherein, the nitrogen source includes, for example, at least one of ammonia, nitrogen, dimethylamine and trimethylamine, and the silicon source includes, for example, at least one of silane, chlorosilane, dichlorodihydrosilane and disilane, and the thickness of the pad nitride layer 400 is, for example, 50Å-200Å. By providing the pad nitride layer 400, the substrate 100 can be protected from the effects of processes such as etching, grinding and ion implantation during the subsequent formation of the shallow trench isolation structure 500, thereby preventing the substrate 100 from being damaged unnecessarily. Moreover, the pad nitride layer 400 can also be used as a mask layer to etch the intermediate material layer 300, the pad oxide layer 200 and the substrate 100, so as to form a shallow trench 503.

[0054] See also Figure 3 to Figure 4As shown, in one embodiment of the present invention, after the pad nitride layer 400 is formed, a barrier layer 700 is formed on the pad nitride layer 400, and the material of the barrier layer 700 includes, for example, carbon or amorphous silicon. Among them, the present invention does not limit the thickness and formation method of the barrier layer 700, which can be selected according to actual needs. In this embodiment, the thickness of the barrier layer 700 is, for example, 1800Å-2200Å, specifically, for example, 1900Å, 2000Å or 2100Å. The barrier layer 700 is prepared by, for example, vacuum evaporation, sputtering or chemical vapor deposition. By setting the barrier layer 700 as a mask layer, the substrate 100, the pad oxide layer 200, the intermediate material layer 300 and the pad nitride layer 400 can be protected in the process of forming the shallow trench 503 to prevent them from being subjected to unnecessary damage.

[0055] See also Figures 4 to 5 As shown, in one embodiment of the present invention, after the barrier layer 700 is formed, an anti-reflection layer 800 is formed on the barrier layer 700, and the material of the anti-reflection layer 800 includes, for example, silicon oxynitride, etc. Among them, the present invention does not limit the thickness and formation method of the anti-reflection layer 800, which can be selected according to actual needs. In this embodiment, the thickness of the anti-reflection layer 800 is, for example, 300Å-400Å, specifically, for example, 350Å, 370Å or 390Å, etc. The anti-reflection layer 800 is prepared, for example, by chemical vapor deposition, physical vapor deposition or high-temperature nitridation. By providing the anti-reflection layer 800, when the groove 502 is subsequently formed, the standing wave effect in the etching process can be suppressed, thereby improving the accuracy of etching.

[0056] See also Figure 5 to Figure 6 As shown, in one embodiment of the present invention, after the anti-reflection layer 800 is formed, a photoresist layer is formed on the anti-reflection layer 800, and the photoresist layer is patterned through processes such as exposure and development to form a photoresist layer 900, and a first opening 501 is formed on the photoresist layer 900, and the first opening 501 exposes a portion of the anti-reflection layer 800. The photoresist layer 900 is provided to locate the position of the subsequent shallow trench isolation structure 500.

[0057] See also Figure 6 to Figure 7As shown, in one embodiment of the present invention, the photoresist layer 900 is used as a mask to etch the exposed anti-reflection layer 800 and the barrier layer 700 to form a groove 502, wherein the groove 502 extends from the first opening 501 into the barrier layer 700, and the groove 502 exposes a portion of the pad nitride layer 400. Moreover, in the process of forming the groove 502, the anti-reflection layer 800 and the photoresist layer 900 are basically completely etched. Among them, the present invention does not limit the etching method, which can be selected according to actual conditions. In this embodiment, for example, the groove 502 is formed by dry etching, and the etching gas, for example, includes one or a mixture of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination of them and oxygen (O2).

[0058] See also Figures 7 and 8 As shown, in one embodiment of the present invention, the barrier layer 700 is used as a mask to etch the exposed pad nitride layer 400, the intermediate material layer 300, the pad oxide layer 200 and the substrate 100 to form a shallow groove 503, and the shallow groove 503 extends from the surface of the pad nitride layer 400 to the substrate 100. Moreover, in the process of forming the shallow groove 503, the barrier layer 700 is basically completely etched, and part of the pad nitride layer 400 will be etched away. Among them, the present invention does not limit the number of shallow grooves 503, the depth of the shallow grooves 503, and the etching method, which can be selected according to actual needs. In this embodiment, for example, the shallow groove 503 is formed by dry etching, and the etching gas includes, for example, Cl2, CHF3, CH2F2, NF3, SF6 or HBr, one or a mixture of several, or a combination of them and O2.

[0059] See also Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the shallow trench 503, an insulating dielectric layer 504 is formed in the shallow trench 503 until the insulating dielectric layer 504 in the shallow trench 503 protrudes from the pad nitride layer 400. The material of the insulating dielectric layer 504 includes, for example, at least one of silicon oxide or silicon oxynitride, etc. The present invention does not limit the method for forming the insulating dielectric layer 504. For example, the insulating dielectric layer 504 can be formed by methods such as high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). In this embodiment, the material of the insulating dielectric layer 504 is, for example, silicon oxide.

[0060] See also Figures 9 and 10As shown, in one embodiment of the present invention, after the insulating dielectric layer 504 is formed, the insulating dielectric layer 504 is planarized until the pad nitride layer 400 is exposed. In this embodiment, for example, the insulating dielectric layer 504 is planarized by chemical mechanical polishing (CMP). Specifically, in chemical mechanical polishing, the polishing liquid includes, for example, abrasives, pH adjusters, and additives. Among them, the abrasive includes, for example, at least one of silicon dioxide particles, aluminum oxide particles, silicon nitride particles, zirconium oxide particles, manganese oxide particles, and cerium oxide particles, and the pH adjuster includes, for example, at least one of potassium hydroxide, sodium hydroxide, and ammonia water, and the pH value of the polishing liquid is, for example, 10-13, and the additive includes, for example, at least one of sodium chloride and ammonium chloride. Since the materials of the insulating dielectric layer 504 and the pad nitride layer 400 are neither the same nor similar, if the pad nitride layer 400 and the insulating dielectric layer 504 are still ground simultaneously after the pad nitride layer 400 is exposed, there will be a large difference in the grinding rates of the pad nitride layer 400 and the insulating dielectric layer 504, which will cause a dish-shaped depression to form on the surface of the insulating dielectric layer 504, thereby destroying the flatness of the surface of the insulating dielectric layer 504. Therefore, in the present application, the pad nitride layer 400 is used as the grinding stop layer, and when it is detected that the grinding reaches the pad nitride layer 400, the mask is stopped immediately, thereby avoiding the formation of a dish-shaped depression on the surface of the insulating dielectric layer 504.

[0061] See also Figure 10 to Figure 11 As shown, in one embodiment of the present invention, after the insulating dielectric layer 504 is planarized, the intermediate material layer 300 is oxidized to obtain an oxidized material layer 600. The material of the oxidized material layer 600 is, for example, silicon oxide, and the thickness of the oxidized material layer 600 is, for example, less than or equal to the thickness of the intermediate material layer 300. The present invention does not limit the oxidation method, which can be selected according to actual needs. In this embodiment, for example, the intermediate material layer 300 is oxidized by ion implantation. Specifically, oxygen plasma is injected into the intermediate material layer 300, and then the intermediate material layer 300 is annealed so that the plasma diffuses and activates in the intermediate material layer 300, thereby achieving the purpose of oxidizing the intermediate material layer 300. The injection energy of the oxygen plasma is, for example, 30keV-150keV, and the injection dose of the oxygen plasma is, for example, 1×10 12 ion / cm 2 -9×10 15 ion / cm 2, the thickness of the oxide material layer 600 is, for example, equal to the thickness of the intermediate material layer 300. In other embodiments of the present invention, part of the intermediate material layer 300 may also be oxidized by controlling the injection energy and injection dose of the oxygen plasma, that is, the thickness of the oxide material layer 600 is less than the thickness of the intermediate material layer 300. Oxidation of the intermediate material layer 300 by ion implantation can not only make the insulating dielectric layer 504 and the oxide material layer 600 of the same material, but also make the insulating dielectric layer 504 and the oxide material layer 600 of the same physical properties, such as compactness, roughness, hardness, density, etc., so as to facilitate the subsequent simultaneous planarization of the insulating dielectric layer 504 and the oxide material layer 600, so that the oxide material layer 600 and the insulating dielectric layer 504 have equal processing rates.

[0062] See also Figure 11 to Figure 12 As shown, in one embodiment of the present invention, after the oxide material layer 600 is formed, the pad nitride layer 400 is etched away. The method of etching away the pad nitride layer 400 is, for example, dry etching or wet etching. In this embodiment, the pad nitride layer 400 is removed by, for example, wet etching. Specifically, during the wet etching process, the etching solution includes, for example, phosphoric acid, and the volume fraction of phosphoric acid in the etching solution is, for example, 80%-90%, and the temperature of the etching solution is, for example, 20°C-180°C. If chemical mechanical polishing is used to planarize the pad nitride layer 400 and the insulating dielectric layer 504, since the materials of the pad nitride layer 400 and the insulating dielectric layer 504 are neither the same nor similar, after chemical mechanical polishing, a dish-shaped depression will be formed on the surface of the insulating dielectric layer 504. In the present application, the pad nitride layer 400 is selectively removed by etching, which will not affect the insulating dielectric layer 504 in the shallow trench 503, thereby avoiding the formation of a dish-shaped depression on the surface of the insulating dielectric layer 504 and improving the flatness of the surface of the insulating dielectric layer 504.

[0063] See also Figure 12 to Figure 13As shown, in one embodiment of the present invention, after removing the pad nitride layer 400, the oxide material layer 600 and the insulating dielectric layer 504 are planarized until the surfaces of the insulating dielectric layer 504 and the oxide material layer 600 are flat, thereby forming a shallow trench isolation structure 500. The present invention does not limit the position of the surface of the shallow trench isolation structure 500. The surface of the shallow trench isolation structure 500 may be within the oxide material layer 600 or at the interface between the oxide material layer 600 and the pad oxide layer 200. The surface may be selected according to actual needs. In this embodiment, for example, the oxide material layer 600 and the insulating dielectric layer 504 are planarized by chemical mechanical polishing. Specifically, in chemical mechanical polishing, the polishing liquid may include, for example, abrasives, pH regulators, and additives. The abrasive material includes at least one of silicon dioxide particles, aluminum oxide particles, silicon nitride particles, zirconium oxide particles, manganese oxide particles, and cerium oxide particles, the pH value adjuster includes at least one of potassium hydroxide, sodium hydroxide, and ammonia water, the pH value of the polishing liquid is 10-13, and the additive includes at least one of sodium chloride and ammonium chloride. Since the material and physical properties of the oxide material layer 600 and the insulating dielectric layer 504 are the same, during the chemical mechanical polishing of the oxide material layer 600 and the insulating dielectric layer 504, the polishing rates of the oxide material layer 600 and the insulating dielectric layer 504 are equal, so that the surface of the insulating dielectric layer 504 can be prevented from having a dish-shaped depression, thereby improving the flatness of the surface of the shallow trench isolation structure 500, improving the isolation performance of the shallow trench isolation structure 500, and improving the electrical performance and yield of the semiconductor structure.

[0064] See also Fig.13 As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 500, the oxide material layer 600 and the pad oxide layer 200 can be etched away first, and then subsequent gate oxide layer, gate, source, drain, side wall and metal interconnection layer and other structures are manufactured. Alternatively, the oxide material layer 600 and the pad oxide layer 200 can be used as an ion implantation buffer layer to form a well region and other structures, and then the oxide material layer 600 and the pad oxide layer 200 are etched away, and then subsequent gate oxide layer, gate, source, drain, side wall and metal interconnection layer and other structures are manufactured to improve the yield and quality of the manufactured semiconductor device, which will not be elaborated here.

[0065] In summary, the present invention provides a method for preparing a semiconductor structure. By improving the processing steps of the pad nitride layer, the insulating dielectric layer and the oxide material layer, the unexpected technical effect of the present application is that the dish-shaped depression on the surface of the shallow trench isolation structure can be avoided, and the quality of the shallow trench isolation structure can be improved. Moreover, the method for preparing a semiconductor structure provided by the present invention can improve the flatness of the surface of the shallow trench isolation structure, thereby improving the quality of the subsequent semiconductor process technology, and ultimately improving the quality and yield of the semiconductor structure. It can also improve the isolation effect of the shallow trench isolation structure, avoid short circuits in the semiconductor structure, and improve the electrical performance of the semiconductor structure.

[0066] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is only limited by the full scope of the claims and equivalents.

Claims

1. A method for preparing a semiconductor structure, characterized in that: At least the following steps are included: providing a substrate; forming a pad oxide layer, an intermediate material layer and a pad nitride layer in sequence on the substrate; Etching the pad nitride layer, the intermediate material layer, the pad oxide layer and the substrate to form a shallow trench, and forming an insulating dielectric layer in the shallow trench until the insulating dielectric layer in the shallow trench protrudes from the pad nitride layer; planarizing the insulating dielectric layer until the pad nitride layer is exposed; Performing oxidation treatment on the intermediate material layer to obtain an oxidized material layer, wherein the thickness of the oxidized material layer is less than or equal to the initial thickness of the intermediate material layer, and the material and physical properties of the oxidized material layer and the insulating dielectric layer are the same; Etching and removing the pad nitride layer; planarizing the oxide material layer and the insulating dielectric layer; as well as Removing the oxide material layer and the pad oxide layer by etching, or, after forming a well region by ion implantation, removing the oxide material layer and the pad oxide layer by etching; Wherein, the oxidation treatment of the intermediate material layer comprises at least the following steps: injecting oxygen plasma into the intermediate material layer; and The intermediate material layer is subjected to annealing treatment.

2. The preparation method according to claim 1, characterized in that: The material of the intermediate material layer includes amorphous silicon.

3. The preparation method according to claim 1, characterized in that: The thickness of the intermediate material layer is 800Å-1100Å.

4. The preparation method according to claim 1, characterized in that: The injection energy of the oxygen plasma is 30keV-150keV, and the injection dose of the oxygen plasma is 1×10 12 ion / cm 2 -9×10 15 ion / cm 2 .

5. The preparation method according to claim 1, characterized in that: The method for planarizing the insulating dielectric layer is chemical mechanical polishing, and the pad nitride layer is used as a polishing stop layer.

6. The preparation method according to claim 1, characterized in that: The preparation method further comprises: after forming the pad nitride layer, sequentially forming a barrier layer, an anti-reflection layer and a photoresist layer on the pad nitride layer.

7. The preparation method according to claim 6, characterized in that: The preparation method further comprises: Patterning the photoresist layer to form a photoresist layer, wherein the photoresist layer exposes a portion of the anti-reflection layer; Using the photoresist layer as a mask, etching the exposed anti-reflection layer and the barrier layer; and Using the barrier layer as a mask, the exposed pad nitride layer, the intermediate material layer, the pad oxide layer and the substrate are etched to form a shallow trench.

Images