Semiconductor device and manufacturing method thereof
By forming an air gap and conductive interconnect structure in the semiconductor structure and sealing with a barrier layer, the problem of excessive parasitic capacitance in the prior art is solved, and better semiconductor device performance is achieved.
Patent Information
- Application Number
- CN202411541482.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-14
AI Technical Summary
In existing semiconductor processes, the parasitic capacitance caused by the conductive interconnect structure is too large to meet the device performance requirements.
By forming a lower and upper air gap in the semiconductor structure, and forming a through hole and an upper conductive interconnect structure between the upper air gap and the lower air gap, the barrier layer seal is used to reduce parasitic capacitance.
It effectively reduces parasitic capacitance and improves the performance of semiconductor devices.
Smart Images
Figure CN119447027A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] In semiconductor processing, the source and drain of a transistor are connected through a back-end conductive interconnect structure. However, one challenge brought by the back-end process is how to reduce the capacitance-resistance delay (RC delay) caused by the conductive interconnect structure when the device is working normally. Among them, forming an air gap above the gate of the transistor is a commonly used solution.
[0003] In the existing process, after the first metal layer (M1) in the conductive interconnect structure is completed, an opening is formed in the dielectric layer between adjacent first metal layers, and then a layer of insulating film with poor step coverage is grown through a chemical vapor deposition process, and its poor hole-filling performance is used to form an air gap; however, due to the characteristics of the hole-filling process of the chemical vapor deposition process, the air gap always starts to close from the middle position of the first metal layer upwards, resulting in a gradual decrease in the width of the air gap above the middle position of the first metal layer, which in turn causes the parasitic capacitance between adjacent first metal layers to be too large and fail to meet the performance requirements of the device.
[0004] Therefore, how to further reduce the parasitic capacitance is an urgent problem to be solved. Summary of the invention
[0005] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so that the parasitic capacitance can be further reduced.
[0006] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0007] Step S1, providing a semiconductor structure, the semiconductor structure comprising: a substrate and a lower insulating dielectric layer, the lower insulating dielectric layer having at least two lower conductive interconnect structures formed therein, and a lower air gap formed in the lower insulating dielectric layer between two adjacent lower conductive interconnect structures;
[0008] Step S2, forming a through hole exposing the top surface of the lower conductive interconnect structure and an upper air gap communicating with the lower air gap, wherein the upper air gap is sealed by a barrier layer;
[0009] Step S3, forming an upper conductive interconnect structure in the through hole.
[0010] Optionally, the method for manufacturing the semiconductor device further includes:
[0011] Step S4, removing the barrier layer to expose the upper air gap;
[0012] Step S5, forming an upper insulating dielectric layer on the lower insulating dielectric layer, wherein the upper insulating dielectric layer covers the upper conductive interconnect structure and seals the upper air gap.
[0013] Optionally, the method for manufacturing the semiconductor device further includes:
[0014] The upper insulating dielectric layer is used as another lower insulating dielectric layer, the upper conductive interconnect structure is used as another lower conductive interconnect structure, and the upper air gap is used as another lower air gap, and steps S2 to S5 are repeatedly performed.
[0015] Optionally, the lower insulating dielectric layer is etched to form an upper air gap connected to the lower air gap, and the top width of the lower air gap before etching the lower insulating dielectric layer is smaller than the top width of the lower air gap after etching the lower insulating dielectric layer.
[0016] Optionally, step S2 includes:
[0017] Etching the lower insulating dielectric layer to form a first through hole above the lower conductive interconnect structure and to form an upper air gap connected to the lower air gap;
[0018] forming a barrier layer on the lower insulating dielectric layer, wherein the barrier layer seals the upper air gap and the first through hole;
[0019] The barrier layer and the lower insulating dielectric layer are etched to form a through hole exposing a top surface of a portion of the lower conductive interconnect structure.
[0020] Optionally, the semiconductor structure includes a transistor formed on the substrate, the transistor includes a gate structure formed on the substrate and a source region and a drain region formed on both sides of the gate structure, the lower conductive interconnect structure is formed on the source region and the drain region, or the lower conductive interconnect structure is formed on the gate structure, the source region and the drain region.
[0021] Optionally, the lower air gap is formed above the gate structure; and / or, the lower air gap is formed between the lower conductive interconnect structure on the source region and the lower conductive interconnect structure on the gate structure; and / or, the lower air gap is formed between the lower conductive interconnect structure on the drain region and the lower conductive interconnect structure on the gate structure.
[0022] The present invention also provides a semiconductor device, comprising:
[0023] A substrate having a lower insulating dielectric layer formed thereon, and at least two lower conductive interconnect structures formed in the lower insulating dielectric layer;
[0024] an upper conductive interconnect structure formed in the lower insulating dielectric layer on the lower conductive interconnect structure, or at least two upper conductive interconnect structures formed in the lower insulating dielectric layer and the upper insulating dielectric layer on the lower conductive interconnect structure;
[0025] The air gap structure extends from between two adjacent lower conductive interconnect structures to between two adjacent upper conductive interconnect structures.
[0026] Optionally, the upper insulating dielectric layer also covers the lower insulating dielectric layer and the upper conductive interconnect structure.
[0027] Optionally, a transistor is formed on the substrate, and the transistor includes a gate structure formed on the substrate and a source region and a drain region formed on both sides of the gate structure, and the lower conductive interconnect structure is formed on the source region and the drain region, or the lower conductive interconnect structure is formed on the gate structure, the source region and the drain region.
[0028] Optionally, the air gap structure is formed above the gate structure; and / or, the air gap structure is formed between the lower conductive interconnect structure on the source region and the lower conductive interconnect structure on the gate structure; and / or, the air gap structure is formed between the lower conductive interconnect structure on the drain region and the lower conductive interconnect structure on the gate structure.
[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0030] 1. The method for manufacturing a semiconductor device of the present invention comprises: step S1, providing a semiconductor structure, the semiconductor structure comprising: a substrate and a lower insulating dielectric layer, the lower insulating dielectric layer having at least two lower conductive interconnect structures formed therein, and a lower air gap formed in the lower insulating dielectric layer between two adjacent lower conductive interconnect structures; step S2, forming a through hole exposing the top surface of the lower conductive interconnect structure and an upper air gap connected to the lower air gap, the upper air gap being sealed by a barrier layer; step S3, forming an upper conductive interconnect structure in the through hole. Thus, the parasitic capacitance is further reduced.
[0031] 2. The semiconductor device of the present invention comprises: a substrate, a lower insulating dielectric layer is formed on the substrate, at least two lower conductive interconnect structures are formed in the lower insulating dielectric layer; an upper conductive interconnect structure is formed in the lower insulating dielectric layer on the lower conductive interconnect structure, or at least two upper conductive interconnect structures are formed in the lower insulating dielectric layer and the upper insulating dielectric layer on the lower conductive interconnect structure; and an air gap structure extends from between two adjacent lower conductive interconnect structures to between two adjacent upper conductive interconnect structures. This further reduces the parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0033] Figure 2a to Figure 2e yes Figure 1 A schematic diagram of a device in a method for manufacturing a semiconductor device shown;
[0034] Figure 3 to Figure 5 is a schematic diagram of a device in a method for manufacturing a semiconductor device according to another embodiment of the present invention;
[0035] Figure 6 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
[0036] Among them, Figure 1 to Figure 6 The reference numerals are described as follows:
[0037] 10-substrate; 101-gate structure; 102-source region; 103-drain region; 11-lower insulating dielectric layer; 111-first insulating layer; 112-second insulating layer; 113-third insulating layer; 114-fourth insulating layer; 12-lower conductive interconnect structure; 121-contact plug; 122-lower metal interconnect layer; 131-lower air gap; 132-upper air gap; 14-through hole; 141-first through hole; 142-second through hole; 15-barrier layer; 16-upper conductive interconnect structure; 17-upper insulating dielectric layer; 171-fifth insulating layer; 172-sixth insulating layer; 18-top conductive structure. DETAILED DESCRIPTION
[0038] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0039] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 ,from Figure 1 It can be seen that the method for manufacturing the semiconductor device includes:
[0040] Step S1, providing a semiconductor structure, the semiconductor structure comprising: a substrate and a lower insulating dielectric layer, the lower insulating dielectric layer having at least two lower conductive interconnect structures formed therein, and a lower air gap formed in the lower insulating dielectric layer between two adjacent lower conductive interconnect structures;
[0041] Step S2, forming a through hole exposing the top surface of the lower conductive interconnect structure and an upper air gap communicating with the lower air gap, wherein the upper air gap is sealed by a barrier layer;
[0042] Step S3, forming an upper conductive interconnect structure in the through hole.
[0043] See below Figure 2a to Figure 2e and Figure 3 to Figure 6 The method for manufacturing the semiconductor device provided in this embodiment is described in detail. Figure 2a to Figure 2e and Figure 3 to Figure 6 It is also a longitudinal cross-sectional schematic diagram.
[0044] Follow step S1, refer to Figure 2a , a semiconductor structure is provided, the semiconductor structure comprising: a substrate 10 and a lower insulating dielectric layer 11, at least two lower conductive interconnect structures 12 are formed in the lower insulating dielectric layer 11, and a lower air gap 131 is formed in the lower insulating dielectric layer 11 between two adjacent lower conductive interconnect structures 12.
[0045] The material of the substrate 10 can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.
[0046] like Figure 2a As shown, a transistor is formed on the substrate 10 , and the lower insulating dielectric layer 11 covers the transistor. The transistor includes a gate structure 101 formed on the substrate 10 and a source region 102 and a drain region 103 formed on both sides of the gate structure 101 .
[0047] The gate structure 101 may include a stacked gate oxide layer and a gate layer, and sidewall spacers formed on sidewalls of the gate layer and the gate oxide layer.
[0048] Preferably, an etch stop layer (not shown) is formed on the transistor, and the lower insulating dielectric layer 11 covers the etch stop layer.
[0049] The lower conductive interconnect structure 12 is formed on the source region 102 and the drain region 103, and the lower conductive interconnect structure 12 includes: a contact plug 121, which is disposed on the source region 102 and the drain region 103; and a lower metal interconnect layer 122, which is stacked on the contact plug 121 and is respectively connected to the contact plug 121 on the source region 102 or the drain region 103. Alternatively, the lower conductive interconnect structure 12 is formed on the gate structure 101, the source region 102, and the drain region 103.
[0050] The lower air gap 131 is formed above the gate structure 101; and / or, the lower air gap 131 is formed between the lower conductive interconnect structure 12 on the source region 102 and the lower conductive interconnect structure 12 on the gate structure 101; and / or, the lower air gap 131 is formed between the lower conductive interconnect structure 12 on the drain region 103 and the lower conductive interconnect structure 12 on the gate structure 101.
[0051] exist Figure 2a In the illustrated embodiment, the lower insulating dielectric layer 11 may include multiple sub-dielectric layers, such as a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, and a fourth insulating layer 114 stacked from bottom to top, wherein the material of the first insulating layer 111, the second insulating layer 112, and the fourth insulating layer 114 is, for example, silicon oxide, and an etch stop layer (not shown) is provided between the first insulating layer 111 and the second insulating layer 112, and the material of the etch stop layer and the third insulating layer 113 is, for example, silicon nitride. The contact plug 121 is formed in the first insulating layer 111, and the lower metal interconnection layer 122 is formed in the second insulating layer 112 and the etch stop layer, and the third insulating layer 113 covers the lower metal interconnection layer 122. It should be noted that the structural composition of the lower insulating dielectric layer 11 is not limited to Figure 2a The embodiment shown.
[0052] by Figure 2aTaking the embodiment shown in the figure as an example, the steps of forming the semiconductor structure may include: first, forming a first insulating layer 111 to cover the transistor; then, etching the first insulating layer 111 to form contact holes exposing the source region 102 and the drain region 103 respectively, and filling the contact holes with metal to form contact plugs 121; then, forming an etch stop layer and a second insulating layer 112 stacked on the first insulating layer 111, the etch stop layer covering the contact plug 121; then, etching the second insulating layer 112 and the etch stop layer to form a groove exposing the contact plug 121 and a portion of the top surface of the first insulating layer 111 around the contact plug 121, and filling the groove with metal to form a A lower metal interconnection layer 122 is formed, and the width of the lower metal interconnection layer 122 is greater than the width of the contact plug 121; then, a third insulating layer 113 is formed on the second insulating layer 112, and the third insulating layer 113 covers the lower metal interconnection layer 122; then, the third insulating layer 113, the second insulating layer 112, the etching stop layer and the second insulating layer 111 between the lower metal interconnection layer 122 above the source region 102 and the drain region 103 are etched to form a lower air gap 131; then, a fourth insulating layer 114 is formed on the third insulating layer 113, and the fourth insulating layer 114 seals the lower air gap 131, and the lower air gap 131 is a closed hollow structure.
[0053] Among them, when the fourth insulating layer 114 seals the lower air gap 131, the fourth insulating layer 114 will also be formed on part of the side wall of the lower air gap 131, and due to the characteristics of the hole filling process of the chemical vapor deposition process, the lower air gap 131 starts to close upward from between the adjacent lower metal interconnection layers 122, resulting in the width of the sealed lower air gap 131 gradually decreasing from between the adjacent lower metal interconnection layers 122 upward.
[0054] In one embodiment, the top of the lower air gap 131 may extend upward to exceed the top surface of the third insulating layer 113 .
[0055] According to step S2, Figure 2d As shown, a through hole 14 exposing the top surface of the lower conductive interconnect structure 12 and an upper air gap 132 communicating with the lower air gap 131 are formed, and the upper air gap 132 is sealed by a barrier layer 15 .
[0056] Preferably, when etching the lower insulating dielectric layer 11 above the lower air gap 131 to form the upper air gap 132, part or all of the lower insulating dielectric layer 11 (i.e., the lower insulating dielectric layer 11 formed on the sidewall of the lower air gap 131 when sealing the lower air gap 131) may also be etched away. Figure 2aPart or all of the fourth insulating layer 114 on the side wall of the lower air gap 131 as shown in the figure increases the top width of the lower air gap 131 after etching, that is, the top width of the lower air gap 131 before etching the lower insulating dielectric layer 11 is smaller than the top width of the lower air gap 131 after etching the lower insulating dielectric layer 11, thereby further reducing the parasitic capacitance formed by the adjacent lower conductive interconnect structure 12 and the lower insulating dielectric layer 11 and the lower air gap 131 therebetween.
[0057] Among them, if the lower insulating dielectric layer 11 above the lower air gap 131 is etched to form the upper air gap 132, the lower insulating dielectric layer 11 formed on the side wall of the lower air gap 131 when the lower air gap 131 is sealed is completely etched away, then the morphology of the lower air gap 131 after etching is the same as the morphology of the lower air gap 131 before sealing; at this time, if the width from the bottom to the top of the lower air gap 131 before sealing is equal, then the width from the bottom to the top of the lower air gap 131 after etching is equal.
[0058] like Figure 2b to Figure 2d As shown, step S2 may include:
[0059] Step S21, etching the lower insulating dielectric layer 11 to form a first through hole 141 above the lower conductive interconnect structure 12 and an upper air gap 132 connected to the lower air gap 131. In one embodiment, a portion of the thickness of the lower insulating dielectric layer 11 may remain at the bottom of the first through hole 141; Figure 2b As shown, the first through hole 141 penetrates the fourth insulating layer 114, and the third insulating layer 113 remains at the bottom of the first through hole 141, and the third insulating layer 113 serves as an etching stop layer; in another embodiment, the first through hole 141 penetrates the fourth insulating layer 114 and the third insulating layer 113, exposing a portion of the top surface of the underlying conductive interconnect structure 12.
[0060] Step S22, as Figure 2c As shown, a barrier layer 15 is formed on the lower insulating dielectric layer 11, and the barrier layer 15 seals the upper air gap 132 and the first through hole 141; the barrier layer 15 may also be formed in small amounts on the sidewalls of the upper air gap 132 and the first through hole 141;
[0061] Step S23 , etching the barrier layer 15 and the lower insulating dielectric layer 11 to form a through hole 14 exposing a portion of the top surface of the lower conductive interconnect structure 12 .
[0062] In one embodiment, the step of etching to form the through hole 14 includes: etching the barrier layer 15 and the lower insulating dielectric layer 11 so that the width of the first through hole 141 at a part of the height is increased to form a second through hole 142, and the first through hole 141 is extended downward to the top surface of the lower conductive interconnect structure 12, the first through hole 141 exposes the top surface of the lower conductive interconnect structure 12, the second through hole 142 is located on the top of the first through hole 141 at the remaining height, and the second through hole 142 and the first through hole 141 at the remaining height constitute the through hole 14. Figure 2d As shown, the second through hole 142 is formed in the fourth insulating layer 114 , the first through hole 141 extends downward from the fourth insulating layer 114 to the third insulating layer 113 , and the first through hole 141 exposes the top surface of the underlying metal interconnection layer 122 .
[0063] The material of the barrier layer 15 can be oxide, such as silane oxide.
[0064] According to step S3, Figure 2e As shown, an upper conductive interconnect structure 16 is formed in the through hole 14 .
[0065] Since the barrier layer 15 seals the upper air gap 132 , it is possible to prevent the upper conductive interconnect structure 16 from being formed in the upper air gap 132 .
[0066] The step S3 may include: Figure 2e As shown, the metal material is first filled in the through hole 14 by an electrochemical plating process to form the upper conductive interconnect structure 16 in the through hole 14, and the metal material also covers the barrier layer 15; then, the metal material above the top surface of the barrier layer 15 is polished away by a chemical mechanical polishing process.
[0067] In one embodiment, the barrier layer 15 is retained.
[0068] In another embodiment, the method for manufacturing the semiconductor device further includes:
[0069] Step S4, such as Figure 3 As shown, the barrier layer 15 is removed to expose the upper air gap 132; wherein, the barrier layer 15 above the top surface of the lower insulating dielectric layer 11 can be removed by a chemical mechanical polishing process; preferably, the barrier layer 15 on the side wall of the upper air gap 132 is also removed.
[0070] Step S5, such as Figure 4As shown, an upper insulating dielectric layer 17 is formed on the lower insulating dielectric layer 11, and the upper insulating dielectric layer 17 covers the upper conductive interconnect structure 16 and seals the upper air gap 132. The sealed upper air gap 132 is a closed hollow structure.
[0071] In one embodiment, the upper insulating dielectric layer 17 may include a fifth insulating layer 171 and a sixth insulating layer 172 stacked from bottom to top.
[0072] When the upper insulating dielectric layer 17 seals the upper air gap 132, the upper insulating dielectric layer 17 will also be formed on part of the side walls of the upper air gap 132, and due to the characteristics of the hole filling process of the chemical vapor deposition process, the upper air gap 132 starts to close upward from between the adjacent upper conductive interconnect structures 16, so that the width of the sealed upper air gap 132 gradually decreases upward from between the adjacent upper conductive interconnect structures 16.
[0073] In one embodiment, the top of the upper air gap 132 may extend upward to exceed the top surface of the lower insulating dielectric layer 11 .
[0074] In one embodiment, the method for manufacturing a semiconductor device further includes: Figure 5 As shown, a top conductive structure 18 is formed in the upper insulating dielectric layer 17 on the upper conductive interconnect structure 16 , and the top conductive structure 18 is electrically connected to the upper conductive interconnect structure 16 .
[0075] In another embodiment, the method for manufacturing the semiconductor device further includes:
[0076] The upper insulating dielectric layer 17 is used as another lower insulating dielectric layer, the upper conductive interconnect structure 16 is used as another lower conductive interconnect structure, and the upper air gap 132 is used as another lower air gap, and steps S2 to S5 are repeatedly performed, so that when the semiconductor device includes a multi-layer stacked conductive interconnect structure, the formed air gap can extend upward from between adjacent conductive interconnect structures at the bottom layer to between adjacent conductive interconnect structures at the top layer, thereby reducing the parasitic capacitance formed by all adjacent conductive interconnect structures and the insulating dielectric layers and air gaps therebetween.
[0077] by Figure 6For example, the semiconductor device includes two stacked upper insulating dielectric layers 17, two stacked upper conductive interconnect structures 16, and two connected upper air gaps 132, and the upper air gap 132 away from the lower air gap 131 extends upward to between adjacent top conductive structures 18; wherein the upper insulating dielectric layer 17 close to the lower insulating dielectric layer 11 serves as another lower insulating dielectric layer, the upper conductive interconnect structure 16 close to the lower conductive interconnect structure 12 serves as another lower conductive interconnect structure, and the upper air gap 132 close to the lower air gap 131 serves as another lower air gap; that is, the semiconductor device includes three stacked conductive interconnect structures, the lower conductive interconnect structure 12 is the bottom conductive interconnect structure, the upper conductive interconnect structure 16 away from the lower conductive interconnect structure 12 is the top conductive interconnect structure, and the air gap extends upward from between the bottom adjacent conductive interconnect structures to between the top adjacent conductive interconnect structures.
[0078] From the above content, it can be known that by forming the upper air gap 132 in the lower insulating dielectric layer 11 between the upper conductive interconnect structures 16 on two adjacent lower conductive interconnect structures 12, and the upper air gap 132 is connected with the lower air gap 131, the volume of the air gap is increased, and the parasitic capacitance formed by the adjacent conductive interconnect structures as a whole (including the lower conductive interconnect structure 12 and the upper conductive interconnect structure 16) and the lower insulating dielectric layer 11 and the air gap (including the lower air gap 131 and the upper air gap 132) therebetween is further reduced, thereby further reducing the parasitic capacitance of the semiconductor device.
[0079] Furthermore, when the semiconductor device includes a multi-layer stacked conductive interconnect structure, by repeatedly executing steps S2 to S5, the air gap can be extended upward from between adjacent conductive interconnect structures at the bottom layer to between adjacent conductive interconnect structures at the top layer, thereby reducing the parasitic capacitance formed by all adjacent conductive interconnect structures and the insulating dielectric layers and air gaps therebetween.
[0080] In addition, when etching to form the upper air gap 132, part or all of the lower insulating dielectric layer 11 formed on the side wall of the lower air gap 131 when sealing the lower air gap 131 can also be etched away, so that the top width of the lower air gap 131 after etching is increased, thereby further reducing the parasitic capacitance formed by the lower insulating dielectric layer 11 and the lower air gap 131 between the adjacent lower conductive interconnect structure 12 and the two.
[0081] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: step S1, providing a semiconductor structure, the semiconductor structure comprising: a substrate and a lower insulating dielectric layer, the lower insulating dielectric layer having at least two lower conductive interconnect structures formed therein, and a lower air gap formed in the lower insulating dielectric layer between two adjacent lower conductive interconnect structures; step S2, forming a through hole exposing the top surface of the lower conductive interconnect structure and an upper air gap connected to the lower air gap, the upper air gap being sealed by a barrier layer; step S3, forming an upper conductive interconnect structure in the through hole. The method for manufacturing a semiconductor device of the present invention further reduces the parasitic capacitance of the semiconductor device.
[0082] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, on which a lower insulating dielectric layer is formed, and at least two lower conductive interconnect structures are formed in the lower insulating dielectric layer; an upper conductive interconnect structure is formed in the lower insulating dielectric layer on the lower conductive interconnect structure, or at least two upper conductive interconnect structures are formed in the lower insulating dielectric layer and the upper insulating dielectric layer on the lower conductive interconnect structure; and an air gap structure extends from between two adjacent lower conductive interconnect structures to between two adjacent upper conductive interconnect structures.
[0083] See below Figure 4 , Figure 5 and Figure 6 The semiconductor device provided in this embodiment is described in detail. Figure 4 , Figure 5 and Figure 6 It is also a schematic diagram of a longitudinal section.
[0084] A lower insulating dielectric layer 11 is formed on the substrate 10 , and at least two lower conductive interconnect structures 12 are formed in the lower insulating dielectric layer 11 .
[0085] The material of the substrate 10 can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.
[0086] A transistor is formed on the substrate 10 . The lower insulating dielectric layer 11 covers the transistor. The transistor includes a gate structure 101 formed on the substrate 10 , and a source region 102 and a drain region 103 formed on both sides of the gate structure 101 .
[0087] The gate structure 101 may include a stacked gate oxide layer and a gate layer, and sidewall spacers formed on sidewalls of the gate layer and the gate oxide layer.
[0088] Preferably, an etch stop layer (not shown) is formed on the transistor, and the lower insulating dielectric layer 11 covers the etch stop layer.
[0089] The lower conductive interconnect structure 12 is formed on the source region 102 and the drain region 103, and the lower conductive interconnect structure 12 includes: a contact plug 121, which is disposed on the source region 102 and the drain region 103; and a lower metal interconnect layer 122, which is stacked on the contact plug 121 and is respectively connected to the contact plug 121 on the source region 102 or the drain region 103. Alternatively, the lower conductive interconnect structure 12 is formed on the gate structure 101, the source region 102, and the drain region 103.
[0090] exist Figure 4 , Figure 5 and Figure 6 In the illustrated embodiment, the lower insulating dielectric layer 11 may include multiple sub-dielectric layers, such as a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, and a fourth insulating layer 114 stacked from bottom to top, wherein the material of the first insulating layer 111, the second insulating layer 112, and the fourth insulating layer 114 is, for example, silicon oxide, and an etch stop layer (not shown) is provided between the first insulating layer 111 and the second insulating layer 112, and the material of the etch stop layer and the third insulating layer 113 is, for example, silicon nitride. The contact plug 121 is formed in the first insulating layer 111, and the lower metal interconnection layer 122 is formed in the second insulating layer 112 and the etch stop layer, and the third insulating layer 113 covers the lower metal interconnection layer 122. It should be noted that the structural composition of the lower insulating dielectric layer 11 is not limited to Figure 4 , Figure 5 and Figure 6 The embodiment shown.
[0091] like Figure 4 and Figure 5 As shown, a layer of the upper conductive interconnect structure 16 is formed in the lower insulating dielectric layer 11 on the lower conductive interconnect structure 12; or Figure 6 As shown, at least two upper conductive interconnect structures 16 are formed in the lower insulating dielectric layer 11 and the upper insulating dielectric layer 17 on the lower conductive interconnect structure 12. The upper conductive interconnect structure 16 is electrically connected to the lower conductive interconnect structure 12.
[0092] In the lower insulating dielectric layer 11 , the upper conductive interconnect structure 16 may extend downward from the fourth insulating layer 114 to the third insulating layer 113 , and the top surface of the upper conductive interconnect structure 16 is flush with the top surface of the fourth insulating layer 114 .
[0093] In one embodiment, the upper insulating dielectric layer 17 may include a fifth insulating layer 171 and a sixth insulating layer 172 stacked from bottom to top.
[0094] In the upper insulating dielectric layer 17 , the top surface of the upper conductive interconnect structure 16 is flush with the top surface of the sixth insulating layer 172 .
[0095] The air gap structure extends from between two adjacent lower conductive interconnect structures 12 to between two adjacent upper conductive interconnect structures 16 .
[0096] The upper insulating dielectric layer 17 seals the air gap structure, and the sealed air gap structure forms a closed hollow structure.
[0097] The air gap structure is formed above the gate structure 101; and / or, the air gap structure is formed between the lower conductive interconnect structure 12 on the source region 102 and the lower conductive interconnect structure 12 on the gate structure 101; and / or, the air gap structure is formed between the lower conductive interconnect structure 12 on the drain region 103 and the lower conductive interconnect structure 12 on the gate structure 101.
[0098] In one embodiment, the upper insulating dielectric layer 17 also covers the lower insulating dielectric layer 11 and the upper conductive interconnect structure 16 .
[0099] exist Figure 4 and Figure 5 In the embodiment shown, the upper conductive interconnect structure 16 is a layer, the upper insulating dielectric layer 17 is a layer, the air gap structure includes a lower air gap 131 formed in the lower insulating dielectric layer 11 between two adjacent lower conductive interconnect structures 12 and an upper air gap 132 formed in the lower insulating dielectric layer 11 between two adjacent upper conductive interconnect structures 16, the upper air gap 132 is located at the top of the lower air gap 131, the upper air gap 132 is connected to the lower air gap 131, and the upper insulating dielectric layer 17 seals the upper air gap 132. The lower air gap 131 extends upward from the first insulating layer 111 to the third insulating layer 113, and the upper air gap 132 is located in the third insulating layer 113 and the fourth insulating layer 114.
[0100] exist Figure 6 In the illustrated embodiment, the upper conductive interconnect structure 16 has at least two layers, the upper insulating dielectric layer 17 has at least two layers, and the air gap structure includes one layer of the lower air gap 131 and at least two layers of the upper air gap 132 .
[0101] Since the upper air gap 132 is formed above the lower air gap 131, the film layer structure (for example, the fourth insulating layer 114) formed on the side wall of the lower air gap 131 when the lower air gap 131 is sealed has been partially or completely removed, thereby increasing the top width of the lower air gap 131 below the upper air gap 132, thereby further reducing the parasitic capacitance formed by the adjacent lower conductive interconnect structure 12 and the lower insulating dielectric layer 11 and the lower air gap 131 therebetween.
[0102] In one embodiment, the width of the lower air gap 131 from the bottom to the top is equal.
[0103] When the upper insulating dielectric layer 17 seals the air gap structure, the upper insulating dielectric layer 17 will also be formed on part of the side walls of the upper air gap 132, and due to the characteristics of the hole filling process of the chemical vapor deposition process, the upper air gap 132 starts to close upward from between the adjacent upper conductive interconnect structures 16, so that the width of the upper air gap 132 after sealing gradually decreases upward from between the adjacent upper conductive interconnect structures 16.
[0104] When the upper insulating dielectric layer 17 also covers the lower insulating dielectric layer 11 and the upper conductive interconnect structure 16, as shown in FIG. Figure 5 and Figure 6 As shown, the semiconductor device further includes: a top conductive structure 18 formed in the upper insulating dielectric layer 17 on the topmost upper conductive interconnect structure 16 , and the top conductive structure 18 is electrically connected to the upper conductive interconnect structure 16 .
[0105] From the above content, it can be seen that since the air gap structure extends from between two adjacent lower conductive interconnect structures 12 to between two adjacent upper conductive interconnect structures 16, the volume of the air gap structure is increased, thereby further reducing the parasitic capacitance of the adjacent conductive interconnect structures as a whole (including the lower conductive interconnect structure 12 and the upper conductive interconnect structure 16) and the lower insulating dielectric layer 11 therebetween and the air gap structure, thereby further reducing the parasitic capacitance of the semiconductor device.
[0106] In summary, the present invention provides a semiconductor device, comprising: a substrate, a lower insulating dielectric layer formed on the substrate, at least two lower conductive interconnect structures formed in the lower insulating dielectric layer; an upper conductive interconnect structure formed in the lower insulating dielectric layer on the lower conductive interconnect structure, or at least two upper conductive interconnect structures formed in the lower insulating dielectric layer and the upper insulating dielectric layer on the lower conductive interconnect structure; an air gap structure extending from between two adjacent lower conductive interconnect structures to between two adjacent upper conductive interconnect structures. The semiconductor device provided by the present invention further reduces parasitic capacitance.
[0107] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Step S1, providing a semiconductor structure, the semiconductor structure comprising: a substrate and a lower insulating dielectric layer, the lower insulating dielectric layer having at least two lower conductive interconnect structures formed therein, and a lower air gap formed in the lower insulating dielectric layer between two adjacent lower conductive interconnect structures; Step S2, forming a through hole exposing the top surface of the lower conductive interconnect structure and an upper air gap communicating with the lower air gap, wherein the upper air gap is sealed by a barrier layer; Step S3, forming an upper conductive interconnect structure in the through hole.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for manufacturing the semiconductor device further includes: Step S4, removing the barrier layer to expose the upper air gap; Step S5, forming an upper insulating dielectric layer on the lower insulating dielectric layer, wherein the upper insulating dielectric layer covers the upper conductive interconnect structure and seals the upper air gap.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: The method for manufacturing the semiconductor device further includes: The upper insulating dielectric layer is used as another lower insulating dielectric layer, the upper conductive interconnect structure is used as another lower conductive interconnect structure, and the upper air gap is used as another lower air gap, and steps S2 to S5 are repeatedly performed.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The lower insulating dielectric layer is etched to form an upper air gap connected to the lower air gap, and the top width of the lower air gap before etching the lower insulating dielectric layer is smaller than the top width of the lower air gap after etching the lower insulating dielectric layer.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The step S2 comprises: Etching the lower insulating dielectric layer to form a first through hole above the lower conductive interconnect structure and to form an upper air gap connected to the lower air gap; forming a barrier layer on the lower insulating dielectric layer, wherein the barrier layer seals the upper air gap and the first through hole; The barrier layer and the lower insulating dielectric layer are etched to form a through hole exposing a top surface of a portion of the lower conductive interconnect structure.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor structure includes a transistor formed on the substrate, the transistor includes a gate structure formed on the substrate and a source region and a drain region formed on both sides of the gate structure, the lower conductive interconnect structure is formed on the source region and the drain region, or the lower conductive interconnect structure is formed on the gate structure, the source region and the drain region.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: The lower air gap is formed above the gate structure; and / or, the lower air gap is formed between the lower conductive interconnect structure on the source region and the lower conductive interconnect structure on the gate structure; And / or, the lower air gap is formed between the lower conductive interconnect structure on the drain region and the lower conductive interconnect structure on the gate structure.
8. A semiconductor device, characterized in that: include: A substrate having a lower insulating dielectric layer formed thereon, and at least two lower conductive interconnect structures formed in the lower insulating dielectric layer; an upper conductive interconnect structure formed in the lower insulating dielectric layer on the lower conductive interconnect structure, or at least two upper conductive interconnect structures formed in the lower insulating dielectric layer and the upper insulating dielectric layer on the lower conductive interconnect structure; The air gap structure extends from between two adjacent lower conductive interconnect structures to between two adjacent upper conductive interconnect structures.
9. The semiconductor device according to claim 8, characterized in that The upper insulating dielectric layer also covers the lower insulating dielectric layer and the upper conductive interconnect structure.
10. The semiconductor device according to claim 8, wherein A transistor is formed on the substrate, and the transistor includes a gate structure formed on the substrate and a source region and a drain region formed on both sides of the gate structure, and the lower conductive interconnect structure is formed on the source region and the drain region, or the lower conductive interconnect structure is formed on the gate structure, the source region and the drain region.
11. The semiconductor device according to claim 10, wherein: The air gap structure is formed above the gate structure; and / or, the air gap structure is formed between the lower conductive interconnect structure on the source region and the lower conductive interconnect structure on the gate structure; And / or, the air gap structure is formed between the lower conductive interconnect structure on the drain region and the lower conductive interconnect structure on the gate structure.